Energy efficiency optimization method and device based on chip stack packaging

Abstract

The invention relates to the technical field of chip packaging, and discloses an energy efficiency optimization method and device based on chip stack packaging, and the method comprises the steps: analyzing a plurality of packaging design indexes of a to-be-packaged object, and obtaining a design guide frame corresponding to each packaging design index; according to the method, the to-be-packaged object is subjected to the packaging design according to the design guiding framework through the pre-trained intelligent model, the packaging scheme of the to-be-packaged object is obtained, the requirements of a client for the packaging design can be input in advance in this way, and then the packaging design scheme corresponding to the requirements of the packaging design is automatically output; the problem that in the prior art, packaging design is conducted according to conventional parameters, and various requirements of customers cannot be met easily is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an energy efficiency optimization method and device based on chip stacking packaging. Background Art

[0002] Currently, customers have increasingly higher requirements for substrate design. How to quickly and efficiently design substrates to meet customer requirements has become a problem that needs to be solved.

[0003] Most current technologies are designed according to conventional parameters, and then optimized and modified through simulation results. This is prone to repeated modifications at a later stage and fails to meet customers' various performance requirements. Summary of the invention

[0004] The purpose of the present invention is to provide an energy efficiency optimization method and device based on chip stacking packaging, aiming to solve the problem in the prior art that packaging design according to conventional parameters is apt to fail to meet various requirements of customers.

[0005] The present invention is implemented in this way. In a first aspect, the present invention provides an energy efficiency optimization method based on chip stacking packaging, comprising: Acquire information of an object to be packaged; wherein the object to be packaged includes a plurality of target chips; Acquire several packaging design indicators of the object to be packaged, and perform mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators; wherein the design guidance framework is used to describe the solution idea for packaging design of the object to be packaged; The information of the object to be packaged is substituted into the design guide framework, so that the design guide framework performs packaging design on the object to be packaged, and obtains a packaging solution for the object to be packaged.

[0006] Preferably, the step of obtaining a plurality of packaging design indicators of the object to be packaged, and performing mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators includes: Acquire several packaging design indicators of the object to be packaged; wherein the packaging design indicators include packaging size indicators, signal performance indicators and heat dissipation performance indicators; Analyze and process each of the package design indicators to obtain a package design direction corresponding to each of the package design indicators; wherein the package design direction is used to describe a design direction for realizing the package design indicator; An intersection analysis is performed on the package design directions of each package design indicator to eliminate incompatible parts of the package design directions of each package design indicator, to obtain the intersection part of the package design directions of each package design indicator, and to use the intersection part as the design guidance framework.

[0007] Preferably, the step of analyzing and processing each of the packaging design indicators to obtain a packaging design direction corresponding to each of the packaging design indicators comprises: Analyze and process the package size index to obtain a package design direction corresponding to the package size index; wherein the package size index is to reduce the package size of the object to be packaged; Analyze and process the signal performance index to obtain a packaging design direction corresponding to the signal performance index; wherein the signal performance index is to improve the signal performance of the object to be packaged after packaging; Analyze and process the heat dissipation performance index to obtain a packaging design direction corresponding to the heat dissipation performance index; wherein the heat dissipation performance index is to improve the heat dissipation performance of the object to be packaged after packaging.

[0008] Preferably, the package design direction corresponding to the package size index includes: Primary and secondary design directions and stacking design directions; The primary and secondary design directions include: dividing the target chips of the object to be packaged into a primary chip and a plurality of secondary chips, arranging the primary chip at the most central position, and arranging the secondary chips around the primary chip; wherein the distance between each secondary chip and the primary chip is between 2.0 and 3.0 mm; The stacking design direction includes: stacking the secondary chip with the smallest size on the primary chip for arrangement.

[0009] Preferably, the packaging design directions corresponding to the signal performance indicators include: Routing layout design direction and power supply layout design direction; The routing layout design direction includes: constructing a connection path on each target chip of the object to be packaged, performing parameter acquisition processing on each connection path, obtaining a signal adaptation parameter of each connection path, and adjusting each connection path according to the signal adaptation parameter of each connection path; wherein the signal adaptation parameter is used to describe the influence of the connection path on the signal quality of the object to be packaged after the packaging design; The power layout design direction includes: constructing a power supply path between the power supply and each of the target chips of the object to be packaged, performing parameter collection and processing on each of the power supply paths to obtain power supply performance parameters of each of the power supply paths, and adjusting the setting position of the power supply according to the power supply performance parameters of each of the power supply paths; wherein the power supply performance parameters are used to describe the degree of influence of the power supply path on the power supply quality.

[0010] Preferably, the packaging design direction corresponding to the heat dissipation performance index includes: Structural design direction, material design direction, thermal simulation design direction; The structural design direction includes: adding a heat dissipation structure to the packaging design of the object to be packaged; wherein the heat dissipation structure includes a heat sink and a heat dissipation channel; The material design direction includes: using a packaging material with thermal conductivity that meets a preset standard to perform packaging design on the object to be packaged; The thermal simulation design direction includes: predicting the temperature distribution of each target chip of the object to be packaged under different load conditions through thermal simulation analysis to obtain the heat concentration area, evaluating the heat dissipation effect of the packaging design of the object to be packaged according to the heat concentration area, and optimizing the packaging design of the object to be packaged according to the result of the heat dissipation effect evaluation.

[0011] Preferably, the information of the object to be encapsulated is substituted into the design guidance framework so that the design guidance framework performs encapsulation design on the object to be encapsulated, and the step of obtaining the encapsulation solution of the object to be encapsulated includes: Substituting the information of the object to be packaged into the design guidance framework, performing packaging design on the object to be packaged according to the design guidance framework through a pre-trained packaging design intelligent model, and obtaining several pre-selected solutions for the object to be packaged; Priority analysis is performed on each of the pre-selected solutions for the object to be encapsulated to obtain priority parameters of each of the pre-selected solutions, and the pre-selected solution with the highest priority parameter is used as the encapsulation solution for the object to be encapsulated.

[0012] Preferably, the training step of the packaging design intelligent model includes: Collecting a data set for training; wherein the data set includes several sets of training data, the training data includes design conditions and design products, the design conditions are the object to be packaged and each of the packaging design indicators corresponding to the object to be packaged, and the design product is the packaging solution corresponding to the object to be packaged; Structuring the collected data set into a package design topology structure; wherein the package design topology structure has conditional topology nodes and finished product topology nodes, the conditional topology nodes are used to feedback the design conditions, and the finished product topology nodes are used to feedback the design finished product; Based on a preset topological structure theory, topological tendency parameters of each of the conditional topological nodes and the finished product topological nodes are determined from the package design topological structure; wherein the topological tendency parameters of the conditional topological nodes and the finished product topological nodes are used to represent the mutual influence and connection between each of the conditional topological nodes and the finished product topological nodes; Performing parameter optimization extraction processing on the topological tendency parameters of each of the conditional topological nodes and the finished topological nodes, so as to select each of the conditional topological nodes and the finished topological nodes whose topological tendency parameters meet the optimization criteria as the preferred training combination; Extract preferred features from each of the preferred training combinations to obtain the preferred features of the preferred training combinations, simulate and generate packaging design solutions based on the preferred features, and select preferred training combinations from the simulated packaging design solutions and the existing preferred training combinations to perform a further round of preferred feature extraction, repeat the optimization process for several times, perform deep learning training on the initial packaging design intelligent model based on the optimized preferred training combinations to obtain a trained packaging design intelligent model.

[0013] In a second aspect, the present invention provides an energy efficiency optimization device based on chip stacking packaging, comprising: An information acquisition module, used to acquire information of an object to be packaged; wherein the object to be packaged includes a plurality of target chips; A scheme construction module is used to obtain several packaging design indicators of the object to be packaged, and perform mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators; wherein the design guidance framework is used to describe the scheme idea for packaging design of the object to be packaged; The solution analysis module is used to substitute the information of the object to be packaged into the design guidance framework, so that the design guidance framework performs packaging design on the object to be packaged and obtains a packaging solution for the object to be packaged.

[0014] The present invention provides an energy efficiency optimization method based on chip stacking packaging, which has the following beneficial effects: The present invention analyzes several packaging design indicators of the object to be packaged to obtain a design guidance framework corresponding to each packaging design indicator, and performs packaging design on the object to be packaged according to the design guidance framework through a pre-trained intelligent model to obtain a packaging scheme for the object to be packaged. In this way, the customer's requirements for packaging design can be input in advance, and then a packaging design scheme corresponding to the packaging design requirements can be automatically output, which solves the problem in the prior art that packaging design according to conventional parameters is prone to fail to meet the various requirements of customers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the steps of an energy efficiency optimization method based on chip stacking packaging provided by an embodiment of the present invention; Figure 2 It is a structural schematic diagram of an energy efficiency optimization device based on chip stacking packaging provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] The implementation of the present invention is described in detail below in conjunction with specific embodiments.

[0018] Reference Figure 1 , Figure 2 As shown, a preferred embodiment of the present invention is provided.

[0019] In a first aspect, the present invention provides an energy efficiency optimization method based on chip stacking packaging, comprising: S1: Obtain information of an object to be packaged; wherein the object to be packaged includes a plurality of target chips; S2: obtaining several packaging design indicators of the object to be packaged, and performing mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators; wherein the design guidance framework is used to describe the solution idea for packaging design of the object to be packaged; S3: Substitute the information of the object to be encapsulated into the design guidance framework, so that the design guidance framework performs encapsulation design on the object to be encapsulated to obtain a packaging solution for the object to be encapsulated.

[0020] Specifically, the objects to be packaged are various target chips that need to be packaged on a substrate. Each target chip has different specifications and models. The specifications and models of these target chips determine how to arrange the packaging design in the subsequent process. Therefore, it is necessary to first obtain the information of each target chip of the object to be packaged.

[0021] More specifically, for the object to be encapsulated, there are multiple packaging design indicators at the same time. These packaging design indicators are used to describe the packaging requirements of the object to be encapsulated. When performing packaging design for the object to be encapsulated, it is necessary to start from each packaging design indicator; therefore, the idea adopted by the present invention is to first generate corresponding packaging design ideas according to each packaging design indicator of the object to be encapsulated, and perform constraint mapping processing on the packaging design ideas corresponding to each packaging design indicator to obtain a design guidance framework.

[0022] It can be understood that the design guidance framework is used to describe the solution ideas for packaging design of the packaging object. This solution idea can simultaneously meet the packaging design ideas corresponding to various packaging design indicators, that is, the intersection of the packaging design ideas of various packaging design indicators.

[0023] More specifically, the object to be encapsulated is substituted into the design guidance framework, so that the design guidance framework performs encapsulation design on the object to be encapsulated, and obtains a packaging solution for the object to be encapsulated.

[0024] The present invention provides an energy efficiency optimization method based on chip stacking packaging, which has the following beneficial effects: The present invention analyzes several packaging design indicators of the object to be packaged to obtain a design guidance framework corresponding to each packaging design indicator, and performs packaging design on the object to be packaged according to the design guidance framework through a pre-trained intelligent model to obtain a packaging scheme for the object to be packaged. In this way, the customer's requirements for packaging design can be input in advance, and then a packaging design scheme corresponding to the packaging design requirements can be automatically output, which solves the problem in the prior art that packaging design according to conventional parameters is prone to fail to meet the various requirements of customers.

[0025] Preferably, the step of obtaining a plurality of packaging design indicators of the object to be packaged, and performing mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators includes: S21: Acquire several packaging design indicators of the object to be packaged; wherein the packaging design indicators include packaging size indicators, signal performance indicators, and heat dissipation performance indicators; S22: Analyze and process each of the package design indicators to obtain a package design direction corresponding to each of the package design indicators; wherein the package design direction is used to describe a design direction for realizing the package design indicator; S23: performing intersection analysis on the package design directions of the respective package design indicators to exclude incompatible parts of the package design directions of the respective package design indicators, obtaining the intersection parts of the package design directions of the respective package design indicators, and using the intersection parts as the design guidance framework.

[0026] Specifically, the packaging design indicators of the object to be packaged include packaging size indicators, signal performance indicators and heat dissipation performance indicators; it can be understood that in addition to the above three, the packaging design indicators can also include other indicators. By adding other indicators, new packaging design ideas can be added.

[0027] More specifically, analysis and processing are performed respectively according to each packaging design indicator to obtain a packaging design direction corresponding to each packaging design indicator, and the packaging design direction is used to describe a design direction for realizing the packaging design indicator.

[0028] More specifically, an intersection analysis is performed on the package design directions of each package design indicator to eliminate incompatible parts of the package design directions of each package design indicator, to obtain the intersection part of the package design directions of each package design indicator, and to use the intersection part as a design guidance framework.

[0029] Preferably, the step of analyzing and processing each of the packaging design indicators to obtain a packaging design direction corresponding to each of the packaging design indicators comprises: S221: Analyze and process the package size indicator to obtain a package design direction corresponding to the package size indicator; wherein the package size indicator is to reduce the package size of the object to be packaged; S222: Analyze and process the signal performance index to obtain a packaging design direction corresponding to the signal performance index; wherein the signal performance index is to improve the signal performance of the object to be packaged after packaging; S223: Analyze and process the heat dissipation performance index to obtain a packaging design direction corresponding to the heat dissipation performance index; wherein the heat dissipation performance index is to improve the heat dissipation performance of the object to be packaged after packaging.

[0030] Specifically, analyze the physical size requirements of the object to be packaged, determine the possibilities and limitations of minimizing the package size, consider how to layout the internal components and how to optimize the package structure to reduce the overall size, and explore the use of high-density packaging technologies such as stacked chips (3D IC), system-level package (SiP), or package-in-package (PiP).

[0031] It is understandable that reducing the package size can make the final product more compact, facilitate integration into space-constrained applications, help reduce weight, improve portability and physical compatibility, and reduce costs by reducing the amount of materials used.

[0032] More specifically, evaluate signal path, shielding, and grounding designs to maximize signal integrity and reduce latency, and consider using high-performance materials and packaging technologies, such as low-dielectric constant (low-k) dielectric materials, to increase signal transmission speed.

[0033] It is understandable that improving the signal performance after packaging, including higher transmission rates and lower signal loss, reducing signal interference and crosstalk, and improving the overall performance and reliability of the system, and optimized signal design helps meet more stringent performance specifications and standards.

[0034] More specifically, evaluate the thermal conductivity of packaging materials and heat dissipation structure design, such as thermal channels and heat sinks, use thermal simulation analysis to determine thermal management strategies, identify hot spots and propose corresponding cooling solutions, and explore integrated passive cooling (such as heat sinks) or active cooling (such as fans or water cooling) technologies.

[0035] It is understandable that improving the heat dissipation performance after packaging ensures that the chip runs at the optimal temperature and extends the product life. Optimized heat dissipation design helps prevent overheating, reduces the risk of performance degradation and failure caused by heat, supports higher power consumption designs, and provides the possibility for enhanced computing and processing capabilities.

[0036] It should be noted that in the above steps, each packaging design indicator is a directional indicator, such as the packaging size indicator is to reduce the packaging size of the object to be packaged, the signal performance indicator is to improve the signal performance of the object to be packaged after packaging, and the heat dissipation performance indicator is to improve the heat dissipation performance of the object to be packaged after packaging.

[0037] More specifically, the package design indicators can be further divided into several different levels. The directions of the package design indicators vary in degree of orientation. For example, the package size indicators can be divided into several specification levels. Different specification levels limit the specific size range of the package design.

[0038] Preferably, the package design directions corresponding to the package size indicators include: Primary and secondary design directions and stacking design directions; the primary and secondary design directions include: dividing several target chips of the object to be packaged into a primary chip and several secondary chips, setting the primary chip at the most central position, and setting the secondary chips around the primary chip; wherein the distance between each secondary chip and the primary chip is between 2.0-3.0mm; the stacking design direction includes: stacking the smallest secondary chip on the primary chip for setting.

[0039] Specifically, the object to be packaged includes several target chips, which are divided into a main chip and several secondary chips. The main chip is generally the largest target chip. The main chip is set at the most central position, and the secondary chips are set around the main chip. The distance between each secondary chip and the main chip is between 2.0-3.0mm.

[0040] It can be understood that in the package layout, placing the main chip in the most central position can ensure that it has the best connection path and the least signal delay; the secondary chips are arranged around the main chip, and each secondary chip is kept at a distance of 2.0 to 3.0 mm from the main chip to optimize the connection path length and signal integrity, while considering heat dissipation and electromagnetic interference (EMI) issues; this design maximizes the use of packaging space, improves packaging density, and reduces the overall package size; by reducing the distance between the main chip and the secondary chip, signal propagation delay and interference can be reduced, thereby improving circuit performance; reasonable distance allocation helps design the heat dissipation path and avoid overheating problems.

[0041] More specifically, the smallest chips are selected from the secondary chips, and these smallest secondary chips are placed on top of the main chip through stacking technology, using appropriate insulation and fixing technologies to ensure the stability of physical and electrical connections, and necessary thermal management measures are designed, such as heat conduction through through silicon vias (TSVs) or integrating a heat dissipation layer in the stacking structure.

[0042] It is understandable that further reducing the package size provides three-dimensional space utilization for the package, making the package more compact and allowing more functions and performance to be integrated in a limited space, especially for application areas such as high-performance computing, storage and network communications. Although stacking may increase the challenges of thermal management, through carefully designed thermal solutions, heat can be effectively exported to ensure stable operation of the system.

[0043] It should be noted that these design directions can be carried out simultaneously or selectively, and the specific arrangement needs to be determined by the subsequent mapping constraint processing between various packaging design directions.

[0044] More specifically, when a package design indicator has a specific required scale, the package design direction corresponding to the package design indicator will also have a corresponding scale. It can be understood that this scale determines the specific details of each design guidance direction.

[0045] Preferably, the packaging design directions corresponding to the signal performance indicators include: The wiring layout design direction and the power supply layout design direction; the wiring layout design direction includes: constructing a connection path in each target chip of the object to be packaged, collecting and processing parameters of each connection path, obtaining signal adaptation parameters of each connection path, and adjusting each connection path according to the signal adaptation parameters of each connection path; wherein the signal adaptation parameters are used to describe the degree of influence of the connection path on the signal quality; the power supply layout design direction includes: constructing a power supply path between the power supply and each target chip of the object to be packaged, collecting and processing parameters of each power supply path, obtaining power supply performance parameters of each power supply path, and adjusting the setting position of the power supply according to the power supply performance parameters of each power supply path; wherein the power supply performance parameters are used to describe the degree of influence of the power supply path on the power supply quality.

[0046] Specifically, a signal connection path is constructed between the object to be packaged and its target chip, and detailed parameter collection is performed on these connection paths, including path length, width, thickness, and surrounding environment, to obtain the signal adaptation parameters of each path, and the connection path is optimized and adjusted based on the obtained signal adaptation parameters. This may include adjusting the length and shape of the path, changing the signal layer, or adding shielding to improve signal quality.

[0047] It can be understood that by optimizing the signal path, the loss and delay of the signal during transmission can be significantly reduced. Precise path adjustment helps to reduce signal interference and crosstalk, thereby improving signal integrity and stability, and overall improving the electrical performance of the packaged object, supporting higher data transmission rates and more reliable communications.

[0048] More specifically, define the power supply path between the power supply and the object to be packaged and its target chip, collect parameters of the power supply path, including resistance, inductance, capacitance and other parameters, to obtain power supply performance parameters, and optimize the layout position of the power supply based on the power supply performance parameters. This may include adjusting the power supply position, improving the design of the power supply network or adding decoupling capacitors to ensure the stability and uniformity of the power supply.

[0049] It is understandable that optimizing the power supply path and power supply layout helps to improve the power supply quality, reduce voltage drop and power supply noise. A stable and efficient power supply system is essential to ensure the stable operation of the target chip and the entire packaged object. A good power supply design is the basis for achieving higher computing performance and lower energy consumption goals, especially for power-sensitive application scenarios.

[0050] Preferably, the packaging design directions corresponding to the heat dissipation performance indicators include: Structural design direction, material design direction, and thermal simulation design direction; the structural design direction includes: adding a heat dissipation structure to the packaging design of the object to be packaged; wherein the heat dissipation structure includes a heat sink and a heat dissipation channel; the material design direction includes: using a packaging material whose thermal conductivity meets the preset standard to perform packaging design on the object to be packaged; the thermal simulation design direction includes: through thermal simulation analysis, predicting the temperature distribution of each target chip of the object to be packaged under different load conditions, obtaining the heat concentration area, evaluating the heat dissipation effect of the packaging design of the object to be packaged according to the heat concentration area, and optimizing the packaging design of the object to be packaged according to the results of the heat dissipation effect evaluation.

[0051] Specifically, heat dissipation structures such as heat sinks and heat dissipation channels are introduced into the packaging design. According to the specific shape and size of the object to be packaged, a reasonable layout of the heat sink and heat dissipation channels is designed to maximize the heat dissipation efficiency.

[0052] It can be understood that the heat dissipation capacity of the packaged object is effectively enhanced, which helps to quickly conduct heat away from the heat source, ensuring that the object to be packaged can be maintained within a safe temperature range under various working conditions, preventing overheating from causing performance degradation or damage.

[0053] More specifically, select packaging materials with high thermal conductivity, such as metals, ceramics or special composite materials with high thermal conductivity, and evaluate whether the thermal conductivity of the selected materials meets the preset heat dissipation standards.

[0054] It can be understood that by using materials with high thermal conductivity, heat can be transferred from the heat source to the heat dissipation structure more effectively, which helps the thermal management of the entire packaging system and ensures long-term stable operation.

[0055] More specifically, thermal simulation software is used to simulate the temperature distribution of the object to be packaged under different load conditions. Based on the simulation results, the hot spot areas where the temperature rises are found, the packaging design is evaluated according to the hot spot areas, and the heat dissipation structure and material usage are optimized accordingly to improve the heat dissipation effect.

[0056] It is understandable that thermal simulation analysis provides accurate temperature distribution data, which helps to scientifically design heat dissipation structures and select materials. By identifying and optimizing hot spots, local overheating can be prevented and product life can be extended. The optimization results of comprehensive structure, materials and simulation analysis can achieve more efficient heat dissipation solutions to adapt to more stringent working conditions.

[0057] Preferably, the information of the object to be encapsulated is substituted into the design guidance framework so that the design guidance framework performs encapsulation design on the object to be encapsulated, and the step of obtaining the encapsulation solution of the object to be encapsulated includes: S31: Substituting the information of the object to be packaged into the design guidance framework, performing packaging design on the object to be packaged according to the design guidance framework through a pre-trained packaging design intelligent model, and obtaining several pre-selected solutions for the object to be packaged; S32: Prioritize and analyze the pre-selected solutions for the object to be encapsulated, obtain priority parameters for the pre-selected solutions, and use the pre-selected solution with the highest priority parameter as the encapsulation solution for the object to be encapsulated.

[0058] Preferably, the training step of the packaging design intelligent model includes: S311: Collecting a data set for training; wherein the data set includes several sets of training data, the training data includes design conditions and design products, the design conditions are the object to be packaged and each of the packaging design indicators corresponding to the object to be packaged, and the design product is the packaging solution corresponding to the object to be packaged; S312: Structuring the collected data set into a package design topology structure; wherein the package design topology structure has conditional topology nodes and finished product topology nodes, the conditional topology nodes are used to feedback the design conditions, and the finished product topology nodes are used to feedback the design finished product; S313: Based on a preset topological structure theory, determine the topological tendency parameters of each of the conditional topological nodes and the finished product topological nodes from the package design topological structure; wherein the topological tendency parameters of the conditional topological nodes and the finished product topological nodes are used to represent the mutual influence and connection between each of the conditional topological nodes and the finished product topological nodes; S314: performing parameter optimization extraction processing on the topological tendency parameters of each of the conditional topological nodes and the finished topological nodes, so as to select each of the conditional topological nodes and the finished topological nodes whose topological tendency parameters meet the optimization criteria as the preferred training combination; S315: Extract preferred features from each of the preferred training combinations to obtain the preferred features of the preferred training combinations, simulate and generate a packaging design solution based on the preferred features, and select a preferred training combination from the simulated packaging design solution and the existing preferred training combination to perform a further round of preferred feature extraction, repeat the optimization process for several times, perform deep learning training on the initial packaging design intelligent model based on the preferred training combination of the optimization process, and obtain a trained packaging design intelligent model.

[0059] Specifically, a data set containing design conditions and finished designs is collected, where the design conditions cover the objects to be packaged and their related packaging design indicators, and the finished designs are the corresponding packaging solutions. In this way, a comprehensive data foundation is constructed, enabling the model to learn the actual effects of packaging solutions under different design conditions, providing support for subsequent intelligent recommendations.

[0060] More specifically, the collected data sets are structured according to certain logic to form a packaged design topology structure containing conditional topology nodes and finished product topology nodes. Through this structured processing, the internal connections and mutual influences of the data can be clearly expressed, providing a good foundation for subsequent in-depth analysis and learning.

[0061] More specifically, based on the preset topological structure theory, the mutual influence and connection between the conditional topological nodes and the finished product topological nodes are analyzed, and the topological tendency parameters representing these connections are extracted, so that the model can understand the relationship between different design conditions and packaging solutions, providing a theoretical basis for making optimization suggestions.

[0062] More specifically, parameters that meet the optimization criteria are screened out from the extracted topological tendency parameters to determine the optimal training combination, which simplifies and optimizes the training data set, making model training more efficient and targeted.

[0063] More specifically, key features are extracted based on the preferred training combination, and these features are used to simulate and generate packaging design solutions. Through continuous iterative optimization, more effective design feature combinations are refined. The model can discover more effective packaging design solutions through iterative learning, while continuously optimizing and updating the training data set to improve training efficiency and accuracy.

[0064] More specifically, the preferred training combination obtained after multiple rounds of optimization processing is used for deep learning training of the initial packaging design intelligent model, and finally the trained model is obtained. Through deep learning training, the model can accurately predict the optimal packaging solution under specific design conditions, effectively improving the energy efficiency performance of chip stacking packaging.

[0065] Reference Figure 2 As shown, in a second aspect, the present invention provides an energy efficiency optimization device based on chip stacking packaging, comprising: An information acquisition module, used to acquire information of an object to be packaged; wherein the object to be packaged includes a plurality of target chips; A scheme construction module is used to obtain several packaging design indicators of the object to be packaged, and perform mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators; wherein the design guidance framework is used to describe the scheme idea for packaging design of the object to be packaged; The solution analysis module is used to substitute the information of the object to be packaged into the design guidance framework, so that the design guidance framework performs packaging design on the object to be packaged and obtains a packaging solution for the object to be packaged.

[0066] In this embodiment, for the specific implementation of each module in the above-mentioned device embodiment, please refer to the above-mentioned method embodiment, which will not be described in detail here.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An energy efficiency optimization method based on chip stacking packaging, characterized in that: include: Acquire information of an object to be packaged; wherein the object to be packaged includes a plurality of target chips; Acquire several packaging design indicators of the object to be packaged, and perform mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators; wherein the design guidance framework is used to describe the solution idea for packaging design of the object to be packaged; The information of the object to be packaged is substituted into the design guide framework, so that the design guide framework performs packaging design on the object to be packaged, and obtains a packaging solution for the object to be packaged.

2. The energy efficiency optimization method based on chip stacking packaging according to claim 1, characterized in that: The steps of obtaining a plurality of packaging design indicators of the object to be packaged, and performing mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators include: Acquire several packaging design indicators of the object to be packaged; wherein the packaging design indicators include packaging size indicators, signal performance indicators, and heat dissipation performance indicators; Analyze and process each of the package design indicators to obtain a package design direction corresponding to each of the package design indicators; wherein the package design direction is used to describe a design direction for achieving the package design indicator; An intersection analysis is performed on the package design directions of each package design indicator to eliminate incompatible parts of the package design directions of each package design indicator, to obtain the intersection part of the package design directions of each package design indicator, and to use the intersection part as the design guidance framework.

3. The energy efficiency optimization method based on chip stacking packaging according to claim 2, characterized in that: The steps of analyzing and processing the respective packaging design indicators to obtain the packaging design directions corresponding to the respective packaging design indicators include: Analyze and process the package size index to obtain a package design direction corresponding to the package size index; wherein the package size index is to reduce the package size of the object to be packaged; Analyze and process the signal performance index to obtain a packaging design direction corresponding to the signal performance index; wherein the signal performance index is to improve the signal performance of the object to be packaged after packaging; Analyze and process the heat dissipation performance index to obtain a packaging design direction corresponding to the heat dissipation performance index; wherein the heat dissipation performance index is to improve the heat dissipation performance of the object to be packaged after packaging.

4. The energy efficiency optimization method based on chip stacking packaging according to claim 3, characterized in that: The package design directions corresponding to the package size indicators include: Primary and secondary design directions and stacking design directions; The primary and secondary design directions include: dividing the target chips of the object to be packaged into a primary chip and a plurality of secondary chips, arranging the primary chip at the most central position, and arranging the secondary chips around the primary chip; wherein the distance between each secondary chip and the primary chip is between 2.0 and 3.0 mm; The stacking design direction includes: stacking the secondary chip with the smallest size on the primary chip for arrangement.

5. The energy efficiency optimization method based on chip stacking packaging according to claim 3, characterized in that: The packaging design directions corresponding to the signal performance indicators include: Routing layout design direction and power supply layout design direction; The routing layout design direction includes: constructing a connection path on each target chip of the object to be packaged, performing parameter acquisition processing on each connection path, obtaining a signal adaptation parameter of each connection path, and adjusting each connection path according to the signal adaptation parameter of each connection path; wherein the signal adaptation parameter is used to describe the influence of the connection path on the signal quality of the object to be packaged after the packaging design; The power layout design direction includes: constructing a power supply path between the power supply and each of the target chips of the object to be packaged, performing parameter collection and processing on each of the power supply paths to obtain power supply performance parameters of each of the power supply paths, and adjusting the setting position of the power supply according to the power supply performance parameters of each of the power supply paths; wherein the power supply performance parameters are used to describe the degree of influence of the power supply path on the power supply quality.

6. The energy efficiency optimization method based on chip stacking packaging according to claim 3, characterized in that: The packaging design directions corresponding to the heat dissipation performance indicators include: Structural design direction, material design direction, thermal simulation design direction; The structural design direction includes: adding a heat dissipation structure to the packaging design of the object to be packaged; wherein the heat dissipation structure includes a heat sink and a heat dissipation channel; The material design direction includes: using a packaging material with thermal conductivity that meets a preset standard to perform packaging design on the object to be packaged; The thermal simulation design direction includes: predicting the temperature distribution of each target chip of the object to be packaged under different load conditions through thermal simulation analysis to obtain the heat concentration area, evaluating the heat dissipation effect of the packaging design of the object to be packaged according to the heat concentration area, and optimizing the packaging design of the object to be packaged according to the result of the heat dissipation effect evaluation.

7. The energy efficiency optimization method based on chip stacking packaging according to claim 3, characterized in that: Substituting the information of the object to be packaged into the design guide framework so that the design guide framework performs package design on the object to be packaged, the step of obtaining the package solution of the object to be packaged includes: Substituting the information of the object to be packaged into the design guidance framework, performing packaging design on the object to be packaged according to the design guidance framework through a pre-trained packaging design intelligent model, and obtaining several pre-selected solutions for the object to be packaged; Priority analysis is performed on each of the pre-selected solutions for the object to be encapsulated to obtain priority parameters of each of the pre-selected solutions, and the pre-selected solution with the highest priority parameter is used as the encapsulation solution for the object to be encapsulated.

8. The energy efficiency optimization method based on chip stacking packaging according to claim 7, characterized in that: The training steps of the package design intelligent model include: Collecting a data set for training; wherein the data set includes several sets of training data, the training data includes design conditions and design products, the design conditions are the object to be packaged and each of the packaging design indicators corresponding to the object to be packaged, and the design product is the packaging solution corresponding to the object to be packaged; Structuring the collected data set into a package design topology structure; wherein the package design topology structure has conditional topology nodes and finished product topology nodes, the conditional topology nodes are used to feedback the design conditions, and the finished product topology nodes are used to feedback the design finished product; Based on a preset topological structure theory, topological tendency parameters of each of the conditional topological nodes and the finished product topological nodes are determined from the package design topological structure; wherein the topological tendency parameters of the conditional topological nodes and the finished product topological nodes are used to represent the mutual influence and connection between each of the conditional topological nodes and the finished product topological nodes; Performing parameter optimization extraction processing on the topological tendency parameters of each of the conditional topological nodes and the finished topological nodes, so as to select each of the conditional topological nodes and the finished topological nodes whose topological tendency parameters meet the optimization criteria as the preferred training combination; Extract preferred features from each of the preferred training combinations to obtain the preferred features of the preferred training combinations, simulate and generate packaging design solutions based on the preferred features, and select preferred training combinations from the simulated packaging design solutions and the existing preferred training combinations to perform a further round of preferred feature extraction, repeat the optimization process for several times, perform deep learning training on the initial packaging design intelligent model based on the optimized preferred training combinations to obtain a trained packaging design intelligent model.

9. An energy efficiency optimization device based on chip stacking packaging, characterized in that: include: An information acquisition module, used to acquire information of an object to be packaged; wherein the object to be packaged includes a plurality of target chips; A scheme construction module is used to obtain several packaging design indicators of the object to be packaged, and perform mapping constraint processing between each of the packaging design indicators to obtain a design guidance framework corresponding to each of the packaging design indicators; wherein the design guidance framework is used to describe the scheme idea for packaging design of the object to be packaged; The solution analysis module is used to substitute the information of the object to be packaged into the design guidance framework, so that the design guidance framework performs packaging design on the object to be packaged and obtains a packaging solution for the object to be packaged.

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