Global wiring method for reusing substrate mask plate of core particle system

Abstract

The invention provides a global wiring method for substrate mask multiplexing of a core particle system, comprising: acquiring wiring parameters and netlist information of each layer of a substrate, the netlist information comprising respective associated ports of a plurality of nets; dividing each layer into a plurality of grid nodes to obtain a grid chart of each layer; mapping the associated port of each line network of each layer into the grid diagram of the corresponding layer, and constructing a minimum tree of each line network of each layer according to the mapping result and the connection relationship of the associated port, including grid nodes and connection edges to which the associated port belongs; based on the minimum tree, constructing a wiring directed acyclic graph of each line network of each layer on each layer of grid graph, including alternative paths constructed according to the minimum tree of the line network; according to the wiring parameters and a dynamic planning algorithm constructed based on a plurality of indexes, a wiring path is searched from the wiring directed acyclic graph of each wire net of each layer, a global wiring result is obtained, and the indexes comprise the distance of the reusing area of the mask plate, the wiring length and the number of via holes.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics engineering and integrated circuit design, in particular to the field of substrate wiring, and more particularly to a global wiring method for substrate mask multiplexing of a core particle system. Background Art

[0002] As semiconductor technology continues to evolve, chiplet technology is developing rapidly as a new design paradigm. As the number and size of chiplets in a chiplet system continue to increase, the complexity of silicon substrate wiring has increased dramatically, and manual wiring is no longer feasible.

[0003] Traditional wiring methods are incapable of coping with complex multi-layer interconnect structures, which can easily lead to wiring congestion, increased signal delays, and increased manufacturing costs. In particular, in the integrated circuit manufacturing process, the mask is the key to determining the chip pattern, but its production cost is high, especially for multi-layer wiring structures. Each design modification or addition of a mask will significantly increase the cost.

[0004] Therefore, existing silicon substrates or substrates made of other materials have the problem of a sharp increase in wiring complexity, which leads to a sharp increase in manufacturing costs. In particular, the cost is even higher when modifying or adding a mask.

[0005] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0006] Therefore, the object of the present invention is to overcome the defects of the prior art and provide a global wiring method for substrate mask multiplexing of a chip system.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] According to a first aspect of the present invention, a global wiring method for a core particle system is provided, comprising: S1, obtaining layout information of a substrate, which includes multiple wiring layers, wiring parameters of each layer and netlist information of each layer, wherein the netlist information includes multiple associated ports to be connected to each of the multiple wire nets; S2, dividing the wiring range of each layer of the substrate into multiple grid nodes to obtain a grid map of each layer; S3, mapping the associated ports of each wire net of the netlist information of each layer to the grid map of the corresponding layer, and constructing a minimum tree of each wire net of each layer according to the mapping results of the associated ports of each wire net of each layer and the connection relationship between the multiple associated ports, wherein the minimum tree of each wire net of each layer includes the minimum tree of the wire net of each layer; The grid nodes to which each associated port of the wire net belongs and the connecting edges between multiple grid nodes; S4, based on the minimum tree of each wire net of each layer, construct a wiring directed acyclic graph of each wire net of each layer on the grid graph of each layer, and the wiring directed acyclic graph of each wire net of each layer includes alternative paths constructed according to the connection relationship between multiple grid nodes in the minimum tree of the wire net; S5, according to the wiring parameters of each layer and a dynamic programming algorithm constructed based on multiple wiring optimization indicators, search for wiring paths from all alternative paths in the wiring directed acyclic graph of each wire net of each layer to obtain a global wiring result, and the multiple wiring optimization indicators include the distance of the mask reuse area, the wiring length and the number of vias.

[0009] In some embodiments of the present invention, S3 includes constructing a minimum tree for each net of each layer in the following manner: mapping the associated ports of each net of the netlist information of each layer to the grid map of the layer to obtain a mapping result of the associated ports, which is the grid node to which the associated ports belong in the grid map of the layer; constructing an initial tree for each net according to the mapping results and connection relationship of multiple associated ports of the net, including the grid nodes to which the multiple associated ports belong and the connecting edges between the grid nodes; introducing Steiner points using the minimum Steiner tree generation algorithm, processing the initial tree corresponding to the net with more than two associated ports, and generating the minimum Steiner tree of the net, which includes the connecting edges between the grid nodes and the connecting edges between the grid nodes and the Steiner points; using the initial tree corresponding to the net with two associated ports as the minimum tree of the net, and using the minimum Steiner tree corresponding to the net with more than two associated ports as the minimum tree of the net.

[0010] In some embodiments of the present invention, in S5, the dynamic programming algorithm includes: searching for routing paths from all alternative paths in the routing directed acyclic graph of each wire net of each layer according to the routing parameters of each layer, with the weighted sum of minimizing the distance of the mask reuse area, the routing length and the number of vias as the optimization goal.

[0011] In some embodiments of the present invention, the wiring parameters of each layer include preset wiring capacities of each grid node in the grid graph of the layer. In S5, the method of searching for wiring paths further includes: calculating the actual wiring capacity of each grid node in the grid graph of each layer using a congestion detection algorithm based on the global wiring results obtained by searching using a dynamic programming algorithm, and judging whether each grid node is congested based on the actual wiring capacity of each grid node in the grid graph of each layer and the size of the preset wiring capacity; for congested grid nodes in the grid graph of each layer, updating the wiring directed acyclic graph of the wire network passing through the congested grid nodes according to preset rules to obtain an updated wiring directed acyclic graph; and searching for a new wiring path for the corresponding wire network from the updated wiring directed acyclic graph based on the dynamic programming algorithm.

[0012] In some embodiments of the present invention, the preset rules include: determining all neighboring mesh nodes of the congested mesh node based on the mesh graph, adding non-congested mesh nodes among all neighboring mesh nodes to an optional node set, and selecting a node from the optional node set; reconstructing a minimum tree based on the selected node and all nodes in the wired directed acyclic graph, or replacing the congested mesh node in the wired directed acyclic graph with the selected node, and reconstructing a minimum tree based on the selected node and the nodes that have not been replaced in the wired directed acyclic graph; reconstructing the wired directed acyclic graph of the corresponding wire network based on the reconstructed minimum tree to obtain an updated wired directed acyclic graph.

[0013] In some embodiments of the present invention, the method of calculating the actual wiring capacity of each grid node in the grid graph of each layer includes: taking a weighted sum of the number of wirings of each grid node in the grid graph of the layer and the number of vias passing through the grid node to obtain the actual wiring capacity.

[0014] In some embodiments of the present invention, in S5, the method of searching for wiring paths also includes: using an A* algorithm according to the grid nodes to which the multiple associated ports of each wire net respectively belong, with the optimization goal of minimizing the wiring path length and the distance of the mask reuse area, searching for a wiring path for connecting the multiple associated ports from the updated wiring directed acyclic graph of the wire net.

[0015] According to a second aspect of the present invention, a global wiring system for implementing the method of the first aspect of the present invention is provided, comprising: a data acquisition module, for acquiring layout information of a substrate, which includes multiple wiring layers, wiring parameters of each layer and netlist information of each layer, wherein the netlist information includes multiple associated ports to be connected to each of the multiple wire nets; a data preprocessing module, for dividing the wiring range of each layer of the substrate into multiple grid nodes, obtaining a grid map of each layer, and mapping the associated ports of each wire net of the netlist information of each layer to the grid map of the corresponding layer, and constructing a minimum tree of each wire net of each layer according to the mapping results of the associated ports of each wire net of each layer and the connection relationship between the multiple associated ports, wherein the minimum tree of each wire net of each layer includes each associated port of the wire net. a grid node to which a port belongs and a connection edge between multiple grid nodes; a global routing module, for constructing a routing directed acyclic graph of each wire net of each layer on the grid graph of each layer based on the minimum tree of each wire net of each layer, the routing directed acyclic graph of each wire net of each layer including an alternative path constructed according to the connection relationship between multiple grid nodes in the minimum tree of the wire net; and searching for routing paths from all the alternative paths in the routing directed acyclic graph of each wire net of each layer according to the routing parameters of each layer and a dynamic programming algorithm constructed based on multiple routing optimization indicators to obtain a global routing result, the multiple routing optimization indicators including the distance of the mask reuse area, the routing length and the number of vias; a result output module, for outputting the global routing result, including the routing paths of each wire net of each layer.

[0016] According to a third aspect of the present invention, there is provided an electronic device comprising: one or more processors; and a memory, wherein the memory is used to store executable instructions; the one or more processors are configured to implement the steps of the method of the first aspect of the present invention by executing the executable instructions.

[0017] Compared with the prior art, the advantages of the present invention are:

[0018] First, after obtaining the layout information of the substrate, the present invention abstracts the wiring area range of each layer of the substrate into a gridded grid map, which can quickly form the architectural foundation for precise layout and wiring. Secondly, a minimum tree is constructed for each wire network, so that all associated ports in the wire network are connected with the shortest wire length, providing clear path selection and planning for subsequent wiring planning, greatly simplifying the optimization of subsequent wiring paths. Finally, a wiring directed acyclic graph is established for the wire network based on the minimum tree of the wire network, and a dynamic programming algorithm is used to search for the optimal wiring path among all alternative paths of the wiring directed acyclic graph. The algorithm of the present invention not only focuses on optimizing the wire length and the number of vias, but also places special emphasis on optimizing the distance of the mask reuse area (that is, the possibility of mask reuse), and gives priority to those wiring paths that can effectively promote mask reuse, so that the present invention not only optimizes the wiring efficiency and quality, but also significantly reduces the mask cost in the substrate manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a global routing method for a core particle system according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of the structure of a minimum tree corresponding to a network with more than two associated ports according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of a wiring directed acyclic graph of a wire network constructed according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a global wiring method process according to an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of a global wiring result of a substrate obtained by using a global wiring method according to an embodiment of the present invention;

[0025] Figure 6 Schematic diagram of a mask reuse area in a global routing result according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] As mentioned in the background technology section, existing silicon substrates or substrates made of other materials have the problem of sharply increasing wiring complexity, which leads to a sharp increase in manufacturing costs. In particular, the cost is even higher when modifying or adding a mask.

[0028] In response to the above problems, the inventors proposed a global wiring method for substrate mask reuse in a core particle system. First, after obtaining the layout information of the substrate, the method abstracts the wiring area range of each layer of the substrate into a gridded grid map, which includes a number of divided grid nodes, and abstractly maps the ports and connection relationships of each wire net of each layer of the substrate to the grid nodes in the grid map of the corresponding layer, so as to quickly form the architectural basis for precise layout and wiring. Secondly, a minimum tree is constructed for each wire net based on the ports and connection relationships of each wire net of each layer, so that all associated ports in the wire net are connected with the shortest line length, providing clear path selection and planning for subsequent wiring planning, and greatly simplifying the optimization of subsequent wiring paths. Finally, a wiring directed acyclic graph is established for the wire network according to the minimum tree of the wire network, which includes multiple alternative paths, and a dynamic programming algorithm is used to search for the optimal wiring path among all the alternative paths of the wiring directed acyclic graph by optimizing the wiring line length, the number of vias and the distance of the mask reuse area, which are related wiring optimization indicators. Therefore, the present invention not only focuses on the efficiency of wiring, such as optimizing the line length and the number of vias, but also emphasizes optimizing the distance of the mask reuse area (that is, the possibility of mask reuse). The distance of the mask reuse area is used as an indicator to measure the effectiveness of wiring optimization, and can identify and give priority to wiring paths that can effectively promote the probability of mask reuse, so as to promote the same path to appear in more areas of the mask and increase the chance of mask reuse as much as possible. Compared with traditional wiring algorithms, the method of the present invention has incomparable advantages. It not only optimizes the wiring efficiency and quality, but also reduces the mask cost in the substrate manufacturing process.

[0029] Before specifically introducing the embodiments of the present invention, some of the terms used therein are explained as follows:

[0030] Mask Reticle: It is a graphic master used in the photolithography process. It is composed of an opaque light-shielding film on a transparent substrate to form a mask pattern structure. The mask pattern structure information is transferred to the substrate through the exposure process.

[0031] Distance of the mask reuse area: refers to the distance between two or more adjacent areas that can be reused on the mask. This distance is crucial to ensure the correct transfer of the mask pattern during the lithography process, and also affects the efficiency of the mask and the number of exposures of the lithography machine.

[0032] According to one embodiment of the present invention, see Figure 1 , which is a flow chart of a global wiring method for a core particle system. The global wiring method includes steps S1, S2, S3, S4 and S5. In order to better understand the present invention, each step is described in detail below in conjunction with specific embodiments.

[0033] In step S1, layout information of the substrate is obtained, which includes multiple wiring layers, wiring parameters of each layer and netlist information of each layer, and the netlist information includes multiple associated ports that each wire net in the multiple wire nets needs to be connected.

[0034] According to an embodiment of the present invention, the core particle system of the present invention uses a silicon substrate or a substrate of other materials, and the substrate includes multiple metal layers, each metal layer is used as a wiring layer, and multiple wiring layers are formed. Among them, by wiring on each metal layer, global wiring of the substrate is realized.

[0035] According to an embodiment of the present invention, the wiring parameters of each layer include wiring rules, metal layer definition, line width, spacing and wiring capacity. Among them, for integrated circuits, the wiring rules designed in general are: all wires in the same wiring layer only go in the same direction, that is, horizontal or vertical, and the wiring directions of adjacent metal layers are perpendicular to each other. Definition of metal layer: means that each metal layer can only specify one wiring direction, such as only horizontal or only vertical. Line width: the width of the wire in the integrated circuit wiring, usually according to the manufacturer's constraints, has a minimum limit value. Spacing: the distance between different wires in the integrated circuit wiring, usually according to the manufacturer's constraints, has a minimum limit value. Wiring capacity: the maximum number of wires that can pass through (or route) within the wiring area, wherein a preset wiring capacity is set for each unit wiring area within the wiring area, and the preset wiring capacity indicates the maximum number of wires that can pass through (via) and / or route in the corresponding unit wiring area. The present invention takes a single grid node in the grid map as a unit wiring area, therefore, the wiring parameters of each layer in the present invention also include the preset wiring capacity of each grid node in the grid map of the layer, and the preset wiring capacity is positively correlated with the size of the grid node in the grid map.

[0036] According to an embodiment of the present invention, the netlist information of each layer records the respective positions of all non-movable ports (fixed ports) of the layer and the associated ports to be connected to each of the multiple nets, and the associated ports are non-movable ports. Each net is used to indicate that multiple associated ports related to the net need to be connected by wires in a real physical scenario so that all associated ports of the net are electrically connected to each other.

[0037] In step S2, the wiring range of each layer of the substrate is divided into a plurality of grid nodes to obtain a grid map of each layer.

[0038] According to one embodiment of the present invention, in the process of constructing the grid map of each layer of the substrate, the entire wiring range of each layer of the substrate is divided into a plurality of grids according to a preset grid size to form a grid map of each layer. In the grid map of each layer, each grid is used as a grid node, and a single grid node is used to represent a wiring sub-area of ​​the layer of the substrate.

[0039] According to one embodiment of the present invention, when dividing the wiring range according to the preset grid size, a grid subdivision strategy can be introduced, which dynamically adjusts the division size of the grid node by real-time analyzing the wiring density of the wiring area during the design of the substrate. The area with higher wiring density is usually the concentrated area of ​​wiring conflicts and design bottlenecks. For these special areas, the system locally applies a higher resolution grid to accurately control the wiring density and ensure that each step of the layout in the high-density wiring area can be refined. Among them, the grid subdivision strategy includes: setting the preset grid size according to the wiring density within the wiring range of the substrate, wherein the preset grid size is negatively correlated with the wiring density within the wiring range of the substrate. If each layer is evenly divided into grids with a preset grid size, when the wiring density of the corresponding wiring layer is identified to be small, the corresponding preset grid size is set to be larger; conversely, when the wiring density of the corresponding wiring layer is identified to be large, the corresponding preset grid size is set to be smaller, so as to be divided into a higher resolution grid, thereby ensuring that the area corresponding to the grid node is finely wired. If each layer can be divided according to different grid sizes, the denser areas of the same layer are divided with smaller grid sizes, and vice versa. The technical solution of this embodiment can at least achieve the following beneficial technical effects: this dynamic adjustment mechanism maintains a balanced strategy between the accuracy of layout and routing and the computational overhead, which can not only reduce the excessive computational overhead caused by over-segmentation in routing design, but also avoid sacrificing routing accuracy due to over-coarse grids, and effectively reduce the risk of routing conflicts, thereby improving the feasibility and reliability of the overall routing solution.

[0040] In step S3, the associated ports of each wire net in the netlist information of each layer are mapped to the grid diagram of the corresponding layer, and based on the mapping results of the associated ports of each wire net in each layer and the connection relationship between multiple associated ports, the minimum tree of each wire net in each layer is constructed. The minimum tree of each wire net in each layer includes the grid nodes to which each associated port of the wire net belongs and the connecting edges between multiple grid nodes.

[0041] According to one embodiment of the present invention, step S3 includes the following steps S31, S32, S33 and S34:

[0042] Step S31: Mapping the associated ports of each net in the netlist information of each layer to the grid map of the layer to obtain a mapping result of the associated ports, which is the grid node to which the associated ports belong in the grid map of the layer.

[0043] According to one embodiment of the present invention, a mapping method for mapping the associated ports of each wire network to the grid map of the layer includes: based on the position of the associated port of the wire network, where the position of the associated port is expressed in the form of coordinates, dividing the coordinates by the size selected during grid division in step S2 to obtain a calculation result, and rounding the calculation result down to obtain the position of the associated port of the wire network mapped in the grid map, and the grid node to which the associated port belongs in the grid map is the grid node corresponding to the position.

[0044] Step S32: constructing an initial tree of each network according to the mapping results and connection relationships of the multiple associated ports of the network, including the grid nodes to which the multiple associated ports belong and the connection edges between the grid nodes.

[0045] According to one embodiment of the present invention, if there are only two associated ports to be connected in the wire network, and they are respectively mapped to the grid nodes V1 and V3 in the corresponding grid map, then the grid nodes V1 and V3 are directly connected to obtain a connection edge to form the initial tree of the wire network. If there are three or more associated ports to be connected in the wire network, all the grid nodes to which the associated ports belong are connected in sequence to form an initial tree. Schematically, there are three associated ports to be connected in the wire network, and they are respectively mapped to the grid nodes V2, V3 and V5 in the corresponding grid map, then the grid nodes V2 and V3 are connected, and the grid nodes V3 and V5 are connected to obtain two connection edges. The grid nodes V2 and V5 are both connected to V3 to realize the connection between V2 and V5, forming the initial tree of the wire network.

[0046] Step S33: using the Steiner Minimal Tree (SMT) generation algorithm to introduce Steiner points (called Steiner points), processing the initial tree corresponding to the line network with more than two associated ports, and generating the minimum Steiner tree of the line network, which includes the connection edges between the grid nodes and the connection edges between the grid nodes and the Steiner points.

[0047] According to one embodiment of the present invention, a minimum Steiner tree generation algorithm can generate a tree structure for a number of associated ports in a wire network and the connection relationship between the associated ports. For a wire network with three or more associated ports, an SMT generation algorithm such as the FLUTE algorithm can be used to disassemble the initial tree of the wire network to generate the minimum Steiner tree of the wire network. The disassembly process includes: adding a Steiner point to the structure of the original initial tree, and reducing the cost (also known as the line length) of the connection edge of the original initial tree structure without changing the structure of the initial tree, so as to generate the minimum Steiner tree of the wire network. Finally, all the connection edges in the minimum Steiner tree are in the form of two-to-two connections, which may be two-to-two connections between two grid nodes to which two associated ports belong, or two-to-two connections between a grid node to which an associated port belongs and a Steiner point. In the present invention, the Steiner point is regarded as a grid node to which an optional port generated when the wire network is wired. During routing, the associated ports in each wire net in the relative netlist information that are considered immovable are considered as movable ports, and in a real physical scenario, the generated optional ports can be set by punching holes on the substrate board to achieve routing. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the initial tree of the wire net corresponding to more than three associated ports is disassembled to generate a minimum Steiner tree, thereby achieving routing with the shortest path and reducing overhead.

[0048] Step S34: taking the initial tree corresponding to the network with two associated ports as the minimum tree of the network, and taking the minimum Steiner tree corresponding to the network with more than two associated ports as the minimum tree of the network.

[0049] According to one embodiment of the present invention, for the minimum tree corresponding to a wire mesh with two associated ports, it has only one connection edge of the two associated ports, and the initial tree in which the two associated ports are directly connected is the minimum tree. For a wire mesh with more than two associated ports, the complexity of the ports and the paths between the ports will increase significantly, and it is not conducive to the implementation of the algorithm. Therefore, the present invention uses the minimum Steiner tree corresponding to a wire mesh with more than two associated ports as the minimum tree of the wire mesh. Subsequently, based on each connection edge in the minimum Steiner tree, an alternative path for connection can be constructed for the two nodes connected to it, which can realize the conversion of complex multi-port connection problems into multiple dual-port connection problems that are easier to handle, greatly simplifying the subsequent selection and optimization of wiring paths, and improving the efficiency of the wiring method.

[0050] Indicatively, see Figure 2, which is a schematic diagram of the structure of the minimum tree corresponding to the wire net with more than two associated ports. The figure includes five mesh nodes, namely mesh nodes V1, V2, V3, V4 and V5. In this minimum tree, V1 and V3 are connected in pairs, V2 and V3 are connected in pairs, V4 and V3 are connected in pairs, and V5 and V3 are connected in pairs, forming four connection edges. The wiring costs corresponding to the four connection edges are 1, 4, 2 and 2 respectively.

[0051] In step S4, based on the minimum tree of each wire net of each layer, a wiring directed acyclic graph (DAG) of each wire net of each layer is constructed on the grid graph of each layer, and the wiring directed acyclic graph of each wire net of each layer includes alternative paths constructed according to the connection relationship between multiple grid nodes in the minimum tree of the wire net.

[0052] According to one embodiment of the present invention, based on the connection relationship between each grid node in the minimum tree, an alternative path is constructed between two nodes connected by each edge. Since the wiring path of each layer in the substrate adopts a horizontal or vertical method, the two nodes cannot be connected by an oblique straight line. Therefore, an L-type wiring method can be used when constructing an alternative path between the two nodes. When it is specifically implemented, it includes an L-type or inverted L-type path to form two alternative paths. If the two nodes are in the same horizontal line or the same vertical line, the two nodes can be connected by a straight line to form an alternative path. In the stage of constructing a wiring directed acyclic graph, an efficient graphic wiring algorithm can also be used. The algorithm can quickly construct a wiring directed acyclic graph, such as using an L-type wiring method, a Z-type wiring method, etc. to construct an alternative path between two nodes. These wiring methods can effectively utilize the substrate space and quickly build a basic framework for wiring, which not only greatly shortens the design cycle, but also provides a clear path planning for subsequent wiring, ensuring that the initial forming stage of wiring design is both fast and accurate.

[0053] According to one embodiment of the present invention, see Figure 3 , which is a schematic diagram of the structure of a wire network wiring directed acyclic graph. This diagram is based on Figure 2The wiring directed acyclic graph is constructed based on the connection relationship between the grid nodes of the given minimum tree. When constructing alternative paths between the two nodes of each connecting edge of the minimum tree, since V1 and V3 are on the same vertical line, there is an alternative path ① between V1 and V3, alternative paths ⑥ and ⑦ between V2 and V3, alternative paths ② and ③ between V4 and V3, and alternative paths ④ and ⑤ between V5 and V3. Each node in the wiring directed acyclic graph represents a wiring decision point, such as an associated port, a line segment intersection, etc., and the edges in the acyclic graph symbolize feasible options for the wiring path. All grid nodes except the grid nodes to which the associated ports belong can be used as line segment intersections, indicating that the wire can pass through the grid node. The wire passes through several line segment intersections from an associated port in a certain order and finally connects to another associated port, thus forming a wiring. Figure 3 For example, if you go from V1 to V4, you can connect V1 and V4 through the alternative path ① between V1 and V3 and one of the two alternative paths between V3 and V4 in turn, forming a wiring between V1 and V4, and at this time V3 is used as the intersection point of the line segments.

[0054] In step S5, according to the wiring parameters of each layer and a dynamic programming algorithm constructed based on multiple wiring optimization indicators, a wiring path is searched from all alternative paths in the wiring directed acyclic graph of each wire net of each layer to obtain a global wiring result. The multiple wiring optimization indicators include the distance of the mask reuse area, the wiring length and the number of vias.

[0055] According to one embodiment of the present invention, in step S5, the dynamic programming algorithm includes: searching for wiring paths from all alternative paths in the wiring directed acyclic graph of each wire net of each layer with the wiring parameters of each layer being based on minimizing the weighted sum of the distance, wiring length and number of vias in the mask reuse area as the optimization target. The distance of the mask reuse area can be calculated using the Euclidean distance metric or the Manhattan distance metric. The smaller the distance of the mask reuse area, the fewer exposure times the photolithography machine needs when using the mask for lithography manufacturing. Therefore, the present invention improves the use efficiency of the mask by minimizing the distance of the mask reuse area, thereby improving the production efficiency in the later stage. At the same time, the weighted sum of the wiring optimization indicators such as the distance, wiring length and number of vias in the mask reuse area is minimized to search for wiring paths, optimize wiring efficiency and reduce manufacturing costs.

[0056] According to one embodiment of the present invention, the global routing result initially obtained by searching using a dynamic programming algorithm includes the routing paths of each wire net of each layer. The global routing result can also be further subjected to real-time congestion detection to identify and mark the current wiring dense congestion area, thereby flexibly adjusting the routing path of the congested area, and replacing the routing path initially obtained using the planning algorithm with the adjusted routing path. The method of adjusting the routing path of the congested area of ​​the present invention includes: removing the routing path of the congested area, and rewiring by moving the position of the movable port in the congested area or expanding the number of ports (removable ports or non-removable ports).

[0057] According to an embodiment of the present invention, in step S5, the method of searching for a wiring path further includes the following steps a1, a2 and a3:

[0058] Step a1: Based on the global routing results obtained by the dynamic programming algorithm, a congestion detection algorithm is used to calculate the actual routing capacity of each grid node in the grid map of each layer, and based on the actual routing capacity of each grid node in the grid map of each layer and the size of the preset routing capacity, it is determined whether each grid node is congested.

[0059] According to one embodiment of the present invention, the congestion detection algorithm includes: calculating the wiring resource information used by each grid node of the grid map based on the preset wiring capacity of each grid node of the grid map and the respective wiring paths of all wire nets, that is, calculating the actual wiring capacity of each grid node in the grid map of each layer; when the actual wiring capacity passing through the grid node is greater than the preset wiring capacity of the node, it indicates that the grid node has overflowed, that is, the grid node is in a congested state; otherwise, the grid node is not congested.

[0060] According to one embodiment of the present invention, the method of calculating the actual wiring capacity of each grid node in the grid diagram of each layer includes: performing weighted summation of the number of wirings of each grid node in the grid diagram of the layer and the number of vias passing through the grid node to obtain the actual wiring capacity. Since vias and wiring (i.e., the routing of this layer) are two forms, there is still a difference in their importance to congestion detection. The present invention can adjust the weights of the number of wirings and the number of vias according to actual conditions. For example, in order to minimize the number of vias, the weight corresponding to the number of vias can be assigned a larger weight and the weight corresponding to the number of wirings can be assigned a smaller weight, thereby determining the actual wiring capacity for congestion detection.

[0061] Step a2: For the congested grid nodes in the grid graph of each layer, the wiring directed acyclic graph of the wire network passing through the congested grid nodes is updated according to a preset rule to obtain an updated wiring directed acyclic graph.

[0062] According to one embodiment of the present invention, a method of updating a wiring directed acyclic graph of a wire network passing through a congested mesh node according to a preset rule includes the following steps a21, a22 and a23:

[0063] Step a21: determining all neighboring mesh nodes of the congested mesh node according to the mesh graph, adding non-congested mesh nodes among all neighboring mesh nodes to a selectable node set, and selecting a node from the selectable node set.

[0064] According to one embodiment of the present invention, in a grid graph, if two grid nodes are located adjacent to each other, it means that the two grid nodes are neighboring grid nodes of each other. Schematically, if all neighboring grid nodes of grid node V1 include V2, V10 and V11, and both V2 and V11 are non-congested grid nodes, then V2 and V11 are added to the optional node set, and a node is randomly selected from the set.

[0065] Step a22: Reconstruct the minimum tree based on the selected node and all nodes in the wired directed acyclic graph, or replace the congested grid node in the wired directed acyclic graph with the selected node, and reconstruct the minimum tree based on the selected node and the unreplaced nodes in the wired directed acyclic graph.

[0066] According to one embodiment of the present invention, the tree is constructed and wired after the number of ports is expanded. The method of reconstructing the minimum tree according to the selected nodes and all nodes in the wired directed acyclic graph includes: using the minimum Steiner tree generation algorithm, according to the selected nodes and all nodes included in the acyclic graph, and introducing Steiner points to generate a minimum Steiner tree, the tree includes the connection edges between the selected nodes and the nodes in the acyclic graph, and the connection edges between the nodes in the acyclic graph and / or the selected nodes and the Steiner points. The selected nodes and the introduced Steiner points are all nodes corresponding to the expanded ports.

[0067] According to one embodiment of the present invention, by moving the position of the movable port in the congested area, the tree is constructed and routed. If the mesh node to which the port (i.e., the movable port) corresponding to the wire network passing through the congested mesh node belongs is the congested mesh node, the minimum tree can be reconstructed in the manner of the above embodiment, or the port can be relocated to the non-congested area, that is, the congested mesh node in the routed directed acyclic graph is replaced with the selected node, and the minimum tree is reconstructed according to the nodes replaced by the nodes that have not been replaced in the routed directed acyclic graph. The construction method includes: using the minimum Steiner tree generation algorithm, according to the selected nodes and the nodes that have not been replaced in the routed directed acyclic graph, and introducing the Steiner point to generate the minimum Steiner tree, the tree includes the connection edges between the selected node and the nodes that have not been replaced in the acyclic graph, and the connection edges between the nodes that have not been replaced in the acyclic graph and / or the selected nodes and the Steiner point. Schematically, if the original wiring directed acyclic graph includes nodes V1, V3, V8, V21 and V31, the mesh node V1 to which the port (i.e., the movable port) corresponding to the wire network belongs is a congested mesh node, and the selected node is V2, then a minimum tree is constructed based on nodes V2, V3, V8, V21 and V31.

[0068] According to an embodiment of the present invention, if the mesh node to which the associated port (i.e., the immovable port) corresponding to the wire mesh passing through the congested mesh node belongs is the congested mesh node, the congested mesh node in the wiring directed acyclic graph corresponding to the wire mesh cannot be replaced with the selected node. In this case, the tree can only be constructed and wired after the number of ports is expanded to ensure that the position of the mesh node to which the associated port belongs is not moved, so as to facilitate the wiring in a real physical scenario.

[0069] Step a23: Reconstruct the wiring directed acyclic graph of the corresponding network according to the reconstructed minimum tree to obtain an updated wiring directed acyclic graph.

[0070] According to an embodiment of the present invention, the wiring directed acyclic graph of the wire network may be reconstructed in the same manner as that of constructing the wiring directed acyclic graph in step S4 of the above embodiment.

[0071] Step a3: Based on the dynamic programming algorithm, search for a new routing path of the corresponding wire net from the updated routing directed acyclic graph.

[0072] According to one embodiment of the present invention, the routing path is searched from all candidate paths in the updated routing directed acyclic graph with the optimization goal of minimizing the weighted sum of the distance of the mask reuse area, the routing length and the number of vias.

[0073] The technical solution of the embodiment of the above steps a1-a3 can at least achieve the following beneficial technical effects: for the identified congested area, a highly flexible wiring removal strategy is adopted, and rewiring is performed by adding ports or migrating movable ports, which not only effectively alleviates the local wiring pressure, but also avoids potential wiring conflicts and ensures smooth wiring. And each time the wire network is wired based on the updated wiring directed acyclic graph, it will calculate how to wire so that the weighted sum of the distance, wiring length and number of vias in the mask reuse area is minimized to achieve optimal wiring efficiency and reduce costs.

[0074] According to one embodiment of the present invention, the method of searching for wiring paths also includes using an A* algorithm to search for wiring paths for connecting multiple associated ports from the updated wiring directed acyclic graph of the wire net according to the grid nodes to which the multiple associated ports of each wire net belong, with the optimization goal of minimizing the wiring path length and the distance to the mask reuse area. The updated wiring directed acyclic graph is obtained through the processing of the above steps a1-a3. The algorithm not only pursues the shortest path or the approximately shortest wiring path, but also comprehensively considers the path length and the distance to the mask reuse area as heuristic information, ensuring that while meeting strict wiring standards, the probability of mask reuse is maximized, further reducing costs, and improving the practicality and rationality of wiring.

[0075] According to one embodiment of the present invention, the A* algorithm will avoid obstacles when searching for a wiring path, that is, it will bypass a congested grid node for wiring, but it will still comply with wiring rules. The wires in the same metal layer will only go in the same direction, that is, horizontally or vertically, and the wiring directions of adjacent metal layers are perpendicular to each other to maintain a 90-degree turn. Therefore, the shape of the wiring may be a maze wiring formed by multiple right-angle wiring. This algorithm is mainly aimed at further re-searching the wiring path with the algorithm when there are still problems such as wiring congestion after congestion detection and rewiring by adding ports or migrating movable ports, and replacing the wiring path obtained in the previous step with the wiring path searched by the A* algorithm.

[0076] According to an embodiment of the present invention, the global routing method of the present invention is now described in general. Figure 4 , which is a schematic diagram of the process principle of the global wiring method, including the following 5 stages:

[0077] 1) Initialization and preprocessing stage

[0078] According to one embodiment of the present invention, after obtaining the layout information of the substrate, the above-mentioned step S2 is used to construct a grid map for each wiring layer, and the associated ports of the wire network are mapped into the grid map, and a minimum tree of the wire network is constructed based on the mapping results and the connection relationship between the associated ports to achieve initialization and preprocessing of the layout information of the substrate.

[0079] 2) Graphic wiring stage

[0080] According to one embodiment of the present invention, a routing directed acyclic graph is constructed based on the minimum tree of the wire net, and the dynamic programming algorithm of the above step S5 is applied to search the routing path of the wire net from the routing directed acyclic graph, and a preliminary global routing result is obtained to achieve preliminary graphic routing.

[0081] 3) Congestion handling and wire removal and rewiring stage

[0082] According to one embodiment of the present invention, based on the preliminary global wiring results, congestion detection is performed on all grid nodes in the manner of the above embodiment, and the grid nodes in congestion are marked. For the identified congested grid nodes, a flexible wiring strategy is adopted, and rewiring is performed by adding ports or migrating movable ports to perform congestion handling and wiring rewiring.

[0083] 4) Maze wiring optimization stage

[0084] According to an embodiment of the present invention, when the wiring result obtained in stage 3 still has problems such as wiring congestion, the A* algorithm is further used to re-search the wiring path, and the wiring path searched by the A* algorithm replaces the wiring path obtained in the previous step. When searching for the path, the A* algorithm avoids obstacles and forms a maze wiring diagram in which the wiring shape may be formed by multiple right-angle routing lines, thereby avoiding congestion and optimizing the wiring path.

[0085] 5) Output results

[0086] According to one embodiment of the present invention, for non-congested areas, the routing path of stage 2) is directly output; for congested areas, the routing path output of stage 3) is used; if the routing path obtained in stage 3) still has many congested areas, the routing path of stage 4) is output.

[0087] Indicatively, see Figure 5 , which is a schematic diagram of the global wiring result of the substrate obtained by using the global wiring method. In the figure, the substrate includes 4 metal layers, which are metal layer 1, metal layer 2, metal layer 3 and metal layer 4 in sequence. Wiring is performed on the 4 metal layers, and the wiring results are as follows Figure 5 As shown in the figure, the outermost box of each layer represents the entire wiring range. The lines inside the box show the wiring results of the metal layer. According to the wiring rules, it can be seen that the lines of layer 1 and layer 3 are horizontal, and the lines of layer 2 and layer 4 are vertical.

[0088] According to one embodiment of the present invention, a global wiring system for implementing the above-mentioned embodiment method is provided, comprising: a data acquisition module, used to acquire layout information of a substrate, which includes multiple wiring layers, wiring parameters of each layer and netlist information of each layer, wherein the netlist information includes multiple associated ports that each wire net in multiple wire nets needs to be connected; a data preprocessing module, used to divide the wiring range of each layer of the substrate into multiple grid nodes, obtain a grid map of each layer, and map the associated ports of each wire net of the netlist information of each layer to the grid map of the corresponding layer, and construct a minimum tree of each wire net of each layer according to the mapping result of the associated ports of each wire net of each layer and the connection relationship between the multiple associated ports, wherein the minimum tree of each wire net of each layer includes each associated port of the wire net The invention relates to a grid node and connection edges between multiple grid nodes; a global routing module, which is used to construct a routing directed acyclic graph of each wire net of each layer on the grid graph of each layer based on the minimum tree of each wire net of each layer, and the routing directed acyclic graph of each wire net of each layer includes alternative paths constructed for the connection relationship between multiple grid nodes in the minimum tree of the wire net; and searching for routing paths from all alternative paths in the routing directed acyclic graph of each wire net of each layer according to the routing parameters of each layer and a dynamic programming algorithm constructed based on multiple routing optimization indicators to obtain global routing results, and the multiple routing optimization indicators include the distance of the mask reuse area, the routing length and the number of vias; a result output module, which is used to output the global routing results, including the routing paths of each wire net of each layer.

[0089] According to one embodiment of the present invention, the data acquisition module is used to execute the process of step S1 of the above embodiment, the data preprocessing module is used to execute the process of step S2 and step S3 of the above embodiment, and the global wiring module is used to execute the process of step S4 and step S5 of the above embodiment. The result output module is used to convert the global wiring result into a readable core global wiring result file for subsequent physical design steps. Since the traditional wiring method is powerless when facing complex multi-layer interconnection structures, it is easy to cause wiring congestion, increased signal delay and increased manufacturing costs. Therefore, the system design of the present invention meets the needs of automation and intelligent optimization. It can automatically handle complex wiring constraints, optimize wiring paths, and consider optimizing indicators such as distance and wiring length of the mask reuse area to achieve fast, low-cost and high-quality wiring.

[0090] Indicatively, see Figure 6, which is a schematic diagram of the mask reuse area in the global wiring result. In the figure, the left and right figures in the figure show different metal layers under the same wiring design, and the red frame and the black frame express the same meaning. Each red frame represents all areas in the entire design that requires wiring that can be used to reuse the mask. The black frame emphasizes that the wiring in the two red frames in its frame has a high similarity, that is, the mask is repeated, which is called a wiring result of mask reuse. It can be seen that the wiring results of the present invention can produce a reuse effect on different metal layers, which can greatly reduce the mask cost in the substrate manufacturing process.

[0091] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0092] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0093] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but are not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0094] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A global routing method for a core particle system, characterized in that: include: S1. Obtaining layout information of a substrate, which includes multiple wiring layers, wiring parameters of each layer, and netlist information of each layer, wherein the netlist information includes multiple associated ports to be connected to each of the multiple wire nets; S2, dividing the wiring range of each layer of the substrate into multiple grid nodes to obtain a grid map of each layer; S3, mapping the associated ports of each wire net of the netlist information of each layer to the grid map of the corresponding layer, and constructing the minimum tree of each wire net of each layer according to the mapping results of the associated ports of each wire net of each layer and the connection relationship between multiple associated ports, wherein the minimum tree of each wire net of each layer includes the grid nodes to which each associated port of the wire net belongs and the connection edges between multiple grid nodes; S4. Based on the minimum tree of each wire net of each layer, a wiring directed acyclic graph of each wire net of each layer is constructed on the grid graph of each layer, wherein the wiring directed acyclic graph of each wire net of each layer includes an alternative path constructed according to the connection relationship between multiple grid nodes in the minimum tree of the wire net; S5. According to the wiring parameters of each layer and a dynamic programming algorithm constructed based on multiple wiring optimization indicators, a wiring path is searched from all alternative paths in the wiring directed acyclic graph of each wire net of each layer to obtain a global wiring result. The multiple wiring optimization indicators include the distance of the mask reuse area, the wiring length and the number of vias.

2. The method according to claim 1, characterized in that The S3 includes constructing the minimum tree of each network of each layer in the following way: Mapping the associated ports of each wire net of the netlist information of each layer to the grid map of the layer, and obtaining a mapping result of the associated ports, which is the grid node to which the associated ports belong in the grid map of the layer; According to the mapping results and connection relationships of the multiple associated ports of the line network, an initial tree of each line network is constructed, including the grid nodes to which the multiple associated ports belong and the connection edges between the grid nodes; The Steiner point is introduced by using the minimum Steiner tree generation algorithm, and the initial tree corresponding to the line network with more than two associated ports is processed to generate the minimum Steiner tree of the line network, which includes the connection edges between grid nodes and the connection edges between grid nodes and Steiner points; The initial tree corresponding to the network with two associated ports is taken as the minimum tree of the network, and the minimum Steiner tree corresponding to the network with more than two associated ports is taken as the minimum tree of the network.

3. The method according to claim 1, characterized in that In S5, the dynamic programming algorithm includes: According to the wiring parameters of each layer, the weighted sum of the distance of the mask reuse area, the wiring length and the number of vias is minimized as the optimization goal, and the wiring path is searched from all alternative paths in the wiring directed acyclic graph of each wire net of each layer.

4. The method according to claim 1, characterized in that The wiring parameters of each layer include the preset wiring capacity of each grid node in the grid diagram of the layer. In S5, the method of searching the wiring path also includes: According to the global routing results obtained by the dynamic programming algorithm, the congestion detection algorithm is used to calculate the actual routing capacity of each grid node in the grid map of each layer, and according to the actual routing capacity of each grid node in the grid map of each layer and the size of the preset routing capacity, it is determined whether each grid node is congested; For the congested grid nodes in the grid graph of each layer, the wiring directed acyclic graph of the wire network passing through the congested grid nodes is updated according to a preset rule to obtain an updated wiring directed acyclic graph; Based on the dynamic programming algorithm, a new routing path of the corresponding wire net is searched from the updated routing directed acyclic graph.

5. The method according to claim 4, characterized in that The preset rules include: Determine all neighboring mesh nodes of the congested mesh node according to the mesh graph, add non-congested mesh nodes among all the neighboring mesh nodes to a selectable node set, and select a node from the selectable node set; Reconstructing a minimum tree based on the selected node and all nodes in the wired directed acyclic graph, or replacing the congested grid node in the wired directed acyclic graph with the selected node, and reconstructing a minimum tree based on the selected node and the nodes in the wired directed acyclic graph that have not been replaced; The wiring directed acyclic graph of the corresponding network is reconstructed according to the reconstructed minimum tree to obtain an updated wiring directed acyclic graph.

6. The method according to claim 4, characterized in that The method of calculating the actual wiring capacity of each grid node in the grid graph of each layer includes: The actual wiring capacity is obtained by performing a weighted summation on the number of wirings of each grid node and the number of vias passing through the grid node in each grid node of the grid graph of the layer.

7. The method according to claim 4, characterized in that In the S5, the method of searching for a wiring path further includes: The A* algorithm is used to search for a wiring path for connecting multiple associated ports from the updated wiring directed acyclic graph of the wire net according to the grid nodes to which the multiple associated ports of each wire net belong, with the minimization of the wiring path length and the distance of the mask reuse area as the optimization goal.

8. A global routing system for implementing any one of the methods of claims 1 to 7, characterized in that: include: A data acquisition module, used to acquire layout information of the substrate, which includes multiple wiring layers, wiring parameters of each layer and netlist information of each layer, and the netlist information includes multiple associated ports that each wire net in multiple wire nets needs to be connected; A data preprocessing module is used to divide the wiring range of each layer of the substrate into multiple grid nodes, obtain the grid map of each layer, and map the associated ports of each wire net of the netlist information of each layer to the grid map of the corresponding layer, and construct a minimum tree of each wire net of each layer according to the mapping results of the associated ports of each wire net of each layer and the connection relationship between the multiple associated ports. The minimum tree of each wire net of each layer includes the grid nodes to which each associated port of the wire net belongs and the connection edges between the multiple grid nodes; A global routing module, for constructing a routing directed acyclic graph of each net of each layer on a grid graph of each layer based on a minimum tree of each net of each layer, wherein the routing directed acyclic graph of each net of each layer includes an alternative path constructed according to a connection relationship between multiple grid nodes in the minimum tree of the net; And according to the routing parameters of each layer and a dynamic programming algorithm built based on multiple routing optimization indicators, the routing path is searched from all alternative paths in the routing directed acyclic graph of each wire net of each layer to obtain the global routing result. The multiple routing optimization indicators include the distance of the mask reuse area, the routing length and the number of vias; The result output module is used to output the global routing results, including the routing paths of each net in each layer.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as A memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1-7 by executing the executable instructions.

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