Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a plurality of pixel circuits, each pixel circuit comprises an amplitude modulation sub-circuit and a pulse width modulation sub-circuit, the display panel further comprises a substrate, a voltage division signal line and a first constant voltage signal line, the voltage division signal line is located on one side of the substrate and extends in the first direction, and the first constant voltage signal line is located on the other side of the substrate. The first constant-voltage signal line is located on one side of the substrate, the first constant-voltage signal line extends in the second direction and transmits high-potential voltage to the pulse width modulation sub-circuit, and the first direction intersects with the second direction. Wherein the plurality of first constant voltage signal lines are electrically connected with the plurality of partial voltage signal lines. According to the embodiment of the invention, the voltage division signal line is additionally arranged in the display panel, and the voltage division signal line and the first constant voltage signal line are connected in a crossed manner, so that a net-shaped structure for transmitting the first power supply voltage is formed, the stability of the first power supply voltage is improved, a light-emitting element can be accurately turned on and off, and the display effect is improved. And the display reliability of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to a display panel and a display device. Background Art

[0002] With the development of science and technology, the field of display panels has also achieved tremendous progress and diversified development. On this basis, people's requirements for display panels are also increasing day by day. How to improve the reliability of display panels while meeting performance requirements has become one of the research directions of manufacturers. Summary of the invention

[0003] Embodiments of the present application provide a display panel and a display device, which can improve the reliability of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel includes a plurality of pixel circuits, the pixel circuit includes an amplitude modulation subcircuit and a pulse width modulation subcircuit, the display panel also includes a substrate, a voltage-dividing signal line, and a first constant voltage signal line, the voltage-dividing signal line is located on one side of the substrate, the voltage-dividing signal line extends along a first direction, the first constant voltage signal line is located on one side of the substrate, the first constant voltage signal line extends along a second direction and transmits a high potential voltage to the pulse width modulation subcircuit, and the first direction intersects with the second direction. Wherein, a plurality of first constant voltage signal lines are electrically connected to a plurality of voltage-dividing signal lines.

[0005] In a second aspect, an embodiment of the present application provides a display device, which includes a display panel in any of the aforementioned embodiments.

[0006] The embodiment of the present application provides a display panel and a display device, by adding a voltage-dividing signal line in the display panel, and cross-connecting the voltage-dividing signal line with the first constant voltage signal line, thereby forming a mesh structure for transmitting the first power supply voltage PWM-vdd, thereby helping to reduce the voltage loss value of the first power supply voltage PWM-vdd during the transmission process, and improving the stability of the first power supply voltage PWM-vdd. In addition, the turn-off reliability at the first node N1 is improved, so that the light-emitting element can be turned on and off accurately, and the display reliability of the display panel is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0008] Figure 1 is a structural schematic diagram of a local circuit in a display panel provided by an embodiment of the present application;

[0009] Figure 2 It is a simplified structural schematic diagram of a local circuit in a display panel provided by an embodiment of the present application;

[0010] Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at AA in the middle;

[0011] Figure 4a and Figure 4b It is a simplified circuit diagram of two pixel circuits in a display panel provided in an embodiment of the present application;

[0012] Figure 5 yes Figure 2 Schematic diagram of the cross-sectional structure at BB in the middle;

[0013] Figure 6 yes Figure 2 Schematic diagram of the cross-sectional structure at EE in the middle;

[0014] Figure 7 This is a simplified structural diagram of a local circuit in another display panel provided by an embodiment of the present application;

[0015] Figure 8 This is a schematic diagram of the positional relationship between a first constant voltage signal line, a first data signal line, and a second data signal line relative to a pixel circuit in another display panel provided by an embodiment of the present application;

[0016] Fig. 9 It is a schematic diagram of the position relationship of a first constant voltage signal line, a frequency sweeping signal line, a first data signal line and a second data signal line relative to a pixel circuit in another display panel provided by an embodiment of the present application;

[0017] Fig.10 This is a schematic diagram of the position relationship of a first constant voltage signal line relative to a pixel circuit in a display panel provided by an embodiment of the present application;

[0018] Fig.11 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present application;

[0019] Fig.12 It is a structural schematic diagram of a display device provided in an embodiment of the present application.

[0020] Marking Description:

[0021] 100. display panel; 200. display device;

[0022] 10. Substrate;

[0023] 20. first conductor layer; 21. voltage division signal line; 22. control signal line; 23. connection signal line;

[0024] 30, second conductor layer; 31, first constant voltage signal line; 32, first data signal line; 321, first sub-data line; 33, second data signal line; 331, second sub-data line; 34, frequency sweep signal line; 341, first type frequency sweep line; 342, second type frequency sweep line; 343, third type frequency sweep line;

[0025] P, pixel circuit; P1, pulse width modulation subcircuit; P2, amplitude modulation subcircuit; P3, circuit column; P4, circuit row; P5, circuit group column; C, repeated circuit group; F, light emitting element; M, transistor;

[0026] H1, first avoidance hole; H11, first type avoidance hole; H12, second type avoidance hole; H2, second avoidance hole; H3, third avoidance hole;

[0027] X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0030] There are many types of display panels. Micro-luminescent display panels have received widespread attention due to their advantages such as higher brightness and wider color gamut. Micro-luminescent display panels use micro devices such as micro-light emitting diodes (Micro LED) or sub-millimeter light emitting diodes (Mini LED) as light-emitting elements to achieve light-emitting display functions. On this basis, how to improve the display reliability of micro-luminescent display panels has become one of the research directions of many manufacturers.

[0031] Regarding the above issues, please refer to Figure 1 As shown in FIG. 4 , an embodiment of the present application provides a display panel 100, which includes a plurality of pixel circuits P, the pixel circuit P includes an amplitude modulation subcircuit P2 and a pulse width modulation subcircuit P1, and the display panel 100 also includes a substrate 10, a voltage-dividing signal line 21, and a first constant voltage signal line 31, the voltage-dividing signal line 21 is located on one side of the substrate 10, and the voltage-dividing signal line 21 extends along a first direction X, the first constant voltage signal line 31 is located on one side of the substrate 10, and the first constant voltage signal line 31 extends along a second direction Y and transmits a high potential voltage to the pulse width modulation subcircuit P1, and the first direction X intersects with the second direction Y. Among them, the plurality of first constant voltage signal lines 31 are electrically connected to the plurality of voltage-dividing signal lines 21.

[0032] The display panel 100 is a device for displaying images. The display panel 100 provided in the embodiment of the present application may be a micro-luminescent display panel 100. Specifically, the display panel 100 may include a light-emitting element F. The light-emitting element F is a main component for realizing the light-emitting function. The light-emitting element F may be a micro light-emitting element F such as a micro light-emitting diode (Micro Light Emitting Diode, MicroLED) or a sub-millimeter light-emitting diode (Mini Light Emitting Diode, Mini LED). Among them, the light-emitting element F may have a variety of structural forms, for example, the light-emitting element F may be a flip-chip, or a face-mounted chip, or a vertical chip, which is not limited in the embodiment of the present application.

[0033] The pixel circuit P is a circuit structure for driving and controlling whether the light-emitting element F emits light or not. There are multiple pixel circuits P, and the multiple pixel circuits P respectively control different light-emitting elements F to realize the light-emitting function. The pixel circuit P includes a pulse width modulation subcircuit P1 and an amplitude modulation subcircuit P2. The pulse width modulation subcircuit P1 is configured to control the pulse width of the driving current provided to the light-emitting element F based on the pulse width modulation data voltage, and the amplitude modulation subcircuit P2 is configured to control the amplitude of the driving current provided to the light-emitting element F based on the pulse amplitude modulation data voltage. Among them, the pulse width of the driving current can be understood as the duration of the driving current, and the amplitude of the driving current can be understood as the current value of the driving current.

[0034] Specifically, the light-emitting element F includes a first electrode, a second electrode and a light-emitting portion. Under the joint action of the first electrode and the second electrode, the light-emitting portion can realize the light-emitting display function. The pixel circuit P generates a driving current under the control of the amplitude modulation subcircuit P2 and the pulse width modulation subcircuit P1. The amplitude modulation subcircuit P2 can be used to control the amplitude of the driving current, and the pulse width modulation subcircuit P1 can be used to adjust the pulse width of the voltage applied to the second electrode of the light-emitting element F. The pulse width modulation subcircuit P1 adjusts the pulse width of the voltage applied to the second electrode of the light-emitting element F, that is, the pulse width modulation subcircuit P1 adjusts the actual emission period of the driving current applied to the light-emitting element F; at the same time, the driving current applied to the light-emitting element F can be maintained at a constant level to adjust the grayscale or brightness displayed by the light-emitting element F, rather than adjusting the grayscale or brightness displayed by the light-emitting element F by adjusting the magnitude of the driving current applied to the light-emitting element F. Therefore, the amplitude modulation subcircuit P2 can provide a driving current to the light emitting element F so that the light emitting element F is driven with the best luminous efficiency, and the light emission duty ratio (i.e., the emission period of the light emitting element F) of the light emitting element F is adjusted through the pulse width modulation subcircuit P1 to adjust the grayscale or brightness displayed by the light emitting element F. Among them, the output end of the pulse width modulation subcircuit P1 can be directly connected to the control end of a driving transistor in the amplitude modulation subcircuit P2 or indirectly controlled through a capacitor structure, that is, the electrical signal output by the output end of the pulse width modulation subcircuit P1 can be directly written to the control end of the driving transistor, or the control end of the driving transistor can be controlled by writing to the capacitor structure to achieve the adjustment of the driving current amplitude.

[0035] Furthermore, the specific circuit composition of the pulse width modulation subcircuit P1 and the amplitude modulation subcircuit P2 is not limited in the present embodiment. Figure 4aAs shown, the pulse width modulation sub-circuit P1 includes a first driving transistor M3, a first gate reset transistor M5, a first data writing transistor M2, a first compensation transistor M4, a first control transistor M1, a second control transistor M6 and a storage capacitor Cst. The first control transistor M1 is connected between the first power supply voltage PWM-vdd and the first electrode of the first driving transistor M3, and the second control transistor M6 is connected between the second electrode of the first driving transistor M3 and the first node N1. The first data writing transistor M2 is connected to the first data signal PWM-data and the first electrode of the first driving transistor M3, the first compensation transistor M4 is connected to the second electrode and the control end of the first driving transistor M3, and the first gate reset transistor M5 is connected to the control end of the first driving transistor M3. The first plate of the storage capacitor Cst is connected to the control end of the first driving transistor M3, and the second plate of the storage capacitor Cst is connected to the sweep signal SWEEP. Among them, the control end of the first gate reset transistor M5 receives the first scan signal PWM-S1, and the control ends of the first data writing transistor M2 and the first compensation transistor M4 receive the second scan signal PWM-S2. The control terminals of the first control transistor M1 and the second control transistor M6 receive the first light emitting control signal PWM-EM.

[0036] The amplitude modulation subcircuit P2 includes a second driving transistor M9, a second gate reset transistor M11, a second data writing transistor M8, a second compensation transistor M10, a third control transistor M7, a fourth control transistor M12, and an electrode reset transistor M13. The third control transistor M7 is connected between the second power supply voltage PAM-vdd and the first electrode of the second driving transistor M9, and the fourth control transistor M12 is connected between the second electrode of the second driving transistor M9 and the light emitting element F. The second driving transistor M9 is configured to generate a driving current under the control of its control terminal voltage, that is, the voltage of the first node N1. The second data writing transistor M8 is connected to the second data signal PAM-data and the first electrode of the second driving transistor M9, the second compensation transistor M10 is connected to the second electrode and the control terminal of the second driving transistor M9, the second gate reset transistor M11 is connected to the control terminal of the second driving transistor M9, the electrode reset transistor M13 is connected to the second electrode of the light emitting element F, and the fourth control transistor M12 is also connected to the second electrode of the light emitting element F, and the first electrode of the light emitting element F is connected to the third power supply voltage PVEE. The control end of the second gate reset transistor M11 receives the third scan signal PAM-S1; the control ends of the second data write transistor M8, the second compensation transistor M10 and the electrode reset transistor M13 receive the fourth scan signal PAM-S2. The control ends of the third control transistor M7 and the fourth control transistor M12 receive the second light emission control signal PAM-EM.

[0037] Or Figure 4bAs shown, the amplitude modulation subcircuit P2 and the pulse width modulation subcircuit P1 both include an initialization unit 111 / 121, a data writing unit 112 / 122, a threshold compensation unit 113 / 123, a light emitting control unit 114 / 124, storage capacitors C1, C2, C3, a compensation module 115, an electrode reset module 116, a voltage stabilization module 125, and a driving transistor PAM-DR / PWM-DR. The amplitude modulation subcircuit P2P2 includes an initialization unit 111, a data writing unit 112, a threshold compensation unit 113, a light emitting control unit 114, a storage capacitor C2, a voltage stabilization module 125, and a driving transistor PAM-DR; the pulse width modulation subcircuit P1P1 includes an initialization unit 121, a data writing unit 122, a threshold compensation unit 123, a light emitting control unit 124, storage capacitors C2 and C3, a compensation module 115, an electrode reset module 116, and a driving transistor PWM-DR. The storage capacitor C3 is located in the compensation module 115 , and the supplement module 115 also includes a plurality of transistor structures.

[0038] The initialization unit 111 / 121 is electrically connected between the initialization signal VREF and the first node N11 / N12. The initialization unit 111 / 121 is used to provide the initialization signal VREF to the first node N1 and the second node N2 during the initialization phase (the initialization signal provided by the initialization signal terminal of the amplitude modulation sub-circuit P2P2 may be the same as or different from the initialization signal of the pulse width modulation sub-circuit P1P1. Figure 4bThe initialization signal VREF includes PAM-REF and PWM-REF respectively. The data writing unit 112 / 122 is electrically connected between the data signal PAM-DATA / PWM-DATA and the first electrode of the driving transistor PAM-DR / PWM-DR, and the control end of the driving transistor PAM-DR / PWM-DR and the first electrode plate of the storage capacitor C2 / C1 are electrically connected to the first node N1 and the second node N2; the data writing unit 112 / 122 is used to provide the data signal PAM-DATA / PWM-DATA to the first node N1 and the second node N2 through the driving transistor PAM-DR / PWM-DR during the data writing phase. The threshold compensation unit 113 / 123 is electrically connected to the second electrode of the driving transistor PAM-DR / PWM-DR, and the threshold compensation unit 113 / 123 is used to compensate the threshold voltage of the driving transistor PAM-DR / PWM-DR to the first node N1 and the second node N2. The electrode reset module 116 is electrically connected between the reset signal PAM-INIT and the second electrode of the light emitting element F. The electrode reset module 116 is used to provide the reset signal PAM-INIT to the second electrode in the initialization stage to achieve the reset of the second electrode. The compensation module 115 is electrically connected to the second plate of the storage capacitor C2 to play a compensation role and reduce the problem of voltage drop in the pixel circuit P. The voltage stabilizing module 125 is electrically connected between the second plate of the storage capacitor C1 and the voltage stabilizing signal SWEEP-GND. The voltage stabilizing module 125 is used to stabilize the potential of the second node N2 when the sweep signal SWEEP is not working.

[0039] On this basis, whether Figure 4a The circuit structure shown is still Figure 4b In the circuit structure shown, the pulse width modulation subcircuit P1 needs to write the first power supply voltage PWM-vdd to meet the operation requirements of the pixel circuit P, and the output end of the pulse width modulation subcircuit P1 and the control end of the driving transistor in the amplitude modulation subcircuit P2 are both electrically connected to the first node N1. Furthermore, the stability of the first power supply voltage PWM-vdd in the display panel 100 often determines whether the pulse width modulation subcircuit P1 can operate well, and further affects whether the first node N1 can be turned off well, that is, it plays a role in controlling the turn-off of the amplitude modulation subcircuit P2 and controlling the light-emitting element F to turn on and off.

[0040] In view of this, the embodiment of the present application improves the stability of the first power supply voltage PWM-vdd by adjusting the signal line layout in the display panel 100, thereby improving the display reliability of the display panel 100. Specifically, the display panel 100 includes a substrate 10, a voltage-dividing signal line 21 and a first constant voltage signal line 31. The substrate 10 is a film layer in the display panel 100 for supporting and bearing. Other film layer structures and device structures are stacked in sequence on the substrate 10. The stacking arrangement mentioned here means that other film layer structures and device structures are arranged in sequence along the thickness direction Z of the substrate 10. Among them, the thickness direction Z of the substrate 10 is usually consistent with the thickness direction Z of other film layers and the thickness direction Z of the display panel 100. For the convenience of description, the embodiment of the present application will subsequently illustrate the thickness direction Z of the substrate 10, the thickness direction Z of the display panel 100 and the thickness direction Z of other film layers in the same direction.

[0041] The first constant voltage signal line 31 is used to transmit a constant voltage signal and transmit a high potential voltage to the pulse width modulation subcircuit P1, that is, the first constant voltage signal line 31 is used to transmit the first power supply voltage PWM-vdd. The voltage-dividing signal line 21 is connected to the first constant voltage signal line 31, that is, the voltage-dividing signal line 21 is also used to transmit the first power supply voltage PWM-vdd. According to different actual needs, the first constant voltage signal line 31 can be set on the same layer with other signal lines, or it can be set on the same layer without any signal lines. The embodiment of the present application does not limit this, and the voltage-dividing signal line 21 is the same.

[0042] The first constant voltage signal line 31 extends along the second direction Y, and the voltage division signal line 21 extends along the first direction X. The first direction X and the second direction Y are two directions perpendicular to the thickness direction Z and intersecting each other. Optionally, the first direction X, the second direction Y and the thickness direction Z are arranged perpendicularly to each other.

[0043] Under this design, multiple first constant voltage signal lines 31 and multiple voltage-dividing signal lines 21 are intersected and distributed in a grid shape, which helps to reduce the resistance value of the whole composed of the multiple first constant voltage signal lines 31 and the multiple voltage-dividing signal lines 21, and reduce the voltage loss value of the first power supply voltage PWM-vdd transmitted in the first constant voltage signal line 31 and the voltage-dividing signal line 21, thereby improving the stability of the first power supply voltage PWM-vdd, improving the shutdown reliability at the first node PAM-N1, so that the light-emitting element F can be accurately turned on and off, thereby improving the display reliability of the display panel 100.

[0044] It should be noted that since the first constant voltage signal line 31 and the voltage-dividing signal line 21 are two routing structures located on the same side of the substrate 10 and have different extension directions, and in order to reduce the interference effect of the first constant voltage signal line 31 on other signal routing lines on the same layer as the voltage-dividing signal line 21, or reduce the interference effect of the voltage-dividing signal line 21 on other signal routing lines on the same layer as the first constant voltage signal line 31, the first constant voltage signal line 31 and the voltage-dividing signal line 21 need to be located in different film layer structures respectively, that is, the first constant voltage signal line 31 and the voltage-dividing signal line 21 are located at different heights in the thickness direction Z, and the two can be electrically connected by vias at at least part of the intersection position.

[0045] The embodiments of the present application do not limit the specific film layer positions, material composition methods, shape and size of the first constant voltage signal line 31 and the voltage-dividing signal line 21. For example, the first constant voltage signal line 31 can be located on the side of the voltage-dividing signal line 21 facing the substrate 10, or it can be located on the side of the voltage-dividing signal line 21 away from the substrate 10. The first constant voltage signal line 31 and the voltage-dividing signal line 21 can include the same material, or they can also include different materials. The width of the first constant voltage signal line 31 in the first direction X can be greater than, equal to, or less than the width of the voltage-dividing signal line 21 in the second direction Y.

[0046] In addition, the specific positional relationship between the first constant voltage signal line 31 and the voltage-dividing signal line 21 relative to the pixel circuit P is not limited in the embodiment of the present application, as long as the voltage-dividing signal line 21 is not directly connected to the pixel circuit P, but is at least electrically connected to the pixel circuit P through the first constant voltage signal line 31. Among them, the orthographic projection of the first constant voltage signal line 31 on the substrate 10 can overlap with the orthographic projection of the pixel circuit P on the substrate 10, and the two are directly connected, or the orthographic projection of the first constant voltage signal line 31 on the substrate 10 can also be located outside the orthographic projection of the pixel circuit P on the substrate 10, in which case the first constant voltage signal line 31 needs to be electrically connected to the pixel circuit P through other signal routings except the voltage-dividing signal line 21. As for the voltage-dividing signal line 21, the orthographic projection of the voltage-dividing signal line 21 on the substrate 10 can overlap with the orthographic projection of the pixel circuit P on the substrate 10, or it can also be located outside the orthographic projection of the pixel circuit P on the substrate 10.

[0047] In summary, in the embodiment of the present application, by adding a voltage-dividing signal line 21 in the display panel 100, and cross-connecting the voltage-dividing signal line 21 with the first constant voltage signal line 31, a mesh structure for transmitting the first power supply voltage PWM-vdd is formed, which helps to reduce the voltage loss value of the first power supply voltage PWM-vdd during the transmission process and improve the stability of the first power supply voltage PWM-vdd. In addition, the turn-off reliability at the first node N1 is improved, so that the light-emitting element F can be turned on and off accurately, and the display reliability of the display panel 100 is improved.

[0048] In some embodiments, see Figure 2 and Figure 5 The display panel 100 includes a first conductor layer 20 located on one side of the substrate 10. The first conductor layer 20 includes a control signal line 22 and a voltage division signal line 21 extending along a first direction X. The control signal line 22 and the voltage division signal line 21 are arranged in a second direction Y.

[0049] The first conductor layer 20 is a film layer structure located on one side of the substrate 10 and includes a conductive material. The control signal line 22 and the voltage-dividing signal line 21 are both arranged in the first conductor layer 20, that is, the control signal line 22 and the voltage-dividing signal line 21 are arranged in the same layer. Furthermore, the control signal line 22 and the voltage-dividing signal line 21 may include the same conductive material and be prepared and formed together in the same preparation process.

[0050] In combination with the above content, it can be known that the pixel circuit P includes a plurality of transistors M, each of which includes a control terminal, a first electrode, a second electrode, and an active structure, wherein the active structure includes a channel region and a first region and a second region located on both sides of the channel region, wherein the first region is electrically connected to the first electrode, and the second region is electrically connected to the second electrode, and the orthographic projection of the control terminal on the substrate 10 overlaps with the orthographic projection of the channel region on the substrate 10. The control terminal is used to control whether the first electrode and the second electrode are turned on or off, and the first electrode and the second electrode are usually located on the side of the control terminal away from the substrate 10.

[0051] As for the control signal line 22, the control signal line 22 is located in the first conductor layer 20 and is used to control the wiring structure of the signal corresponding to the control end of the transistor. Specifically, the display panel 100 also includes an active layer, and the active structure is located in the active layer, and at least some of the active structures of different transistors can be connected and integrated. On this basis, the part of the structure of the control signal line 22 that overlaps with the active layer on the substrate 10 is the control end of the corresponding transistor.

[0052] It should be noted that the control signal line 22 has various types and forms. For example, the control signal line 22 can be used to control the control end of at least one of the driving transistor, gate reset transistor, data write transistor, compensation transistor and control transistor located in the pulse width modulation sub-circuit P1, or the control signal line 22 can also be used to control the control end of at least one of the driving transistor, gate reset transistor, electrode reset transistor, data write transistor, compensation transistor and control transistor located in the amplitude modulation sub-circuit P2.

[0053] Furthermore, the first conductor layer 20 may include only one type of control signal line 22, or may include multiple types of control signal lines 22, that is, different control signal lines 22 located in the first conductor layer 20 may be used to control only the control end of one of the above-mentioned multiple transistors, or may respectively control the control ends of different types of transistors.

[0054] In addition, the control signal line 22 and the voltage-dividing signal line 21 have the same extension direction, and both extend along the first direction X and are arranged in the second direction Y, so that the control signal line 22 and the voltage-dividing signal line 21 can be arranged parallel to each other, thereby reducing the risk of contact interference between the two and improving the reliability of internal signal transmission of the control signal line 22 and the voltage-dividing signal line 21.

[0055] In the embodiment of the present application, the voltage-dividing signal line 21 and the control signal line 22 are both arranged in the first conductor layer 20, that is, the arrangement of the voltage-dividing signal line 21 does not cause the display panel 100 to add a new film layer structure, so that the voltage-dividing signal line 21 for transmitting the first power supply voltage PWM-vdd can be formed without adding a new film layer structure, which is conducive to the thin and light design of the display panel 100. At the same time, the voltage-dividing signal line 21 and the control signal line 22 can include the same material and be prepared together in the same preparation process, which helps to simplify the preparation process of the display panel 100 and improve production efficiency.

[0056] In some embodiments, see Figure 2 , Figure 3 as well as Figure 6 The display panel 100 further includes a second conductor layer 30 disposed on a side of the first conductor layer 20 facing away from the substrate 10 , and the first constant voltage signal line 31 is located in the second conductor layer 30 .

[0057] In the embodiment of the present application, the second conductor layer 30 is a film layer structure including a conductive material located on the side of the first conductor layer 20 away from the substrate 10 in the display panel 100. Since the voltage-dividing signal line 21 is located in the first conductor layer 20 and the first constant voltage signal line 31 is located in the second conductor layer 30, the first constant voltage signal line 31 will be located on the side of the voltage-dividing signal line 21 away from the substrate 10. This design can make the first constant voltage signal line 31 and the voltage-dividing signal line 21 form a mesh structure together to reduce the voltage loss value of the first power supply voltage PWM-vdd during the transmission process. It can also reduce the contact interference between the first constant voltage signal line 31 and the control signal line 22 located in the first conductor layer 20, thereby improving the signal transmission reliability corresponding to the first power supply voltage PWM-vdd and the control signal.

[0058] It should be noted that the first constant voltage signal line 31 can have a variety of positional relationships relative to the first pole and the second pole of the transistor M in the pixel circuit P. For example, if the orthographic projection of the first constant voltage signal line 31 on the substrate 10 overlaps with the orthographic projection of the pixel circuit P on the substrate 10, that is, the orthographic projection corresponding to the first constant voltage signal line 31 will pass through the orthographic projection corresponding to the pixel circuit P along the second direction Y, the first constant voltage signal line 31 needs to be located on the side of the first pole and the second pole away from the substrate 10, that is, the second conductor layer 30 is located on the side of the film layer where the first pole and the second pole are located away from the substrate 10, so as to reduce the interference between the first constant voltage signal line 31 and some transistors that are not used to connect the first power supply voltage PWM-vdd.

[0059] If the orthographic projection of the first constant voltage signal line 31 on the substrate 10 is located outside the orthographic projection of the pixel circuit P on the substrate 10, that is, the orthographic projection corresponding to the first constant voltage signal line 31 will not pass through the orthographic projection corresponding to the pixel circuit P, the first constant voltage signal line 31 can be set in the same layer as the first electrode and the second electrode, that is, the first electrode and the second electrode of the transistor in the pixel circuit P can also be located in the second conductor layer 30.

[0060] In some embodiments, Figure 2 , Figure 3 and Figure 6 As shown, the second conductor layer 30 further includes a first data signal line 32 and a second data signal line 33. The first data signal line 32 is used to transmit the first data signal PWM-data to the pulse modulation subcircuit, and the second data signal line 33 is used to transmit the second data signal PAM-data to the amplitude modulation subcircuit P2. The first data signal line 32 and the second data signal line 33 both extend along the second direction Y, and the first constant voltage signal line 31, the first data signal line 32, and the second data signal line 33 are arranged in the first direction X.

[0061] The first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31 are all located in the second conductor layer 30, and the three may include the same material and be formed together in the same preparation process. Among them, there are various positional relationships between the first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31. For example, among the three signal lines of the first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31 that are closest to each other, the first data signal line 32 and the second data signal line 33 may be arranged adjacent to each other, and the first constant voltage signal line 31 may be located on the same side of the two data lines, or the first constant voltage signal line 31 may also be located between the first data signal line 32 and the second data signal line 33.

[0062] Furthermore, similar to the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 may also have a variety of positional relationships relative to the pixel circuit P. For example, the orthographic projection of one of the first data signal line 32 and the second data signal line 33 on the substrate 10 may overlap with the orthographic projection of the pixel circuit P on the substrate 10, or the orthographic projections of the first data signal line 32 and the second data signal line 33 on the substrate 10 may both be located outside the orthographic projection of the pixel circuit P on the substrate 10.

[0063] In the embodiment of the present application, considering that the extension directions of the first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31 are all the second direction Y, the first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31 are all arranged in the second conductor layer 30 and arranged in the first direction X, so that the number of film layers in the display panel 100 can be reduced while meeting the need for the three signal lines to extend independently, which is conducive to a lightweight design. Furthermore, the first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31 can also include the same material and be prepared together in the same preparation process, which helps to simplify the preparation process of the display panel 100 and improve production efficiency.

[0064] In some embodiments, see Figure 5 and Figure 7 The positive projection of the voltage-dividing signal line 21 on the substrate 10 is located outside the positive projection of the pixel circuit P on the substrate 10 , that is, the projection of the voltage-dividing signal line 21 in the thickness direction Z does not overlap with the projection of the pixel circuit P in the thickness direction Z.

[0065] In the embodiment of the present application, although the voltage-dividing signal line 21 is used to transmit the first power supply voltage PWM-vdd, the voltage-dividing signal line 21 is not directly connected to the pixel circuit P, but needs to be electrically connected to the pixel circuit P with the help of at least the first constant voltage signal line 31. On this basis, by displacing the voltage-dividing signal line 21 with the orthographic projection corresponding to the pixel circuit P, the risk of contact interference of the voltage-dividing signal line 21 with respect to the device structure such as the transistor in the pixel circuit P can be reduced, thereby improving the operational reliability of the pixel circuit P. Furthermore, at least part of the device structure in the pixel circuit P can be located in the first conductor layer 20, that is, arranged in the same layer as the voltage-dividing signal line 21, so as to improve the space utilization rate of the first conductor layer 20 and facilitate a lightweight design.

[0066] In some embodiments, Figure 5 and Figure 7 As shown, a plurality of pixel circuits P arranged in the second direction Y form a circuit column P3, and the orthographic projection of at least part of the first constant voltage signal line 31 on the substrate 10 is located between the orthographic projections of adjacent circuit columns P3 on the substrate 10; and / or, a plurality of pixel circuits P arranged in the first direction X form a circuit row P4, and the orthographic projection of at least part of the voltage dividing signal line 21 on the substrate 10 is located between the orthographic projections of adjacent circuit rows P4 on the substrate 10.

[0067] The first direction X corresponds to the row direction in which the plurality of pixel circuits P are arranged, and the plurality of pixel circuits P passed through by the virtual straight line parallel to the first direction X together constitute a circuit row P4, and the plurality of circuit rows P4 are arranged in the second direction Y. The second direction Y corresponds to the column direction in which the plurality of pixel circuits P are arranged, and the plurality of pixel circuits P passed through by the virtual straight line parallel to the second direction Y together constitute a circuit column P3, and the plurality of circuit columns P3 are arranged in the first direction X.

[0068] For the two circuit rows P4 that are closest to each other, there is a gap space extending along the first direction X between the two. On this basis, since the voltage-dividing signal line 21 also extends along the first direction X and the voltage-dividing signal line 21 is not directly connected to the pixel circuit P, the voltage-dividing signal line 21 can be set between two adjacent circuit rows P4. Among them, only one voltage-dividing signal line 21 can be set between two adjacent circuit rows P4, or multiple voltage-dividing signal lines 21 can be set between two adjacent circuit rows P4 at the same time.

[0069] Similarly, for the two circuit columns P3 that are closest to each other, there is a gap space extending along the second direction Y between the two. On this basis, since the first constant voltage signal line 31 also extends along the second direction Y, the first constant voltage signal line 31 can be correspondingly arranged between two adjacent circuit columns P3. Among them, only one first constant voltage signal line 31 can be arranged between two adjacent circuit columns P3, or multiple first constant voltage signal lines 31 can be arranged between two adjacent circuit columns P3 at the same time.

[0070] It should be noted that, for the solution in which the first constant voltage signal line 31 is located between adjacent circuit columns P3, since the first constant voltage signal line 31 does not overlap with the pixel circuit P, the two cannot be directly connected. On this basis, other signal lines need to be provided in the display panel 100 to achieve electrical connection between the first constant voltage signal line 31 and the pixel circuit P to meet the transmission requirements of the first power supply voltage PWM-vdd.

[0071] In the embodiment of the present application, by correspondingly setting the voltage-dividing signal line 21 between two adjacent circuit rows P4, or correspondingly setting the first constant-voltage signal line 31 between two circuit columns P3, the risk of contact and interference between the voltage-dividing signal line 21 or the first constant-voltage signal line 31 and the device structure in the pixel circuit P is reduced while meeting the corresponding extension needs of the voltage-dividing signal line 21 or the first constant-voltage signal line 31, thereby improving the reliability of the corresponding signal transmission and the operating reliability of the pixel circuit P.

[0072] In some optional embodiments, a plurality of pixel circuits P arranged in the second direction Y form a circuit column P3, and at least a portion of the first constant voltage signal line 31 is projected on the substrate 10 between the orthographic projections of adjacent circuit columns P3 on the substrate 10; and a plurality of pixel circuits P arranged in the first direction X form a circuit row P4, and at least a portion of the orthographic projections of the voltage-dividing signal line 21 on the substrate 10 are projected on the substrate 10 between the orthographic projections of adjacent circuit rows P4 on the substrate 10.

[0073] In some embodiments, Figure 2 , Figure 3 , Figure 6 as well as Figure 7As shown, the display panel 100 further includes a first data signal line 32 and a second data signal line 33 extending along the second direction Y, and the orthographic projections of at least part of the first data signal line 32 and the second data signal line 33 on the substrate 10 are located between the orthographic projections of adjacent circuit columns P3 on the substrate 10. The distance between the circuit column P3 and the first data signal line 32 electrically connected thereto in the first direction X is smaller than the distance between the circuit column P3 and the first constant voltage signal line 31 in the first direction X; and / or the distance between the circuit column P3 and the second data signal line 33 electrically connected thereto in the first direction X is smaller than the distance between the circuit row P4 and the first constant voltage signal line 31 in the first direction X.

[0074] In combination with the above content, it can be known that the first data signal line 32 is used to transmit the first data signal PWM-data to the pulse modulation subcircuit, and the second data signal line 33 is used to transmit the second data signal PAM-data to the amplitude modulation subcircuit P2. Since the first data signal line 32 and the second data signal line 33 both extend along the second direction Y, the first data signal line 32 and the second data signal line 33 can also be correspondingly arranged in the gap area between adjacent circuit columns P3. Further, similar to the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 also require other signal routings to realize electrical connection with the pixel circuit P.

[0075] Considering that the first power supply voltage PWM-vdd will be transmitted through the mesh structure composed of the first constant voltage signal line 31 and the voltage-dividing signal line 21, the resistance corresponding to the signal routing structure used to transmit the first power supply voltage PWM-vdd is usually small, and the corresponding signal delay and other problems are also small. As for the first data signal PWM-data and the second data signal PAM-data, they usually only rely on the strip-shaped first data signal line 32 and the second data signal line 33 to realize the transmission of the corresponding signal, which will have a larger resistance value relative to the first power supply voltage PWM-vdd, that is, it is more likely to cause signal delay problems.

[0076] In view of this, the embodiment of the present application adjusts the positions of the first data signal line 32 and the second data signal line 33 relative to the first constant voltage signal line 31, so as to improve the overall operation reliability of the pixel circuit P. Next, the embodiment of the present application will be described in detail with reference to the accompanying drawings. Figure 7 As shown, for the two adjacent circuit columns P3 on the left and right, the circuit column on the left is the first circuit column P31, and the circuit column on the right is the second circuit column P32. The first data signal line 32 located between the two needs to be electrically connected to the pixel circuit P in the second circuit column P32 through other signal lines, and the second data signal line 33 located between the two needs to be electrically connected to the pixel circuit P in the first circuit column P31 through other signal lines.

[0077] On this basis, the embodiment of the present application can set the distance between the second circuit column P32 and the first data signal line 32 electrically connected thereto in the first direction X to be smaller than the distance between the right circuit column P3 and the first constant voltage signal line 31 in the first direction X, that is, the first data signal line 32 is located on the right side of the first constant voltage signal line 31 close to the second circuit column P32. In this way, the extension length of the signal routing required for realizing the electrical connection between the first data signal line 32 and the second circuit column P32 in the first direction X is reduced, and the signal delay problem corresponding to the first data signal PWM-data is reduced. The mesh structure formed by the first constant voltage signal line 31 and the voltage-dividing signal line 21 can reduce the signal delay problem corresponding to the first power supply voltage PWM-vdd. Therefore, the embodiment of the present application can take into account the transmission reliability of the first data signal PWM-data and the first power supply voltage PWM-vdd at the same time, and improve the operation reliability of the pixel circuit P.

[0078] Similarly, in the embodiment of the present application, the distance between the first circuit column P31 and the second data signal line 33 electrically connected thereto in the first direction X can be set to be smaller than the distance between the first circuit column P31 and the first constant voltage signal line 31 in the first direction X, that is, the second data signal line 33 is located on the left side of the first constant voltage signal line 31 close to the first circuit column P31. In this way, the extension length of the signal routing required for realizing the electrical connection between the second data signal line 33 and the first circuit column P31 in the first direction X is reduced, and the signal delay problem corresponding to the second data signal PAM-data is reduced. The mesh structure formed by the first constant voltage signal line 31 and the voltage-dividing signal line 21 can reduce the signal delay problem corresponding to the first power supply voltage PWM-vdd. Therefore, the embodiment of the present application can take into account the transmission reliability of the second data signal PAM-data and the first power supply voltage PWM-vdd at the same time, and improve the operation reliability of the pixel circuit P.

[0079] It should be noted that Figure 7, the first data signal line 32 and the second data signal line 33 located between two adjacent circuit columns P3 are respectively connected to different circuit columns P3. In some other embodiments, the first data signal line 32 and the second data signal line 33 located between two adjacent circuit columns P3 can also be electrically connected to the same circuit column P3, for example, both data lines are electrically connected to the first circuit column P31. On this basis, at this time, in order to take into account the transmission reliability of the first data signal PWM-data, the second data signal PAM-data and the first power supply voltage PWM-vdd at the same time, the first data signal line 32 and the second data signal line 33 need to be set on the left side of the first constant voltage signal line 31, that is, the first data signal line 32 and the second data signal line 33 need to be located on the same side of the first constant voltage signal line 31, rather than being set on both sides of the first constant voltage signal line 31.

[0080] In some embodiments, a first constant voltage signal line 31, a first data signal line 32 and a second data signal line 33 are arranged between at least part of adjacent circuit columns P3, the first data signal line 32 and the second data signal line 33 are arranged on both sides of the first constant voltage signal line 31 along the first direction X, and the first data signal line 32 and the second data signal line 33 are electrically connected to the pixel circuit P in the adjacent circuit column P3 respectively.

[0081] In the embodiment of the present application, “the first data signal line 32 and the second data signal line 33 are respectively electrically connected to the pixels in the adjacent circuit column P3” refers to: corresponding to the first data signal line 32, the circuit column P3 that is closest to the first data signal line 32 in the first direction X; corresponding to the second data signal line 33, the circuit column P3 that is closest to the second data signal line 33 in the first direction X.

[0082] Combination Figure 7For example, in the embodiment of the present application, the first data signal line 32 and the second data signal line 33 are respectively arranged on both sides of the first constant voltage signal line 31, and the circuit column P3 electrically connected to the first data signal line 32 is located on a side of the first data signal line 32 away from the first constant voltage signal line 31 and the second data signal line 33, and the circuit column P3 electrically connected to the second data signal line 33 is located on a side of the second data signal line 33 away from the first constant voltage signal line 31 and the first data signal line 32. Under this design, the extension length of the signal routing line required for realizing the electrical connection between the first data signal line 32 and the corresponding circuit column P3 in the first direction X will not be adversely affected by the second data signal line 33 and the first constant voltage signal line 31; the extension length of the signal routing line required for realizing the electrical connection between the second data signal line 33 and the corresponding circuit column P3 in the first direction X will not be adversely affected by the first data signal line 32 and the first constant voltage signal line 31, thereby further taking into account the transmission reliability of the first data signal PWM-data, the second data signal PAM-data and the first power supply voltage PWM-vdd, thereby improving the operating reliability of the pixel circuit P.

[0083] In some embodiments, see Figure 3 , Figure 6 , Figure 7 as well as Figure 8 The display panel 100 includes a repeating circuit group C, the repeating circuit group C includes a plurality of pixel circuits P, the plurality of repeating circuit groups C are repeatedly arranged in a first direction X and a second direction Y, the first data signal line 32 includes a plurality of first sub-data lines 321, the plurality of first sub-data lines 321 are respectively connected to different pixel circuits P in the same repeating circuit group C. The second data signal line 33 includes a plurality of second sub-data lines 331, the plurality of second sub-data lines 331 are respectively electrically connected to different pixel circuits P in the same repeating circuit group C.

[0084] The repeating circuit group C is the smallest repeating unit composed of a plurality of pixel circuits P, and the plurality of repeating circuit groups C can be arranged repeatedly along the first direction X and the second direction Y. The distance between adjacent repeating circuit groups C in the first direction X is usually kept consistent, and the distance between adjacent repeating circuit groups C in the second direction Y is also usually kept consistent. However, according to different actual needs, a special design can be made at a position close to the edge of the display panel 100. For example, at a position close to the edge, the distance between adjacent repeating circuit groups C in the first direction X may be somewhat different from that at the center, or may be kept consistent. Similarly, at a position close to the edge, the distance between adjacent repeating circuit groups C in the second direction Y may be somewhat different from that at the center, or may be kept consistent, and the embodiments of the present application do not limit this.

[0085] The multiple pixel circuits P in the repeating circuit group C may have multiple types and arrangements. For example, the repeating circuit group C includes a first pixel circuit P, a second pixel circuit P, and a third pixel circuit P arranged along the first direction X. The first pixel circuit P, the second pixel circuit P, and the third pixel circuit P are respectively used to drive one of a red light-emitting element, a green light-emitting element, and a blue light-emitting element, and the multiple light-emitting elements electrically connected to the multiple pixel circuits P in the same repeating circuit group C together constitute a pixel unit. The pixel unit is the smallest repeating unit in the light-emitting element arrangement structure.

[0086] In the display panel 100, in the first direction X, the distance between two adjacent pixel circuits P in two adjacent repeating circuit groups C is often greater than the distance between two adjacent pixel circuits P in the same repeating circuit group C. On this basis, in the embodiment of the present application, the first data signal line 32 and the second data signal line 33 are correspondingly arranged between adjacent repeating circuit groups C, and the first data signal line 32 and the second data signal line 33 are not arranged in the area where the single repeating circuit group C is located, thereby reducing the influence of the first data signal line 32 and the second data signal line 33 on the size of the single repeating circuit group C in the first direction X.

[0087] Furthermore, in order to meet the needs of multiple pixel circuits P in a single repeating circuit group C corresponding to different first data signals PWM-data and second data signals PAM-data, the embodiment of the present application further sets the first data signal line 32 to include multiple first sub-data lines 321, and the multiple first sub-data lines 321 are respectively used to electrically connect to different pixel circuits P in a single repeating circuit group C to meet the needs of different first data signals PWM-data for multiple pixel circuits P in a single repeating circuit group C. Among them, the number of first sub-data lines 321 included in the first data signal line 32 can match the number of pixel circuits P in a single repeating circuit group C, and further optionally, the arrangement of the multiple first sub-data lines 321 in the first data signal line 32 is consistent with the arrangement of the multiple pixel circuits P in the corresponding repeating circuit group C.

[0088] In the embodiment of the present application, the first data signal line 32 and the second data signal line 33 are correspondingly arranged between adjacent repeating circuit groups C, rather than being correspondingly arranged at the corresponding area of ​​a single repeating circuit group C, so as to reduce the influence of the first data signal line 32 and the second data signal line 33 on the size of a single repeating circuit group C in the first direction X. Furthermore, in the embodiment of the present application, the first data signal line 32 is arranged to include a plurality of first sub-data lines 321 corresponding to different pixel circuits P in the same repeating circuit group C, and the second data signal line 33 is arranged to include a plurality of second sub-data lines 331 corresponding to different pixel circuits P in the same repeating circuit group C, so as to meet the transmission needs of the first data signal PWM-data and the second data signal PAM-data of each of the plurality of pixel circuits P in the single repeating circuit group C.

[0089] It should be noted that the first constant voltage signal line 31 is also located between adjacent repeated circuit groups C. Considering that multiple pixel circuits P in the same repeated circuit group C can be electrically connected to the same first power supply voltage PWM-vdd at the same time, only one first constant voltage signal line 31 can be provided between adjacent repeated circuit groups C. Of course, in other embodiments, multiple first constant voltage signal lines 31 can also be provided between adjacent repeated circuit groups C to improve the transmission reliability of the first power supply voltage PWM-vdd, and the embodiments of the present application are not limited to this.

[0090] In addition, combined Figure 7 and Figure 8 For example, between adjacent repeated circuit groups C, a plurality of first sub-data lines 321 in the first data signal line 32 are located on the same side of the first constant voltage signal line 31, and a plurality of second sub-data lines 331 in the second data signal line 33 are also located on the same side of the first constant voltage signal line 31, and the plurality of first sub-data lines 321 and the plurality of second sub-data lines 331 are arranged on different sides of the first constant voltage signal line 31, thereby helping to reduce the distance between the first sub-data line 321 and the corresponding electrically connected pixel circuit P in the first direction X, and reducing the distance between the second sub-data line 331 and the corresponding electrically connected pixel circuit P in the first direction X, thereby taking into account the transmission reliability of the first data signal PWM-data, the second data signal PAM-data and the first power supply voltage PWM-vdd.

[0091] In some embodiments, see Fig. 9 The display panel 100 also includes a sweep signal line 34 extending along the second direction Y, the sweep signal line 34 is used to transmit a sweep signal SWEEP to the amplitude modulation sub-circuit P2, and the sweep signal line 34, the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 are arranged in the first direction X.

[0092] The frequency sweep signal line 34 is a signal line for transmitting the frequency sweep signal SWEEP. Like the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33, the frequency sweep signal line 34 is also extended along the second direction Y. The frequency sweep signal line 34 may be arranged in the same layer relative to at least one of the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33, or may be located in a different conductor film layer with the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 at the same time, and the embodiment of the present application does not limit this.

[0093] It should be noted that, for ease of understanding, Fig. 9 The frequency sweep signal line 34 is illustrated in a different cross-sectional form relative to the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33, but it does not mean that the frequency sweep signal line 34 needs to be located in a different film layer relative to the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33.

[0094] The embodiment of the present application does not limit the specific positional relationship of the frequency sweep signal line 34 relative to the first constant voltage signal line 31, the first data signal line 32, and the second data signal line 33. For example, the orthographic projection of the frequency sweep signal line 34 on the substrate 10 is also located between two adjacent repeated circuit groups C in the first direction X, and between two adjacent repeated circuit groups C, the frequency sweep signal line 34 can be located between any adjacent other types of signal routing lines, or can also be located on the same side of multiple other types of signal routing lines.

[0095] On this basis, the embodiment of the present application arranges the frequency scanning signal line 34, the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 along the first direction X, so that the frequency scanning signal line 34, the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 are spaced from each other in the first direction X of the orthographic projection of the substrate 10, thereby reducing the risk of contact interference and large parasitic capacitance of the above-mentioned signal lines, and improving the reliability of the corresponding signal transmission of the multiple signal lines.

[0096] In some optional embodiments, the frequency sweep signal line 34, the first constant voltage signal line 31, the first data signal line 32 and the second data signal line 33 are all located in the second conductor layer 30, that is, the above signal lines are all arranged in the same layer, which helps to further reduce the number of film layers in the display panel 100 and facilitates a thin and light design. At the same time, the various signal lines can also include the same material and be formed together in the same process, thereby simplifying the process of the display panel 100 and reducing the manufacturing cost.

[0097] It should be noted that in the embodiment of the present application, the sweep frequency signal SWEEP is transmitted in a direct drive manner. By way of example, the display panel 100 also includes a driver chip IC, which is disposed on a side of the substrate 10 away from the first constant voltage signal line 31, wherein the driver chip IC can be directly or indirectly connected to the sweep frequency signal line 34, thereby realizing direct driving of the sweep frequency signal SWEEP.

[0098] In other embodiments, the display panel 100 may further include a plurality of shift registers arranged in cascade, the shift registers may be arranged between adjacent circuit rows P4, or between adjacent circuit columns P3, and the output end of the shift register is used to provide a sweep signal SWEEP to meet the transmission requirements of the sweep signal SWEEP.

[0099] In some embodiments, Fig. 9 As shown, at least part of the scanning frequency signal line 34 is located between the first data signal line 32 and the first constant voltage signal line 31 which are closest to each other, and the scanning frequency signal line 34 and the first data signal line 32 are electrically connected to the same pixel circuit P; and / or, at least part of the scanning frequency signal is located between the second data signal line 33 and the first constant voltage signal line 31 which are closest to each other, and the scanning frequency signal line 34 and the second data signal line 33 are electrically connected to the same pixel circuit P.

[0100] The "at least part of the frequency sweeping signal lines 34 are located between the first data signal line 32 and the first constant voltage signal line 31 that are closest to each other" mentioned in the embodiment of the present application means that for a single frequency sweeping signal line 34, the specific first data signal line 32 and the specific first constant voltage signal line 31 that are the closest to each other in the first direction X. Among them, there may be other signal lines between the frequency sweeping signal line 34 and the first data signal line 32 that is closest to each other, or there may be no other signal lines, and the embodiment of the present application does not limit this, and there is at least the first data signal line 32 between the frequency sweeping signal line 34 and the first constant voltage signal line 31 that is closest to each other. In addition, the relationship between the frequency sweeping signal line 34 and the second data signal line 33 and the first constant voltage signal line 31 that are closest to each other is similar, and the embodiment of the present application will not be repeated.

[0101] Similar to the first data signal line 32, the second data signal line 33 and the first constant voltage signal line 31, the frequency scanning signal line 34 is also located between adjacent circuit columns P3. Further optionally, the orthographic projection of the frequency scanning signal line 34 on the substrate 10 is located between the orthographic projections of adjacent repeated circuit groups C in the first direction X on the substrate 10.

[0102] Considering that the first power supply voltage PWM-vdd will be transmitted through the mesh structure composed of the first constant voltage signal line 31 and the voltage-dividing signal line 21, the resistance corresponding to the signal routing structure used to transmit the first power supply voltage PWM-vdd is usually small, and the corresponding signal delay and other problems are also small. As for the sweep signal SWEEP, it is similar to the first data signal PWM-data and the second data signal PAM-data, and only relies on the strip-shaped sweep signal line 34 to realize the transmission of the corresponding signal. It has a larger resistance value relative to the first power supply voltage PWM-vdd, that is, it is more likely to cause signal delay problems.

[0103] In view of this, the embodiment of the present application adjusts the position of the frequency sweep signal line 34 relative to the first constant voltage signal line 31, so as to improve the overall operation reliability of the pixel circuit P. For example, between two circuit columns P3 adjacent to each other on the left and right, there are the first constant voltage signal line 31, the first data signal line 32, the second data signal line 33 and the frequency sweep signal line 34, the first data signal line 32 is located on the left side of the first constant voltage signal line 31 and is electrically connected to the circuit column P3 on the left, and the second data signal line 33 is located on the right side of the first constant voltage signal line 31 and is electrically connected to the circuit column P3 on the right.

[0104] On this basis, at least part of the scanning signal line 34 can be located between the first data signal line 32 and the first constant voltage signal line 31 and electrically connected to the left circuit column P3, that is, at least part of the scanning signal line 34 and the first data signal line 32 are located on the same side of the first constant voltage signal line 31 and are electrically connected to the same pixel circuit P, thereby simultaneously reducing the size of the signal line used to electrically connect the first data signal line 32 and the pixel circuit P and the signal line used to connect the scanning signal line 34 and the pixel circuit P in the first direction X, thereby taking into account the transmission reliability of the first data signal PWM-data and the scanning signal SWEEP.

[0105] Alternatively, at least part of the scanning signal line 34 can be located between the second data signal line 33 and the first constant voltage signal line 31 and electrically connected to the right circuit column P3, that is, at least part of the scanning signal line 34 and the second data signal line 33 are located on the same side of the first constant voltage signal line 31 and are electrically connected to the same pixel circuit P, thereby simultaneously reducing the size of the signal line for electrically connecting the second data signal line 33 and the pixel circuit P and the signal line for connecting the scanning signal line 34 and the pixel circuit P in the first direction X, thereby taking into account the transmission reliability of the second data signal PAM-data and the scanning signal SWEEP.

[0106] It should be noted that, in the embodiment of the present application, according to different actual needs, the number of the sweeping signal lines 34 between adjacent circuit columns P3 may be one, or may be multiple. When the number of the sweeping signal lines 34 between two adjacent circuit columns P3 is multiple, the multiple sweeping signal lines 34 may be all located between the first data signal line 32 and the first constant voltage signal line 31, or all located between the second data signal line 33 and the first constant voltage signal line 31, or some of the sweeping signal lines 34 may be located between the first data signal line 32 and the first constant voltage signal line 31, and some of the sweeping signal lines 34 may be located between the second data signal line 33 and the first constant voltage signal line 31.

[0107] And in some other embodiments, between adjacent circuit columns P3, at least part of the frequency scanning signal line 34 may also be located on the side of the first data signal line 32 away from the first constant voltage signal line 31; and / or, at least part of the frequency scanning signal line 34 may also be located on the side of the second data signal line 33 away from the first constant voltage signal line 31.

[0108] In some embodiments, Fig. 9 As shown, the frequency scanning signal line 34 includes a first type of frequency scanning line 341, a second type of frequency scanning line 342 and a third type of frequency scanning line 343, and the first type of frequency scanning line 341, the second type of frequency scanning line 342 and the third type of frequency scanning line 343 are used to drive the pixel circuits P located in different rows along the second direction Y. Among them, the first type of frequency scanning line 341 is located between the first data signal line 32 and the first constant voltage signal line 31 which are closest to each other, and the second type of frequency scanning line 342 and the third type of frequency scanning line 343 are located between the second data signal line 33 and the first constant voltage signal line 31 which are closest to each other.

[0109] The first type of scanning line 341, the second type of scanning line 342 and the third type of scanning line 343 are all used to transmit the scanning signal SWEEP, but the three are used to drive the pixel circuits P located in different rows along the second direction Y. For example, the first type of scanning line 341 is used to drive the 1 / 4 / 7...row pixel circuits P, the second type of scanning line 342 is used to drive the 2 / 5 / 8...row pixel circuits P, and the third type of scanning line 343 is used to drive the 3 / 6 / 9...row pixel circuits P.

[0110] It should be noted that the embodiment of the present application provides that the scanning signal line 34 includes three signal lines for transmitting the scanning signal SWEEP to different rows of pixel circuits P, but according to different actual needs, the scanning signal line 34 may also include only one, two or more than three signal line lines.

[0111] Furthermore, considering that the first type of scanning line 341, the second type of scanning line 342 and the third type of scanning line 343 are simultaneously located between the same adjacent circuit columns P3, if the three signal lines are arranged adjacent to each other and the scanning signal SWEEP is transmitted to the same circuit column P3, one of the signal lines will be far away from the corresponding pixel circuit P in the first direction X, which may easily cause signal delay problems.

[0112] In view of this, the embodiment of the present application arranges the first type of scanning line 341 on both sides of the first constant voltage signal line 31 relative to the second type of scanning line 342 and the third type of scanning line 343, so that the first type of scanning line 341 can be located between the first data signal line 32 and the first constant voltage signal line 31 that are closest to it, and is electrically connected to the same pixel circuit P as the first data signal line 32. At the same time, the second type of scanning line 342 and the third type of scanning line 343 are located between the second data signal line 33 and the first constant voltage signal line 31 that are closest to it, and are electrically connected to the same pixel circuit P as the second data signal line 33. In this way, the transmission reliability of the scanning signals SWEEP in the various signal lines in the scanning signal line 34 is taken into account, the risk of signal delay of the scanning signal SWEEP is reduced, and the operation reliability of the pixel circuit P is improved.

[0113] Of course, in other embodiments, the first type of scanning frequency line 341 and the second type of scanning frequency line 342 can also be located between the nearest first data signal line 32 and the first constant voltage signal line 31, and the third type of scanning frequency line 343 is located between the nearest second data signal line 33 and the first constant voltage signal line 31.

[0114] In some embodiments, the number of circuit rows P4 between at least some adjacent voltage-dividing signal lines 21 is the same. The spacing between adjacent voltage-dividing signal lines 21 in the second direction Y may be the same, or may have a certain difference, which is not limited in the present embodiment.

[0115] In combination with the above content, it can be known that the voltage-dividing signal line 21 is correspondingly located between adjacent circuit rows P4, and only one circuit row P4 may be provided between adjacent voltage-dividing signal lines 21, or multiple circuit rows P4 may be provided at the same time. On this basis, in the embodiment of the present application, the number of circuit rows P4 between at least some adjacent voltage-dividing signal lines 21 is the same, so that the pixel circuit P and the voltage-dividing signal line 21 can be arranged in the second direction Y according to a specific rule, thereby reducing the risk of contact and interference between the device structure in the pixel circuit P and the voltage-dividing signal line 21, and improving the operational reliability of the pixel circuit P.

[0116] In some embodiments, at least some of the voltage-dividing signal lines 21 have the same spacing in the second direction Y.

[0117] In the embodiment of the present application, by enabling at least some adjacent voltage-dividing signal lines 21 to have the same distance in the second direction Y, the voltage-dividing signal lines 21 are arranged more regularly in the second direction Y, thereby reducing the difficulty of signal line layout in the display panel 100, and helping to reduce the risk of contact interference between the voltage-dividing signal lines 21 and other signal lines, thereby improving the reliability of signal transmission.

[0118] In some embodiments, in the second direction Y, N circuit rows P4 are arranged between at least some adjacent voltage-dividing signal lines 21, N≥1; and / or, in the second direction Y, M voltage-dividing signal lines 21 are arranged between at least some adjacent circuit rows P4, M≥1.

[0119] In the embodiment of the present application, taking into account that for different display panels 100, there are certain differences in the number of circuit rows P4, the distance between adjacent circuit rows P4, and the number of required voltage-dividing signal lines 21, on this basis, according to different actual needs, one or more circuit rows P4 can be selectively set between at least some of the adjacent voltage-dividing signal lines 21, or one or more voltage-dividing signal lines 21 can be selectively set between at least some of the adjacent circuit rows P4, so as to adapt to display panels 100 in different situations and improve flexibility.

[0120] In some embodiments, Figure 7 As shown, the display panel 100 includes a repeated circuit group C, the repeated circuit group C includes a plurality of pixel circuits P, the plurality of repeated circuit groups C are repeatedly arranged in a first direction X and a second direction Y, and the plurality of repeated circuit groups C arranged in the second direction Y form a circuit group column P5. A first constant voltage signal line 31 is arranged between at least some adjacent circuit group columns P5.

[0121] A plurality of repeated circuit groups C arranged in the second direction Y together constitute a circuit group column P5. The plurality of circuit group columns P5 are arranged side by side in the first direction X, and there can be a large gap space between adjacent circuit group columns P5 for arranging signal lines extending along the second direction Y, such as the first constant voltage signal line 31, the first data signal line 32, the second data signal line 33, and the sweep frequency signal line 34.

[0122] Furthermore, in the embodiment of the present application, similar to the voltage-dividing signal line 21, the number and arrangement of the first constant-voltage signal lines 31 can be flexibly adjusted according to different actual needs. It can be selected to provide the first constant-voltage signal line 31 only between some adjacent circuit groups P5, or it can be selected to provide the first constant-voltage signal line 31 between all adjacent circuit groups P5, so as to meet different needs and have strong practicality.

[0123] In some embodiments, see Fig.10 , the circuit group P5 includes i circuit group columns P5 spaced apart in the first direction X, the first constant voltage signal line 31 is not provided in the area between the first circuit group column P51 and the second circuit group column P52, and the first constant voltage signal line 31 is provided in the area on the side of the first circuit group column P51 away from other circuit group columns P5; and / or, the first constant voltage signal line 31 is not provided in the area between the i-1th circuit group column P53 and the i-th circuit group column P54, and the first constant voltage signal line 31 is provided in the area on the side of the i-th circuit group column P54 away from other circuit group columns P5.

[0124] With reference to the drawings, i circuit groups P5 are arranged in the first direction X, and the circuit group P5 on the far left is the first circuit group P51, and the circuit group P5 on the far right is the i-th circuit group P54, which is also the last circuit group P5.

[0125] Depending on actual needs, the structure of the display panel 100 is usually different. For some display panels 100, the circuit groups P5 on both sides in the first direction X need to be designed to be retracted, that is, the distance between the first circuit group P51 and the second circuit group P52 is smaller than the distance between adjacent circuit groups P5 in the center of the display panel 100. Similarly, the distance between the i-th circuit group P54 and the i-1-th circuit group P53 is smaller than the distance between adjacent circuit groups P5 in the center of the display panel 100.

[0126] In view of this, in the embodiment of the present application, the area between the first circuit group P51 and the second circuit group P52 is not provided with the first constant voltage signal line 31, thereby reducing the influence of the existence of the first constant voltage signal line 31 on the distance between the first circuit group P51 and the second circuit group P52. Similarly, the area between the i-1th circuit group P53 and the i-th circuit group P54 is not provided with the first constant voltage signal line 31, thereby reducing the influence of the existence of the first constant voltage signal line 31 on the distance between the i-1th circuit group P53 and the i-th circuit group P54, thereby helping to meet the inward design of the circuit groups P5 on both sides of the display panel 100 in the first direction X.

[0127] Furthermore, in the embodiment of the present application, a first constant voltage signal line 31 is provided in an area on the side of the first circuit group P51 away from other circuit groups P5, or a first constant voltage signal line 31 is provided in an area on the side of the i-th circuit group P54 away from other circuit groups P5, so as to meet the quantity requirement corresponding to the first constant voltage signal line 31 and improve the transmission reliability of the first power supply voltage PWM-vdd.

[0128] In some embodiments, Figure 2 As shown, the dimension L1 of the first constant voltage signal line 31 in the first direction X is greater than the dimension L2 of the voltage-dividing signal line 21 in the second direction Y.

[0129] The dimension L1 of the first constant voltage signal line 31 in the first direction X is the width of the first constant voltage signal line 31, and the dimension L2 of the voltage-dividing signal line 21 in the second direction Y is the width of the voltage-dividing signal line 21. In the embodiment of the present application, considering that the voltage-dividing signal line 21 can be arranged in the first conductor layer 20 together with a variety of control signal lines 22 and other signal lines, and the number and types of the control signal lines 22 are usually large, in order to reduce the occupation of the space where the control signal line 22 and other signal lines in the first conductor layer 20 are located by the existence of the voltage-dividing signal line 21, the width of the voltage-dividing signal line 21 is designed to be smaller. As for the first constant voltage signal line 31, since it can have a certain design space, its width can be designed to be greater than the width of the voltage-dividing signal line 21, so as to further reduce the resistance value of the mesh structure used to transmit the first power supply voltage PWM-vdd, and improve the transmission reliability of the first power supply voltage PWM-vdd.

[0130] In some embodiments, the dimension L1 of at least part of the first constant voltage signal line 31 in the first direction X is not less than 10 μm. Optionally, the dimension L1 of the first constant voltage signal line 31 in the first direction X is one of 10 μm, 15 μm, 20 μm, 50 μm and 80 μm.

[0131] In the embodiment of the present application, by setting the dimension of the first constant voltage signal line 31 in the first direction X to L1 not less than 10 μm, the first constant voltage signal line 31 can have a larger width dimension, thereby reducing the resistance value of the first constant voltage signal line 31, thereby reducing the transmission load of the first power supply voltage PWM-vdd, reducing the risk of signal delay, and improving the operating reliability of the pixel circuit P.

[0132] In some embodiments, 2.5 μm≤L2≤50 μm. Optionally, L2 is one of 2.5 μm, 5 μm, 10 μm, 20 μm and 50 μm.

[0133] In the embodiment of the present application, by setting the width of the voltage-dividing signal line 21 to no more than 50 μm, it helps to reduce the occupation of the space of the film layer where the voltage-dividing signal line 21 is located, and reduces the risk of contact interference between the voltage-dividing signal line 21 and other signal lines in the same layer, thereby improving the reliability of respective signal transmission. At the same time, the width of the voltage-dividing signal line 21 is set to no less than 2.5 μm, thereby reducing the problem of excessive resistance value caused by the small width of the voltage-dividing signal line 21, thereby improving the transmission reliability of the first power supply voltage PWM-vdd.

[0134] In some embodiments, Figure 2 As shown, the display panel 100 further includes a connection signal line 23 extending along the first direction X, and the connection signal line 23 is connected to the first constant voltage signal line 31. The connection signal line 23 overlaps with the orthographic projection of the pixel circuit P on the substrate 10, and the connection signal line 23 provides a high potential voltage to the pulse width modulation subcircuit P1.

[0135] The connecting signal line 23 is a signal line directly connected to the pixel circuit P in the display panel 100 to directly provide the first power supply voltage PWM-vdd to the pixel circuit P. Similar to the voltage-dividing signal line 21, the connecting signal line 23 also extends along the first direction X and is connected to the first constant voltage signal line 31. However, the difference is that the orthographic projection of the voltage-dividing signal line 21 on the substrate 10 is located outside the orthographic projection of the pixel circuit P on the substrate 10, while the orthographic projection of the connecting signal line 23 on the substrate 10 overlaps with the orthographic projection of the pixel circuit P on the substrate 10. According to different design layout conditions, the width of the connecting signal line 23 can be the same as the width of the voltage-dividing signal line 21, or can be less than or greater than the width of the voltage-dividing signal line 21.

[0136] In some optional embodiments, the connecting signal line 23 and the voltage-dividing signal line 21 are both located in the first conductor layer 20, and both include the same material and are prepared and formed together in the same process, thereby simplifying the preparation process of the connecting signal line 23 and the voltage-dividing signal line 21 and improving the preparation efficiency.

[0137] In the embodiment of the present application, the display panel 100 includes three signal lines, namely, a first constant voltage signal line 31, a voltage dividing signal line 21, and a connecting signal line 23, for transmitting the first power supply voltage PWM-vdd. The three can form a mesh structure together, thereby further reducing the transmission load corresponding to the first power supply voltage PWM-vdd and improving the operation reliability of the pixel circuit P. At the same time, the existence of the connecting signal line 23 allows the orthographic projection of the first constant voltage signal line 31 on the substrate 10 to be arranged without overlapping with the pixel circuit P, thereby reducing the risk of contact interference between the first constant voltage signal line 31 and some device structures in the pixel circuit P, which helps to improve the reliability of the respective signal transmission and the manufacturing yield of the display panel 100.

[0138] In some embodiments, the display panel 100 further includes a control signal line 22 extending along the first direction X, and the orthographic projections of the control signal line 22 and the connection signal line 23 on the substrate 10 overlap with the orthographic projections of the same pixel circuit P on the substrate 10 .

[0139] In the embodiment of the present application, the control signal line 22 and the connection signal line 23 are both directly connected to the pixel circuit P to directly provide the corresponding signal voltage to the pixel circuit P. Therefore, the orthographic projections of the control signal line 22 and the connection signal line 23 on the substrate 10 must pass through the orthographic projection of the pixel circuit P, and the two types of signal line routings need to overlap with the same pixel circuit P to meet the transmission needs of the corresponding signal of the pixel circuit P.

[0140] In some optional embodiments, since the connection signal line 23 and the connection signal line 23 are both overlapped with the same pixel circuit P, the distance between the connection signal line 23 and the control signal line 22 is often closer than that between the voltage-dividing signal line 21. On this basis, the width of the connection signal line 23 can be set to be smaller than the width of the voltage-dividing signal line 21, so as to meet the layout requirements of the connection signal line 23 and the control signal line 22, reduce the risk of contact interference between the two, and improve the reliability of their respective signal transmission.

[0141] In some embodiments, the control signal line 22 includes a first scanning signal line for transmitting a first type of scanning signal PWM-SCAN to the pulse width modulation sub-circuit P1, a first light-emitting control signal line for transmitting a first light-emitting control signal PWM-EM to the pulse width modulation sub-circuit P1, a second scanning signal line for transmitting a second type of scanning signal PAM-SCAN to the amplitude modulation sub-circuit P2, and a second light-emitting control signal line for transmitting a second light-emitting control signal PAM-EM to the amplitude modulation sub-circuit P2.

[0142] The control signal line 22 includes multiple types. The first scan signal line is a signal line for transmitting the first type of scan signal PWM-SCAN. Considering that the first type of scan signal PWM-SCAN includes a first scan signal PWM-S1 and a second scan signal PWM-S2, the first scan signal line will include a first scan sub-line for transmitting the first scan signal PWM-S1, and a second scan sub-line for transmitting the second scan signal PWM-S2.

[0143] The second scan signal line is a signal line for transmitting the second type of scan signal PAM-SCAN. Considering that the second type of scan signal PAM-SCAN includes a third scan signal PAM-S1 and a fourth scan signal PAM-S2, the second scan signal line will include a third scan sub-line for transmitting the third scan signal PAM-S1, and a fourth scan sub-line for transmitting the fourth scan signal PAM-S2.

[0144] The first light-emitting control signal line is a signal line for transmitting the first light-emitting control signal PWM-EM, and the second light-emitting control signal line is a signal line for transmitting the second light-emitting control signal PAM-EM. The first scanning signal line, the second scanning signal line, the first light-emitting control signal line, and the second light-emitting control signal line are all used to connect or multiplex as control terminals of different transistors in the pixel circuit P, so as to realize the control of turning off or on different transistors.

[0145] Furthermore, the first scanning signal line, the second scanning signal line, the first light-emitting control signal line and the second light-emitting control signal line are all arranged together with the connecting signal line 23 to overlap with multiple pixel circuits P in the same repeated circuit group C, so that the above-mentioned various types of control signal lines 22 and connecting signal lines 23 can be connected to the same pixel circuit P through vias and directly provide corresponding signal voltages to the same pixel circuit P, thereby meeting the normal operation needs of the pixel circuit P.

[0146] In some embodiments, Figure 1 As shown, the first constant voltage signal line 31 has a first avoidance hole H1 , and at least a portion of the orthographic projection of the first avoidance hole H1 on the substrate 10 is overlapped with the orthographic projection of the control signal line 22 on the substrate 10 .

[0147] The first avoidance hole H1 is a hole-shaped structure that penetrates the first constant voltage signal line 31. According to different actual needs, the number of the first avoidance hole H1 is one, or the number of the first avoidance hole H1 can also be multiple. When the number of the first avoidance holes H1 is multiple, different first avoidance holes H1 can be arranged along the first direction X, or can also be arranged along the second direction Y, or can also be arranged along the first direction X and the second direction Y at the same time. And the size and shape of the orthographic projection of different first avoidance holes H1 on the substrate 10 can be consistent, or there can be differences, which is not limited in the embodiments of the present application.

[0148] The first avoidance hole H1 is set corresponding to the control signal line 22. The control signal line 22 can have various types of signal routing. On this basis, a single first avoidance hole H1 can have various position forms relative to the control signal line 22. For example, at least part of the first avoidance hole H1 can be set to overlap with only one control signal line 22, or at least part of the first avoidance hole H1 can also be set to overlap with multiple control signal lines 22.

[0149] In the embodiment of the present application, considering that the first constant voltage signal line 31 and the control signal line 22 are respectively used to transmit different signals and the corresponding extension directions of the two intersect, a first avoidance hole H1 is provided in the first constant voltage signal line 31, and the first avoidance hole H1 is overlapped with the control signal line 22, thereby reducing the overlapping area between the first constant voltage signal line 31 and the control signal line 22, reducing the parasitic capacitance generated by the overlap between the two, and improving the reliability of their respective signal transmission.

[0150] In some embodiments, see Fig.11 , at least a portion of the orthographic projection of the first avoidance hole H1 on the substrate 10 is overlapped with the orthographic projection of the plurality of control signal lines 22 on the substrate 10 .

[0151] In the embodiment of the present application, at least part of the first avoidance hole H1 can have a larger size in the second direction Y, so as to overlap with multiple control signal lines 22 in the second direction Y at the same time. The design of the first avoidance hole H1 with a larger size can reduce the difficulty of forming the first avoidance hole H1 while reducing the crosstalk problem between the first constant voltage signal line 31 and the multiple control signal lines 22.

[0152] In some embodiments, the first avoidance holes H1 include first-type avoidance holes H11 and second-type avoidance holes H12 , and the orthographic projection area of ​​the first-type avoidance holes H11 on the substrate 10 is larger than the orthographic projection area of ​​the second-type avoidance holes H12 on the substrate 10 .

[0153] The number of the first avoidance holes H1 is multiple, and includes first-type avoidance holes H11 with larger sizes and second-type avoidance holes H12 with smaller sizes, wherein the size of the first-type avoidance holes H11 in the first direction X can be larger than the size of the second-type avoidance holes H12 in the first direction X; and / or, the size of the first-type avoidance holes H11 in the second direction Y can be larger than the size of the second-type avoidance holes H12 in the second direction Y.

[0154] In addition, the orthographic projection of the first type of avoidance hole H11 on the substrate 10 can be arranged to overlap with only one control signal line 22, or can also be arranged to overlap with multiple control signal lines 22 at the same time. And the orthographic projection of the second type of avoidance hole H12 on the substrate 10 can also be arranged to overlap with only one control signal line 22, or can also be arranged to overlap with multiple control signal lines 22 at the same time. Of course, in other cases, at least one of the first type of avoidance hole H11 and the second type of avoidance hole H12 may not be arranged to overlap with the control signal line 22, but may be arranged to overlap with other signal lines or be used to play other roles, which can also improve the reliability of signal transmission in the first constant voltage signal line 31.

[0155] In the embodiment of the present application, the plurality of first avoidance holes H1 include large-sized first-type avoidance holes H11, thereby reducing the difficulty of hole formation through the first-type avoidance holes H11 and improving the manufacturing yield of the display panel 100. It also includes small-sized second-type avoidance holes H12, thereby reducing the adverse effect on the resistance of the first constant voltage signal line 31 as much as possible through the second-type avoidance holes H12, thereby further improving the reliability of signal transmission.

[0156] In some embodiments, the orthographic projection of the first type avoidance hole H11 on the substrate 10 overlaps with g control signal lines 22 , and the orthographic projection of the second type avoidance hole H12 on the substrate 10 overlaps with f control signal lines 22 ; wherein g>f≥1.

[0157] Optionally, the size of the first type of avoidance hole H11 in the second direction Y is larger than the size of the first type of avoidance hole H11 in the second direction Y, and the orthographic projection of the first type of avoidance hole H11 on the substrate 10 overlaps with the orthographic projection of multiple control signal lines 22 on the substrate 10, while the orthographic projection of the second type of avoidance hole H12 on the substrate 10 only overlaps with the orthographic projection of a single control signal line 22 on the substrate 10.

[0158] In the embodiment of the present application, the first type of avoidance hole H11 and the second type of avoidance hole H12 are both arranged to overlap with at least one control signal line 22, thereby reducing the signal crosstalk problem between the first constant voltage signal line 31 and the control signal line 22. At the same time, the number of control signal lines 22 overlapping with the first type of avoidance hole H11 is set to be greater than the number of control signal lines 22 overlapping with the second type of avoidance hole H12, so as to match the sizes of the two with the number of overlapping control signal lines 22 as much as possible, thereby improving the reliability of the design layout of the display panel 100.

[0159] In some embodiments, the orthographic projection of a portion of the first avoidance hole H1 on the substrate 10 is located outside the orthographic projection of the control signal line 22 on the substrate 10, that is, the orthographic projection of a portion of the first avoidance hole H1 on the substrate 10 overlaps with the orthographic projection of the control signal line 22 on the substrate 10, and the orthographic projection of a portion of the first avoidance hole H1 on the substrate 10 does not overlap with the orthographic projection of the control signal line 22 on the substrate 10.

[0160] It should be noted that the portion of the first avoidance hole H1 that does not overlap with the orthographic projection of the control signal line 22 on the substrate 10 may overlap with other signal lines, or may not overlap with other signal lines, and the embodiment of the present application is not limited to this.

[0161] In the embodiment of the present application, since the control signal line 22 is usually arranged to overlap with the pixel circuit P, the part of the first avoidance hole H1 arranged to overlap with the control signal line 22 will be located between adjacent pixel circuits P along the first direction X. For the area located between adjacent pixel circuits P in the second direction Y, the control signal line 22 is usually not provided. However, in the embodiment of the present application, the first avoidance hole H1 can be selected to be provided in the area, so that the multiple first avoidance holes H1 can be arranged at intervals along a specific regular pattern in the second direction Y, which helps to reduce the difficulty of forming the multiple first avoidance holes H1 and improve the manufacturing yield of the display panel 100.

[0162] In some embodiments, Figure 1 and Fig.11 As shown, the voltage-dividing signal line 21 has a second avoidance hole H2; and / or the connecting signal line 23 has a third avoidance hole H3.

[0163] Similar to the first avoidance hole H1, a second avoidance hole H2 can also be provided on the voltage-dividing signal line 21, and the second avoidance hole H2 can reduce the risk of signal crosstalk between the voltage-dividing signal line 21 and other signal lines. The number of the second avoidance hole H2 can be one or more, and when the number of the second avoidance holes H2 is more than one, the sizes and shapes of different second avoidance holes H2 can be the same, or there can be differences.

[0164] Similarly, a third avoidance hole H3 can also be provided on the connection signal line 23, and the third avoidance hole H3 can reduce the risk of signal crosstalk between the connection signal line 23 and other signal lines. The number of the third avoidance holes H3 can be one or more. When the number of the third avoidance holes H3 is more than one, the sizes and shapes of different third avoidance holes H3 can be the same, or they can be different.

[0165] Of course, in other embodiments, a fourth avoidance hole H4 may also be provided on the control signal line 22 to reduce the risk of signal crosstalk between the control signal line 22 and other signal lines through the fourth avoidance hole H4.

[0166] It should be noted that when the first avoidance hole H1 and the fourth avoidance hole H4 exist at the same time, there may be a variety of positional relationships between the first avoidance hole H1 and the fourth avoidance hole H4, for example, the first avoidance hole H1 may overlap with the fourth avoidance hole H4, or the two may not overlap, and the embodiment of the present application does not limit this. Optionally, the orthographic projection of the fourth avoidance hole H4 on the substrate 10 is located outside the orthographic projection of the first avoidance hole H1 on the substrate 10, and the orthographic projection of the fourth avoidance hole H4 on the substrate 10 overlaps with the orthographic projection of at least one of the data signal line and the frequency sweeping signal line 34 on the substrate 10.

[0167] In the embodiment of the present application, by providing at least one of the second avoidance hole H2 and the third avoidance hole H3, it helps to reduce the risk of signal crosstalk between the voltage-dividing signal line 21 or the connecting signal line 23 and other signal lines, thereby further improving the reliability of signal transmission of various signal lines inside the display panel 100.

[0168] Second, see Fig.12 An embodiment of the present application provides a display device 200, and the display device 200 includes a display panel in any of the aforementioned embodiments.

[0169] It should be noted that the display device 200 provided in the embodiment of the present application has the beneficial effects of the display panel in any of the aforementioned embodiments. Please refer to the aforementioned description of the beneficial effects of the display panel for details, and the embodiment of the present application will not be repeated.

[0170] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted for facilitating the understanding of this application and are not intended to limit the present invention. Any technician in the technical field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be subject to the scope defined in the attached claims.

[0171] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel circuits, each of which includes an amplitude modulation subcircuit and a pulse width modulation subcircuit. The display panel also includes: substrate; A voltage-dividing signal line, located at one side of the substrate, and extending along a first direction; a first constant voltage signal line, located at one side of the substrate, extending along a second direction and used to transmit a high potential voltage to the pulse width modulation subcircuit, the first direction intersecting with the second direction; Wherein, the plurality of first constant voltage signal lines are electrically connected to the plurality of divided voltage signal lines.

2. The display panel according to claim 1, characterized in that: The display panel includes a first conductor layer located at one side of the substrate, the first conductor layer includes a control signal line and the voltage-dividing signal line extending along the first direction, and the control signal line and the voltage-dividing signal line are arranged in the second direction.

3. The display panel according to claim 2, characterized in that: It also includes a second conductor layer disposed on a side of the first conductor layer away from the substrate, and the first constant voltage signal line is located in the second conductor layer.

4. The display panel according to claim 3, characterized in that: The second conductor layer further includes a first data signal line and a second data signal line, the first data signal line is used to transmit a first data signal to the pulse width modulation subcircuit, and the second data signal line is used to transmit a second data signal to the amplitude modulation subcircuit; The first data signal line and the second data signal line both extend along the second direction, and the first constant voltage signal line, the first data signal line and the second data signal line are arranged in the first direction.

5. The display panel according to claim 1, characterized in that: The orthographic projection of the voltage-dividing signal line on the substrate is located outside the orthographic projection of the pixel circuit on the substrate.

6. The display panel according to claim 5, characterized in that: A plurality of the pixel circuits arranged in the second direction form a circuit column, and at least part of the orthographic projections of the first constant voltage signal lines on the substrate are located between the orthographic projections of adjacent circuit columns on the substrate; And / or, a plurality of the pixel circuits arranged in the first direction form a circuit row, and orthographic projections of at least part of the voltage-dividing signal lines on the substrate are located between orthographic projections of adjacent circuit rows on the substrate.

7. The display panel according to claim 6, characterized in that: It also includes a first data signal line and a second data signal line extending along the second direction, wherein at least part of the orthographic projections of the first data signal line and the second data signal line on the substrate are located between the orthographic projections of adjacent circuit columns on the substrate; Among them, the distance between the circuit column and the first data signal line electrically connected thereto in the first direction is smaller than the distance between the circuit column and the first constant voltage signal line in the first direction; and / or the distance between the circuit column and the second data signal line electrically connected thereto in the first direction is smaller than the distance between the circuit row and the first constant voltage signal line in the first direction.

8. The display panel according to claim 7, characterized in that: The first constant voltage signal line, the first data signal line and the second data signal line are arranged between at least some of the adjacent circuit columns, the first data signal line and the second data signal line are arranged on both sides of the first constant voltage signal line along the first direction, and the first data signal line and the second data signal line are respectively electrically connected to the pixel circuits in the adjacent circuit columns.

9. The display panel according to claim 7, characterized in that: The display panel includes a repeated circuit group, the repeated circuit group includes a plurality of the pixel circuits, and the plurality of repeated circuit groups are repeatedly arranged in the first direction and the second direction; The first data signal line includes a plurality of first sub-data lines, and the plurality of first sub-data lines are electrically connected to different pixel circuits in the same repeated circuit group respectively; The second data signal line includes a plurality of second sub-data lines, and the plurality of second sub-data lines are respectively electrically connected to different pixel circuits in the same repeating circuit group.

10. The display panel according to claim 7, characterized in that: It also includes a frequency sweep signal line extending along the second direction, the frequency sweep signal line is used to transmit the frequency sweep signal to the amplitude modulation sub-circuit, and the frequency sweep signal line, the first constant voltage signal line, the first data signal line and the second data signal line are arranged in the first direction.

11. The display panel according to claim 10, characterized in that: At least part of the frequency scanning signal lines are located between the first data signal line and the first constant voltage signal line which are closest to each other, and the frequency scanning signal lines and the first data signal lines are electrically connected to the same pixel circuit; and / or, At least part of the frequency scanning signal lines are located between the second data signal line and the first constant voltage signal line which are closest to each other, and the frequency scanning signal lines and the second data signal lines are electrically connected to the same pixel circuit.

12. The display panel according to claim 11, characterized in that: The frequency scanning signal lines include a first type of frequency scanning lines, a second type of frequency scanning lines and a third type of frequency scanning lines, wherein the first type of frequency scanning lines, the second type of frequency scanning lines and the third type of frequency scanning lines are used to drive the pixel circuits located in different rows along the second direction; The first type of scanning frequency line is located between the first data signal line and the first constant voltage signal line which are closest to each other, and the second type of scanning frequency line and the third type of scanning frequency line are located between the second data signal line and the first constant voltage signal line which are closest to each other.

13. The display panel according to claim 6, characterized in that: The number of the circuit rows between at least some adjacent voltage-divided signal lines is the same.

14. The display panel according to claim 13, characterized in that: At least some of the adjacent voltage-dividing signal lines have the same spacing in the second direction.

15. The display panel according to claim 6, characterized in that: In the second direction, N circuit rows are arranged between at least some of the adjacent voltage-dividing signal lines, where N≥1; and / or, In the second direction, M voltage-dividing signal lines are arranged between at least some of the adjacent circuit rows, where M≥1.

16. The display panel according to claim 1, characterized in that: The display panel includes a repeating circuit group, the repeating circuit group includes a plurality of the pixel circuits, the plurality of the repeating circuit groups are repeatedly arranged in the first direction and the second direction, and the plurality of the repeating circuits arranged in the second direction form a circuit group column; Wherein, the first constant voltage signal line is arranged between at least some of the adjacent circuit group columns.

17. The display panel according to claim 16, characterized in that: The circuit group includes i circuit group arrays spaced apart in the first direction, the first constant voltage signal line is not arranged in an area corresponding to the first circuit group array and the second circuit group array, and the first constant voltage signal line is arranged in an area on one side of the first circuit group array away from the other circuit group arrays; and / or, The first constant voltage signal line is not disposed in the region between the i-1th circuit group column and the i-th circuit group column, and the first constant voltage signal line is disposed in the region on one side of the i-th circuit group column away from the other circuit groups.

18. The display panel according to claim 1, characterized in that: A size L1 of the first constant voltage signal line in the first direction is greater than a size L2 of the divided voltage signal line in the second direction.

19. The display panel according to claim 18, characterized in that: A dimension L1 of at least a portion of the first constant-voltage signal line in the first direction is not less than 10 μm.

20. The display panel according to claim 18, characterized in that: 2.5μm≤L2≤50μm.

21. The display panel according to claim 1, characterized in that: It also includes a connection signal line extending along the first direction, wherein the connection signal line is connected to the first constant voltage signal line; The connecting signal line overlaps with the orthographic projection of the pixel circuit on the substrate, and the connecting signal line provides the high potential voltage to the pulse width modulation subcircuit.

22. The display panel according to claim 21, characterized in that: It also includes a control signal line extending along the first direction, wherein the orthographic projections of the control signal line and the connection signal line on the substrate overlap with the orthographic projection of the same pixel circuit on the substrate.

23. The display panel according to claim 22, characterized in that: The control signal line includes a first scanning signal line for transmitting a first type of scanning signal to the pulse width modulation sub-circuit, a first light-emitting control signal line for transmitting a first light-emitting control signal to the pulse width modulation sub-circuit, a second scanning signal line for transmitting a second type of scanning signal to the amplitude modulation sub-circuit, and a second light-emitting control signal line for transmitting a second light-emitting control signal to the amplitude modulation sub-circuit.

24. The display panel according to claim 22, characterized in that: The first constant voltage signal line has a first avoidance hole, and at least a portion of the first avoidance hole is disposed such that an orthographic projection of the substrate overlaps with an orthographic projection of the control signal line on the substrate.

25. The display panel according to claim 24, characterized in that: At least part of the first avoidance holes are arranged to overlap with the orthographic projections of the plurality of control signal lines on the substrate.

26. The display panel according to claim 24, characterized in that: The first avoidance holes include first-type avoidance holes and second-type avoidance holes, and the orthographic projection area of ​​the first-type avoidance holes on the substrate is larger than the orthographic projection area of ​​the second-type avoidance holes on the substrate.

27. The display panel according to claim 26, characterized in that: The first type of avoidance holes are arranged so that the orthographic projection of the substrate overlaps with g control signal lines, and the second type of avoidance holes are arranged so that the orthographic projection of the substrate overlaps with f control signal lines; Among them, g>f≥1.

28. The display panel according to claim 24, characterized in that: The orthographic projection of a portion of the first avoidance holes on the substrate is located outside the orthographic projection of the control signal line on the substrate.

29. The display panel according to claim 22, characterized in that: The voltage-dividing signal line has a second avoidance hole; and / or the connecting signal line has a third avoidance hole.

30. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 29.

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