Driving circuit, display device, in-cell touch panel device, and control device

Abstract

A driving circuit, a display device, an in-cell touch panel device, and a control device of the driving circuit capable of arbitrarily setting presence or absence of stop of operation of the driving circuit by a latch circuit are provided. A gate driving circuit (20) includes a plurality of unit circuits (21), a latch circuit (22), and a connection circuit (23). The latch circuit (22) is connected in parallel to the plurality of unit circuits (21). When a TPC signal is input, the connection circuit (23) resets the unit circuits (21) constituting an n-th stage and an n+1-th stage, and stops operation of the gate driving circuit (20). When an RSM signal is input, the latch circuit charges a node (N1) of the n+1-th stage unit circuit (21) via a transistor (T5) of the connection circuit (23), and starts the operation of the gate driving circuit (20) again.

Description

Technical Field

[0001] This disclosure relates to drive circuits, display devices, embedded touch panel devices, and control devices for drive circuits. Background Technology

[0002] Patent Document 1 discloses a drive circuit capable of stopping operation midway through a scan. The drive circuit (shift register) includes multiple unit circuits, each constituting multiple stages. The multiple unit circuits include: a first unit circuit that outputs shift pulses to the gate bus and subsequent stages; and a second unit circuit that outputs shift pulses to subsequent stages. The second unit circuit includes a transistor having a first electrode connected to a subsequent stage and an internal node connected to the control electrode of that transistor. The potential of the internal node is continuously maintained at a high level during the period when the drive circuit stops operating. Then, slightly before the moment when the operation of the drive circuit is to restart, the level of the signal supplied to the second electrode of the transistor becomes high. Thus, by the transistor being turned on by the internal node maintaining a high level, a shift pulse is output to the subsequent stage, restarting the operation of the drive circuit. Existing technical documents Patent documents

[0003] Patent Document 1: International Publication No. 2017 / 006815 Summary of the Invention The problem the invention aims to solve

[0004] In the drive circuit described in Patent Document 1, the first unit circuit and the second unit circuit (latch circuit) are connected in series, and the latch circuit constitutes part of a multi-stage circuit. Therefore, in the existing drive circuit, the operation will inevitably stop in the latch circuit, and thus the presence or absence of the stop of the drive circuit's operation cannot be arbitrarily set through the latch circuit.

[0005] Therefore, this disclosure was made to solve the above-mentioned problems, and its purpose is to provide a drive circuit, a display device, an embedded touch panel device, and a control device for the drive circuit that can arbitrarily set the presence or absence of the stop of the operation of the drive circuit through a latching circuit. Solution to the problem

[0006] To address the aforementioned issues, the driving circuit in the first aspect of this disclosure comprises multiple stages. In response to the input of multiple clock signals, it supplies driving signals to the scan signal line group. The driving circuit includes: multiple unit circuits constituting each stage of the multiple stages and outputting the driving signals; a latching circuit connected in parallel with the multiple unit circuits; and a connection circuit connected to the output node of the latching circuit. The latching circuit receives a first output signal from a first unit circuit as a first set signal. The first unit circuit constitutes the first stage of the multiple unit circuits. After receiving the first set signal, the latching circuit is input to restart the operation of the driving circuit. When the first control signal is received, a latch circuit output signal is output to the connection circuit via the output node. The latch circuit is input with a second output signal from the second unit circuit as a first reset signal. The second unit circuit constitutes the second stage of the plurality of unit circuits, which is a stage following the first stage. The connection circuit includes: a reset circuit that resets the first unit circuit and the third unit circuit in response to the input of a second control signal that stops the operation of the drive circuit. The third unit circuit constitutes the next stage of the plurality of unit circuits after the first stage; and a set circuit that supplies the latch circuit output signal as a second set signal to the third unit circuit.

[0007] The display device involved in the second method includes: the driving circuit involved in the first method described above; and a display that is configured with the scanning signal line group.

[0008] The embedded touch panel device involved in the third approach includes: the driving circuit involved in the first approach described above; and an embedded touch panel configured with the scanning signal line group, which detects touch based on an indicator during the period when the operation of the driving circuit stops.

[0009] The control device for the drive circuit involved in the third method is a control device that supplies the plurality of clock signals, the first control signal, and the second control signal to the drive circuit involved in the first method. The drive circuit includes: a plurality of latch circuits, which are arranged in parallel with the plurality of unit circuits; and a plurality of connection circuits, which are respectively connected to the output nodes of the plurality of latch circuits. In the control device of the drive circuit, an action connection circuit is determined from the plurality of connection circuits, and the second control signal is not supplied to the connection circuits other than the action connection circuit, but the second control signal is supplied to the action connection circuit. Invention Effects

[0010] Based on the above configuration, since the latch circuit is connected in parallel with multiple unit circuits, if a second control signal is not supplied to the drive circuit to stop its operation, the drive circuit can continue operating without stopping within the latch circuit. Furthermore, if the second control signal is supplied to the drive circuit, its operation can be stopped; if the first control signal is supplied, its operation can be restarted. As a result, the latch circuit can arbitrarily set whether the operation of the drive circuit is stopped or not. Attached Figure Description

[0011] Figure 1 This is a block diagram showing the configuration of the display device 100 according to the first embodiment. Figure 2 This is a schematic circuit diagram showing the configuration of the display unit 10. Figure 3 This is a diagram showing the configuration of touch panel 1. Figure 4 This is a diagram showing the configuration of a portion of the gate drive circuit 20. Figure 5 It is the circuit diagram of the unit circuit 21 that constitutes the levels other than the nth and n+1th levels. Figure 6 This is a circuit diagram showing a portion of the nth unit circuit 21 and the connecting circuit 23. Figure 7 This is a circuit diagram showing a portion of the (n+1)th unit circuit 21 and the connecting circuit 23. Figure 8 This is a circuit diagram showing the configuration of latch circuit 22. Figure 9 This is a timing diagram of each signal in the gate drive circuit 20 based on the non-stop drive. Figure 10 This is a timing diagram of each signal in the gate drive circuit 20 with stop drive. Figure 11 This is a block diagram of a display device 200 based on the second embodiment. Figure 12 This is a diagram showing the configuration of the gate drive circuit 220 of the display device 200 based on the second embodiment. Figure 13 This is a timing diagram when the gate drive circuit 220 based on the second embodiment performs uninterrupted drive. Figure 14 This is a timing diagram when the gate drive circuit 220 based on the second embodiment performs a stop drive. Figure 15 This is a timing diagram of a display device based on a variation of the second embodiment. Figure 16 This is a block diagram of a display device 300 based on the third embodiment. Figure 17 This is a diagram showing the configuration of the gate drive circuit 320 of the display device 300 based on the third embodiment. Figure 18 It is a timing diagram related to the operation of circuits other than the operating circuit based on the third embodiment. Figure 19 It is a timing diagram related to the operation of the operating circuit based on the third embodiment. Detailed Implementation

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same or equivalent parts as those in the drawings will be labeled with the same reference numerals, and their descriptions will not be repeated. Furthermore, in the drawings referred to below, the structure is shown in a simplified or schematic manner to facilitate understanding, or some components may be omitted. Additionally, the dimensional ratios between the components shown in the figures do not necessarily represent actual dimensional proportions.

[0013] [First Implementation Method] (Overall structure of the display device) The configuration of the display device 100 based on the first embodiment will be described. Figure 1 This is a block diagram showing the configuration of the display device 100 according to the first embodiment. Figure 2 This is a schematic circuit diagram showing the configuration of the display unit 10. Figure 3 This is a diagram showing the configuration of touch panel 1.

[0014] like Figure 1 As shown, the display device 100 includes a touch panel 1 and a control circuit 2. In the first embodiment, the touch panel 1 is configured as an embedded touch panel that performs touch detection and image display functions. That is, the touch panel 1 also functions as a display. Furthermore, in the first embodiment, the display device 100 is an embedded touch panel device.

[0015] The control circuit 2 includes a processor that performs control processing on the display device 100. Furthermore, the control circuit 2 sends control signals to the touch panel 1 based on the input image signal. The touch panel 1 displays the image based on the control signals. Additionally, the control circuit 2 sends a touch detection command to the touch panel 1 and receives information indicating the touch coordinates of the indicator from the touch panel 1 (hereinafter referred to as "touch detection processing"). Moreover, within one frame period, the control circuit 2 performs display processing that causes the gate drive circuit 20 to operate and touch detection processing in a time-division multiplexing manner. That is, one frame period includes a touch detection period TP (refer to...) which is the period for performing touch detection processing. Figure 10) and the display period TD (refer to) during the display processing. Figure 7 The control circuit 2 performs multiple touch detection processes, for example, during one frame. Furthermore, during the touch detection process, the operation of the gate drive circuit 20 is suspended. Additionally, the suspension period TR (refer to...) is the period during which the operation of the gate drive circuit 20 is suspended. Figure 10 This includes TP during touch detection.

[0016] Furthermore, in the first embodiment, the control circuit 2 is configured to execute a state that prevents the operation of the gate drive circuit 20 from being stopped (see reference). Figure 9 ) and the state of the interruption period TR during which the operation of the gate drive circuit 20 is suspended for one frame (refer to Figure 10 The control circuit 2 controls the switching of the touch panel 1. For example, when the touch panel 1 is used as a display without touch detection function, the control circuit 2 controls the operation of the gate drive circuit 20 without stopping it (hereinafter referred to as "no-stop drive"). When the touch detection function of the touch panel 1 is used, the control circuit 2 controls the operation of the gate drive circuit 20 to stop during the stop period TR in a frame (hereinafter referred to as "stop drive").

[0017] like Figure 1 As shown, the touch panel 1 includes a display unit 10, a gate driving circuit 20, a source driving circuit 30, and a touch detection control circuit 40. Furthermore, in Figure 1 The diagram illustrates a gate drive circuit 20, a source drive circuit 30, and a touch detection control circuit 40 disposed within a touch panel 1. However, at least one of these circuits can also be disposed on other substrates located outside the touch panel 1. In this case, at least one of the touch panel 1, the gate drive circuit 20, the source drive circuit 30, and the touch detection control circuit 40 is connected via wiring or a flexible printed circuit board.

[0018] like Figure 2 As shown, the display unit 10 includes multiple gate lines 11, multiple source lines 12, multiple transistors 13, multiple pixel electrodes 14, and multiple common electrodes 15. The multiple gate lines 11 intersect with the multiple source lines 12 when viewed from above. Furthermore, in each region divided by the multiple gate lines 11 and the multiple source lines 12, transistors 13 and pixel electrodes 14 are arranged. Each transistor 13 includes a gate electrode 13a, a source electrode 13b, and a drain electrode 13c. The gate electrode 13a is connected to the gate line 11. The source electrode 13b is connected to the source line 12. The drain electrode 13c is connected to the pixel electrode 14. The multiple gate lines 11 are an example of a scan signal line group. Furthermore, in... Figure 2The example shown is that the gate drive circuit 20 is arranged on one side of the display unit 10, but the gate drive circuit 20 can also be arranged on both sides of the display unit 10.

[0019] A gate driving circuit 20 is formed on the substrate of the touch panel 1 (formed as a monolithic chip). The gate driving circuit 20 sequentially outputs gate signals to a plurality of gate lines 11. A source driving circuit 30 is mounted on the substrate of the touch panel 1. The source driving circuit 30 receives an image signal and a source control signal output from the control circuit 2, and generates a source signal (data signal) based on the image signal and the source control signal. Then, the source driving circuit 30 supplies a source signal to each of the plurality of source lines 12. Then, when a gate signal is supplied to the transistor 13 (when it becomes a gate on voltage), the source signal is written to the pixel electrode 14 via the transistor 13. As a result, an electric field is generated between the pixel electrode 14 and the common electrode 15, driving a liquid crystal layer (not shown) to display an image on the touch panel 1.

[0020] like Figure 3 As shown, multiple common electrodes 15 are configured, for example, in a matrix. A touch detection control circuit 40 is connected to each of the multiple common electrodes 15 via wiring 16. The common electrodes 15 undergo electrostatic capacitance changes through capacitive coupling with the indicator. During touch detection processing (touch detection period TP), the touch detection control circuit 40 supplies touch drive signals (pulse signals) to the multiple common electrodes 15. The waveform of the pulse signal varies according to the magnitude of the electrostatic capacitance of the common electrodes 15. The touch detection control circuit 40 detects touch (touch position) based on the waveform of the pulse signal from the common electrodes 15. That is, the common electrodes 15 also serve as touch detection electrodes. The touch panel 1 is a self-capacitance type touch panel. Furthermore, not limited to this example, the touch panel 1 may also be configured as a mutual capacitance type touch panel.

[0021] (Configuration of gate drive circuit 20) Next, refer to Figures 4 to 8 The configuration of the gate drive circuit 20 will be explained. Figure 4 This is a diagram showing the configuration of a portion of the gate drive circuit 20. Figure 5 It is the circuit diagram of the unit circuit 21 that constitutes the levels other than the nth and n+1th levels. Figure 6 This is a circuit diagram showing a portion of the nth unit circuit 21 and the connecting circuit 23. Figure 7 This is a circuit diagram showing a portion of the (n+1)th unit circuit 21 and the connecting circuit 23. Figure 8 This is a circuit diagram showing the configuration of latch circuit 22.

[0022] like Figure 4As shown, the gate drive circuit 20 includes a shift register circuit 20a, which is composed of multiple stages and supplies gate signals to multiple gate lines 11 in response to the input of multiple clock signals. Figure 4 The diagram illustrates the nth level (n is a natural number), the three levels preceding the nth level, and the four levels following the nth level. Additionally, Figure 4 This shows a connection example where two-phase clock signals (GCK1 and GCK2 signals) are input to shift register circuit 20a.

[0023] <Construction of Unit Circuit 21> The shift register circuit 20a comprises multiple unit circuits 21 that form a multi-stage structure. For example... Figure 5 As shown, the unit circuit 21 includes transistors T1 to T3, capacitor C1, and node N1.

[0024] The gate and drain electrodes of transistor T1 are connected to terminal S, which receives the set signal. The source electrode of transistor T1 is connected to node N1. That is, transistor T1 is connected to the diode at terminal S and node N1. Thus, when a set signal is input, transistor T1 charges node N1.

[0025] The drain electrode of transistor T2 is connected to node N1. The source electrode of transistor T2 is supplied with a VSS signal having a reference potential (low potential). The gate electrode of transistor T2 is connected to terminal R, which receives a reset signal. Thus, transistor T2 discharges from node N1 when a reset signal is input.

[0026] The drain electrode of transistor T3 is connected to the terminal GCK where the input clock signal is received. The gate electrode of transistor T3 is connected to node N1. The source electrode of transistor T3 is connected to the terminal Q where the output signal (gate signal G) is received. Furthermore, in... Figure 4 In this context, the gate signal output from the unit circuit 21 constituting the (n-3)th stage is recorded as "Gn-3".

[0027] Capacitor C1 is connected between the gate electrode and the source electrode of transistor T3. Capacitor C1 stores charge when node N1 is charged. Capacitor C1 is a bootstrap capacitor. That is, when a clock signal is input to the drain electrode of transistor T3, the potential of the source electrode of transistor T3 rises, and the potential of node N1 rises due to the charge in capacitor C1 (bootstrap).

[0028] like Figure 4 As shown, the output signal of unit circuit 21 is output to gate line 11 as gate signal G, and is simultaneously input to terminal S of unit circuit 21 constituting the next stage as set signal, and input to terminal R of unit circuit 21 constituting the previous stage as reset signal.

[0029] Furthermore, "level n" is an example of the "first level" of this disclosure. Additionally, "level n+1" is an example of the "second level" of this disclosure. Furthermore, "the unit circuit constituting level n" is an example of the "first unit circuit" of this disclosure. Furthermore, "the unit circuit constituting level n+1" is an example of both the "second unit circuit" and the "third unit circuit" of this disclosure. Furthermore, "the unit circuit constituting level n+2" is an example of the "fourth unit circuit" of this disclosure.

[0030] <Construction of Connection Circuit 23> like Figure 6 As shown, the connection circuit 23 includes a transistor T4a. The drain electrode of transistor T4a is connected to node N1 of the unit circuit 21 constituting the nth stage. The source electrode of transistor T4a is supplied with a VSS signal. The gate electrode of transistor T4a is connected to the terminal TPC, which is the signal input when the operation of the gate drive circuit 20 is stopped. Thus, if a TPC signal is input to transistor T4a, discharge occurs from node N1 of the unit circuit 21 constituting the nth stage, and the unit circuit 21 constituting the nth stage is reset. Furthermore, the "TPC signal" is an example of the "second control signal" of this disclosure. Additionally, transistor T4a is an example of the "reset circuit" of this disclosure.

[0031] like Figure 4 As shown, the output signal of the unit circuit 21 constituting the nth stage is output to the gate line 11 as a gate signal Gn, and simultaneously input to the terminal S of the unit circuit 21 constituting the (n+1)th stage as a set signal, and input to the terminal R of the unit circuit 21 constituting the (n-1)th stage as a reset signal. Furthermore, the output signal of the unit circuit 21 constituting the nth stage is also input to the terminal Lset of the latch circuit 22 as a set signal.

[0032] like Figure 7 As shown, the connection circuit 23 includes transistors T4b and T5. The drain electrode of transistor T4b is connected to node N1 of the unit circuit 21 constituting the (n+1)th stage. The source electrode of transistor T4b is supplied with a VSS signal. The gate electrode of transistor T4b is connected to terminal TPC. Thus, if a TPC signal is input to transistor T4b, discharge occurs from node N1 of the unit circuit 21 constituting the (n+1)th stage, and the unit circuit 21 constituting the (n+1)th stage is reset. Furthermore, transistor T4b is an example of the "reset circuit" of this disclosure. Additionally, transistor T5 is an example of the "set circuit" of this disclosure.

[0033] The gate and drain electrodes of transistor T5 are connected to the terminal Lout, which outputs the output signal from latch circuit 22. The source electrode of transistor T5 is connected to node N1. That is, transistor T5 is connected to the diode at terminal Lout and node N1. Thus, when the output signal is output from latch circuit 22, transistor T5 charges node N1.

[0034] like Figure 4 As shown, the output signal of the unit circuit 21 constituting the (n+1)th stage is output to the gate line 11 as the gate signal Gn+1, and simultaneously input to the terminal S of the unit circuit 21 constituting the (n+2)th stage as a set signal, and input to the terminal R of the unit circuit 21 constituting the nth stage as a reset signal. Furthermore, the output signal of the unit circuit 21 constituting the (n+1)th stage is also input to the terminal Lrst of the latch circuit 22 as a reset signal.

[0035] <Construction of latch circuit 22> like Figure 4 As shown, the latch circuit 22 is connected in parallel with multiple unit circuits 21. That is, the output signal from the unit circuit 21 constituting the nth stage is input to the latch circuit 22, and also to the unit circuit 21 constituting the (n+1)th stage. Then, the output signal from the unit circuit 21 constituting the (n+1)th stage is input to the latch circuit 22, and also to the unit circuit 21 constituting the (n+2)th stage.

[0036] like Figure 8 As shown, the latch circuit 22 includes transistors T1L to T3L, capacitor C1L, and node N1L.

[0037] The gate and drain electrodes of transistor T1L are connected to terminal Lset, which receives the set signal. The source electrode of transistor T1L is connected to node N1L. That is, transistor T1L is connected to the diodes at terminal Lset and node N1L. Thus, when a set signal is input, transistor T1L charges node N1L.

[0038] The drain electrode of transistor T2L is connected to node N1L. The source electrode of transistor T2L is supplied with a VSS signal having a reference potential (low potential). The gate electrode of transistor T2L is connected to the terminal Lrst where a reset signal is input. Thus, transistor T2L discharges from node N1L when a reset signal is input.

[0039] The drain electrode of transistor T3L is connected to the terminal RSM, which receives the input RSM signal to restart the operation of the gate drive circuit 20. The gate electrode of transistor T3L is connected to node N1L. The source electrode of transistor T3L is connected to the terminal Lout, which receives the output signal. Furthermore, the "RSM signal" is an example of the "first control signal" of this disclosure. Additionally, the terminal Lout is an example of the "output node" of this disclosure.

[0040] Capacitor C1L is connected between the gate electrode and the source electrode of transistor T3L. Capacitor C1L stores charge when node N1L is charged. Capacitor C1L is a bootstrap capacitor. That is, when an RSM signal is input to the drain electrode of transistor T3L, the potential of the source electrode of transistor T3L rises, and the potential of node N1L rises due to the charge in capacitor C1L (bootstrap).

[0041] like Figure 4 As shown, the output signal of the latch circuit 22 is input to the gate electrode of the transistor T5 connected to the circuit 23.

[0042] (Operation of gate drive circuit 20) Next, refer to Figure 9 and Figure 10 The operation of the gate drive circuit 20 is explained. The first diagram shows the timing of each signal in the gate drive circuit 20 without stop drive. The second diagram shows the timing of each signal in the gate drive circuit 20 with stop drive.

[0043] <No-stop drive> like Figure 9 As shown, when the control circuit 2 is driving without interruption, it does not supply the TPC signal and RSM signal to the gate drive circuit 20 (becoming an off-level state).

[0044] At time t1, node N1 of the unit circuit 21 constituting the nth stage is charged according to the output signal from the unit circuit 21 constituting the (n-1)th stage. At time t2, the unit circuit 21 constituting the nth stage is supplied with a clock signal GCK2 and outputs an output signal to the gate line 11, the latch circuit 22, and the unit circuit 21 constituting the (n+1)th stage. At this time, node N1L of the latch circuit 22 and node N1 of the unit circuit 21 constituting the (n+1)th stage are charged.

[0045] At time t3, clock signal GCK1 is supplied to unit circuit 21 constituting stage (n+1), and the output signal is output to gate line 11, latch circuit 22, and unit circuit 21 constituting stage (n+2). Since the output signal from unit circuit 21 constituting stage (n+1) is input to latch circuit 22 as a reset signal, node N1L is discharged (reset). Then, unit circuits 21 from stage (n+2) onwards sequentially output gate signal G to gate line 11.

[0046] <With interruption driver> like Figure 10 As shown, when the control circuit 2 is performing a stop drive, it supplies a TPC signal to the gate drive circuit 20 at the beginning of the stop period TR and an RSM signal to the gate drive circuit 20 at the end of the stop period TR. Furthermore, touch detection processing is performed during the stop period TR.

[0047] At time t11, node N1 of the unit circuit 21 constituting the nth stage is charged according to the output signal from the unit circuit 21 constituting the (n-1)th stage. At time t12, the unit circuit 21 constituting the nth stage is supplied with clock signal GCK2 and outputs an output signal to gate line 11, latch circuit 22, and unit circuit 21 constituting the (n+1)th stage. At this time, node N1L of latch circuit 22 and node N1 of unit circuit 21 constituting the (n+1)th stage are charged.

[0048] At time t13, the pause period TR begins, and the TPC signal is input to the connection circuit 23. Thus, by time t14, nodes N1 constituting the unit circuit 21 of the nth stage and the unit circuit 21 of the (n+1)th stage are reset. Furthermore, node N1L remains in a charged state.

[0049] At time t15, the RSM signal is input to the latch circuit 22. Consequently, the output signal from the terminal Lout of the latch circuit 22 is supplied via transistor T5 of the connection circuit 23 to node N1 of the unit circuit 21 constituting the (n+1)th stage. Node N1 of the unit circuit 21 constituting the (n+1)th stage is charged.

[0050] At time t16, the unit circuit 21 constituting the (n+1)th stage is supplied with clock signal GCK1, and an output signal is output from the unit circuit 21 constituting the (n+1)th stage. Through the output signal from the unit circuit 21 constituting the (n+1)th stage, the latch circuit 22 is reset, and the unit circuit 21 constituting the (n+2)th stage is charged. Thereafter, whenever clock signals GCK1 and GCK2 are supplied, gate signals are output sequentially for each stage.

[0051] As described above, depending on whether the TPC signal and RSM signal are supplied, the gate drive circuit 20 based on the first embodiment can perform uninterrupted drive (see reference). Figure 9 ) and has a stop drive (see reference) Figure 10 These two.

[0052] [Second Implementation] Next, refer to Figures 11 to 14 The configuration of the display device 200 based on the second embodiment will be described. The second embodiment is an example of a configuration in which a 4-phase clock signal is input to the shift register circuit 220a. Furthermore, configurations identical to those in the first embodiment described above will be labeled with the same reference numerals, and descriptions will be omitted. Figure 11 This is a block diagram of a display device 200 based on the second embodiment. Figure 12 This is a diagram showing the configuration of the gate drive circuit 220 of the display device 200 based on the second embodiment. Figure 13 This is a timing diagram when the gate drive circuit 220 based on the second embodiment performs uninterrupted drive. Figure 14 This is a timing diagram when the gate drive circuit 220 based on the second embodiment performs a stop drive.

[0053] like Figure 11 As shown, the display device 200 includes a control circuit 202 and a gate drive circuit 220. In the second embodiment, the control circuit 202 inputs four-phase clock signals GCK1 to GCK4 to the gate drive circuit 220. The gate drive circuit 220 includes a shift register circuit 220a, a latch circuit 222, and a connection circuit 223. The four-phase clock signals GCK1 to GCK4 are input to the shift register circuit 220a. Furthermore, the output signal of the unit circuit 21 of the shift register circuit 220a is input to terminal S of the unit circuit 21 constituting the second stage and terminal R of the unit circuit 21 constituting the first stage. Additionally, the output signal of the unit circuit 21 constituting the n+3 stage is input as a reset signal to terminal Lrst of the latch circuit 222.

[0054] The connection circuit 223 includes: a transistor T4a connected to node N1 of the unit circuit 21 constituting the (n-2)th stage; a transistor T4a connected to node N1 of the unit circuit 21 constituting the (n-1)th stage; and a transistor T4a connected to node N1 of the unit circuit 21 constituting the nth stage. Additionally, the connection circuit 223 includes: transistors T4b and T5 connected to node N1 of the unit circuit 21 constituting the (n+1)th stage; and transistors T4b and T5 connected to node N1 of the unit circuit 21 constituting the (n+2)th stage.

[0055] The latch circuit 222's terminal Lout is connected to two transistors T5 respectively.

[0056] like Figure 13 As shown, at time t21, by supplying a clock signal GCK4 to the unit circuit 21 constituting the nth stage, the output signal is input from the unit circuit 21 to the terminal Lset of the latch circuit 222 and the unit circuit 21 constituting the (n+2)th stage. As a result, node N1L and node N1 of the unit circuit 21 constituting the (n+2)th stage are charged. Then, at time t22, by supplying a clock signal GCK3 to the unit circuit 21 constituting the (n+3)th stage, the output signal is input from the unit circuit 21 to the terminal Lrst of the latch circuit 222 and the unit circuit 21 constituting the nth stage. As a result, the latch circuit 222 and the unit circuit 21 constituting the nth stage are reset. Then, starting from the (n+4)th stage and beyond, the unit circuits 21 sequentially output gate signals G to the gate line 11.

[0057] like Figure 14 As shown, at time t31, by supplying a clock signal GCK4 to the unit circuit 21 constituting the nth stage, the output signal is input from the unit circuit 21 to the terminal Lset of the latch circuit 222 and the unit circuit 21 constituting the (n+2)th stage. As a result, node N1L and node N1 of the unit circuit 21 constituting the (n+2)th stage are charged. Then, by inputting a TPC signal to the connection circuit 223 at time t32, node N1 of the unit circuits 21 of each stage from the (n-2)th to the (n+2)th stage is reset up to time t33. Then, during the pause period TR, the operation of the gate drive circuit 220 stops, and at time t34, an RSM signal is input to the latch circuit 222. As a result, the output signal from the terminal Lout of the latch circuit 222 is input to node N1 of the unit circuits 21 constituting the (n+1)th and (n+2)th stages via the transistor T5 of the connection circuit 223.

[0058] At time t35, the unit circuit 21 constituting the (n+1)th stage receives the clock signal GCK1 and outputs an output signal (gate signal Gn+1), ending the pause period TR. Then, at time t36, the output signal from the unit circuit 21 constituting the (n+3)th stage is input as a reset signal to the latch circuit 222, resetting the latch circuit 222. Then, from the (n+4)th stage onwards, the unit circuits 21 sequentially output gate signals G to the gate line 11.

[0059] As described above, according to the second embodiment, even when a 4-phase clock signal is input to the shift register circuit 220a, it is possible to switch between no-stop drive and stop drive based on whether an RSM signal is input to the latch circuit 222 and a TPC signal is input to the connection circuit 223. Furthermore, the other configurations and effects of the second embodiment are the same as those of the first embodiment.

[0060] (A variation of the second embodiment) Next, refer to Figure 15 The operation of the display device based on a modified example of the second embodiment will be explained. Figure 15 This is a timing diagram of a display device based on a variation of the second embodiment.

[0061] In the second embodiment, such as Figure 14 As shown, the time t34 when the RSM signal is input to the latch circuit 222 is one horizontal synchronization signal earlier than the time t35 when the clock signal GCK1 is input again, but as Figure 15 As shown, the time t41 when the RSM signal is input to the latch circuit 222 is two horizontal synchronization signals earlier than the time t42 when the restart clock signal GCK1 is input. In this case, as... Figure 15 As shown, the latch circuit 222 can be reset as a reset signal from the output signal of the unit circuit 21 constituting the (n+2)th stage.

[0062] [Third Implementation Method] Next, refer to Figures 16 to 19 The configuration of the display device 300 based on the third embodiment will be described. In the third embodiment, a plurality of latch circuits 322 and a plurality of connection circuits 323 are connected in parallel with the shift register circuit 320a. Furthermore, the gate drive circuit 320 is configured to operate only the selected latch circuit 322 among the plurality of latch circuits 322. In addition, the same reference numerals are used for configurations that are the same as those in the first embodiment described above, and descriptions are omitted. Figure 16 This is a block diagram of a display device 300 based on the third embodiment. Figure 17 This is a diagram showing the configuration of the gate drive circuit 320 of the display device 300 based on the third embodiment. Figure 18 It is a timing diagram related to the operation of circuits other than the operating circuit based on the third embodiment. Figure 19 It is a timing diagram related to the operation of the operating circuit based on the third embodiment.

[0063] like Figure 16 As shown, the display device 300 includes a control circuit 302 and a gate driving circuit 320. (As indicated...) Figure 17 As shown, the gate drive circuit 320 includes a shift register circuit 320a, a plurality of latch circuits 322 connected in parallel with the shift register circuit 320a, and a plurality of connection circuits 323. The shift register circuit 320a contains a plurality of (e.g., 800) unit circuits 21 (see reference 1). Figure 5The latch circuits 322 and 323 are respectively configured in each specified stage (e.g., 100 stages) of the shift register circuit 320a. For example, seven latch circuits 322 and seven 323 are provided in the gate drive circuit 320. The latch circuit 322 and 323 connected to the unit circuit 21 constituting the 100th stage of the shift register circuit 320a are designated as "latch unit L1", and the subsequent latch circuits 322 and 323 are designated as "latch unit L2", ..., "latch unit L7".

[0064] In the third embodiment, the control circuit 302 is configured to perform control based on four modes—basic drive, intermittent drive, alternating drive, and non-stop drive—as the mode for operating the gate drive circuit 320. The control circuit 302 switches between these four modes by determining the operating circuit to be operated from the latch units L1 to L7. Figure 19 As shown, TPC and RSM signals are input to the latch units L1 to L7 that are determined to be the operating circuits, and the operation of the gate drive circuit 320 is stopped. Figure 18 As shown, no TPC signal and RSM signal are input to the latch units other than the latch units determined as the operating circuit in latch units L1 to L7, and the operation of the gate drive circuit 320 is not stopped.

[0065] "Basic drive" refers to a driving method in which all latch units L1 to L7 are identified as operating circuits and the gate drive circuit 320 is stopped in all latch units L1 to L7. "Intermittent drive" refers to a driving method in which a portion of latch units L1 to L7 (e.g., only L2, L4, and L6) are identified as operating circuits, and the gate drive circuit 320 is stopped only in a portion of latch units L1 to L7. "Alternating drive" refers to a driving method in which the operating circuits are changed each frame. For example, in odd-numbered frames, the control circuit 302 identifies latch units L2, L4, and L6 as operating circuits, and in even-numbered frames, the control circuit 302 identifies latch units L1, L3, L5, and L7 as operating circuits. "Non-stop drive" refers to a driving method in which all latch units L1 to L7 are not identified as operating circuits.

[0066] According to the third embodiment, the operation of the gate drive circuit 320 can continue outside the operation circuits in the latching units L1 to L7, and the operation of the gate drive circuit 320 can be stopped within the operation circuits. The stage at which the operation of the gate drive circuit 320 is stopped can be arbitrarily set according to four modes: basic drive, intermittent drive, alternating drive, and non-stop drive. Furthermore, the other configurations and effects of the third embodiment are the same as those of the first embodiment.

[0067] [Deformation, etc.] The above-described embodiments are merely illustrative examples for implementing this disclosure. Therefore, this disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments without departing from its spirit.

[0068] (1) In the first to third embodiments described above, an example of providing a capacitor element (bootstrap capacitor) in a unit circuit was shown, but this disclosure is not limited thereto. For example, the capacitor component of transistor T3 may replace the function of capacitor element C1 described in the first to third embodiments.

[0069] (2) In the first and second embodiments described above, examples were shown of providing the gate driving circuit in display devices that perform both non-stop driving and stop driving, but this disclosure is not limited thereto. That is, the gate driving circuit can be provided in either a display device that performs only non-stop driving or a touch panel that performs only stop driving. In other words, the gate driving circuit of this disclosure can be mounted on devices of various specifications.

[0070] (3) In the first to third embodiments described above, examples of connections within the gate drive circuit were shown, but this disclosure is not limited thereto. That is, the connection configuration within the gate drive circuit (the input destination of the set signal and the reset signal) can also be changed according to the number of phases of the clock signal.

[0071] (4) In the first to third embodiments described above, examples of providing a touch detection function in the display device were shown, but this disclosure is not limited thereto. That is, the touch detection function may not be provided in the display device.

[0072] (5) In the first to fourth embodiments described above, examples of display devices constituted by liquid crystal display panels including liquid crystal layers were shown, but this disclosure is not limited thereto. For example, display devices may also be constituted by organic EL (Electro Luminescence) display panels.

[0073] The aforementioned driving circuit, display device, embedded touch panel device, and control device for the driving circuit can also be described as follows.

[0074] The first configuration involves a driving circuit composed of multiple stages, which responds to multiple clock signals input and supplies driving signals to a scan signal line group. The driving circuit includes: multiple unit circuits constituting each stage of the multiple stages and outputting the driving signals; a latching circuit connected in parallel with the multiple unit circuits; and a connection circuit connected to the output node of the latching circuit. The latching circuit receives a first output signal from a first unit circuit as a first set signal, the first unit circuit constituting the first stage of the multiple unit circuits. After receiving the first set signal, when the latching circuit receives a first control signal that restarts the operation of the driving circuit, it outputs a latching circuit output signal to the connection circuit via its output node. The latching circuit receives a second output signal from a second unit circuit as a first reset signal, the second unit circuit constituting the second stage of the multiple unit circuits, following the first stage. The connection circuit includes: a reset circuit that resets the first unit circuit and the third unit circuit in response to a second control signal that stops the operation of the drive circuit being input, the third unit circuit constituting the next stage of the first stage in the plurality of unit circuits; and a set circuit that supplies the output signal of the latch circuit as a second set signal to the third unit circuit (first configuration).

[0075] According to the first configuration described above, since the latch circuit is connected in parallel with multiple unit circuits, if a second control signal is not supplied to the drive circuit to stop its operation, the operation of the drive circuit can continue without stopping it in the latch circuit. Furthermore, if the second control signal is supplied to the drive circuit, its operation can be stopped; if the first control signal is supplied to the drive circuit, its operation can be restarted. As a result, the presence or absence of stopping the operation of the drive circuit can be arbitrarily set via the latch circuit.

[0076] In the first configuration, the third unit circuit may also include: an internal node; a first transistor that charges the internal node in response to the first output signal from the first unit circuit being input; a second transistor that, while the internal node is charged and is input to any one of the plurality of clock signals, outputs the drive signal to any one of the scan signal line groups; and a third transistor that discharges from the internal node in response to the second reset signal from the fourth unit circuit being input. The reset circuit and the set circuit may also be connected to the internal node. The reset circuit may also be configured to discharge from the internal node in response to the second control signal being input. The set circuit may also be configured to charge the internal node in response to the latch circuit output signal being input (second configuration).

[0077] According to the second configuration described above, the reset circuit can directly discharge the internal nodes of the third unit circuit. Furthermore, the set circuit can directly charge the internal nodes of the third unit circuit. Therefore, it is not necessary to provide additional circuitry between the reset circuit and the third unit circuit, or between the set circuit and the third unit circuit.

[0078] In either the first or second configuration, the second stage formed by the second unit circuit can also be the next stage after the first stage. The third unit circuit can also serve as the second unit circuit (third configuration).

[0079] According to the third configuration mentioned above, it is possible to prevent the configuration of the drive circuit from becoming too complicated.

[0080] In either the first or second configuration, the second stage formed by the second unit circuit can also be a stage that is later than the stage formed by the third unit circuit (fourth configuration).

[0081] According to the fourth configuration described above, even when the number of phases of multiple clock signals is large, the second output signal from the second unit circuit can be input to the latch circuit to reset the latch circuit.

[0082] The display device involved in the fifth configuration includes: a driving circuit of any one of the first to seventh configurations; and a display that is configured with the scanning signal line group (the fifth configuration).

[0083] According to the fifth configuration described above, a display device is provided that allows the presence or absence of stopping the operation of the drive circuit to be arbitrarily set via a latching circuit.

[0084] The embedded touch panel device involved in the sixth configuration includes: a driving circuit of any one of the first to seventh configurations; and an embedded touch panel configured with the scanning signal line group, which detects touch based on an indicator during the period when the operation of the driving circuit stops (sixth configuration).

[0085] According to the sixth configuration described above, an embedded touch panel device is provided that allows the presence or absence of stopping the operation of the drive circuit to be arbitrarily set via a latching circuit.

[0086] The control device for the drive circuit involved in the seventh configuration is a control device for a drive circuit that supplies the plurality of clock signals, the first control signal, and the second control signal to any one of the drive circuits in the first to fourth configurations. The drive circuit includes: a plurality of latch circuits connected in parallel with the plurality of unit circuits; and a plurality of connection circuits, each connected to the output node of the plurality of latch circuits. In the control device of the drive circuit, an operating connection circuit is determined from the plurality of connection circuits, and the second control signal is not supplied to the connection circuits other than the operating connection circuit, but is supplied to the operating connection circuit (seventh configuration).

[0087] In existing display devices, the stop operation position (level) is fixed and cannot be changed. In contrast, according to the seventh configuration described above, the operation of the drive circuit can continue in multiple connection circuits except for the operation connection circuit, and the operation of the drive circuit can be stopped in the operation connection circuit. Therefore, the stop operation level (position) can be arbitrarily changed according to the operation connection circuit determined from the multiple connection circuits. Explanation of reference numerals in the attached figures

[0088] 1: Touch panel; 2: Control circuit; 10: Display unit; 11: Gate line; 12: Source line; 13: Transistor; 13a: Gate electrode; 13b: Source electrode; 13c: Drain electrode; 14: Pixel electrode; 15: Common electrode; 16: Wiring; 20: Gate drive circuit; 20a: Shift register circuit; 21: Unit circuit; 22: Latch circuit; 23: Connection circuit; 30: Source drive circuit; 40: Touch detection control circuit; 100: Display device; 200: Display device; 202: Control circuit; 220: Gate drive circuit; 220a: Shift register circuit; 222: Latch circuit; 223: Connection circuit; 300: Display device; 302: Control circuit; 320: Gate drive circuit. 320a: Shift register circuit; 322: Latch circuit; 323: Connection circuit; C1: Capacitor element; C1L: Capacitor element; G: Gate signal; GCK: Terminal; GCK1~GCK4: Clock signal; Gn: Gate signal; L1~L7: Latch unit; Lout: Terminal; Lrst: Terminal; Lset: Terminal; N1: Node; N1L: Node; Q: Terminal; R: Terminal; RSM: Terminal; S: Terminal; T1: Transistor; T1L: Transistor; T2: Transistor; T2L: Transistor; T3: Transistor; T3L: Transistor; T4a: Transistor; T4b: Transistor; T5: Transistor; TD: Display period; TP: Touch detection period; TPC: Terminal; TR: Abort period.

Claims

1. A driving circuit comprising multiple stages, which, in response to the input of multiple clock signals, supplies driving signals to a scan signal line group, characterized in that the driving circuit includes: Multiple unit circuits, which constitute each stage of the multiple stages, and output the drive signal; A latching circuit is connected in parallel with the plurality of unit circuits; as well as The connection circuit is connected to the output node of the latch circuit. The latch circuit receives a first output signal from the first unit circuit as a first set signal, and the first unit circuit constitutes the first stage of the plurality of unit circuits. When the latch circuit receives the first set signal and then receives a first control signal that restarts the operation of the drive circuit, it outputs a latch circuit output signal to the connection circuit via the output node. The latch circuit receives a second output signal from the second unit circuit as a first reset signal. The second unit circuit constitutes the second stage of the plurality of unit circuits, which is a stage following the first stage. The connection circuit includes: A reset circuit, in response to the input of a second control signal that stops the operation of the drive circuit, resets the first unit circuit and the third unit circuit, wherein the third unit circuit constitutes the next stage of the first stage in the plurality of unit circuits; as well as The set circuit supplies the output signal of the latch circuit as a second set signal to the third unit circuit. The drive circuit is controlled to stop operating by the second control signal input to the connection circuit, and to restart operating by the first control signal input to the latch circuit.

2. A display device, characterized in that, include: The driving circuit as described in claim 1; as well as A display, which is equipped with the aforementioned scan signal line group.

3. An embedded touch panel device, characterized in that, include: The driving circuit as described in claim 1; as well as An embedded touch panel is provided with the scanning signal line group and detects touch based on an indicator during the period when the operation of the drive circuit stops.

4. A driving circuit comprising multiple stages, which, in response to the input of multiple clock signals, supplies driving signals to a scan signal line group, the driving circuit being characterized in that it includes: Multiple unit circuits, which constitute each stage of the multiple stages, and output the drive signal; A latching circuit, which is connected in parallel with the plurality of unit circuits; as well as The connection circuit is connected to the output node of the latch circuit. The latch circuit receives a first output signal from the first unit circuit as a first set signal, and the first unit circuit constitutes the first stage of the plurality of unit circuits. When the latch circuit receives the first set signal and then receives a first control signal that restarts the operation of the drive circuit, it outputs a latch circuit output signal to the connection circuit via the output node. The latch circuit receives a second output signal from the second unit circuit as a first reset signal. The second unit circuit constitutes the second stage of the plurality of unit circuits, which is a stage following the first stage. The connection circuit includes: A reset circuit, in response to an input of a second control signal that stops the operation of the drive circuit, resets the first unit circuit and the third unit circuit, the third unit circuit constituting the next stage of the first stage in the plurality of unit circuits; and The set circuit supplies the output signal of the latch circuit as a second set signal to the third unit circuit. The third unit circuit includes: Internal nodes; The first transistor, in response to the input of the first output signal from the first unit circuit, charges its internal node. The second transistor, when the internal node is charged and any one of the plurality of clock signals is input, outputs the drive signal to any one of the scan signal lines in the scan signal line group. as well as The third transistor, in response to a second reset signal input from the fourth unit circuit, discharges from its internal node. The fourth unit circuit constitutes a subsequent stage compared to the stage constituted by the third unit circuit. The reset circuit and the set circuit are connected to the internal node. The reset circuit discharges from the internal node in response to the input of the second control signal. The set circuit charges the internal node in response to the input of the output signal of the latch circuit.

5. A driving circuit comprising multiple stages, which, in response to the input of multiple clock signals, supplies driving signals to a scan signal line group, characterized in that the driving circuit includes: Multiple unit circuits, which constitute each stage of the multiple stages, and output the drive signal; A latching circuit, which is connected in parallel with the plurality of unit circuits; as well as The connection circuit is connected to the output node of the latch circuit. The latch circuit receives a first output signal from the first unit circuit as a first set signal, and the first unit circuit constitutes the first stage of the plurality of unit circuits. When the latch circuit receives the first set signal and then receives a first control signal that restarts the operation of the drive circuit, it outputs a latch circuit output signal to the connection circuit via the output node. The latch circuit receives a second output signal from the second unit circuit as a first reset signal. The second unit circuit constitutes the second stage of the plurality of unit circuits, which is a stage following the first stage. The connection circuit includes: A reset circuit, in response to the input of a second control signal that stops the operation of the drive circuit, resets the first unit circuit and the third unit circuit, wherein the third unit circuit constitutes the next stage of the first stage in the plurality of unit circuits; as well as The set circuit supplies the output signal of the latch circuit as a second set signal to the third unit circuit. The second stage, formed by the second unit circuit, is the next stage after the first stage. The third unit circuit also serves as the second unit circuit.

6. A driving circuit comprising multiple stages, which, in response to the input of multiple clock signals, supplies driving signals to a scan signal line group, the driving circuit being characterized in that it includes: Multiple unit circuits, which constitute each stage of the multiple stages, and output the drive signal; A latching circuit, which is connected in parallel with the plurality of unit circuits; as well as The connection circuit is connected to the output node of the latch circuit. The latch circuit receives a first output signal from the first unit circuit as a first set signal, and the first unit circuit constitutes the first stage of the plurality of unit circuits. When the latch circuit receives the first set signal and then receives a first control signal that restarts the operation of the drive circuit, it outputs a latch circuit output signal to the connection circuit via the output node. The latch circuit receives a second output signal from the second unit circuit as a first reset signal. The second unit circuit constitutes the second stage of the plurality of unit circuits, which is a stage following the first stage. The connection circuit includes: A reset circuit, in response to the input of a second control signal that stops the operation of the drive circuit, resets the first unit circuit and the third unit circuit, wherein the third unit circuit constitutes the next stage of the first stage in the plurality of unit circuits; as well as The set circuit supplies the output signal of the latch circuit as a second set signal to the third unit circuit. The second stage formed by the second unit circuit is a stage that follows the stage formed by the third unit circuit.

7. A control device for a drive circuit, comprising supplying a plurality of clock signals, a first control signal, and a second control signal to the drive circuit, the drive circuit being composed of multiple stages, and supplying drive signals to a scan signal line group in response to the input of the plurality of clock signals, characterized in that... The driving circuit includes: Multiple unit circuits, which constitute each stage of the multiple stages, and output the drive signal; Multiple latching circuits are connected in parallel with the multiple unit circuits; as well as Multiple connection circuits, each connected to the output node of the multiple latch circuits, The latch circuit receives a first output signal from the first unit circuit as a first set signal, and the first unit circuit constitutes the first stage of the plurality of unit circuits. When the latch circuit receives the first set signal and then receives the first control signal that restarts the operation of the drive circuit, it outputs a latch circuit output signal to the connection circuit via the output node. The latch circuit receives a second output signal from the second unit circuit as a first reset signal. The second unit circuit constitutes the second stage of the plurality of unit circuits, which is a stage following the first stage. The connection circuit includes: A reset circuit, in response to the input of a second control signal that stops the operation of the drive circuit, resets the first unit circuit and the third unit circuit, wherein the third unit circuit constitutes the next stage of the first stage in the plurality of unit circuits; as well as The set circuit supplies the output signal of the latch circuit as a second set signal to the third unit circuit. In the control device of the drive circuit The action connection circuit that performs the action is determined from the plurality of connection circuits. The second control signal is not supplied to the connection circuits other than the action connection circuit among the plurality of connection circuits, but is supplied to the action connection circuit.

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