A TFT_LCD display screen driving electromagnetic interference noise reduction control circuit, display screen and method

Abstract

The application provides a control circuit for reducing EMI noise in TFT_LCD display screen driving, which comprises at least polarity exchange circuit (2), EMI noise control module (1), N column first channel load 31, second channel load 32, S3…SN, and adjacent first channel load (31) and second channel load (32) as a group of basic working units; first NMOS switch tube (CSP1) and second NMOS switch tube (CSP2) are respectively connected to the ground at the positions of intermediate nodes EX1_P and EX2_P of the polarity exchange circuit (2), and the gates of all positive polarity channel NMOS discharge tubes in the N column first channel load 31, second channel load 32, S3…SN are connected together; first PMOS switch tube (CSN1) and second PMOS switch tube (CSN2) are respectively connected to the ground at the positions of intermediate nodes EX_N1 and EX_N2 of the polarity exchange circuit (2), and the gates of all negative polarity channel PMOS discharge tubes in the N column first channel load 31, second channel load 32, S3…SN are connected together. The application well combines soft discharge and hard discharge, and reaches the best level.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of chip, in particular, it relates to display driving chip, especially TFT_LCD chip field, especially the chip control applied to TFT_LCD display screen, especially the control circuit for reducing electromagnetic interference (EMI) noise and the corresponding control method for reducing electromagnetic interference (EMI) noise in the process of TFT_LCD display screen driving. BACKGROUND

[0002] At present, in the process of TFT_LCD screen display driving, in order to avoid the problem of polarity aging of liquid crystal molecules due to long time keeping the same flip angle, it is necessary to periodically exchange the positive and negative polarity of the voltage on the liquid crystal molecules, that is, the driving source changes the electric field direction on each pixel point through polarity exchange control, so that the liquid crystal molecules periodically change the flip direction and angle. However, in the actual driving display, in order to reduce the driving power consumption and solve the problem of device voltage resistance, the voltage on the channel load is generally discharged to 0V before polarity exchange in the pixel point, and then the channel load is driven to the gray scale voltage with opposite polarity by the driving buffer. However, due to the large parasitic capacitance on the channel load, a large discharge peak current will be generated in the process of discharging the channel load to ground, which will generate a large electromagnetic interference noise (EMI) on the display screen, becoming the main source of electromagnetic interference (EMI) noise in TFT_LCD display driving.

[0003] At present, the channel load discharging method mainly has the following two kinds:

[0004] (1) Switching tube hard discharge: a discharging MOS tube is connected to the MOS tube path of source polarity exchange, sometimes a current limiting resistor is connected in series on the discharging MOS tube for current limiting. When the channel load needs to be discharged to ground, the discharging MOS tube of the channel load to ground is directly opened, so as to realize the discharge of the channel load to ground.

[0005] (2) Switching tube maximum current limiting discharge: on the basis of switching tube hard discharge, the maximum value of the discharge current of the channel load is limited. The realization method is that when the channel load is discharged, the opening gate voltage of the discharging MOS tube is clamped at a voltage much lower than the power supply. At this time, the MOS is equivalent to a linear resistor with very large resistance. When the channel load is discharged, the maximum discharge current flowing through the discharging tube is limited below the set current value.

[0006] There are many defects in the prior art, such as:

[0007] (1) Switching tube hard discharge: This ground discharge method has a particularly fast discharge speed, but the discharge current peak value is particularly large. At the moment when the discharge MOS tube is opened, the voltage on the channel load is at the maximum voltage state, and the on-state impedance of the discharge MOS tube is at the minimum state. At the moment when the discharge tube is opened, a large current peak value will be generated. Specifically, at the moment when the positive and negative channel discharge tubes are opened, a positive current from the channel load to ground will be generated on the voltage on the positive channel load, and a negative current from the channel load to ground will be generated on the voltage on the negative channel load. Due to the asymmetry of the absolute values of the voltages on the positive and negative channel loads, the difference in the types of the positive and negative channel load discharge tubes, and the difference in the positive and negative channel load discharge tube control circuits themselves, it is very easy to cause the discharge peak current of the positive and negative channel loads to be not only very large, but also easily misaligned in time, and cannot be mutually offset, thereby generating a large electromagnetic interference (EMI) noise.

[0008] (2) Maximum current limiting discharge: This scheme is an improvement and optimization of the switching tube hard discharge. The biggest feature is to limit the discharge peak current of the positive and negative channel loads. In the (channel) ground discharge, the discharge peak current is limited to a lower level, and the currents of the positive and negative channel loads are mutually offset, which can reduce the electromagnetic interference (EMI) noise to a certain extent. However, this scheme has the disadvantages of slow discharge speed and long discharge time, and the electromagnetic interference noise (EMI) is not ideal.

[0009] In the prior art, it is always necessary to better solve the influence of electromagnetic interference noise (EMI), but there is no better and efficient technical scheme. SUMMARY

[0010] The application aims at providing a control circuit for reducing EMI noise in TFT_LCD display screen driving, which is used for reducing EMI noise in TFT_LCD display screen driving, and characterized in that it comprises at least polarity exchange circuit 2, EMI noise control module 1, and N-column first channel load 31, second channel load 32, S3…SN, and the adjacent first channel load 31 and second channel load 32 are taken as a group of basic working units; wherein the polarity exchange circuit 2 provides positive voltage driving for the first channel load 31 through positive polarity driving buffer, and provides negative voltage driving for the second channel load 32 through the control of negative polarity driving buffer; wherein the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 are connected to the ground at the positions of the intermediate nodes EX1_P and EX2_P of the polarity exchange circuit 2 respectively, and are used for discharging the positive polarity channel NMOS discharge tube to the ground, and the gates of all the positive polarity channel NMOS discharge tubes in the N-column first channel load 31, second channel load 32, S3…SN are connected together; the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 are connected to the ground at the positions of the intermediate nodes EX_N1 and EX_N2 of the polarity exchange circuit 2 respectively, and are used for discharging the negative polarity channel PMOS discharge tube to the ground, and the gates of all the negative polarity channel PMOS discharge tubes in the N-column first channel load 31, second channel load 32, S3…SN are connected together; wherein S3…SN represents channel load.

[0011] Wherein the EMI noise control module 1 comprises at least the first EMI noise control submodule EMI_P and the second EMI control submodule EMI_N, the output end OUTP_EMI of the first EMI noise control submodule EMI_P connects the gates of the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 together for control, and the output end OUTN_EMI of the second EMI control submodule EMI_N connects the gates of the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 together for control.

[0012] Wherein the first EMI noise control submodule EMI_P comprises at least current mirror current replication circuit, output end voltage down clamping circuit, and output current modulation circuit, wherein the output end voltage down clamping circuit is used for limiting the minimum value of the voltage of the output end OUTP_EMI, so that it is not lower than the voltage clamping value; and the output current modulation circuit is used for adjusting the size of the output end output current, so that the output current is controlled to slowly charge and discharge the gate of the discharge tube.

[0013] Specifically, the skilled in the art understands that S3…SN represents the same or similar channel load as the first channel load 31, second channel load 32, for example, S3 is the same as the first channel load 31, S4 is the same as the second channel load 32, and so on.

[0014] Preferably, the current mirror current replication circuit comprises at least a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, and a fourth MOS tube M4, the gate of the first MOS tube M1 is connected to the drain, the gate of the first MOS tube M1 is connected to the gate of the second MOS tube M2, the second MOS tube M2 replicates the current of the first MOS tube M1, the drain of the second MOS tube M2 is connected to the drain of the third MOS tube M3, the gate of the third MOS tube M3 is connected to the drain, the gate of the third MOS tube M3 is connected to the gate of the fourth MOS tube M4, and the fourth MOS tube M4 replicates the current of the third MOS tube M3; the output voltage down clamping circuit comprises at least a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, and an eighth MOS tube M8, the gate of the fifth MOS tube M5 is connected to the drain, the gate of the sixth MOS tube M6 is connected to the drain, the drain of the fifth MOS tube M5 is connected to the source of the sixth MOS tube M6, the drain of the sixth MOS tube M6 is connected to the fourth MOS tube M4, the drain voltage of the sixth MOS tube M6 is about two threshold voltages higher than GND, the gate of the eighth MOS tube M8 is connected to the drain of the sixth MOS tube M6, and the source of the eighth MOS tube M8 is connected to the output OUTP_EMI, so that the voltage of OUTP_EMI is clamped to about one threshold voltage higher than GND; the output current modulation circuit comprises at least a third MOS tube M3, a ninth MOS tube M9, and a tenth MOS tube M10, the gate of the tenth MOS tube M10 is connected to the drain of the ninth MOS tube M9, the source of the ninth MOS tube M9 is connected to the gate of the third MOS tube M3, by controlling the opening and closing of the ninth MOS tube M9, the tenth MOS tube M10 replicates the current of the third MOS tube M3 in the first tube size ratio.

[0015] Preferably, the tube size ratio of the tenth MOS tube M10 to the third MOS tube is N1:1, which is the first tube size ratio, and the value of N1 ranges from 1 to 30.

[0016] Preferably, the second EMI noise control sub-module EMI_N comprises at least a current mirror current copying circuit, an output terminal voltage upper clamping circuit, and an output current modulation circuit, wherein the output terminal voltage upper clamping circuit is used to limit the maximum value of the voltage of the output terminal OUTN_EMI to be not higher than a voltage clamping value, and the output current modulation circuit is used to adjust the size of the output current of the output terminal to slowly charge and discharge the gate of the discharge tube under control.

[0017] Preferably, the current mirror current copying circuit comprises at least a fourteenth MOS tube M14 and a fifteenth MOS tube M15, wherein the gate of the fourteenth MOS tube M14 is connected with the drain, the gate of the fourteenth MOS tube M14 is connected with the gate of the fifteenth MOS tube M15, and the fifteenth MOS tube M15 copies the current of the fourteenth MOS tube M14; the output terminal voltage upper clamping circuit comprises at least a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, and a twenty-first MOS tube M21, wherein the gate of the seventeenth MOS tube M17 is connected with the drain, the gate of the eighteenth MOS tube M18 is connected with the drain, the gate of the nineteenth MOS tube M19 is connected with the drain, the source of the seventeenth MOS tube M17 is connected with a positive power supply voltage VDDS, the drain voltage of the nineteenth MOS tube M19 is about three threshold voltages lower than the positive power supply voltage, the gate of the twenty-first MOS tube M21 is connected with the drain of the nineteenth MOS tube M19, and the source of the twenty-first MOS tube M21 is connected with the output terminal OUTN_EMI, so that the OUTN_EMI voltage is clamped at about two threshold voltages lower than the positive power supply voltage; and the output current modulation circuit comprises at least the fourteenth MOS tube M14, a twenty-second MOS tube M22, and a twenty-sixth MOS tube M26, wherein the gate of the twenty-sixth MOS tube M26 is connected with the drain of the twenty-second MOS tube M22, the gate of the fourteenth MOS tube M14 is connected with the source of the twenty-second MOS tube M22, and the twenty-sixth MOS tube M26 copies the current of the fourteenth MOS tube M14 in the second tube size ratio by controlling the opening and closing of the twenty-second MOS tube M22.

[0018] Preferably, the tube size ratio of the twenty-sixth MOS tube M26 to the fourteenth MOS tube M14 is N2:1, which is the second tube size ratio, and the value of N2 is in the range of 1-30.

[0019] According to another aspect of the present application, a novel TFT_LCD display screen with reduced EMI noise is provided, which comprises the above-mentioned control circuit.

[0020] According to another aspect of the present application, a control method applied to a new TFT_LCD display screen for reducing EMI noise is provided, which is used for reducing display screen driving EMI noise in the TFT_LCD display screen, and characterized in that it at least comprises the following steps:

[0021] a. Firstly, when the channel load enters the discharging stage, the lower clamp circuit enables the discharging tube of the first channel load 31 to quickly enter the critical opening state, and the upper clamp circuit enables the discharging tube of the second channel load 32 to quickly enter the critical opening state;

[0022] b. The first EMI noise control submodule EMI_P and the second EMI control submodule EMI_N simultaneously output a small current respectively modulated in size, for slowly charging and discharging the gate of the discharging tube of the positive polarity channel load and the negative polarity channel load, and the discharging current of the first channel load 31 and the second channel load 32 changes from small to large, and the polarities of the two discharging currents are opposite and the sizes are equal;

[0023] c. The discharging current of the first channel load 31 and the second channel load 32 changes from small to large, and when the discharging current reaches the maximum value, i.e. the soft discharging stage is completed, the soft discharging function is closed at this time, and the hard discharging switches M11 and M24 are opened respectively and simultaneously in the first EMI noise control submodule EMI_P and the second EMI control submodule EMI_N, so that the gate of the discharging tube of the first channel load 31 and the second channel load 32 is quickly pulled to the power supply voltage, and the positive and negative channel load voltages are quickly discharged to GND.

[0024] Preferably, after the positive and negative channel load voltages are discharged to GND, the discharging path of the first channel load 31 to the ground is turned off, the first channel load 31 is positively pre-charged, and the discharging path of the second channel load 32 to the ground is always kept open until the first channel load 31 is pre-charged and then turned off.

[0025] Preferably, the positive polarity driving buffer and the negative polarity driving buffer enable OP_EN state is high, PS1, PS3 and NS1, NS3 are high, PS2, PS4 and NS2, NS4 are low, and CS_GND1P, CS_GND2P and CS_GND1N, CS_GND2N are low; the positive polarity driving buffer and the negative polarity driving buffer drive the first channel load 31 to display positive voltage through PS1, PS3, the negative polarity driving buffer drives the second channel load 32 to display negative voltage through NS1, NS3, after the driving display of a row is completed, the positive polarity driving buffer and the negative polarity driving buffer enable EN changes from high to low, the positive polarity driving buffer and the negative polarity driving buffer stop working, and the output end OUT_P of the positive polarity driving buffer and the output end OUT_N of the negative polarity driving buffer are in a suspended state. For this step, reference can be made to Figure 1 .

[0026] Preferably, after the driving of the first channel load 31 and the second channel load 32 is completed, the first NMOS switch tube CSP1, the second NMOS switch tube CSP2, the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 slowly open under the control of the EMI control circuit to perform controlled discharge to ground for the first channel load 31 and the second channel load 32; for the positive polarity first channel load 31, the first EMI noise control submodule EMI_P circuit input signal CS_GND1P changes from low to high, and CS_GND2P remains unchanged, at this time, M7 and M9 are opened, and M11, M12 and M13 are closed, M5, M6 and M8 voltage clamp the output OUTP_EMI, M8 quickly pulls up the EMI_OUP voltage by an NMOS threshold voltage Vthn, so that the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 are weakly opened, and M1 and M2, M3 and M10 form a current mirror structure, a small current ip is continuously poured into OUTP_EMI through M10 to make the gate voltage of the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 slowly rise, and the voltage of the first channel load 31 slowly decreases, and the discharge current slowly increases from small to large.

[0027] Preferably, for the second channel load 32, the second EMI control sub-module EMI_N circuit input signal CS_GND1N changes from low to high, and CS_GND2N remains low, at this time M16, M20, M22 are open, and M23, M24, M25 are closed, M17, M18, M19 voltage clamp the output OUTN_EMI, M21 quickly pulls down the EMI_OUN voltage by a PMOS threshold voltage Vthp, allowing the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 to open slightly, and M14 and M15, M14 and M26 form a current mirror structure, which continuously draws a small current in through M26 to OUTN_EMI, allowing the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 gate voltage to slowly decrease, and the second channel load 32 voltage to slowly increase, and the discharge current to slowly increase from small to large.

[0028] Preferably, as the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2 sub-gate voltage slowly increases, while the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 tube sub-gate voltage slowly decreases, the positive polarity first channel load 31 injects positive current ip to ground, and the negative polarity second channel load 32 injects negative current in to ground, and the currents ip and in slowly change from small to large, and the directions are opposite, and the EMI noise generated by the two positive and negative polarity first channel load 31 and second channel load 32 reaches mutual cancellation; as the channel load slowly discharges, the positive polarity channel S1 voltage slowly decreases and approaches GND, and the second channel load 32 voltage slowly increases and approaches GND, and the discharge current ip and in gradually increases, by adjusting the size of N1 and N2, the discharge current ip and in reaches the maximum current peak at the same time, to realize the maximum cancellation of the channel load discharge current EMI noise.

[0029] Preferably, after the discharge current ip, in of the first channel load 31, the second channel load 32 reaches the maximum value, ip, in no longer increases and starts to decrease; at this time, the control signal CS_GND1P in the first EMI noise control submodule EMI_P module changes from high to low, and CS_GND2P changes from low to high, M7, M9, M11 in the first EMI noise control submodule EMI_P module are closed, M12 is opened, the gate of M10 is pulled low to AGND, so that M10 is fully opened, OUTP_EMI is pulled high to AVDD, and the NMOS discharge tube, i.e. the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2, is fully opened to discharge to ground with maximum capacity, so that the voltage of the first channel load 31 is quickly pulled to GND, and the discharge function of the first channel load 31 is completed; in the second EMI control submodule EMI_N, the control signal CS_GND1N changes from high to low, and CS_GND2N changes from low to high, M20, M22, M23 in the second EMI control submodule EMI_N are closed, M24 is opened, the gate of M26 is pulled low to VDDS, so that M26 is fully opened, OUTN_EMI is pulled low to AVCL, the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2 are fully opened to discharge to ground with maximum capacity, the voltage of the second channel load 32 is quickly pulled to GND, and the discharge function of the second channel load 32 is completed.

[0030] Preferably, after the first channel load 31 and the second channel load 32 are discharged to GND, the control signal CS_GND2P changes from high level to low level, the ground discharge NMOS tube, i.e. the first NMOS switch tube CSP1 and the second NMOS switch tube CSP2, is closed; then the control polarity exchange circuit PS2 and PS4 changes from low level to high level to be opened, and PS1 and PS3 change from high level to low level to be closed, so as to select the negative polarity driving channel for the first channel load 31, and the control polarity exchange circuit NS2 and NS4 change from low level to high level to be opened, and NS1 and NS3 change from high level to low level to be closed, so as to select the positive polarity driving channel for the second channel load 32, thereby completing the polarity exchange of the channel load; after the positive polarity second channel load 32 is precharged to VCI voltage, and after the precharge function is completed, the control signal CS_GND2N changes from high level to low level, the ground discharge PMOS tube, i.e. the first PMOS switch tube CSN1 and the second PMOS switch tube CSN2, is closed, the enable OP_EN of the positive polarity driving buffer and the negative polarity driving buffer changes from low level to high level, the positive polarity driving buffer drives the second channel load 32 to display positive voltage through PS2 and PS4, and the negative polarity driving buffer drives the first channel load 31 to display negative voltage through NS2 and NS4, thereby entering the driving display of the next row period.

[0031] The patent aims at the traditional channel load (channel) ground hard switch discharge mode, and has the disadvantages of large discharge peak current, poor mutual offset of positive and negative channel load (channel) discharge current, and difficult compatibility between discharge speed and electromagnetic interference (EMI) noise. A channel load (channel) ground soft discharge scheme with slowly changing current-limiting resistance and dynamically controllable discharge current is invented, which well combines soft discharge and hard discharge. The scheme not only can well reduce electromagnetic interference (EMI) noise, but also can achieve consideration between discharge speed and electromagnetic interference (EMI) noise, and can be flexibly adjusted according to different application requirements to reach the best level. The technical scheme has high efficiency, and compared with the prior art, realizes low cost and easy application, and is easy to effectively popularize. BRIEF DESCRIPTION OF DRAWINGS

[0032] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0033] Figure 1 A circuit schematic diagram of a control circuit applied to TFT_LCD display screen driving to reduce EMI noise is shown according to the specific embodiment of the present application;

[0034] Figure 2Fig. 1 shows a circuit schematic diagram of a first EMI noise control submodule EMI_P applied in a control circuit for reducing EMI noise of a TFT_LCD display screen drive according to a first embodiment of the present application;

[0035] Figure 3 Fig. 2 shows a circuit schematic diagram of a second EMI control submodule EMI_N applied in a control circuit for reducing EMI noise of a TFT_LCD display screen drive according to the first embodiment of the present application;

[0036] Figure 4 Fig. 3 shows a discharge waveform and control signal schematic diagram applied in a control method of a new type of TFT_LCD display screen for reducing EMI noise according to the first embodiment of the present application;

[0037] Figure 5 Fig. 4 shows a current peak value and common discharge current peak value comparison schematic diagram applied in a control method of a new type of TFT_LCD display screen for reducing EMI noise according to the first embodiment of the present application; and

[0038] Figure 6 Fig. 5 shows a circuit schematic diagram of a control circuit for reducing EMI noise of a TFT_LCD display screen drive according to another embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the technical solutions of the present application more clearly, the present application is further described below with reference to the accompanying drawings.

[0040] REFERENCE Figure 1 , Figure 2 , Figure 3 and Figure 6, those skilled in the art understand that in a preferred embodiment, the first EMI noise control submodule EMI_P at least includes a current mirror current replication circuit composed of a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, and a fourth MOS tube M4, the gate of the first MOS tube M1 is connected with the drain, the gate of the first MOS tube M1 is connected with the gate of the second MOS tube M2, M2 replicates the current of M1, the drain of the second MOS tube M2 is connected with the drain of the third MOS tube M3, the gate of the third MOS tube M3 is connected with the drain, the gate of the third MOS tube M3 is connected with the gate of the fourth MOS tube M4, M4 replicates the current of M3; an output voltage down clamping circuit composed of a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, and an eighth MOS tube M8, the gate of the fifth MOS tube M5 is connected with the drain, the gate of the sixth MOS tube M6 is connected with the drain, and the drain of the fifth MOS tube M5 is connected with the source of the sixth MOS tube M6, the drain of the sixth MOS tube M6 is connected with M4, the drain voltage of the sixth MOS tube M6 is about two threshold voltages higher than GND, then the gate of the eighth MOS tube M8 is connected with the drain of the sixth MOS tube M6, the source of M8 is connected with the output OUTP_EMI, and then the voltage of OUTP_EMI is clamped to be about one threshold voltage higher than GND; an output current modulation circuit composed of a third MOS tube M3, a ninth MOS tube M9, and a tenth MOS tube M10, and some simple logic control circuits to realize the control of soft discharge and hard discharge, the gate of the tenth MOS tube M10 is connected with the drain of M9, the source of M9 is connected with the gate of the third MOS tube M3, by controlling the opening and closing of M9, M10 replicates the current of M3 in proportion to the size.The tenth MOS transistor M10 and M3 have a tube size ratio of N1:1, and the size of N1 depends on the number of channel loads N and the size of the discharge tube CSN1, CSN2, and the size of the parasitic capacitance on the gate line of the discharge tube CSN1, CSN2, and N1 is in the range of 1-30; the second EMI noise control sub-module EMI_N at least includes a current mirror current replication circuit composed of the fourteenth MOS transistor M14 and the fifteenth MOS transistor M15, the gate of the fourteenth MOS transistor M14 is connected with the drain, and the gate of the fifteenth MOS transistor M15 is connected with the gate of the fourteenth MOS transistor M14, and M15 replicates the current of M14; the output voltage clamping circuit composed of the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the gate of the seventeenth MOS transistor M17 is connected with the drain, the gate of the eighteenth MOS transistor M18 is connected with the drain, the gate of the nineteenth MOS transistor M19 is connected with the drain, the source of the seventeenth MOS transistor M17 is connected with the positive power supply voltage VDDS, the drain voltage of the nineteenth MOS transistor M19 is about three threshold voltages lower than the positive power supply voltage, the gate of the twenty-first MOS transistor M21 is connected with the drain of the nineteenth MOS transistor M19, and the source of the twenty-first MOS transistor M21 is connected with the output OUTN_EMI. The OUTN_EMI voltage is clamped to be about two threshold voltages lower than the positive power supply voltage; the output current modulation circuit composed of the fourteenth MOS transistor M14, the twenty-second MOS transistor M22, and the twenty-sixth MOS transistor M26, and some simple logic control circuits to realize the control of soft discharge and hard discharge. The gate of the twenty-sixth MOS transistor M26 is connected with the drain of the twenty-second MOS transistor M22, the gate of the fourteenth MOS transistor M14 is connected with the source of the twenty-second MOS transistor M22, by controlling the opening and closing of M22, M26 replicates the current of M14 in proportion to the size, and the tube size ratio of M26 and M14 is N2:1, and the size of N2 depends on the number of channel loads N and the size of the discharge tube CSP1, CSP2, and the size of the parasitic capacitance on the gate line of the discharge tube CSP1, CSP2, and N2 is in the range of 1-30.

[0041] Further, with reference to Figure 1 and Figure 6 which shows the circuit composition of the control circuit applied to the TFT_LCD display screen driving to reduce EMI noise, that is, it includes:

[0042] 1. Main circuit module composition:

[0043] (1) Logic control and level conversion module: the main role is to convert digital timing control signal D2A_AUX_GND, D2A_CSP_GND, D2A_CSN_AUX_GND, through logic processing, and then level conversion, finally produce suitable voltage domain signal to the CTR_EMI module, wherein D2A_AUX_GND is the control signal of soft discharge start, D2A_CSP_GND is the control signal of positive channel start hard discharge, D2A_CSN_GND is the control signal of negative channel start hard discharge;

[0044] (2) CTR_EMI module: the core circuit of the patent, this module has only one, which is composed of first EMI noise control submodule EMI_P and second EMI noise control submodule EMI_N, directly control the gate of all channel load (hereinafter referred to as: channal) discharge tube; the first EMI noise control submodule EMI_P generates CSP_GND signal, which provides gate control voltage for all positive channel discharge tube (NMOS), the second EMI noise control submodule EMI_N generates CSN_GND signal, which provides gate control voltage for all negative channel discharge tube (PMOS), when the channal needs to be discharged to ground, under the slow control of CSP_GND and CSP_GND, controllable soft discharge is carried out. The circuit structure of the first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N is shown in Figure 2 and Figure 3 ;

[0045] (3) polarity exchange circuit and channal load: the polarity exchange circuit is mainly composed of polarity exchange MOS tube and ground discharge MOS tube, in order to realize soft discharge control, the connection relationship between the discharge tubes is improved, the gate of the two discharge tubes (NMOS) corresponding to the positive amplifier (OP) output is connected together and directly controlled by CSP_GND, the gate of the two discharge tubes (PMOS) corresponding to the negative amplifier (OP) output is connected together and directly controlled by CSN_GND, through this way of directly connecting the control signal and the MOS gate of the discharge tube, the controlled discharge of all channals by two signals is realized; the other part is the load model of channal, which is a typical three order channal RC load model.

[0046] Further, referring to Figure 1 , Figure 4 and Figure 5 , those skilled in the art understand that in the application of the control method of the new TFT_LCD display screen with reduced EMI noise, the control process of EMI noise reduction can be completed in the following way:

[0047] (1) t1 before: the last line of the source driving display ends, the source amplifier (OP) stops working, and the next line porch stage begins;

[0048] (2) t1-t2: from t1, the next line porch stage is entered, and at this time, the channal needs to be discharged to the ground. On the digital timing control, first, the D2A_AUX_GND signal becomes 1, representing that the circuit begins to enter the controlled soft discharge stage.

[0049] First, in the first EMI noise control submodule EMI_P, the gate voltage of the fifth MOS tube M5 is clamped at 2VTH by the sixth MOS tube M6 and the seventh MOS tube M7, and the CSP_GND voltage will be quickly charged from 0V to the vicinity of the VTH voltage by M5, so that the discharge tube of the positive channal can quickly enter the open state; in the second EMI noise control submodule EMI_N, the gate of the twentieth MOS tube M20 is clamped at VDDS-3VTH voltage (here, the influence of the substrate bias effect of the PMOS discharge tube of the negative channal is considered) by the twenty-first MOS tube M21, the twenty-second MOS tube M22, and the twenty-third MOS tube M23, and the CSN_GND voltage will be quickly discharged from the VDDS voltage to the vicinity of VDDS-1.5*VTH by M20, so that the discharge tube of the negative channal can quickly enter the open state;

[0050] Then, in the first EMI noise control submodule EMI_P, the eighth MOS tube M8 closes the ninth MOS tube M9, the tenth MOS tube M10 gate is connected with the VBP voltage, and the tenth MOS tube M10 and the third MOS tube M3 form a current mirror to charge the CSP_GND with a constant small current, so that the CSP_GND voltage slowly rises, the on-resistance of the positive channal discharge tube NMOS slowly changes from large to small, and the positive channal slowly discharges voltage decreases; in the second EMI noise control submodule EMI_N, the seventeenth MOS tube M17 closes the sixteenth MOS tube M16, the eighteenth MOS tube M18 gate is connected with the VBN voltage, and the eighteenth MOS tube M18 and the fourteenth MOS tube M14 form a current mirror to discharge the CSN_GND with a constant small current, so that the CSN_GND voltage slowly decreases, the on-resistance of the negative channal discharge tube PMOS slowly changes from large to small, and the negative channal slowly discharges voltage decreases;

[0051] (3) t2-t3: as the channal discharging, the channal voltage gradually decreases, when the positive and negative channal voltage drops to a small value, at this time the discharge current of the positive and negative channal (i.e. the first channel load 31, the second channel load 32) has begun to decay, in order to save the discharge time, it is necessary to open the discharge tube of the positive and negative channal completely, accelerate the discharge speed of the channal, that is, open the M11 in the first EMI noise control submodule EMI_P to quickly pull the CSP_GND to the VSP power supply voltage, the positive channal discharge tube is completely opened to discharge quickly, open the nineteenth MOS tube M19 in the second EMI noise control submodule EMI_N to quickly pull the CSN_GND to the VSN power supply voltage, and the negative channal discharge tube is completely opened to discharge quickly.

[0052] (4) After t3: into this stage, the channal discharge to ground has been completed, the positive and negative channal voltage is 0V, at this time it is necessary to turn off the positive channal discharge path to ground, precharge the positive channal in the positive direction, and the negative channal discharge path to ground is always kept open until the positive channal precharge is completed and then closed, and then the source enters the next row of display driving stage.

[0053] Reference Figure 5 which is the comparison result of the two modes when discharging the positive and negative channal to ground, S<1>, S<2> are respectively the voltage on the positive channal and the negative channal.

[0054] (1) In the moment of channal entering the discharge stage, that is, at the moment of t1, at this moment, the voltage on the channal is the largest, the traditional hard discharge mode directly opens the discharge tube with the power supply voltage, at this moment, the channal voltage is the largest, the VGS voltage of the discharge tube is the largest (that is, the on-resistance of the discharge tube is the smallest), the positive and negative channal will generate very large peak currents Ip(peak) and In(peak) at the moment of opening the discharge tube, as shown in the figure, due to the gate control signals of the positive and negative channal discharge tubes being generated by circuits in different voltage domains, being affected by the inherent transmission delay difference of the circuit and the corner, in fact, the positive and negative channal discharge tubes are difficult to open at the same time, which will inevitably cause the positive and negative channal peak currents Ip(peak) and In(peak) to be out of position in time and unable to offset each other, thereby generating a large EMI noise, in addition, it also needs to be considered that in the TFT_LCD display driving, the negative gray scale voltage is often significantly smaller than the positive gray scale voltage, that is, Ip(peak) will be more than one time larger than In(peak) when the channal discharges, that is, the positive and negative channal discharge peak currents cannot be completely offset, based on the above two reasons, the EMI noise of the traditional hard discharge mode will be large;

[0055] (2) The soft discharge mode of the present patent invention, in the moment of channal entering the discharge, that is, at the moment of t1, in order to save the discharge time, will quickly drive the discharge tube to a weak open state, at this moment, the on-resistance is very large, the discharge current slowly changes from small to large, and no channal current discharge peak will be generated, even if the positive and negative channal discharge tubes cannot be opened at the same time due to the inherent transmission delay difference of the circuit and the corner, since the discharge current is small and smooth, no obvious EMI noise will be generated; along with the channal discharge time to the ground, that is, in the time period of t1-t2, the channal voltage gradually decreases, the discharge tube gate voltage gradually increases, the on-resistance decreases, and the discharge current gradually increases, since the positive and negative channal discharge currents have very smooth change curves, they can well offset each other to minimize the EMI noise; when the channal voltage is discharged to a certain value, at this moment, the discharge current size has begun to decrease obviously, and the channal voltage has also decreased obviously, indicating that the discharge current has passed the maximum value, and the on-resistance of the discharge tube is already relatively small, that is, at the moment of t2, at this moment, in order to speed up the discharge speed, the discharge tube is completely opened through the control signal, and the positive and negative channal starts to discharge with the maximum capacity, since the channal voltage is already in a relatively low voltage state, when the discharge tube is completely opened, there will be no large current peak, that is, no large EMI noise will be generated.

[0056] (3) t1-t2 period, called the soft discharge phase, t2-t3 period, called the hard discharge phase, in actual work, through the digital register mode to realize the flexible adjustment of two time periods, if the EMI noise requirement is high, the t1-t2 period is adjusted to be long, the t12-t3 period is adjusted to be short, or even the t2-t3 period is cancelled, and the channal is allowed to perform full soft discharge work; if the discharge speed requirement is high, the t1-t2 period can be shortened, the t2-t3 period can be lengthened, or even the t1-t2 period is cancelled, and the channal is allowed to perform full hard discharge work, in short, different specifications of glass and different application requirements can be flexibly adjusted to achieve the most ideal EMI noise level.

[0057] (4) Through simulation comparison, it is found that the channal ground soft discharge scheme proposed in the patent can reduce the EMI noise by 3-4 times compared with the traditional channal ground hard switch discharge, and the effect is improved very obviously.

[0058] Further, in a preferred embodiment, the above control process can also be completed in the following manner:

[0059] Firstly, step a is performed. When the channel load enters the discharge phase, the lower clamping circuit allows the discharge tube of the first channel load 31 to quickly enter the critical opening state, and the upper clamping circuit allows the discharge tube of the second channel load 32 to quickly enter the critical opening state.

[0060] Then step b is entered. The first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N simultaneously output a small current which is respectively modulated in size, for slowly charging and discharging the gate of the discharge tube of the positive polarity channel load 31 and the negative polarity channel load 32, so that the discharge tube of the first channel load 31 and the second channel load 32 are slowly opened at the same time, and the discharge current of the first channel load 31 and the second channel load 32 changes from small to large, the discharge current is opposite in polarity and equal in size, achieving the purpose of mutual cancellation of EMI noise.

[0061] Then step c is performed. The discharge current of the first channel load 31 and the second channel load 32 changes from small to large, and when the discharge current reaches the maximum value, the soft discharge phase is completed, at this time, the soft discharge function is closed, and the hard discharge switches M11 and M24 are opened in the first EMI noise control submodule EMI_P and the second EMI noise control submodule EMI_N respectively and simultaneously, so that the gate of the discharge tube of the first channel load 31 and the second channel load 32 is quickly pulled to the power supply voltage, the discharge switch tube is completely opened, and the conduction impedance becomes minimum, and the positive and negative channel load voltage is quickly discharged to GND.

[0062] Finally, step d. When the positive and negative channel load voltage is discharged to GND, the channel load discharge phase is completed, at this time the first channel load 31 to ground discharge path is turned off, the first channel load 31 is forward pre-charged, and the second channel load 32 to ground discharge path is always kept open until the first channel load 31 pre-charging is completed.

[0063] Further, those skilled in the art understand that, with reference to Figure 1 In the above process, the positive polarity drive buffer, the negative polarity drive buffer enable OP_EN state is high, PS1, PS3 and NS1, NS3 are high, PS2, PS4 and NS2, NS4 are low, and CS_GND1P, CS_GND2P and CS_GND1N, CS_GND2N are low level state; the positive polarity drive buffer drives the channel load S1 to display positive voltage through PS1, PS3, and the negative polarity drive buffer drives the channel load S2 to display negative voltage through NS1, NS3. After the end of a row of driving display, the positive polarity drive buffer, the negative polarity drive buffer enable EN changes from high to low, the positive polarity drive buffer, the negative polarity drive buffer stop working, and no longer provide driving for the first channel load 31, the second channel load 32, and the output end OUT_P, OUT_N of the positive polarity drive buffer, the negative polarity drive buffer is in a suspended state.

[0064] Further, those skilled in the art understand that, with reference to Figure 2 , Figure 3In the above process, after the driving of the first channel load 31 and the second channel load 32 is completed, the first discharge switch tube CSP1 (hereinafter referred to as CSP1), the second discharge switch tube CSP2 (hereinafter referred to as CSP2), the third discharge switch tube CSN1 (hereinafter referred to as CSN1), and the second PMOS switch tube CSN2 (hereinafter referred to as CSN2) are slowly opened for the first channel load 31 and the second channel load 32 to perform controlled discharge to ground under the control of the EMI control circuit; for the positive polarity path load S1, the first EMI noise control submodule EMI_P circuit input signal CS_GND1P changes from low level to high level, and CS_GND2P remains low level unchanged, at this time M7 and M9 are opened, and M11, M12, and M13 are closed, M5, M6, and M8 voltage clamp the output OUTP_EMI, M8 quickly pulls up the EMI_OUP voltage by one NMOS threshold voltage Vthn, so that CSP1 and CSP2 are weakly opened, and M1 and M2, M3 and M10 form a current mirror structure, a small current ip modulated in size is continuously poured into OUTP_EMI through M10, so that the gate voltage of CSP1 and CSP2 slowly rises, the voltage of the first channel load 31 slowly decreases, and the discharge current slowly increases from small to large; for the second channel load 32 (i.e. the negative polarity channel load), the second EMI noise control submodule EMI_N circuit input signal CS_GND1N changes from low level to high level, and CS_GND2N remains low level unchanged, at this time M16, M20, and M22 are opened, and M23, M24, and M25 are closed, M17, M18, and M19 voltage clamp the output OUTN_EMI, M21 quickly pulls down the EMI_OUN voltage by one PMOS threshold voltage Vthp, so that CSN1 and CSN2 are weakly opened, and M14 and M15, M14 and M26 form a current mirror structure, a small current in modulated in size is continuously extracted from OUTN_EMI through M26, so that the gate voltage of CSN1 and CSN2 slowly decreases, the voltage of the second channel load 32 slowly rises, and the discharge current slowly increases from small to large.

[0065] Those skilled in the art understand that the first NMOS switch tube (CSP1) and the second NMOS switch tube (CSP2) are NMOS tubes for discharging to ground; the first PMOS switch tube (CSN1) and the second PMOS switch tube (CSN2) are PMOS tubes for discharging to ground.

[0066] Further, still referring to Figure 2 , Figure 3, with the CSP1, CSP2 tube grid voltage slowly rising, while the CSN1, CSN2 tube grid voltage slowly decreases, the first channel load 31 of positive polarity injects positive current ip to ground, the second channel load 32 of negative polarity injects negative current in to ground, and the currents ip and in slowly change from small to large and opposite in direction, the EMI noise generated by the two positive and negative polarity first channel load 31, second channel load 32 reaches mutual cancellation; with the slow discharge of the channel load, the positive polarity channel S1 voltage slowly decreases and approaches GND, the second channel load 32 voltage slowly increases and approaches GND, the discharge current ip, in gradually increases, by adjusting the size of N1, N2, the discharge current ip, in reaches the maximum current peak at the same time, to achieve the maximum cancellation of the channel load discharge current EMI noise.

[0067] Further, with reference to Figure 2 , Figure 3 , Figure 4 , after the discharge current ip, in of the first channel load 31, second channel load 32 reaches the maximum value at the same time, ip, in no longer increases and starts to decrease; at this time, the control signal CS_GND1P in the first EMI noise control submodule EMI_P changes from high level to low level, and CS_GND2P changes from low level to high level, M7, M9, M11 in the first EMI noise control submodule EMI_P are closed, M12 is opened, the gate of M10 is pulled low to AGND, so that M10 is fully opened to pull OUTP_EMI voltage high to AVDD, and NMOS discharge tube CSP1, CSP2 is fully opened to discharge to ground with maximum capacity, so as to quickly pull the voltage of the first channel load 31 to GND, and complete the discharge function of the first channel load 31 (i.e. positive channel load); in the second EMI noise control submodule EMI_N, the control signal CS_GND1N changes from high level to low level, and CS_GND2N changes from low level to high level, M20, M22, M23 in the second EMI noise control submodule EMI_N are closed, M24 is opened, the gate of M26 is pulled low to VDDS voltage, so that M26 is fully opened to pull OUTN_EMI voltage low to AVCL, and PMOS discharge tube CSN1, CSN2 is fully opened to discharge to ground with maximum capacity, so as to quickly pull the voltage of the second channel load 32 to GND, and complete the discharge function of the second channel load 32.

[0068] With reference to Figure 4 , those skilled in the art understand that the size difference of different screen channel loads is large, the discharge rate is different, and the time required for the discharge current to reach the peak value is different, so in chip testing, the pulse width of CS_GND1P, CS_GND1N needs to be adjusted according to the load of different screens, so as to achieve the minimum EMI noise.

[0069] Further, after discharging the first channel load 31 and the second channel load 32 to GND, the control signal CS_GND2P changes from high level to low level, the ground discharge NMOS tubes CSP1 and CSP2 are closed; then the control polarity exchange circuit PS2 and PS4 change from low level to high level to open, and PS1 and PS3 change from high level to low level to close, the negative polarity driving channel is selected for the first channel load 31, the control polarity exchange circuit NS2 and NS4 change from low level to high level to open, and NS1 and NS3 change from high level to low level to close, the positive polarity driving channel is selected for the second channel load 32, the polarity exchange of the channel load is completed; then the positive polarity second channel load 32 is precharged to VCI voltage, after the precharge function is completed, the control signal CS_GND2N changes from high level to low level, the ground discharge PMOS tubes CSN1 and CSN2 are closed, the enable OP_EN of the positive polarity driving buffer and the negative polarity driving buffer changes from low level to high level, the positive buffer drives the second channel load 32 to display positive voltage through PS2 and PS4, the negative buffer drives S1 to display negative voltage through NS2 and NS4, and the driving display of the next row period is entered.

[0070] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the above specific embodiments, and various modifications or changes can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application.

Claims

1. A control circuit for reducing EMI noise in TFT-LCD display driving, used to reduce display driving EMI noise in TFT-LCD displays, characterized in that... It includes at least a polarity switching circuit (2), an EMI noise control module (1), and N columns of first channel loads (31), second channel loads (32), S3…SN, with adjacent first channel loads (31) and second channel loads (32) forming a basic working unit; The polarity switching circuit (2) provides positive voltage drive to the first channel load (31) through a positive polarity drive buffer and provides negative voltage drive to the second channel load (32) through the control of a negative polarity drive buffer. In the polarity switching circuit (2), at the intermediate nodes EX1_P and EX2_P, a first NMOS switch (CSP1) and a second NMOS switch (CSP2) are respectively connected to ground for the positive polarity channel load to discharge to ground, and the gates of all positive polarity channel NMOS discharge transistors in the N columns of first channel load (31), second channel load (32), S3…SN are connected together; at the intermediate nodes EX_N1 and EX_N2 of the polarity switching circuit (2), a first PMOS switch (CSN1) and a second PMOS switch (CSN2) are respectively connected to ground for the negative polarity channel load to discharge to ground, and the gates of all negative polarity channel PMOS discharge transistors in the N columns of first channel load (31), second channel load (32), S3…SN are connected together; Wherein, S3…SN represents the channel load; The EMI noise control module (1) includes at least a first EMI noise control submodule (first EMI noise control submodule EMI_P) and a second EMI control submodule (EMI_N). The output terminal OUTP_EMI of the first EMI noise control submodule (first EMI noise control submodule EMI_P) connects the gates of the first NMOS switch (CSP1) and the second NMOS switch (CSP2) together for control. The output terminal OUTN_EMI of the second EMI control submodule (EMI_N) connects the gates of the first PMOS switch (CSN1) and the second PMOS switch (CSN2) together for control. The first EMI noise control submodule (first EMI noise control submodule EMI_P) includes at least a current mirror current replication circuit, an output voltage clamping circuit, and an output current modulation circuit. The output voltage clamping circuit is used to limit the minimum voltage of the output terminal OUTP_EMI to ensure that it is not lower than the voltage clamping value. The output current modulation circuit is used to adjust the magnitude of the output current so that the output current slowly charges and discharges the gate of the discharge tube under control.

2. The control circuit according to claim 1, characterized in that, The current mirror current replication circuit includes at least a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4. The gate and drain of the first MOSFET M1 are connected, and the gate of the second MOSFET M2 is connected through the gate of the first MOSFET M1. The second MOSFET M2 replicates the current of the first MOSFET M1. The drain of the second MOSFET M2 is connected to the drain of the third MOSFET M3. The gate and drain of the third MOSFET M3 are connected, and the gate of the third MOSFET M3 is connected to the gate of the fourth MOSFET M4. The fourth MOSFET M4 replicates the current of the third MOSFET M3. The output voltage clamping circuit includes at least a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, and an eighth MOSFET M8. The gate and drain of the fifth MOSFET M5 are connected, the gate and drain of the sixth MOSFET M6 are connected, the drain of the fifth MOSFET M5 is connected to the source of the sixth MOSFET M6, and the drain of the sixth MOSFET M6 is connected to the fourth MOSFET M4. The drain voltage of the sixth MOSFET M6 is approximately two threshold voltages higher than GND. The gate of the eighth MOSFET M8 is then connected to the drain of the sixth MOSFET M6, and the source of the eighth MOSFET M8 is connected to the output terminal OUTP_EMI. Thus, the OUTP_EMI voltage is clamped at approximately one threshold voltage higher than GND. The output current modulation circuit comprises at least a third MOSFET M3, a ninth MOSFET M9, and a tenth MOSFET M10. The gate of the tenth MOSFET M10 is connected to the drain of the ninth MOSFET M9, and the source of the ninth MOSFET M9 is connected to the gate of the third MOSFET M3. By controlling the opening and closing of the ninth MOSFET M9, the tenth MOSFET M10 replicates the current of the third MOSFET M3 according to the first transistor size ratio.

3. The control circuit according to claim 2, characterized in that, The size ratio of the tenth MOS transistor M10 to the third MOS transistor is N1:1, which represents the first transistor size ratio. The value of N1 ranges from 1 to 30.

4. The control circuit according to claim 2 or 3, characterized in that, The second EMI control submodule (EMI_N) includes at least a current mirror current replication circuit, an output voltage clamping circuit, and an output current modulation circuit. The output voltage clamping circuit is used to limit the maximum voltage of the output terminal OUTN_EMI so that it does not exceed the voltage clamping value. The output current modulation circuit is used to adjust the magnitude of the output current so that the output current slowly charges and discharges the gate of the discharge tube under controlled conditions.

5. The control circuit according to claim 4, characterized in that, The current mirror current replication circuit includes at least a fourteenth MOS transistor M14 and a fifteenth MOS transistor M15, wherein the gate and drain of the fourteenth MOS transistor M14 are connected, and the gate of the fifteenth MOS transistor M15 is connected to the gate of the fourteenth MOS transistor M14, and the fifteenth MOS transistor M15 replicates the current of the fourteenth MOS transistor M14. The output voltage clamping circuit comprises at least a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, and a twentieth MOSFET M20. The gate and drain of the seventeenth MOSFET M17 are connected, the gate and drain of the eighteenth MOSFET M18 are connected, the gate and drain of the nineteenth MOSFET M19 are connected, the source of the seventeenth MOSFET M17 is connected to the positive power supply voltage VDDS, and the drain voltage of the nineteenth MOSFET M19 is approximately three threshold voltages lower than the positive power supply voltage. The gate of the twenty-first MOSFET M21 is then connected to the drain of the nineteenth MOSFET M19, and the source of the twenty-first MOSFET M21 is connected to the output terminal OUTN_EMI. The OUTN_EMI voltage is clamped to approximately two threshold voltages lower than the positive power supply voltage. The output current modulation circuit includes at least a fourteenth MOSFET M14, a twenty-second MOSFET M22, and a twenty-sixth MOSFET M26. The gate of the twenty-sixth MOSFET M26 is connected to the drain of the twenty-second MOSFET M22, and the gate of the fourteenth MOSFET M14 is connected to the source of the twenty-second MOSFET M22. By controlling the opening and closing of the twenty-second MOSFET M22, the twenty-sixth MOSFET M26 replicates the current of the fourteenth MOSFET M14 according to the second transistor size ratio.

6. The control circuit according to claim 5, characterized in that, The size ratio of the 26th MOS transistor M26 to the 14th MOS transistor M14 is N2:1, which is the second transistor size ratio. The value of N2 ranges from 1 to 30.

7. A novel TFT-LCD display screen with reduced EMI noise, characterized in that, Includes the control circuit according to any one of claims 1 to 6.

8. A control method for a novel TFT-LCD display screen with reduced EMI noise, used to reduce display screen driving EMI noise in the TFT-LCD display screen according to claim 7, characterized in that, It should include at least the following steps: a. First, when the channel load enters the discharge stage, the lower clamping circuit enables the discharge tube of the first channel load (31) to quickly enter the critical opening state, and the upper clamping circuit enables the discharge tube of the second channel load (32) to quickly enter the critical opening state. b. The first EMI noise control submodule (EMI_P) and the second EMI control submodule (EMI_N) simultaneously output a small current of modulated magnitude to slowly charge and discharge the gates of the discharge tubes of the positive and negative polarity channel loads. The discharge currents of the first channel load (31) and the second channel load (32) change from small to large. The two discharge currents have opposite polarities and equal magnitudes. c. The discharge current of the first channel load (31) and the second channel load (32) changes from small to large. When the discharge current reaches the maximum value, the soft discharge stage is completed. At this time, the soft discharge function is turned off. The hard discharge switches M11 and M24 are turned on simultaneously in the first EMI noise control submodule (EMI_P) and the second EMI control submodule (EMI_N), respectively, so that the gate of the discharge tube of the first channel load (31) and the second channel load (32) is quickly pulled to the power supply voltage, and the positive and negative channel load voltages are quickly discharged to GND. d. After the positive and negative channel load voltages are discharged to GND, the discharge path to ground of the first channel load (31) is turned off, and the first channel load (31) is pre-charged in the positive direction. The discharge path to ground of the second channel load (32) remains open until the pre-charging of the first channel load (31) is completed and then turned off.

9. The control method according to claim 8, characterized in that, The positive and negative drive buffers are enabled at OP_EN level, PS1, PS3 and NS1, NS3 are at high level, PS2, PS4 and NS2, NS4 are at low level, and CS_GND1P, CS_GND2P and CS_GND1N, CS_GND2N are all at low level. The positive and negative drive buffers drive the first channel load (31) through PS1 and PS3 to display a positive voltage, and the negative drive buffer drives the second channel load (32) through NS1 and NS3 to display a negative voltage. After one line of drive display ends, the positive and negative drive buffers enable EN level changes from high level to low level, the positive and negative drive buffers stop working, and the output terminals OUT_P and OUT_N of the positive and negative drive buffers are in a floating state.

10. The control method according to claim 8 or 9, characterized in that, After driving the first channel load (31) and the second channel load (32), the first NMOS switch (CSP1), the second NMOS switch (CSP2), the first PMOS switch (CSN1), and the second PMOS switch (CSN2) are slowly turned on under the control of the EMI control circuit to perform controlled discharge to ground for the first channel load (31) and the second channel load (32). For the positive polarity first channel load (31), the input signal CS_GND1P of the first EMI noise control submodule (EMI_P) circuit changes from low level to high level, and CS_GND2P remains low. At this time, M7 and M9 are turned on, and M11, M12 and M13 are turned off, and M5, M6 and M8 clamp the output OUTP_EMI. M8 quickly pulls the EMI_OUP voltage up by an NMOS threshold voltage Vthn, so that the first NMOS switch (CSP1) and the second NMOS switch (CSP2) are slightly turned on. At the same time, M1 and M2, M3 and M10 form a current mirror structure. Through M10, a small current ip modulated by size is continuously injected into OUTP_EMI, so that the gate voltage of the first NMOS switch (CSP1) and the second NMOS switch (CSP2) slowly increases, the voltage of the first channel load (31) slowly decreases, and the discharge current slowly increases from small to large.

11. The control method according to claim 10, characterized in that, For the second channel load (32), the input signal CS_GND1N of the second EMI control submodule (EMI_N) circuit changes from low level to high level, and CS_GND2N remains at low level. At this time, M16, M20, and M22 are turned on, and M23, M24, and M25 are turned off. M17, M18, and M19 clamp the output OUTN_EMI. M21 quickly pulls the EMI_OUN voltage down by a PMOS threshold voltage Vthp, so that the first PMOS switch (CSN1) and the second PMOS switch (CSN2) are slightly turned on. At the same time, M14 and M15, and M14 and M26 form a current mirror structure. Through M26, a small current in modulated by size is continuously extracted from OUTN_EMI, so that the gate voltage of the first PMOS switch (CSN1) and the second PMOS switch (CSN2) slowly decreases, the voltage of the second channel load (32) slowly increases, and the discharge current slowly increases from small to large.

12. The control method according to claim 8 or 9, characterized in that, As the gate voltages of the first NMOS switch (CSP1) and the second NMOS switch (CSP2) slowly increase, and the gate voltages of the first PMOS switch (CSN1) and the second PMOS switch (CSN2) slowly decrease, the positive first channel load (31) injects a positive current ip to ground, and the negative second channel load (32) injects a negative current in to ground. The currents ip and in change slowly from small to large and in opposite directions, so that the EMI noise generated by the two positive and negative first channel loads (31) and second channel loads (32) cancels each other out. As the channel load slowly discharges, the voltage of the positive channel S1 slowly decreases and approaches GND, while the voltage of the second channel load (32) slowly increases and approaches GND. The discharge currents ip and in gradually increase. By adjusting the values ​​of N1 and N2, the discharge currents ip and in simultaneously reach their maximum current peak values, thereby achieving maximum cancellation of EMI noise from the channel load discharge current.

13. The control method according to claim 8 or 9, characterized in that, When the discharge currents ip and in of the first channel load (31) and the second channel load (32) reach their maximum values ​​simultaneously, ip and in stop increasing and begin to decrease. At this time, in the first EMI noise control submodule (EMI_P), the control signal CS_GND1P changes from high level to low level, and at the same time, CS_GND2P changes from low level to high level. In the first EMI noise control submodule (EMI_P), M7, M9, and M11 are turned off, and M12 is turned on. The gate of M10 is pulled low to AGND, so that M10 is fully turned on and the OUTP_EMI voltage is pulled high to AVDD. The NMOS discharge transistors, namely the first NMOS switch (CSP1) and the second NMOS switch (CSP2), are fully turned on to discharge to ground with maximum capacity, and the voltage of the first channel load (31) is quickly pulled to GND, thus completing the discharge function of the first channel load (31).

14. The control method according to claim 13, characterized in that, In the second EMI control submodule (EMI_N), the control signal CS_GND1N changes from high level to low level, and at the same time, CS_GND2N changes from low level to high level. In the second EMI control submodule (EMI_N), M20, M22, and M23 are turned off, and M24 is turned on. The gate of transistor M26 is pulled down to VDDS voltage, so that transistor M26 is fully turned on and the OUTN_EMI voltage is pulled down to AVCL. The first PMOS switch (CSN1) and the second PMOS switch (CSN2) are fully turned on to discharge to ground with maximum capacity, and the voltage of the second channel load (32) is quickly pulled to GND, thus completing the discharge function of the second channel load (32).

15. The control method according to claim 8 or 9, characterized in that, After the first channel load (31) and the second channel load (32) discharge to GND, the control signal CS_GND2P changes from high to low, turning off the NMOS transistors that discharge to ground, namely the first NMOS switch (CSP1) and the second NMOS switch (CSP2). Then, the polarity switching circuits PS2 and PS4 change from low to high to turn on, and PS1 and PS3 change from high to low to turn off, selecting the negative polarity drive channel for the first channel load (31). The polarity switching circuits NS2 and NS4 change from low to high to turn on, and NS1 and NS3 change from high to low to turn off, selecting the positive polarity drive channel for the second channel load (32), thus completing the discharge. The polarity of the load is switched; then the positive polarity second channel load (32) is precharged to VCI voltage. After the precharge function is completed, the control signal CS_GND2N changes from high level to low level, and the discharge PMOS transistors to ground, namely the first PMOS switch (CSN1) and the second PMOS switch (CSN2), are turned off. The enable OP_EN of the positive polarity drive buffer and the negative polarity drive buffer changes from low level to high level. The positive polarity drive buffer drives the second channel load (32) to display a positive voltage through PS2 and PS4, and the negative polarity drive buffer drives the first channel load (31) to display a negative voltage through NS2 and NS4, and enters the drive display of the next row cycle.

Images