Memory wafer

Abstract

The invention discloses a memory wafer which comprises a memory device. The memory device comprises a first memory circuit, a first control circuit, a second memory circuit and a second control circuit, wherein the first memory circuit is used for outputting a first data signal to a first node; the first control circuit comprises a first switch, a second switch and a third switch; the second memory circuit is used for outputting a second data signal to a second node. The second control circuit comprises a fourth switch, a fifth switch and a sixth switch.

Description

[0001] This application is a divisional application. The filing date of the parent application is April 2, 2022, the priority date is November 18, 2021, the application number is 202210340863.8, the applicant is AU Optronics Corporation, and the name of the invention is memory chip. Technical Field

[0002] The present disclosure relates to a memory technology, and more particularly to a memory chip. Background Art

[0003] The NFC chip includes a memory device for storing data. The memory device can be formed by a thin film transistor (TFT). However, the impedance between the source and drain of the TFT is large and the mobility is low. The uniformity of the TFT is poor and it is not suitable for designing an amplifier. Therefore, how to design a memory circuit architecture suitable for TFT elements is an important issue in this field. Summary of the invention

[0004] An embodiment of the present invention includes a memory chip. The memory chip includes a first decoding device and a memory device. The first decoding device is used to generate a plurality of word line signals. The memory device is used to generate a third data signal based on at least a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is used to generate a first data signal at a first node according to the word line signal during a first period. The second memory circuit is used to generate a second data signal at a second node different from the first node according to the word line signal during a second period after the first period.

[0005] An embodiment of the present invention includes a memory chip. The memory chip includes a memory device. The memory device includes a first memory circuit, a first control circuit, a second memory circuit and a second control circuit. The first memory circuit is used to output a first data signal at a first node. The first control circuit includes a first switch, a second switch and a third switch. A control end of the first switch is used to receive a first enable signal, and a first end of the first switch is coupled to the first node. A control end of the second switch is used to receive a pulse signal, and a first end of the second switch is coupled to the first node. A control end of the third switch is used to receive the first enable signal, and a first end of the third switch is coupled to a second end of the second switch. The second memory circuit is used to output a second data signal at a second node. The second control circuit includes a fourth switch, a fifth switch and a sixth switch. A control end of the fourth switch is used to receive a second enable signal, and a first end of the fourth switch is coupled to the second node. A control end of the fifth switch is used to receive the pulse signal, and a first end of the fifth switch is coupled to the second node. A control end of the sixth switch is used to receive the second enable signal, and a first end of the sixth switch is coupled to a second end of the fifth switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a memory chip according to an embodiment of the present invention.

[0007] Figure 2 is a schematic diagram of a memory chip according to an embodiment of the present invention.

[0008] Figure 3 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0009] Figure 4 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0010] Figure 5 FIG. 4 is a timing diagram illustrating an operation of a memory device according to an embodiment of the present disclosure according to an enable signal.

[0011] Fig. 6A is a schematic diagram of a logic circuit according to an embodiment of the present invention.

[0012] Figure 6B is a schematic diagram of a logic circuit according to an embodiment of the present invention.

[0013] Figure 7 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0014] Figure 8 is a schematic diagram of a logic circuit according to an embodiment of the present invention.

[0015] Fig. 9 is a schematic diagram of a logic circuit according to an embodiment of the present invention.

[0016] Fig.10 FIG. 1 is a timing diagram illustrating a memory chip generating data signals according to an embodiment of the present disclosure.

[0017] Fig.11 FIG. 1 is a timing diagram illustrating a memory chip generating data signals according to an embodiment of the present disclosure.

[0018] Wherein, the reference numerals are:

[0019] 100, 200: memory chip

[0020] 110: Communication device

[0021] 120: Rectification device

[0022] 130: Frequency division device

[0023] 140, 240: counting device

[0024] 150, 160, 250, 260: decoding device

[0025] 170, 270, 300, 400, 700: memory devices

[0026] 180: Encoding device

[0027] BF11, BF12: Buffer device

[0028] AC11, VDD, VSS, Q2, Q3, Q5, Q6: voltage signal

[0029] N11~N14、N31~N34、N40~N43、N71~N79: nodes

[0030] C11, C12: capacitors

[0031] CLK, CLKB, DV1, DV1B, C0~C6: clock signals

[0032] EN, ENB, ENB0~ENB3, EN0~EN3, EL2, ELB2: enable signal

[0033] W0~W3、WM: word line signal

[0034] B0~B7、BN: bit line signal

[0035] DT1, DT2, DT31, DT40~DT43: data signal

[0036] 271-274, 310, 410-413, 710: memory circuit

[0037] 320, 420~423, 720: control circuit

[0038] PL: Pulse signal

[0039] T31~T35, T403~T405, T413~T415, T423~T425, T433~T435, T73~T75, Z0~Z7, X00~X03, X10~X13, X20~X23, X30~X33, X40~X43, X50~X53, X60~X63, X70~X73: switch

[0040] 500, 1000, 1100: Timing diagram

[0041] P51~P510、Q1~Q15、J1~J9: Period

[0042] VL, VH: voltage level

[0043] 600A, 600B, 800, 900: Logic circuits

[0044] NR60~NR63、IV60~IV63、OR61、ND81~ND84、NR81~NR88、NV81~NV86、IV81~IV86、AD91~AD94、NR91~NR95、NV91~NV94、IV91~IV94:Logic elements

[0045] 712: Cutting Area DETAILED DESCRIPTION

[0046] In this document, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present case.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which this case belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this case, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such in this article.

[0048] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0049] The following will disclose multiple embodiments of the present invention with drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.

[0050] Figure 1 FIG. 1 is a schematic diagram of a memory chip 100 according to an embodiment of the present invention. In some embodiments, the memory chip 100 can be implemented as a Near Field Communication (NFC) communication chip. Figure 1 The memory chip 100 includes a communication device 110, a rectifying device 120, a frequency dividing device 130, a counting device 140, decoding devices 150, 160, a memory device 170, an encoding device 180 and buffer devices BF11, BF12.

[0051] like Figure 1 As shown, the communication device 110 is used to receive the voltage signal AC11 at nodes N11 and N12. The rectifier device 120 is used to receive the voltage signal AC11 at nodes N11 and N12, and to generate voltage signals VDD and VSS at nodes N13 and N14 respectively according to the voltage signal AC11. In some embodiments, the voltage signal AC11 is an AC power signal, voltage signals VDD and VSS. In some embodiments, the rectifier device 120 is used to convert the voltage signal AC11 into voltage signals VDD and VSS. In some embodiments, the voltage level of the voltage signal VDD is higher than the voltage level of the voltage signal VSS.

[0052] In some embodiments, the memory chip 100 further includes capacitors C11 and C12. Figure 1As shown, capacitor C11 is used to receive voltage signal AC11 at nodes N11 and N12. Capacitor C12 is used to receive voltage signal VDD at node N13 and to receive voltage signal VSS at node N14. In some embodiments, the capacitance of capacitor C11 is approximately thirty-nine pico-farads.

[0053] like Figure 1 As shown, the frequency dividing device 130 is used to receive the voltage signal AC11 at the node N11, and generate the voltage signals Q2, Q3, Q5 and Q6 according to the voltage signal AC11. In some embodiments, the voltage signals Q2, Q3, Q5 and Q6 are implemented as clock signals. In some embodiments, the frequency of the voltage signal Q6 corresponds to the frequency of the voltage signal AC11, the frequency of the voltage signal Q5 is approximately half of the frequency of the voltage signal Q6, the frequency of the voltage signal Q3 is approximately one-quarter of the frequency of the voltage signal Q5, and the frequency of the voltage signal Q2 is approximately half of the frequency of the voltage signal Q3.

[0054] In some embodiments, the buffer device BF11 is used to generate the clock signal DV1 according to the voltage signal Q6, and the buffer device BF12 is used to generate the clock signal CLK according to the voltage signal Q5. Figure 1 As shown, the input end of the buffer device BF11 is used to receive the voltage signal Q6, and the output end of the buffer device BF11 is used to output the clock signal DV1. The input end of the buffer device BF12 is used to receive the voltage signal Q5, and the output end of the buffer device BF12 is used to output the clock signal CLK. In some embodiments, each of the buffer devices BF11 and BF12 includes one or more inverters coupled in series. In some embodiments, the frequency of the clock signal DV1 is substantially equal to the frequency of the voltage signal Q6, and the frequency of the clock signal CLK is substantially equal to the frequency of the voltage signal Q5. Details about the clock signals CLK and DV1 are described below with respect to Figures 4 to 11 The embodiments are further described in the examples.

[0055] like Figure 1 As shown, the counting device 140 is used to generate clock signals C0-C6 and an enable signal EN according to the clock signals CLK and CLKB. In some embodiments, the clock signal CLKB is a complementary signal of the clock signal CLK. In some embodiments, the frequency of a signal is equal to the frequency of the complementary signal of the signal. In some embodiments, the counting device 140 is implemented as an asynchronous counter. The details of the clock signals C0-C6, CLKB and the enable signal EN are described below. Figures 4 to 11 The embodiments are further described in the examples.

[0056] like Figure 1As shown, the decoding device 150 is used to generate word line signals W0-W3 according to the clock signals C3, C4, DV1 and DV1B. The decoding device 160 is used to generate bit line signals B0-B7 according to the clock signals C0-C2, DV1 and DV1B. In some embodiments, the clock signal DV1B is a complementary signal of the clock signal DV1. In some embodiments, the decoding devices 150 and 160 are implemented as synchronous decoders. Details about the word line signals W0-W3, the bit line signals B0-B7 and the clock signal DV1B are described below. Figures 4 to 11 The embodiments are further described in the examples.

[0057] like Figure 1 As shown, the memory device 170 is used to generate a data signal DT1 according to word line signals W0-W3, bit line signals B0-B7, and clock signals DV1, DV1B, C5, C6, and CLKB.

[0058] like Figure 1 As shown, the encoding device 180 is used to output the data signal DT2 according to the data signal DT1, the enable signal EN, the clock signal DV1 and the voltage signals Q2 and Q3. In some embodiments, the encoding device 180 is used to encode the data signal DT1 according to the ISO format to generate the data signal DT2. In some embodiments, the encoding device 180 is used to transmit the data signal DT2 to the communication device 110, and the communication device 110 is used to transmit the data signal DT2 to an external device and / or apparatus.

[0059] Figure 2 FIG. 2 is a schematic diagram of a memory chip 200 according to an embodiment of the present invention. Figure 2 As shown, the memory chip 200 includes a counting device 240, decoding devices 250, 260 and a memory device 270. Figure 2 and Figure 1 , the memory chip 200 is an embodiment of the memory chip 100. The counting device 240, the decoding devices 250, 260 and the memory device 270 correspond to the counting device 140, the decoding devices 150, 160 and the memory device 170 respectively, so some details are not repeated. In some embodiments, the memory chip 200 further includes various devices corresponding to the communication device 110, the rectifying device 120, the frequency dividing device 130, the encoding device 180 and the buffer devices BF11, BF12.

[0060] In some embodiments, the counting device 240 is used to provide various signals, such as Figure 1 The clock signals C3-C4 are shown to the decoding device 250 and used to provide various signals, such as Figure 1The clock signals C0-C2 are shown to the decoding device 260. The decoding device 250 is used to generate word line signals W0-W3. The decoding device 260 is used to generate bit line signals B0-B7. The memory device 270 is used to operate according to the word line signals W0-W3 and the bit line signals B0-B7.

[0061] In some embodiments, the memory device 270 includes memory circuits 271-274. In some embodiments, each of the memory circuits 271-274 is used to operate synchronously according to word line signals W0-W3 and bit line signals B0-B7. In some embodiments, each of the memory circuits 271-274 is used to store thirty-two bits of data, wherein the number of thirty-two bits corresponds to the number of word line signals W0-W3 multiplied by the number of bit line signals B0-B7. In the above embodiment, the memory device 270 is used to store one hundred and twenty-eight bits of data. In some embodiments, each of the memory circuits 271-274 is implemented as a dynamic programmable read only memory (DPROM). In some embodiments, each of the memory circuits 271-274 is referred to as a data bank.

[0062] In various embodiments, the memory device 270 may include various numbers of memory circuits, and the decoding device 250 is used to generate a corresponding number of word line signals.

[0063] In some previous practices, the memory device includes only one memory circuit. The decoding device needs to generate a large number of word line signals to asynchronously control the memory circuit. As a result, the decoding device and the counting device used to control the decoding device occupy a large area, and short-circuit current may be generated when the phases of the word line signals overlap.

[0064] Compared to the above method, in the embodiment of the present invention, the decoding device 250 synchronously controls the memory circuits 271-274 with the same word line signals W0-W3, so that the area required by the decoding device 250 and the counting device 240 is smaller and the short-circuit current is reduced.

[0065] Figure 3 FIG. 3 is a schematic diagram of a memory device 300 according to an embodiment of the present invention. Figure 3 As shown, the memory device 300 includes a memory circuit 310 and a control circuit 320. Figure 2 and Figure 3 Memory device 300 is an embodiment of memory device 270. Each of memory circuits 271-274 can be implemented as memory circuit 310, so some details are not repeated.

[0066] like Figure 3 As shown, the memory circuit 310 and the control circuit 320 are coupled to the node N32. In some embodiments, the control circuit 320 is used to adjust the voltage level of the node N32 according to the enable signal ENB and the pulse signal PL to control the memory circuit 310. The memory circuit 310 is used to start or stop according to the voltage level of the node N32, and generates a data signal DT31 according to the word line signal WM and the bit line signal BN when started. Wherein N and M in the word line signal WM and the bit line signal BN are integers greater than or equal to zero. Please refer to Figure 3 and Figure 1 The data signal DT31 is an embodiment of the data signal DT1, the word line signal WM corresponds to the word line signals W0-W3, and the bit line signal BN corresponds to the bit line signals B0-B7. In some embodiments, the enable signal ENB is a complementary signal of the enable signal EN.

[0067] In some embodiments, the memory circuit 310 includes switches T31 and T32. Figure 3 As shown, the control end of the switch T31 ​​is used to receive the bit line signal BN, one end of the switch T31 ​​is coupled to the node N32, and the other end of the switch T31 ​​is coupled to the node N31. The control end of the switch T32 is used to receive the word line signal WM, one end of the switch T32 is coupled to the node N31, and the other end of the switch T32 is used to receive the voltage signal VSS or the ground voltage.

[0068] In some embodiments, the control circuit 320 includes switches T33-T35. Figure 3 As shown, the control end of the switch T33 is used to receive the enable signal ENB, one end of the switch T33 is coupled to the node N33, and the other end of the switch T33 is used to receive the voltage signal VDD or other voltage signals with an enable voltage level. The control end of the switch T34 is used to receive the pulse signal PL, one end of the switch T34 is coupled to the node N33, and the other end of the switch T34 is coupled to the node N32. The control end of the switch T35 is used to receive the enable signal ENB, one end of the switch T35 is coupled to the node N32, and the other end of the switch T35 is used to receive the voltage signal VSS or the ground voltage.

[0069] In some embodiments, the types of switches T31, T32 and T35 are different from the types of switches T33 and T34. For example, switches T31, T32 and T35 are implemented as N-type thin film transistors (NTFT), and switches T33 and T34 are implemented as P-type thin film transistors (PTFT).

[0070] In some embodiments, when the switch T33 is turned on according to the enable signal ENB, the switch T35 is turned off according to the enable signal ENB. When the switch T33 is turned off according to the enable signal ENB, the switch T35 is turned on according to the enable signal ENB.

[0071] In some embodiments, the switch T35 is turned on to pull the voltage level of the node N32 to the voltage level of the voltage signal VSS. When the node N32 has the voltage level of the voltage signal VSS, the voltage difference between the node N32 and the node N34 is substantially equal to zero, and the memory circuit 310 does not generate the data signal DT31. In other words, the switch T35 is turned on to disable the memory circuit 310.

[0072] In some embodiments, the switch T33 is turned on to pull the voltage level of the node N33 to the voltage level of the voltage signal VDD. When the node N33 has the voltage level of the voltage signal VDD, the switch T34 can charge the node N32 when turned on, so that the memory circuit 310 can generate the data signal DT31 according to the word line signal WM and the bit line signal BN. In other words, the switch T33 is turned on to start the memory circuit 310.

[0073] In some previous methods, the nodes in the memory circuit for outputting data signals need to be charged regularly, and the control circuit needs to provide a large current, which results in a large required area and is prone to leakage current.

[0074] Compared to the above-mentioned method, in the embodiment of the present invention, the control circuit 320 disables or activates the memory circuit 310 by the enable signal ENB. When the memory circuit 310 is disabled, no current flows through it, and when the memory circuit 310 is activated, the current flowing through the node N32 is small. The control circuit 320 charges the node N32 at an appropriate time by the pulse signal PL. In this way, the required area of ​​the memory device 300 is smaller and the leakage current is less. Correspondingly, the data signal DT31 has a higher signal quality.

[0075] Figure 4 FIG. 4 is a schematic diagram of a memory device 400 according to an embodiment of the present invention. Figure 1 and Figure 4 , the memory device 400 is an embodiment of the memory device 170. Figure 4 As shown, the memory device 400 includes memory circuits 410-413 and control circuits 420-423. Figure 2 and Figure 4 Memory device 400 is an embodiment of memory device 270. Memory circuits 410-413 correspond to memory circuits 271-274, respectively, so some details are not repeated.

[0076] like Figure 4 As shown, memory circuit 410 is coupled to control circuit 420 at node N40, memory circuit 411 is coupled to control circuit 421 at node N41, memory circuit 412 is coupled to control circuit 422 at node N42, and memory circuit 413 is coupled to control circuit 423 at node N43. In some embodiments, nodes N40-N43 are electrically isolated from each other.

[0077] In some embodiments, the control circuit 420 is used to control the memory circuit 410 according to the enable signal ENB0 and the pulse signal PL, so that the memory circuit 410 generates a data signal DT40 at the node N40. In some embodiments, the control circuit 420 includes switches T403-T405. Figure 3 and Figure 4 The configuration of switches T403-T405 is similar to the configuration of switches T33-T35, and the operation of the control circuit 420 controlling the memory circuit 410 to generate the data signal DT40 according to the enable signal ENB0 and the pulse signal PL is similar to the operation of the control circuit 320 controlling the memory circuit 310 to generate the data signal DT31 according to the enable signal ENB and the pulse signal PL, so some details are not repeated.

[0078] In some embodiments, the control circuit 421 is used to control the memory circuit 411 according to the enable signal ENB1 and the pulse signal PL, so that the memory circuit 411 generates a data signal DT41 at the node N41. In some embodiments, the control circuit 421 includes switches T413-T415. Figure 3 and Figure 4 The configuration of switches T413 to T415 is similar to the configuration of switches T33 to T35, and the operation of the control circuit 421 controlling the memory circuit 411 to generate the data signal DT41 according to the enable signal ENB0 and the pulse signal PL is similar to the operation of the control circuit 320 controlling the memory circuit 310 to generate the data signal DT31 according to the enable signal ENB and the pulse signal PL, so some details are not repeated.

[0079] In some embodiments, the control circuit 422 is used to control the memory circuit 412 according to the enable signal ENB2 and the pulse signal PL, so that the memory circuit 412 generates a data signal DT42 at the node N42. In some embodiments, the control circuit 422 includes switches T423-T425. Figure 3 and Figure 4The configuration of switches T423 to T425 is similar to the configuration of switches T33 to T35, and the operation of the control circuit 422 controlling the memory circuit 412 to generate the data signal DT42 according to the enable signal ENB2 and the pulse signal PL is similar to the operation of the control circuit 320 controlling the memory circuit 310 to generate the data signal DT31 according to the enable signal ENB and the pulse signal PL, so some details will not be repeated.

[0080] In some embodiments, the control circuit 423 is used to control the memory circuit 413 according to the enable signal ENB3 and the pulse signal PL, so that the memory circuit 413 generates a data signal DT43 at the node N43. In some embodiments, the control circuit 423 includes switches T433-T435. Figure 3 and Figure 4 The configuration of switches T433-T435 is similar to the configuration of switches T33-T35, and the operation of the control circuit 423 controlling the memory circuit 413 to generate the data signal DT43 according to the enable signal ENB0 and the pulse signal PL is similar to the operation of the control circuit 320 controlling the memory circuit 310 to generate the data signal DT31 according to the enable signal ENB and the pulse signal PL, so some details are not repeated.

[0081] Please refer to Figure 2 and Figure 4 In some embodiments, each of the memory circuits 410-413 is used to generate a corresponding one of the data signals DT40-DT43 according to the word line signals W0-W4. In some embodiments, the memory circuits 410-413 are further used to generate the data signals DT40-DT43 according to the bit line signals B0-B7.

[0082] In some embodiments, the type of switches T403, T404, T413, T414, T423, T424, T433, T434 is different from the type of switches T405, T415, T425, T435. For example, switches T403, T404, T413, T414, T423, T424, T433, T434 are implemented as PTFTs, and switches T405, T415, T425, T435 are implemented as NTFTs.

[0083] Figure 5 A timing diagram 500 is shown for illustrating the operation of the memory device 400 according to the enable signals ENB0-ENB3 in one embodiment of the present disclosure. Figure 5 As shown, the timing diagram 500 includes periods P51 to P510 that are sequentially and continuously arranged.

[0084] like Figure 5As shown, during period P53, the enable signal ENB0 has a voltage level VL, and the enable signals ENB1-ENB3 have a voltage level VH. Figure 5 and Figure 4 In period P53, in response to the enable signal ENB0 having a voltage level VL, the switch T403 is turned on and the switch T405 is turned off, so that the memory circuit 410 generates the data signal DT40. In period P53, in response to the enable signals ENB1-ENB3 having a voltage level VH, the switches T415, 425 and 435 are turned on and the switches T413, 423 and 433 are turned off, so that the memory circuits 411-413 are disabled. In some embodiments, each of the memory circuits 410-413 does not generate a corresponding one of the data signals DT40-DT43 when disabled.

[0085] like Figure 5 As shown, during period P54, the enable signal ENB1 has a voltage level VL, and the enable signals ENB0, ENB2, and ENB3 have a voltage level VH. Figure 5 and Figure 4 In period P54, in response to the enable signal ENB1 having a voltage level VL, the switch T413 is turned on and the switch T415 is turned off, so that the memory circuit 411 generates the data signal DT41. In period P54, in response to the enable signals ENB0, ENB2, ENB3 having a voltage level VH, the switches T405, 425 and 435 are turned on and the switches T403, 423 and 433 are turned off, so that the memory circuits 410, 412 and 413 are disabled.

[0086] like Figure 5 As shown, during period P55, the enable signal ENB2 has a voltage level VL, and the enable signals ENB0, ENB1, and ENB3 have a voltage level VH. Figure 5 and Figure 4 In period P55, in response to the enable signal ENB2 having a voltage level VL, the switch T423 is turned on and the switch T425 is turned off, so that the memory circuit 412 generates the data signal DT42. In period P55, in response to the enable signals ENB0, ENB1, ENB3 having a voltage level VH, the switches T405, 415 and 435 are turned on and the switches T403, 413 and 433 are turned off, so that the memory circuits 410, 411 and 413 are disabled.

[0087] like Figure 5 As shown, during period P56, the enable signal ENB3 has a voltage level VL, and the enable signals ENB0-ENB2 have a voltage level VH. Figure 5 and Figure 4In period P56, in response to the enable signal ENB3 having a voltage level VL, the switch T433 is turned on and the switch T435 is turned off, so that the memory circuit 413 generates the data signal DT43. In period P56, in response to the enable signal ENB0-ENB2 having a voltage level VH, the switches T415, 425 and 405 are turned on and the switches T413, 423 and 403 are turned off, so that the memory circuits 410-412 are disabled.

[0088] Please refer to Figures 2 to 5 In some embodiments, during periods P53-P56, memory circuits 410-413 are sequentially activated and sequentially generate data signals DT40-DT43 according to the same word line signals W0-W3 and bit line signals B0-B7 when activated.

[0089] like Figure 5 As shown, the operations during periods P57 to P510 are similar to the operations during periods P53 to P56, and the operations during periods P51 to P52 are similar to the operations during periods P55 to P56, so some details are not repeated.

[0090] Fig. 6A FIG. 6 is a schematic diagram of a logic circuit 600A according to an embodiment of the present invention. Figure 4 and Fig. 6A In some embodiments, the logic circuit 600A is included in the memory device 400. Figure 1 , Figure 4 and Fig. 6A , the logic circuit 600A is used to generate enable signals ENB0-ENB3 according to the clock signals C5 and C6.

[0091] In some embodiments, the logic circuit 600A includes logic elements NR60-NR63 and IV60-IV63. In some embodiments, each of the logic elements NR60-NR63 is implemented as a NOR logic gate, and each of the logic elements IV60-IV63 is implemented as an inverter. In some embodiments, the logic elements IV60-IV63 are used to operate according to the clock signal DV1. In various embodiments, the logic elements NR60-NR63 and IV60-IV63 can be implemented as various types of logic elements.

[0092] like Fig. 6A As shown, the two input terminals of the logic element NR60 are used to receive the clock signals C5 and C6 respectively, and the output terminal of the logic element NR60 is used to output the enable signal EN0. The input terminal of the logic element IV60 is used to receive the enable signal EN0, and the output terminal of the logic element IV60 is used to output the enable signal ENB0. In some embodiments, the enable signal EN0 is a complementary signal of the enable signal ENB0.

[0093] like Fig. 6A As shown, the two input terminals of the logic element NR61 are used to receive the clock signals C6 and CB5 respectively, and the output terminal of the logic element NR61 is used to output the enable signal EN1. The input terminal of the logic element IV61 is used to receive the enable signal EN1, and the output terminal of the logic element IV61 is used to output the enable signal ENB1. In some embodiments, the enable signal EN1 is a complementary signal of the enable signal ENB1, and the clock signal CB5 is a complementary signal of the clock signal C5.

[0094] like Fig. 6A As shown, the two input terminals of the logic element NR62 are used to receive the clock signals C5 and CB6 respectively, and the output terminal of the logic element NR62 is used to output the enable signal EN2. The input terminal of the logic element IV62 is used to receive the enable signal EN2, and the output terminal of the logic element IV62 is used to output the enable signal ENB2. In some embodiments, the enable signal EN2 is a complementary signal of the enable signal ENB2, and the clock signal CB6 is a complementary signal of the clock signal C6.

[0095] like Fig. 6A As shown, the two input terminals of the logic element NR63 are used to receive the clock signals CB5 and CB6 respectively, and the output terminal of the logic element NR63 is used to output the enable signal EN3. The input terminal of the logic element IV63 is used to receive the enable signal EN3, and the output terminal of the logic element IV63 is used to output the enable signal ENB3. In some embodiments, the enable signal EN3 is a complementary signal of the enable signal ENB3.

[0096] Figure 6B FIG. 6 is a schematic diagram of a logic circuit 600B according to an embodiment of the present invention. Figure 4 and Figure 6B In some embodiments, the logic circuit 600B is included in the memory device 400. Figure 1 and Fig. 6A , the logic circuit 600B is used to generate the data signal DT1 according to the data signals DT40 ˜ DT43 .

[0097] In some embodiments, the logic circuit 600B includes a logic element OR61. In some embodiments, the logic element OR61 is implemented as an OR logic element. In various embodiments, the logic element OR61 can be implemented as various types of logic elements.

[0098] Figure 6BAs shown, the logic element OR61 is used to receive the data signals DT40-DT43, and to perform an OR operation on the data signals DT40-DT43 to generate the data signal DT1. In some embodiments, the data signal DT1 includes information of the data signals DT40-DT43. For example, each of the data signals DT40-DT43 includes thirty-two bits of information, and the data signal DT1 includes the corresponding one hundred and twenty-eight bits of information.

[0099] Figure 7 FIG. 7 is a schematic diagram of a memory device 700 according to an embodiment of the present invention. Figure 7 As shown, the memory device 700 includes a memory circuit 710 and a control circuit 720. The control circuit 720 is used to control the memory circuit 710 so that the memory circuit 710 generates a data signal DT71 at a node N71. Figure 7 and Figure 3 Memory device 700 is an embodiment of memory device 300. The operation of memory circuit 710 and control circuit 720 to generate data signal DT71 corresponds to the operation of memory circuit 310 and control circuit 320 to generate data signal DT31, so some details are not repeated.

[0100] In some embodiments, the control circuit 720 includes switches T73-T75. In some embodiments, the switch T75 is implemented as an NTFT, and the switches T73 and T74 are implemented as PTFTs. The switches T73-T75 are used to operate according to the enable signal ENB and the pulse signal PL. Figure 7 and Figure 3 The configuration of switches T73-T75 and the operation of switches T73-T75 according to the enable signal ENB and the pulse signal PL are similar to the configuration of switches T33-T35 and the operation of switches T33-T35 according to the enable signal ENB and the pulse signal PL, so some details are not repeated.

[0101] In some embodiments, the memory circuit 710 includes switches Z0-Z7, X00-X03, X10-X13, X20-X23, X30-X33, X40-X43, X50-X53, X60-X63, and X70-X73. Figure 7 and Figure 4, memory circuit 710 is an embodiment of each of memory circuits 410-413. In some embodiments, each of memory circuits 410-413 has a configuration similar to memory circuit 710. In the above embodiments, the operation of memory circuits 410-413 to generate data signals DT40-DT43 is similar to the operation of memory circuit 710 to generate data signal DT71. In some embodiments, switches Z0-Z7, X00-X03, X10-X13, X20-X23, X30-X33, X40-X43, X50-X53, X60-X63, and X70-X73 are implemented as NTFTs.

[0102] like Figure 7 As shown, the control terminals of the switches Z0-Z7 are respectively used to receive the bit line signals B0-B7. The first terminals of the switches Z0-Z7 are coupled to the node N71, and the second terminals of the switches Z0-Z7 are respectively coupled to the nodes N72-N79.

[0103] like Figure 7 As shown, the control ends of switches X00, X10, X20, X30, X40, X50, X60 and X70 are used to receive word line signal W0, the control ends of switches X01, X11, X21, X31, X41, X51, X61 and X71 are used to receive word line signal W1, the control ends of switches X02, X12, X22, X32, X42, X52, X62 and X72 are used to receive word line signal W2, and the control ends of switches X03, X13, X23, X33, X43, X53, X63 and X73 are used to receive word line signal W3.

[0104] like Figure 7 As shown, the first ends of the switches X00-X03 are coupled to the node N79, the first ends of the switches X10-X13 are coupled to the node N78, the first ends of the switches X20-X23 are coupled to the node N77, the first ends of the switches X30-X33 are coupled to the node N76, the first ends of the switches X40-X43 are coupled to the node N75, the first ends of the switches X50-X53 are coupled to the node N74, the first ends of the switches X60-X63 are coupled to the node N73, and the first ends of the switches X70-X73 are coupled to the node N72. The second ends of the switches Z0-Z7, X00-X03, X10-X13, X20-X23, X30-X33, X40-X43, X50-X53, X60-X63 and X70-X73 are used to receive the voltage signal VSS or the ground voltage.

[0105] exist Figure 7In the illustrated embodiment, the memory circuit 710 is used to store thirty-two bits of data, wherein switches X00-X03, X10-X13, X20-X23, X30-X33, X40-X43, X50-X53, X60-X63 and X70-X73 are respectively used to read a corresponding bit of data to generate a data signal DT71 having thirty-two bits.

[0106] Please refer to Figure 7 and Figure 3 For integers i and j greater than or equal to zero and less than or equal to 7, and an integer k greater than or equal to zero and less than or equal to 3, the configuration of switches Zi and Xjk and the operation of switches Zi and Xjk generating data signal DT71 according to word line signals W0~W3 and bit line signals B0~B7 are similar to the configuration of switches T31 and T32 and the operation of switches T31 and T32 generating data signal DT31 according to word line signal WM and bit line signal BN, so some details will not be repeated.

[0107] In some embodiments, the control circuit 710 further includes a cutting area 712. Figure 7 As shown, the cutting area 712 is between switches Z0-Z7, X00-X03, X10-X13, X20-X23, X30-X33, X40-X43, X50-X53, X60-X63, X70-X73 and a voltage source providing voltage signal VSS. In some embodiments, the cutting area 712 includes a bus line for laser cutting.

[0108] Figure 8 FIG. 8 is a schematic diagram of a logic circuit 800 according to an embodiment of the present invention. Figure 1 and Figure 8 In some embodiments, the logic circuit 800 is included in the decoding device 160. Figure 8 As shown, the logic circuit 800 is used to generate bit line signals B0-B7 according to the clock signals C0-C2 and CB0-CB2. In some embodiments, the clock signals CB0-CB2 are complementary signals of the clock signals C0-C2 respectively.

[0109] In some embodiments, the logic circuit 800 includes logic elements ND81-ND84, NR81-NR88, NV81-NV86, and IV81-IV86. In some embodiments, each of the logic elements ND81-ND84 is implemented as a NAND logic gate, each of the logic elements NR81-NR88 is implemented as a NOR logic gate, and each of the logic elements NV81-NV86 and IV81-IV86 is implemented as an inverter. In some embodiments, each of IV81-IV86 is used to operate according to the clock signal DV1.

[0110] like Figure 8 As shown, the input end of the logic element IV81 is used to receive the clock signal CB2, and the output end of the logic element IV81 is coupled to the input end of the logic element NV81. The output end of the logic element NV81 is used to output the enable signal EL2. The input end of the logic element IV82 is used to receive the clock signal C2, and the output end of the logic element IV82 is coupled to the input end of the logic element NV82. The output end of the logic element NV82 is used to output the enable signal ELB2.

[0111] like Figure 8 As shown, the two input terminals of the logic element ND81 are respectively used to receive the clock signals C1 and C0, and the output terminal of the logic element ND81 is coupled to the input terminal of the logic element IV83. The output terminal of the logic element IV83 is coupled to the input terminal of the logic element NV83. An input terminal of the logic element NR81 is used to receive the enable signal EL2, the other input terminal of the logic element NR81 is coupled to the output terminal of the logic element NV83, and the output terminal of the logic element NR81 is used to output the bit line signal B0. An input terminal of the logic element NR82 is used to receive the enable signal ELB2, the other input terminal of the logic element NR82 is coupled to the output terminal of the logic element NV83, and the output terminal of the logic element NR82 is used to output the bit line signal B4.

[0112] like Figure 8 As shown, the two input terminals of the logic element ND82 are respectively used to receive the clock signals C1 and CB0, and the output terminal of the logic element ND82 is coupled to the input terminal of the logic element IV84. The output terminal of the logic element IV84 is coupled to the input terminal of the logic element NV84. An input terminal of the logic element NR83 is used to receive the enable signal EL2, the other input terminal of the logic element NR83 is coupled to the output terminal of the logic element NV84, and the output terminal of the logic element NR83 is used to output the bit line signal B1. An input terminal of the logic element NR84 is used to receive the enable signal ELB2, the other input terminal of the logic element NR84 is coupled to the output terminal of the logic element NV84, and the output terminal of the logic element NR84 is used to output the bit line signal B5.

[0113] like Figure 8 As shown, the two input terminals of the logic element ND83 are respectively used to receive the clock signals CB1 and C0, and the output terminal of the logic element ND83 is coupled to the input terminal of the logic element IV85. The output terminal of the logic element IV85 is coupled to the input terminal of the logic element NV85. An input terminal of the logic element NR85 is used to receive the enable signal EL2, the other input terminal of the logic element NR85 is coupled to the output terminal of the logic element NV85, and the output terminal of the logic element NR85 is used to output the bit line signal B2. An input terminal of the logic element NR86 is used to receive the enable signal ELB2, the other input terminal of the logic element NR86 is coupled to the output terminal of the logic element NV85, and the output terminal of the logic element NR86 is used to output the bit line signal B6.

[0114] like Figure 8 As shown, the two input terminals of the logic element ND84 are respectively used to receive the clock signals CB1 and CB0, and the output terminal of the logic element ND84 is coupled to the input terminal of the logic element IV86. The output terminal of the logic element IV86 is coupled to the input terminal of the logic element NV86. An input terminal of the logic element NR87 is used to receive the enable signal EL2, the other input terminal of the logic element NR87 is coupled to the output terminal of the logic element NV86, and the output terminal of the logic element NR87 is used to output the bit line signal B3. An input terminal of the logic element NR88 is used to receive the enable signal ELB2, the other input terminal of the logic element NR88 is coupled to the output terminal of the logic element NV86, and the output terminal of the logic element NR88 is used to output the bit line signal B7.

[0115] Fig. 9 FIG. 9 is a schematic diagram of a logic circuit 900 according to an embodiment of the present invention. Figure 1 and Fig. 9 In some embodiments, the logic circuit 900 is included in the decoding device 150. Fig. 9 As shown, logic circuit 900 is used to generate pulse signal PL according to clock signals CLKB and DV1B, and to generate word line signals W0-W3 according to pulse signal PL, clock signals C3-C4 and CB3-CB4. In some embodiments, clock signals CB3-CB4 are complementary signals of clock signals C3-C4 respectively.

[0116] In some embodiments, the logic circuit 900 includes logic elements AD91-AD94, NR91-NR95, NV91-NV94, and IV91-IV94. In some embodiments, each of the logic elements AD91-AD94 is implemented as an AND logic gate, each of the logic elements NR91-NR95 is implemented as a NOR logic gate, and each of the logic elements NV91-NV94 and IV91-IV94 is implemented as an inverter. In some embodiments, each of IV91-IV94 is used to operate according to the clock signal DV1.

[0117] like Fig. 9 As shown, the two input terminals of the logic element NR91 are respectively used to receive the clock signals CLKB and DV1B, and the output terminal of the logic element NR91 is used to output the pulse signal PL.

[0118] like Fig. 9 As shown, the two input terminals of the logic element NR92 are used to receive the clock signals C3 and C4 respectively, and the output terminal of the logic element NR92 is coupled to the input terminal of the logic element IV91. The output terminal of the logic element IV91 is coupled to the input terminal of the logic element NV91. An input terminal of the logic element AD91 is coupled to the output terminal of the logic element NV91, and the other input terminal of the logic element AD91 is used to receive the pulse signal PL. The output terminal of the logic element AD91 is used to output the word line signal W0.

[0119] like Fig. 9 As shown, the two input terminals of the logic element NR93 are used to receive the clock signals CB3 and C4 respectively, and the output terminal of the logic element NR93 is coupled to the input terminal of the logic element IV92. The output terminal of the logic element IV92 is coupled to the input terminal of the logic element NV92. An input terminal of the logic element AD92 is coupled to the output terminal of the logic element NV92, and the other input terminal of the logic element AD92 is used to receive the pulse signal PL. The output terminal of the logic element AD92 is used to output the word line signal W1.

[0120] like Fig. 9 As shown, the two input terminals of the logic element NR94 are used to receive the clock signals C3 and CB4 respectively, and the output terminal of the logic element NR94 is coupled to the input terminal of the logic element IV93. The output terminal of the logic element IV93 is coupled to the input terminal of the logic element NV93. An input terminal of the logic element AD93 is coupled to the output terminal of the logic element NV93, and the other input terminal of the logic element AD93 is used to receive the pulse signal PL. The output terminal of the logic element AD93 is used to output the word line signal W2.

[0121] like Fig. 9As shown, the two input terminals of the logic element NR95 are used to receive the clock signals CB3 and CB4 respectively, and the output terminal of the logic element NR95 is coupled to the input terminal of the logic element IV94. The output terminal of the logic element IV94 is coupled to the input terminal of the logic element NV94. An input terminal of the logic element AD94 is coupled to the output terminal of the logic element NV94, and the other input terminal of the logic element AD94 is used to receive the pulse signal PL. The output terminal of the logic element AD94 is used to output the word line signal W3.

[0122] Fig.10 A timing diagram 1000 is shown for generating a data signal DT1 by a memory chip 100 according to an embodiment of the present disclosure. Fig.10 As shown, the timing diagram 1000 includes periods Q1 to Q15 which are arranged sequentially and continuously. Figure 1 , Figure 4 and Figure 7 ,exist Fig.10 In the illustrated embodiment, the memory device 170 may be implemented as the memory device 400 and / or the memory device 700 to operate according to the timing diagram 1000 .

[0123] Please refer to Figure 5 and Fig.10 , period P53 corresponds to period Q1-Q15. In some embodiments, during period Q1-Q15, enable signal ENB0 has a voltage level VL, and enable signals ENB1-ENB3 have a voltage level VH. Correspondingly, please refer to Figure 4 , Figure 5 and Fig.10 During the period Q1-Q15, the memory circuit 410 generates the data signal DT40 at the node N40, and the memory circuits 411-413 are disabled.

[0124] like Fig.10 As shown, during period Q1, the clock signals CLK, C0-C2 and DV1 have a voltage level VL, so that the pulse signal PL has a voltage level VH, and the bit line signal B7 and the word line signal W0 have a voltage level VL.

[0125] Please refer to Fig.10 and Figure 7 In period Q1, switch Z7 is closed according to bit line signal B7, switch X70 is closed according to word line signal W0, and switch T74 is closed according to pulse signal PL.

[0126] like Fig.10 As shown, during period Q2, clock signals CLK and C0-C2 have voltage levels VL, clock signal DV1 has voltage level VH, so that pulse signal PL has voltage level VL, bit line signal B7 has voltage level VH, and word line signal W0 has voltage level VL.

[0127] Please refer to Fig.10 and Figure 7 In period Q2, switch Z7 is turned on according to bit line signal B7, switch X70 is turned off according to word line signal W0, switch T74 is turned on according to pulse signal PL, and switch T73 is turned on according to pulse signal ENB. At this time, switches T73 and T74 provide voltage signal VDD to node N71 to charge node N71, so that data signal DT71 is pulled to voltage level VH. Correspondingly, data signal DT1 including information of data signal DT71 has voltage level VH. In some embodiments, period Q2 is called charging period.

[0128] like Fig.10 As shown, during period Q3, clock signals C0-C2 and DV1 have voltage levels VL, clock signal CLK has voltage level VH, so that pulse signal PL has voltage level VH, bit line signal B7 has voltage level VH, and word line signal W0 has voltage level VH.

[0129] Please refer to Fig.10 and Figure 7 In period Q3, switch Z7 is turned on according to bit line signal B7, switch X70 is turned on according to word line signal W0, switch T74 is turned off according to pulse signal PL, and switch T73 is turned on according to pulse signal ENB. At this time, node N71 is discharged through switches Z7 and X70 to generate data signal DT71.

[0130] exist Fig.10 In the embodiment shown, the bits corresponding to the switches Z7 and X70 have a first logic value (eg, logic value 1), so that the data signal DT71 has a voltage level VH during period Q3. Correspondingly, the data signal DT1 including information of the data signal DT71 has a voltage level VH.

[0131] like Fig.10 As shown, during period Q4, clock signals C0-C2 have voltage level VL, clock signals CLK and DV1 have voltage level VH, so that pulse signal PL has voltage level VH, bit line signal B7 has voltage level VH, and word line signal W0 has voltage level VH.

[0132] Please refer to Fig.10 and Figure 7 In period Q4, switch Z7 is turned on according to bit line signal B7, switch X70 is turned on according to word line signal W0, switch T74 is turned off according to pulse signal PL, and switch T73 is turned on according to pulse signal ENB. At this time, node N71 is discharged through switches Z7 and X70 to generate data signal DT71.

[0133] exist Fig.10In the embodiment shown, the bits corresponding to the switches Z7 and X70 have the first logic value, so that the data signal DT71 has the voltage level VH during the period Q4. Correspondingly, the data signal DT1 including the information of the data signal DT71 has the voltage level VH.

[0134] like Fig.10 As shown, during period Q5, clock signals CLK, C1-C2 and DV1 have voltage levels VL, clock signal C0 has voltage level VH, so that pulse signal PL has voltage level VH, bit line signal B7 has voltage level VH, and word line signal W0 has voltage level VH.

[0135] Please refer to Fig.10 and Figure 7 In period Q5, switch Z7 is turned on according to bit line signal B7, switch X70 is turned on according to word line signal W0, switch T74 is turned off according to pulse signal PL, and switch T73 is turned on according to pulse signal ENB. At this time, node N71 is discharged through switches Z7 and X70 to generate data signal DT71. In some embodiments, periods Q3 to Q5 are called discharge periods.

[0136] exist Fig.10 In the embodiment shown, the bits corresponding to the switches Z7 and X70 have the first logic value, so that the data signal DT71 has the voltage level VH during the period Q5. Correspondingly, the data signal DT1 including the information of the data signal DT71 has the voltage level VH.

[0137] like Fig.10 As shown, during period Q6, clock signals CLK and C1-C2 have voltage level VL, clock signals C0 and DV1 have voltage level VH, so that pulse signal PL, bit line signal B7 and word line signal W0 have voltage level VL, and bit line signal B6 has voltage level VH.

[0138] Please refer to Fig.10 and Figure 7 In period Q6, switch Z7 is closed according to bit line signal B7, switch Z6 is turned on according to bit line signal B6, switch X60 is closed according to word line signal W0, switch T74 is turned on according to pulse signal PL, and switch T73 is turned on according to pulse signal ENB. At this time, switches T73 and T74 provide voltage signal VDD to node N71 to charge node N71, so that data signal DT71 is pulled to voltage level VH. Correspondingly, data signal DT1 including information of data signal DT71 has voltage level VH. In some embodiments, period Q6 is called charging period.

[0139] Please refer to Fig.10 and Figure 7In period Q7, the pulse signal PL has a voltage level VH, the bit line signal B6 has a voltage level VH, and the word line signal W0 has a voltage level VH, so that the switch Z6 is turned on according to the bit line signal B6, the switch X60 is turned on according to the word line signal W0, the switch T74 is turned off according to the pulse signal PL, and the switch T73 is turned on according to the pulse signal ENB. At this time, the node N71 is discharged through the switch Z6 and X60 to generate the data signal DT71 and the corresponding data signal DT1.

[0140] In some embodiments, the operation of the memory device 700 discharging through switches Z6 and X60 to generate the data signal DT71 during period Q7 according to the pulse signal PL, the bit line signal B6 and the word line signal W0 is similar to the operation of the memory device 700 discharging through switches Z7 and X70 to generate the data signal DT71 during periods Q3 to Q5 according to the pulse signal PL, the bit line signal B7 and the word line signal W0, so some details are not repeated.

[0141] like Fig.10 As shown, during period Q8, bit line signals B7 and B6 have voltage level VL, and bit line signal B5 has voltage level VH. In some embodiments, the operation of the memory device 700 charging node N71 according to pulse signal PL, bit line signal B5 and word line signal W0 during period Q8, and discharging through switches Z5 and X50 to generate data signal DT71 is similar to the operation of the memory device 700 charging node N71 according to pulse signal PL, bit line signal B7 and word line signal W0 during periods Q2-Q5, and discharging through switches Z7 and X70 to generate data signal DT71, so some details are not repeated.

[0142] like Fig.10 As shown, the bit line signals B4-B0 have a voltage level VH during periods Q9-Q13, respectively. The node N71 is discharged through switches Z4-Z0 during periods Q9-Q13, respectively, to generate a data signal DT71. Each of the operations of the memory device 700 corresponding to the bit line signal B4 during period Q9, the operations corresponding to the bit line signal B3 during period Q10, the operations corresponding to the bit line signal B2 during period Q11, the operations corresponding to the bit line signal B1 during period Q12, and the operations corresponding to the bit line signal B0 during period Q13 are similar to the operations of the memory device 700 corresponding to the bit line signal B7 during periods Q2-Q5, and therefore some details are not repeated.

[0143] exist Fig.10 In the illustrated embodiment, during periods Q11-Q13, the bits corresponding to switches X20, X10 and X00 have a second logic value (eg, logic value 0), so that data signal DT1 has a voltage level VL when word line signal W0 has a voltage level VH during periods Q11-Q13.

[0144] Please refer to Fig.10 and Figure 7 During periods Q1 to Q13, switches X70, X60, X50, X40, X30, X20, X10, and X00 that receive word line signal W0 sequentially generate data signal DT71. Fig.10 In the illustrated embodiment, the logic values ​​of the eight bits corresponding to switches X70, X60, X50, X40, X30, X20, X10 and X00 are 1, 1, 1, 1, 1, 0, 0 and 0, respectively.

[0145] like Fig.10 As shown, during period Q14, the word line signal W0 has a voltage level VL, and the word line signal W1 ( Fig.10 ) and the bit line signal B7 has a voltage level VH. Fig.10 and Figure 7 In period Q14, switch Z7 is turned on according to bit line signal B7, and switch X71 is turned on according to word line signal W1. At this time, node N71 is discharged through switches Z7 and X71 to generate data signal DT71.

[0146] like Fig.10 As shown, during period Q15, the word line signal W0 has a voltage level VL, and the word line signal W1 ( Fig.10 ) and the bit line signal B6 has a voltage level VH. Fig.10 and Figure 7 In period Q15, switch Z6 is turned on according to bit line signal B6, and switch X61 is turned on according to word line signal W1. At this time, node N71 is discharged through switches Z6 and X61 to generate data signal DT71.

[0147] In some embodiments, the operation of the memory device 700 corresponding to the bit line signal B7 and the word line signal W1 during period Q14, and the operation of the memory device 700 corresponding to the bit line signal B6 and the word line signal W1 during period Q15 are each similar to the operation of the memory device 700 corresponding to the bit line signal B7 and the word line signal W0 during periods Q2 to Q5, so some details are not repeated.

[0148] In some embodiments, the duration of the periods Q1-Q4 is approximately 1 / 106,000 of a second. In some embodiments, the frequency of the clock signal DV1 is approximately 212 kHz.

[0149] Fig.11 A timing diagram 1100 is shown for generating a data signal DT1 by a memory chip 100 according to an embodiment of the present disclosure. Fig.11 As shown, the timing diagram 1100 includes periods J1 to J9 which are arranged sequentially and continuously. Figure 1 , Figure 4, Figure 6B ,exist Fig.10 In the illustrated embodiment, the memory device 170 may be implemented as the memory device 400 and / or the memory device 700 , and may include a logic circuit 600B to operate according to the timing diagram 1100 .

[0150] like Fig.11 As shown, in period J1, clock signals C3-C6 have a voltage level VL, so that word line signal W0 and enable signals ENB1-ENB3 have a voltage level VH, and word line signals W1-W3 and enable signal ENB0 have a voltage level VL.

[0151] Please refer to Fig.11 and Figure 7 During period J1, switches X00, X10, X20, X30, X40, X50, X60 and X70 are turned on according to word line signal W0, so that memory device 700 generates data signal DT71 corresponding to the bits of switches X00, X10, X20, X30, X40, X50, X60 and X70.

[0152] Similarly, see Fig.11 and Figure 4 In period J1, the control circuit 420 activates the memory circuit 410 according to the enable signal ENB0, so that the memory circuit 410 generates the data signal DT40 corresponding to the word line signal W0 according to the word line signal W0. At this time, the control circuits 421-423 disable the memory circuits 411-413 according to the enable signals ENB1-ENB3, so that the nodes N41-N43 have the voltage level VL.

[0153] like Fig.11 As shown, during period J2, clock signals C4-C6 have voltage level VL, clock signal C3 has voltage level VH, so that word line signal W1 and enable signals ENB1-ENB3 have voltage level VH, and word line signals W0, W2-W3 and enable signal ENB0 have voltage level VL.

[0154] Please refer to Fig.11 and Figure 7 During period J2, switches X01, X11, X21, X31, X41, X51, X61 and X71 are turned on according to word line signal W1, so that memory device 700 generates data signal DT71 corresponding to the bits of switches X01, X11, X21, X31, X41, X51, X61 and X71.

[0155] Similarly, see Fig.11 and Figure 4During period J2, the control circuit 420 activates the memory circuit 410 according to the enable signal ENB0, so that the memory circuit 410 generates the data signal DT40 corresponding to the word line signal W1 according to the word line signal W1. At this time, the control circuits 421-423 disable the memory circuits 411-413 according to the enable signals ENB1-ENB3, so that the nodes N41-N43 have the voltage level VL.

[0156] Please refer to Fig.11 and Fig.10 In some embodiments, the memory circuit 410 operates according to the word line signal W0 during the period J1 and the period Q1 to Q13, and operates according to the word line signal W1 during the period J2 and the period Q14 to Q15.

[0157] In some embodiments, the duration of period J1 is approximately equal to the duration of periods Q1 to Q13. Fig.11 and Fig.10 As shown, the frequency of the clock signal DV1 is approximately twice the frequency of the clock signal CLK, the frequency of the clock signal CLK is approximately twice the frequency of the clock signal C0, the frequency of the clock signal C0 is approximately twice the frequency of the clock signal C1, the frequency of the clock signal C1 is approximately twice the frequency of the clock signal C2, the frequency of the clock signal C2 is approximately twice the frequency of the clock signal C3, the frequency of the clock signal C3 is approximately twice the frequency of the clock signal C4, the frequency of the clock signal C4 is approximately twice the frequency of the clock signal C5, and the frequency of the clock signal C5 is approximately twice the frequency of the clock signal C6.

[0158] like Fig.11 As shown, during period J3, clock signals C3, C5-C6 have voltage level VL, clock signal C4 has voltage level VH, so that word line signal W2 and enable signals ENB1-ENB3 have voltage level VH, and word line signals W0, W1, W3 and enable signal ENB0 have voltage level VL.

[0159] Please refer to Fig.11 and Figure 7 During period J3, switches X02, X12, X22, X32, X42, X52, X62 and X72 are turned on according to word line signal W2, so that memory device 700 generates data signal DT71 corresponding to the bits of switches X02, X12, X22, X32, X42, X52, X62 and X72.

[0160] Similarly, see Fig.11 and Figure 4During period J3, the control circuit 420 activates the memory circuit 410 according to the enable signal ENB0, so that the memory circuit 410 generates the data signal DT40 corresponding to the word line signal W2 according to the word line signal W2. At this time, the control circuits 421-423 disable the memory circuits 411-413 according to the enable signals ENB1-ENB3, so that the nodes N41-N43 have the voltage level VL.

[0161] like Fig.11 As shown, during period J4, clock signals C5 and C6 have voltage level VL, clock signals C3 and C4 have voltage level VH, so that word line signal W3 and enable signals ENB1-ENB3 have voltage level VH, and word line signals W0, W1, W2 and enable signal ENB0 have voltage level VL.

[0162] Please refer to Fig.11 and Figure 7 During period J4, switches X03, X13, X23, X33, X43, X53, X63 and X73 are turned on according to word line signal W3, so that memory device 700 generates data signal DT71 corresponding to the bits of switches X03, X13, X23, X33, X43, X53, X63 and X73.

[0163] Similarly, see Fig.11 and Figure 4 In period J4, the control circuit 420 activates the memory circuit 410 according to the enable signal ENB0, so that the memory circuit 410 generates the data signal DT40 corresponding to the word line signal W3 according to the word line signal W3. At this time, the control circuits 421-423 disable the memory circuits 411-413 according to the enable signals ENB1-ENB3, so that the nodes N41-N43 have the voltage level VL.

[0164] like Fig.11 As shown, during period J5, clock signals C4, C3 and C6 have voltage level VL, clock signal C5 has voltage level VH, so that word line signal W0 and enable signals ENB0, ENB2, ENB3 have voltage level VH, and word line signals W3, W1, W2 and enable signal ENB1 have voltage level VL.

[0165] Please refer to Fig.11 and Figure 7 During period J5, switches X00, X10, X20, X30, X40, X50, X60 and X70 are turned on according to word line signal W0, so that memory device 700 generates data signal DT71 corresponding to the bits of switches X00, X10, X20, X30, X40, X50, X60 and X70.

[0166] Similarly, see Fig.11 and Figure 4 In period J5, the control circuit 421 activates the memory circuit 411 according to the enable signal ENB1, so that the memory circuit 411 generates the data signal DT41 corresponding to the word line signal W0 according to the word line signal W0. At this time, the control circuits 420, 422, 423 disable the memory circuits 410, 412, and 413 according to the enable signals ENB0, ENB2, and ENB3, so that the nodes N40, N42, and N43 have the voltage level VL.

[0167] During the period J6, the enable signal ENB1 has a voltage level VL, and the memory circuit 411 generates the data signal DT41 corresponding to the word line signals W1-W3 in sequence according to the word line signals W1-W3. The operation of the memory circuit 411 generating the data signal DT41 according to the enable signal ENB1 and the word line signals W1-W3 during the period J6 is similar to the operation of the memory circuit 410 generating the data signal DT40 according to the enable signal ENB0 and the word line signals W1-W3 during the periods J2-J4, so some details are not repeated.

[0168] During the period J7, the enable signal ENB2 has a voltage level VL, and the memory circuit 412 generates the data signal DT42 corresponding to the word line signals W0-W3 in sequence according to the word line signals W0-W3. The operation of the memory circuit 412 generating the data signal DT42 according to the enable signal ENB2 and the word line signals W0-W3 during the period J7 is similar to the operation of the memory circuit 410 generating the data signal DT40 according to the enable signal ENB0 and the word line signals W0-W3 during the periods J1-J4, so some details are not repeated.

[0169] During the period J8, the enable signal ENB3 has a voltage level VL, and the memory circuit 413 generates the data signal DT43 corresponding to the word line signals W0-W3 in sequence according to the word line signals W0-W3. The operation of the memory circuit 413 generating the data signal DT43 according to the enable signal ENB3 and the word line signals W0-W3 during the period J8 is similar to the operation of the memory circuit 410 generating the data signal DT40 according to the enable signal ENB0 and the word line signals W0-W3 during the periods J1-J4, so some details are not repeated.

[0170] During the period J9, the enable signal ENB0 has a voltage level VL, and the memory circuit 410 generates data signals DT40 corresponding to the word line signals W0-W3 in sequence according to the word line signals W0-W3. The operation of the memory circuit 410 generating the data signal DT40 according to the enable signal ENB0 and the word line signals W0-W3 during the period J9 is similar to the operation of the memory circuit 410 generating the data signal DT40 according to the enable signal ENB0 and the word line signals W0-W3 during the periods J1-J4, so some details are not repeated.

[0171] Please refer to Fig.11 and Figure 5 , periods J1 to J4 correspond to period P53, periods J5 to J6 correspond to period P54, period J7 corresponds to period P55, period J8 corresponds to period P56, and period J8 corresponds to period P57.

[0172] like Fig.11 As shown, during the periods J1 to J8, the memory circuits 410 to 413 sequentially generate data signals DT40 to DT43. Fig.11 and Figure 6B , the logic circuit 600B is used to combine the data signals DT40 ˜ DT43 together during the periods J1 ˜ J8 to generate the data signal DT1 .

[0173] The aforementioned various control timings and circuit configurations of the present disclosure are for illustration only, and other various control timings and circuit configurations are within the scope of the present disclosure.

[0174] In summary, in the embodiment of the present invention, the memory chip controls the memory device 170 according to the clock signals C0-C6, so that the multiple memory circuits 410-413 in the memory device 170 sequentially generate multiple data signals DT40-DT43 according to the same word line signals W0-W3. In this way, the current required by the memory device 170 is lower, and the required area of ​​the decoding device 150 for generating the word line signals W0-W3 is smaller. In some embodiments, the memory device 170 is suitable for low temperature polysilicon (LTPS) process.

[0175] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A memory chip, characterized in that: A memory device is provided, the memory device comprising: a first memory circuit, configured to output a first data signal at a first node; A first control circuit, comprising: a first switch, a control terminal of the first switch is used to receive a first enabling signal, and a first terminal of the first switch is coupled to the first node; a second switch, a control terminal of the second switch is used to receive a pulse signal, and a first terminal of the second switch is coupled to the first node; and a third switch, a control terminal of the third switch is used to receive the first enabling signal, a first terminal of the third switch is coupled to a second terminal of the second switch, a second memory circuit for outputting a second data signal at a second node; and A second control circuit comprising: a fourth switch, a control terminal of the fourth switch being used to receive a second enabling signal, and a first terminal of the fourth switch being coupled to the second node; a fifth switch, a control terminal of the fifth switch is used to receive the pulse signal, and a first terminal of the fifth switch is coupled to the second node; and A sixth switch, a control end of the sixth switch is used to receive the second enabling signal, and a first end of the sixth switch is coupled to a second end of the fifth switch.

2. The memory chip according to claim 1, wherein: The memory device further comprises: a first logic circuit for performing a first logic operation to generate the first enable signal according to a first clock signal and a second clock signal, and for performing a second logic operation to generate the second enable signal according to a complementary signal of the first clock signal and the second clock signal, A frequency of the second clock signal is approximately twice a frequency of the first clock signal.

3. The memory chip as claimed in claim 2, characterized in that: Also includes: a second logic circuit for performing a third logic operation to generate the pulse signal according to a third clock signal and a fourth clock signal, wherein a frequency of the fourth clock signal is approximately twice a frequency of the third clock signal, and A frequency of the third clock signal is approximately sixty-four times a frequency of the second clock signal.

4. The memory chip as claimed in claim 1, wherein: The first memory circuit comprises: a seventh switch, a first terminal of the seventh switch being coupled to the first node; and an eighth switch, a first terminal of the eighth switch being coupled to a second terminal of the seventh switch, The second switch, the third switch, the fifth switch and the sixth switch are of a type different from the first switch, the fourth switch, the seventh switch and the eighth switch.

5. The memory chip as claimed in claim 4, characterized in that: The second memory circuit is further configured to generate the second data signal according to at least a word line signal and a bit line signal. A control terminal of the seventh switch is used to receive the bit line signal, and A control terminal of the eighth switch is used for receiving the word line signal.

6. The memory chip as claimed in claim 1, wherein: The memory device further comprises: a third memory circuit, configured to output a third data signal at a third node; A third control circuit, comprising: a seventh switch, a control terminal of the seventh switch being used to receive a third enabling signal, and a first terminal of the seventh switch being coupled to the third node; an eighth switch, a control terminal of the eighth switch is used to receive the pulse signal, and a first terminal of the eighth switch is coupled to the third node; and A ninth switch, a control end of the ninth switch is used to receive the third enabling signal, and a first end of the ninth switch is coupled to a second end of the eighth switch.

7. The memory chip as claimed in claim 6, characterized in that: The memory device further comprises: a fourth memory circuit, configured to output a fourth data signal at a fourth node; A fourth control circuit comprising: a tenth switch, a control terminal of the tenth switch is used to receive a fourth enabling signal, and a first terminal of the tenth switch is coupled to the fourth node; an eleventh switch, a control end of the eleventh switch is used to receive the pulse signal, and a first end of the eleventh switch is coupled to the fourth node; and A twelfth switch, a control end of the twelfth switch is used to receive the fourth enabling signal, and a first end of the twelfth switch is coupled to a second end of the eleventh switch.

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