A dry, contamination-free method of patterning wafer-level two-dimensional semiconductors

Abstract

A dry and pollution-free method for patterning wafer-level two-dimensional semiconductor, comprising the following steps: (1) preparing a grid-shaped patterned three-dimensional stamp; (2) preparing a metal-modified grid-shaped patterned three-dimensional stamp; (3) pressing the metal-modified grid-shaped patterned three-dimensional stamp on the wafer-level two-dimensional semiconductor to form a shape-retaining contact; (4) separating the metal-modified grid-shaped patterned three-dimensional stamp from the wafer-level two-dimensional semiconductor, thereby obtaining a dry and pollution-free patterned wafer-level two-dimensional semiconductor. The method can be used to pattern wafer-level two-dimensional semiconductor in a pollution-free, efficient and scalable manner.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a dry and non-polluted method for patterning wafer-level two-dimensional semiconductors. BACKGROUND

[0002] Two-dimensional (2D) semiconductors have attracted great interest as the channel material for future transistors due to their atomic-thin thickness and dangling-bond-free surface. Patterning of 2D semiconductors separates the continuous monolayer into independent units, which is crucial for the electrical isolation of 2D semiconductors and further integration into complex circuits. However, current 2D patterning techniques largely follow the silicon-based approach, i.e. using photolithography as a mask and then using plasma (or active ion) etching to remove the unwanted 2D material. In this process, the photoresist inevitably leaves photoresist residues on the 2D surface after removal, leading to large device-to-device variations in 2D transistors. More importantly, the randomly distributed polymer residues also exist in the metal contact area, leading to inhomogeneous contact resistance and contact barrier, further expanding the device-to-device variations and reducing the electrical performance. Since 2D materials have a monolayer thickness, 2D transistors are essentially a "full-surface device", whose overall device performance depends not only on its intrinsic properties, but also largely on its surface properties. Therefore, even a small amount of polymer residues (caused by the patterning process) will become scattering or doping centers, thus reducing the uniformity and yield of wafer-scale devices.

[0003] To avoid polymer residues in the traditional patterning process and improve the uniformity of devices, people have devoted to developing dry patterning processes. In other dry patterning processes, 2D monolayers are patterned (or cut) by pure mechanical force or thermal-mechanical indentation, and the patterning process does not come into direct contact with any polymer, so the patterned area presents an atomically clean surface without residues. Similarly, laser can also directly remove the unwanted 2D material through simple local thermal effect, thus realizing a photoresist-free process and a residue-free 2D surface. However, these methods are based on the slow movement of probe tips or laser spots, which are both time-consuming and cannot be further expanded in size. Moreover, the laser cutting process can cause local temperature rise, so that the edge may appear in an oxidized state.

[0004] In the existing technology, wafer-level patterning needs to use photoresist as a mask, and there is currently no method that can pattern 2D semiconductors in large size and batch without using photoresist mask. Therefore, it is crucial to develop a wafer-level 2D semiconductor patterning technology that does not contain polymers and is efficient and easy to expand for its practical application. SUMMARY

[0005] The present application aims to overcome the deficiencies in the prior art and provides a method for dry patterning of wafer-level two-dimensional semiconductor, which can contaminate, efficiently and scalable pattern wafer-level two-dimensional semiconductor.

[0006] The technical problem solved by the present application is solved by the following technical solution:

[0007] A dry and non-polluting method for patterning wafer-level two-dimensional semiconductor, comprising:

[0008] Step (1) making a grid-shaped patterned three-dimensional stamp;

[0009] Step (2) making a metal-modified grid-shaped patterned three-dimensional stamp;

[0010] Step (3) pressing the metal-modified grid-shaped patterned three-dimensional stamp on the wafer-level two-dimensional semiconductor to form a shape-retaining contact;

[0011] Step (4) separating the metal-modified grid-shaped patterned three-dimensional stamp from the wafer-level two-dimensional semiconductor, i.e. obtaining a dry and non-polluting patterned wafer-level two-dimensional semiconductor.

[0012] When the metal-modified grid-shaped patterned three-dimensional stamp is lifted, due to the strong force of the grid-shaped metal and the two-dimensional semiconductor, the two-dimensional semiconductor in the contact area (the convex area of the stamp) will be taken away, while the two-dimensional semiconductor material in the non-contact area (the concave area of the stamp) will remain on the original substrate. At this time, the metal-modified grid-shaped patterned three-dimensional stamp successfully completes the patterning of the wafer-level two-dimensional semiconductor. In the whole process, the two-dimensional semiconductor remaining on the original substrate is not contacted with any polymer and solution, realizing truly scalable dry and non-polluting patterning.

[0013] Further, the step (1) of making a grid-shaped patterned three-dimensional stamp is: spin-coating photoresist on a sacrificial substrate and preparing a grid-shaped patterned mold by standard photolithography, and making a grid-shaped patterned three-dimensional stamp by inverse molding process.

[0014] Further, the grid-shaped patterned shape is an ordered arrangement of single pattern or a combination of different patterns.

[0015] Further, the step (2) of making a metal-modified grid-shaped patterned three-dimensional stamp is: evaporating a metal film on the grid-shaped patterned three-dimensional stamp of step (1). The metal film can increase the adhesion between the grid-shaped patterned three-dimensional stamp and the wafer-level two-dimensional semiconductor.

[0016] Further, the step (3) presses the metal-modified grid-like patterned three-dimensional stamp on the wafer-level two-dimensional semiconductor to form a conformal contact: the metal-modified grid-like patterned three-dimensional stamp is attached to the top of the wafer-level two-dimensional semiconductor, slowly pressed, and annealed at low temperature, so that the metal-modified grid-like patterned three-dimensional stamp and the wafer-level two-dimensional semiconductor form a conformal contact.

[0017] Further, in the step (3), the low-temperature annealing treatment time is 3-10 minutes, and the temperature is 130-150°C. The low-temperature annealing treatment is to remove the bubbles at the interface between the metal-modified grid-like patterned three-dimensional stamp and the top of the two-dimensional semiconductor, so that the metal-modified grid-like patterned three-dimensional stamp and the two-dimensional semiconductor form a tight contact.

[0018] Further, the three-dimensional stamp is polydimethylsiloxane (PDMS).

[0019] Further, in the step (2), the metal is an adhesion metal layer and a functional metal layer, the adhesion metal layer has a thickness of 5-10 nm, and the functional metal layer has a thickness of 20-50 nm; the metal deposition rate is 0.1-0.5 nm / s. to ensure that a dense metal film is formed and the stamp does not wrinkle and deform.

[0020] Further, the adhesion metal is Ti or Cr; and the functional metal is Au or Ag or Pd.

[0021] Further, in the step (3), the two-dimensional semiconductor is fixed with an adhesive tape before the pressing, to ensure that the metal-modified grid-like patterned three-dimensional stamp and the two-dimensional semiconductor are quickly separated subsequently.

[0022] Further, the height difference of the patterned three-dimensional stamp needs to be more than 5 μm, to ensure that the concave part of the patterned three-dimensional stamp cannot contact the bottom two-dimensional semiconductor when contacting, so that it can be retained on the original substrate.

[0023] The beneficial effects of the present application are as follows:

[0024] (1) The present application shows that a two-dimensional semiconductor is quickly wafer-level dry patterned by a three-dimensional metal stamp.

[0025] (2) The method of the present application produces a two-dimensional array with an atomically flat surface and clean and pollution-free edges, which is beneficial to form better electrical contact.

[0026] (3) The method of the present application is scalable and can realize etching of any customized pattern, such as a circle, a square, a triangle, a letter, etc.

[0027] (4) The great advantage of the present application is that the dry patterning process does not involve any polymer or solution, thus maintaining the inherent properties of the fine two-dimensional lattice.

[0028] (5) The method of the present application has wide applicability and can be applied to common two-dimensional layered semiconductors such as MoS2, WSe2, MoSe2, MoTe2, etc.

[0029] (6) The method of the present application has high scalability and can be further extended to larger wafers, such as 8-inch or 12-inch or even larger size two-dimensional semiconductor patterning, the size is only limited by the CVD

[0030] growth of the material. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 Preparation flowchart of a metal-modified grid-shaped patterned three-dimensional stamp in a dry non-polluting wafer-level two-dimensional semiconductor patterning method of Example 1 of the present application;

[0032] Figure 2 Preparation flowchart of a metal-modified grid-shaped patterned three-dimensional stamp in a dry non-polluting wafer-level two-dimensional semiconductor patterning method of Example 1 of the present application; and corresponding optical diagram of the contact and separation of the metal-modified grid-shaped patterned three-dimensional stamp and the two-dimensional semiconductor;

[0033] Figure 3 Atomic force microscope image and optical diagram of patterned two-dimensional semiconductors of different shapes in a dry non-polluting wafer-level two-dimensional semiconductor patterning method of Example 1 of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, method and advantages of the present application clearer, the technical solutions of the present application will be described in detail and clearly below in combination with the drawings and examples. It should be understood that the specific examples described herein are only a part of the embodiments of the present application, which are used to explain the present application, but not to limit all the embodiments of the present application. It should be noted that the features in the examples and the examples in the embodiments of the present application can be used in combination with each other without conflict. In addition, in all the embodiments based on the present application, all other embodiments obtained by the skilled in the art without making creative technology belong to the scope of protection of the present application.

[0035] Example 1

[0036] The method flowchart of Example 1 of the present application is shown in FIG. 1. Figure 1 and FIG. 2. Figure 2The two-dimensional semiconductor in the present application is a wafer-level MoS2, WSe2, MoSe2, and other two-dimensional layered semiconductor commonly used in chemical vapor deposition (CVD), and the two-dimensional semiconductor in the embodiment 1 is selected as MoS2. The specific preparation method of the embodiment 1 comprises the following steps:

[0037] Step (1) making a grid-shaped patterned three-dimensional stamp;

[0038] 1.1 Spin-coating a layer of photoresist (SU8, 5 μm thick) on a sacrificial substrate (see attached Figure 1 a), making a grid pattern through standard photolithography technology, and after development, appropriately cleaning the surface of the mold through plasma and treating with hexamethyldisilazane (HMDS), so as to prepare a mold of the grid-shaped patterned three-dimensional stamp (see attached Figure 1 b).

[0039] 1.2 Pouring PDMS elastomer (Sylgard 184, Dow Corning) on the mold, baking at 80°C for 6 hours, and then peeling off from the mold to form a grid-shaped patterned three-dimensional PDMS stamp (see attached Figure 1 c).

[0040] 1.3 Treating the back of the grid-shaped patterned three-dimensional PDMS stamp with oxygen plasma (power 100 W, time 10 s), and after treatment, attaching the back of the grid-shaped patterned three-dimensional PDMS stamp to a hard quartz substrate.

[0041] The front of the grid-shaped patterned three-dimensional PDMS stamp has an atomically flat surface due to the replication of the flatness of the surface of the sacrificial substrate.

[0042] Step (2) making a metal-modified grid-shaped patterned three-dimensional stamp;

[0043] Through high-vacuum electron beam evaporation (speed ), depositing a layer of chromium (10 nm thick) on the grid-shaped patterned three-dimensional stamp, and then through high-vacuum electron beam evaporation (speed ), depositing a layer of gold film (30 nm thick) on the chromium. Through the above process, a metal-modified grid-shaped patterned three-dimensional stamp can be made to perform the next step of patterning the two-dimensional semiconductor (see attached Figure 1 d).

[0044] Step (3) pressing the metal-modified patterned three-dimensional stamp on the wafer-level two-dimensional semiconductor to form a shape-retaining contact;

[0045] The two-dimensional semiconductor is first fixed by an adhesive tape, and then a metal-modified grid-shaped patterned three-dimensional stamp is transferred to the surface of the two-dimensional semiconductor MoS2, and slowly pressed to make close contact, and then annealed at 130 DEG C for 3 minutes to make the gold and the two-dimensional semiconductor MoS2 more closely combined (see attached Figure 2 a-b).

[0046] Step (4) separates the metal-modified grid-shaped patterned three-dimensional stamp from the two-dimensional semiconductor, i.e. obtains a dry and non-polluted patterned wafer-level two-dimensional semiconductor.

[0047] Slowly lift the metal-modified grid-shaped patterned three-dimensional stamp to separate it from the two-dimensional semiconductor, and when the three-dimensional stamp leaves the two-dimensional semiconductor wafer, the two-dimensional semiconductor in the contact area (the convex area) is also picked up and taken away, and since the three-dimensional stamp has a patterned recessed area which is not in contact with the two-dimensional semiconductor, the non-contact area (the recessed area) of the three-dimensional stamp is retained on the substrate (see attached Figure 2 c) At this point, the three-dimensional stamp has completed the dry and non-polluted patterning of the two-dimensional semiconductor.

[0048] From attached Figure 2 c, it can be seen that after the three-dimensional stamp contacts, the stamp takes away the material in the contact area (which needs to be etched), the continuous two-dimensional film becomes a discrete two-dimensional array, and the material in the non-contact area is retained, thereby copying the pattern defined by the stamp. By further observing the two-dimensional semiconductor patterned by the three-dimensional gold stamp through AFM, it can be seen that the patterned two-dimensional semiconductor has an atomically flat surface with a roughness of 0.28 nm (see attached Figure 3 a, 3b), the edges are clear, and there is no residual polymer, which shows that the gold stamp dry patterning technology can realize non-polluted etching and there is no glue pollution, and the intrinsic two-dimensional lattice structure is retained.

[0049] The technical solution of the application can be used to design different patterns, and any pattern can be defined by traditional photolithography, such as square, circle, triangle or letter, etc. (see attached Figure 3 c-f).

[0050] In summary, the application explores a method for realizing dry patterning of wafer-level two-dimensional semiconductor, which realizes non-polymer contact patterning, and the pattern obtained by the method has an atomically flat surface, clear edges, and realizes fast, non-polluted and scalable wafer-level patterning.

[0051] The scope of protection of the present application is not limited to the above examples, and the details set forth in the above description are provided to give a better understanding of the present application. The present application can be implemented in many different ways, and the above examples are only the preferred embodiments of the present application. Therefore, the present application is not limited to the specific implementations disclosed above. Meanwhile, any skilled person in the art can make some possible changes and modifications to the present application using the disclosed methods and technical means without departing from the scope of the present application. Any simple changes and equivalent modifications made to the above examples based on the technical essence of the present application without departing from the technical solutions of the present application are still within the scope of protection of the present application.

Claims

1. A method of dry, contamination-free, patterned wafer-scale two-dimensional semiconductor, characterized by: The application relates to a method for manufacturing a patterned wafer-level two-dimensional semiconductor, comprising the following steps: (1) preparing a grid-shaped patterned three-dimensional stamp with a concave-convex pattern; (2) preparing a metal-modified grid-shaped patterned three-dimensional stamp, wherein the metal is formed on the pattern surface; (3) pressing the metal-modified convex region surface of the grid-shaped patterned three-dimensional stamp on a wafer-level two-dimensional semiconductor to form a shape-retaining contact; (4) separating the metal-modified grid-shaped patterned three-dimensional stamp from the wafer-level two-dimensional semiconductor, wherein the convex region of the three-dimensional stamp takes away the two-dimensional semiconductor in contact therewith, and the two-dimensional semiconductor corresponding to the concave region is retained on the substrate, that is, a dry and non-polluted patterned wafer-level two-dimensional semiconductor is obtained. In the step (2), the metal is an adhesion metal layer and a functional metal layer, the thickness of the adhesion metal layer is 5-10 nm, the thickness of the functional metal layer is 20-50 nm, the metal deposition rate is 3-8 A / s, the adhesion metal is Ti or Cr, and the functional metal is Au or Ag or Pd. In the step (3), the metal-modified grid-shaped patterned three-dimensional stamp is pressed on the wafer-level two-dimensional semiconductor to form a shape-retaining contact, that is, the metal-modified grid-shaped patterned three-dimensional stamp is attached to the top of the wafer-level two-dimensional semiconductor, is slowly pressed, and is annealed at low temperature, so that the metal-modified grid-shaped patterned three-dimensional stamp and the wafer-level two-dimensional semiconductor form a shape-retaining contact. The grid-shaped patterned shape is an ordered arrangement of single patterns or a combination of different patterns. In the step (2), the metal-modified grid-shaped patterned three-dimensional stamp is prepared by evaporating a metal film on the grid-shaped patterned three-dimensional stamp in the step (1). In the step (3), the low-temperature annealing treatment time is 3-10 minutes, and the temperature is 130-150 DEG C. The three-dimensional stamp is polydimethylsiloxane (PDMS).

2. A method of dry, contamination-free, patterned wafer-scale two-dimensional semiconductor as claimed in claim 1, wherein, In the step (3), the two-dimensional semiconductor is fixed by using an adhesive tape before the pressing.

3. A method of dry, contamination-free patterned wafer-scale two-dimensional semiconductor as claimed in claim 1, wherein, The concave-convex height difference of the patterned three-dimensional stamp needs to be more than 5 mu m.

4. The method of claim 1, wherein the method is a dry, non-polluting method of patterning a two-dimensional semiconductor wafer. ​ 5. The method of claim 1, wherein the method is a dry, non-polluting method of patterning a two-dimensional semiconductor wafer. ​ 6. A method of dry, contamination-free patterned wafer-scale two-dimensional semiconductor as claimed in claim 1, wherein, ​ 7. The method of claim 1, wherein the method is a dry, non-polluting method of patterning a two-dimensional semiconductor wafer. ​

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