Semiconductor manufacturing method, manufacturing system, device and storage medium

Abstract

A semiconductor manufacturing method, a manufacturing system, a device and a storage medium are used for performing target operation on a target layer on the surface of a wafer, the target operation is used for realizing specific process processing, and the manufacturing method comprises the following steps: performing imaging processing on the wafer to obtain an image of the target layer as a to-be-processed image; the to-be-processed image is analyzed to obtain the current size of the target layer according to image parameters, and the image parameters are related to the current size of the target layer; determining a target parameter of the target operation based on the current size of the target layer; and performing target operation on the target layer based on the target parameter. Through imaging processing, the global current state information of the target layer can be obtained, the information is richer, so that the current state of the target layer can be more accurately obtained, after the target parameters of the target operation are determined based on the current size of the target layer, the accuracy of the target parameters is correspondingly improved, the uniformity of the target operation is improved, and the user experience is improved. And the yield of semiconductor manufacturing is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor manufacturing method, manufacturing system, equipment and storage medium. Background Art

[0002] In semiconductor manufacturing, in order to meet the demand for the yield of the final product, it becomes very important to control the uniformity of the process. As semiconductor devices shrink rapidly, the uniformity within the wafer and between wafers becomes more and more critical. Since the uniformity of the process will affect the yield of the wafer, semiconductor manufacturing requires stricter process control.

[0003] The uniformity of the process is affected by the process parameters. At present, in order to accurately control the process parameters to achieve better uniformity control, a feedforward control system and a feedback control system have been introduced. However, the uniformity of the process still needs to be improved. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor manufacturing method, manufacturing system, equipment and storage medium to improve the accuracy of determining target parameters, thereby improving the yield of semiconductor manufacturing.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor manufacturing method for performing a target operation on a target layer on the surface of a wafer, wherein the target operation is used to implement a specific process treatment, and the semiconductor manufacturing method comprises: performing imaging processing on the wafer to obtain an image of the target layer as a to-be-processed image; analyzing the to-be-processed image to obtain a current size of the target layer according to image parameters of the to-be-processed image, wherein the image parameters are related to the current size of the target layer; determining target parameters of the target operation based on the current size of the target layer; and performing a target operation on the target layer based on the target parameters.

[0006] Correspondingly, an embodiment of the present invention also provides a semiconductor manufacturing system for performing a target operation on a target layer on the surface of a wafer, wherein the target operation is used to implement a specific process treatment, and the semiconductor manufacturing system includes: an imaging device for performing imaging processing on the wafer to obtain an image of the target layer as an image to be processed; an image analysis device for analyzing the image to be processed to obtain a current size of the target layer based on image parameters of the image to be processed, wherein the image parameters are related to the current size of the target layer; a parameter setting device for determining target parameters of the target operation based on the current size of the target layer; and an operating device for performing a target operation on the target layer based on the target parameters.

[0007] Accordingly, an embodiment of the present invention also provides a device, comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the semiconductor manufacturing method described in the embodiment of the present invention.

[0008] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the semiconductor manufacturing method described in the embodiment of the present invention.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the semiconductor manufacturing method provided by the embodiment of the present invention, the wafer is first imaged to obtain an image of the target layer as a to-be-processed image, and the to-be-processed image is analyzed to obtain the current size of the target layer according to the image parameters of the to-be-processed image, and then the target parameters of the target operation are determined based on the current size of the target layer; wherein, compared with the solution of detecting the wafer surface by optical emission spectroscopy (optical emission spectroscopy, OES) technology and light signal reflectometry (light signal reflectometry, LSR) technology to obtain single point signal intensity, by imaging the wafer, the global current state information of the target layer can be obtained, and the information provided by the to-be-processed image is richer, so that the current state of the target layer on the wafer surface can be obtained more accurately, then based on the current size of the target layer, after the target parameters of the target operation are determined, the accuracy of the target parameters is correspondingly improved, therefore, after the target operation is performed on the target layer based on the target parameters, the uniformity of the target operation is improved, thereby improving the yield of semiconductor manufacturing.

[0011] In the semiconductor manufacturing system provided by the embodiment of the present invention, the wafer is first imaged by an imaging device to obtain an image of the target layer as a to-be-processed image, and the to-be-processed image is analyzed by an image analysis device to obtain the current size of the target layer according to the image parameters of the to-be-processed image, and then the target parameters of the target operation are determined based on the current size of the target layer by a parameter setting device; wherein, compared with the solution of detecting the wafer surface by optical detection technology such as optical emission spectroscopy technology or optical signal reflection technology to obtain the single-point signal intensity, by imaging the wafer, the global current state information of the target layer can be obtained, and the information provided by the to-be-processed image is richer, so that the current state of the target layer on the wafer surface can be obtained more accurately, then after the target parameters of the target operation are determined based on the current size of the target layer, the accuracy of the target parameters is correspondingly improved, and it is easy to match with the current size of different positions on the wafer, therefore, after the target operation is performed on the target layer based on the target parameters, the uniformity of the target operation is improved, thereby improving the yield of semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flow chart of an embodiment of a semiconductor manufacturing method of the present invention;

[0013] Figure 2 yes Figure 1 A schematic diagram of a wafer embodiment corresponding to step S1;

[0014] Figure 3 yes Figure 1 The pending processing corresponding to step S1 Figure 1 A schematic diagram of an embodiment;

[0015] Figure 4 yes Figure 1 A relationship diagram between the target layer thickness and the grayscale corresponding to step S2 in an embodiment;

[0016] Figure 5 yes Figure 1 A schematic diagram of the structure of a convolutional neural network according to step S2 in the embodiment;

[0017] Figure 6 yes Figure 1 A schematic diagram of an embodiment of a wafer state corresponding to steps S4 to S6;

[0018] Figure 7 is a schematic diagram of an embodiment of a semiconductor manufacturing system of the present invention;

[0019] Figure 8 It is a hardware structure diagram of a device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] As can be seen from the background technology, even if a feedforward control system and a feedback control system are introduced, the uniformity of the current process still needs to be improved.

[0021] Research has found that in traditional process flow, optical emission spectroscopy technology and light signal reflection technology are usually used to detect the wafer surface for wafer measurement or endpoint detection. However, this method can only obtain single-point signal strength on the wafer, resulting in less wafer information collected, making it difficult to evaluate the overall condition of the wafer, which in turn affects the uniformity inside the wafer.

[0022] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor manufacturing method for performing a target operation on a target layer on a wafer surface, wherein the target operation is used to implement a specific process. Figure 1 , shows a flow chart of an embodiment of a semiconductor manufacturing method of the present invention. The semiconductor manufacturing method of this embodiment includes the following basic steps:

[0023] Step S1: performing imaging processing on the wafer to obtain an image of the target layer as an image to be processed;

[0024] Step S2: analyzing the image to be processed to obtain the current size of the target layer according to image parameters of the image to be processed, wherein the image parameters are related to the current size of the target layer;

[0025] Step S3: determining a target parameter of the target operation based on the current size of the target layer;

[0026] Step S4: Based on the target parameters, perform a target operation on the target layer.

[0027] By imaging the wafer, the global current state information of the wafer surface can be obtained. The information provided by the processed image is richer, so that the current state of the target layer on the wafer surface can be obtained more accurately. After the target parameters of the target operation are determined based on the current size of the target layer, the accuracy of the target parameters is also improved accordingly, and it is easy to match the current size of different positions on the wafer. Therefore, after the target operation is performed on the target layer based on the target parameters, the uniformity of the target operation is improved, thereby improving the yield of semiconductor manufacturing.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 1 It is a flow chart of an embodiment of a semiconductor manufacturing method of the present invention.

[0030] Combined with reference Figures 2 to 6 , Figure 2 yes Figure 1 A schematic diagram of a wafer embodiment corresponding to step S1 in FIG. Figure 3 yes Figure 1 The pending processing corresponding to step S1 Figure 1 Schematic diagram of an embodiment, Figure 4 yes Figure 1 The relationship diagram between the target layer thickness and the grayscale corresponding to step S2 in the embodiment, Figure 5 yes Figure 1 A schematic diagram of the structure of a convolutional neural network according to step S2 in the embodiment of FIG. Figure 6 yes Figure 1 FIG. 1 is a schematic diagram of an embodiment of wafer states corresponding to steps S4 to S6 in FIG.

[0031] In this embodiment, the manufacturing method is used to process a wafer W (such as Figure 2 The target layer 300 (as shown) on the surface Figure 2 As shown) perform target operations, which are used to achieve specific process processing.

[0032] The target operation may include an etching operation, a chemical mechanical polishing operation, or a deposition operation.

[0033] When the target operation is an etching operation, the manufacturing method is used to perform an etching process on the target layer 300 so that the etching amount of the target layer 300 can meet the requirements, and the process treatment is correspondingly an etching process.

[0034] When the target operation is a chemical mechanical polishing operation, the manufacturing method is used to perform chemical mechanical polishing on the target layer 300 so that the removal amount of the target layer 300 and the surface flatness of the remaining target layer 300 can meet the requirements, and the process treatment is correspondingly a chemical mechanical polishing treatment.

[0035] When the target operation is a deposition operation, the manufacturing method is used to perform a deposition process on the surface of the target layer 300 to form a film layer that meets the thickness requirements and surface flatness requirements on the surface of the target layer 300, and the process treatment is correspondingly a deposition process.

[0036] In this embodiment, the target operation is an etching operation.

[0037] In this embodiment, the target layer 300 is a non-patterned film layer that completely covers the top surface of the wafer W. In other embodiments, an opening may also be formed in the target layer.

[0038] Specifically, step S1 is executed to perform imaging processing on the wafer W to obtain an image of the target layer 300 as the image to be processed 400 .

[0039] The image to be processed 400 is subsequently analyzed to obtain the current size of the target layer 300 according to the image parameters of the image to be processed 400 .

[0040] It should be noted that the imaging process of the wafer W reduces the difficulty of collecting the state information of the surface of the wafer W. Moreover, by adopting the method of imaging the wafer W, it is convenient to analyze the image to be processed 400 in combination with image processing technology, thereby improving the efficiency of subsequently obtaining the current size of the target layer 300.

[0041] In this embodiment, a CCD (Charge Coupled Device) image sensor is used to image the wafer W to collect the to-be-processed image 400 corresponding to the target layer 300. Using a CCD image sensor for imaging is beneficial to reducing process costs, and the process compatibility of the CCD image sensor is also high. In other embodiments, a CMOS (Complementary Metal-Oxide Semiconductor) device image sensor may also be used.

[0042] like Figure 3 As an example, the type of the image to be processed 400 includes a grayscale image, and accordingly, the image parameter of the image to be processed 400 is grayscale. Compared with a color image, a grayscale image has only one channel (for example, the grayscale value of an image point is usually any value from 0 to 255), thereby reducing the complexity of analyzing the image to be processed 400, and thus helping to improve the feedback speed in the semiconductor manufacturing process. As an example, the image to be processed 400 is subsequently analyzed by machine learning. Therefore, using a grayscale image as the input of a machine learning model (for example, a convolutional neural network model) is also helpful in reducing the difficulty of training the model and the complexity of the model.

[0043] In other embodiments, other to-be-processed images that can be analyzed to obtain the current size of the target layer may also be selected. For example, when the hardware performance of the device is powerful enough (for example, the performance of the processor is powerful enough), a color image may also be used to further improve the accuracy of the result obtained after the subsequent analysis of the to-be-processed image.

[0044] Continue to refer Figures 1 to 3 , execute step S2, for the to-be-processed graph 400 (such as Figure 3 ) is analyzed to obtain the target layer 300 (as shown) according to the image parameters of the image to be processed 400 Figure 2 The image parameters are related to the current size of the target layer 300.

[0045] The current size can reflect the state of the surface of the wafer W before the target operation is performed. The current size of the target layer 300 is first obtained, and the current size is used as reference data for subsequent determination of target parameters, so that when the target operation is performed later, appropriate target parameters can be determined based on the current size of the target layer 300.

[0046] Among them, the image to be processed 400 is an image obtained by imaging wafer W, and the image to be processed 400 contains the status information of the entire surface of wafer W. Compared with the solution of detecting the wafer surface through optical detection technology such as optical emission spectroscopy technology or light signal reflection technology to obtain single-point signal strength, the information provided by the image to be processed 400 is richer, so that the current state of the target layer 300 on the surface of wafer W can be obtained more accurately. Then, after determining the target parameters of the target operation based on the current size of the target layer 300, the accuracy of the target parameters is also improved accordingly, and it is easy to match the current size of different positions on wafer W. Therefore, after performing the target operation on the target layer based on the target parameters, the uniformity of the target operation is improved, that is, the uniformity inside the wafer is improved, thereby improving the yield of semiconductor manufacturing.

[0047] In this embodiment, the current size includes the thickness of the target layer 300 .

[0048] like Figure 4 As shown, Figure 4 This is a relationship diagram of an embodiment of the target layer thickness and grayscale. The horizontal axis represents different radial positions along the radial direction with the center of the wafer as the origin, the main vertical axis (i.e. the vertical axis on the left) represents the target layer thickness, and the secondary vertical axis (i.e. the vertical axis on the right) represents the grayscale. Curve A composed of diamond points represents the target layer thickness that changes with the radial position, and curve B composed of circles represents the grayscale that changes with the radial position.

[0049] It can be seen that the thickness of the target layer 300 has a strong correlation with the grayscale of the image. Therefore, by analyzing the image to be processed 400 , the thickness of the target layer 300 can be obtained according to the grayscale of the image to be processed 400 .

[0050] Taking the target operation as an etching operation as an example, the target layer 300 is the etched object, the thickness of the target layer 300 affects the etching amount of the etching operation, and the etching parameters affect the etching amount. Therefore, the thickness of the target layer 300 at different positions on the wafer W is first obtained, so that appropriate target parameters can be determined for the thickness of the target layer 300 at different positions.

[0051] For example, the manufacturing method is used to perform back etching on the target layer 300 , and then the thickness of the target layer 300 is determined to determine appropriate target parameters, so that the top surface height consistency of the remaining target layer 300 at various positions after etching is improved.

[0052] For another example, the manufacturing method implements the patterning of the gate material layer, and then the appropriate target parameters are determined by determining the thickness of the target layer 300, so that the etching uniformity of the gate material layer at various positions on the wafer is improved. Specifically, the patterning of the gate material layer usually uses a hard mask layer, so the target layer 300 can include the sum of the thickness of the gate material layer and the hard mask layer (for example, the sum of the thickness of the gate material layer and the hard mask layer above the top of the fin).

[0053] In other embodiments, taking the target operation as a chemical mechanical polishing operation as an example, the target layer is the object to be polished. In order to improve the surface flatness of the remaining target layer after polishing, the thickness of the target layer affects the polishing amount of the chemical mechanical polishing operation, and the polishing parameters affect the polishing amount. Therefore, the target layer thickness at different positions on the wafer is first obtained, so that appropriate target parameters can be determined for the target layer thickness at different positions.

[0054] In other embodiments, taking the target operation as an etching operation, and in the case where an opening is formed in the target layer, the current size may also be the line width (CD) of the opening in the target layer. The line width of the opening will also affect the etching effect, therefore, the line width of the opening at different positions on the wafer is first obtained, so that appropriate target parameters can be determined for the line width of the opening at different positions.

[0055] In this embodiment, a machine learning model is used to analyze the graph to be processed 400.

[0056] Correspondingly, the input of the machine learning model is the image to be processed 400, and the output is the current size of the target layer 300. Analyzing the image to be processed 400 through the machine learning model is helpful to improve the efficiency of obtaining the current size, and is helpful to obtain the accurate current size, and is helpful to shorten the production cycle and save manpower.

[0057] Specifically, the machine learning model includes a convolutional neural network (CNN) model, which is used to extract image parameters of the image to be processed 400 and output the current size of the target layer 300 according to the image parameters.

[0058] The convolutional neural network model has the advantages of self-adaptation, highly nonlinear approximation and self-learning. The use of convolutional neural network is conducive to improving the accuracy of the current size.

[0059] In this embodiment, the convolutional neural network model includes an input layer, a convolutional layer (Convolutional Layer), a pooling layer (Pooling Layer), a fully connected layer (Full Connected Layer), a linear rectifier function layer (Rectified Linear Unit Layer, ReLU Layer) and a normalized exponential layer (Softmax Layer), and the Softmax layer serves as the output layer of the convolutional neural network model.

[0060] Specifically, in the Softmax layer, calculations are performed using a regularization algorithm, which helps to improve the generalization ability of the convolutional neural network and avoid the problem of overfitting.

[0061] In this embodiment, the machine learning model is obtained in the following manner: obtaining a first data set, the first data set including a plurality of data pairs, each data pair including the actual size of a sample point on a wafer, and an image parameter of an image point corresponding to the sample point, and the first data set including a first training data set and a first verification data set; obtaining an initial analysis model; training the initial analysis model using the first training data set; iteratively optimizing the trained initial analysis model using the first verification data set to achieve parameter optimization of the initial analysis model, and using the initial analysis model that has completed parameter optimization as the machine learning model.

[0062] The first data set includes multiple data pairs, each data pair contains the actual size of a sample point on the wafer and the image parameters of the image point corresponding to the sample point. Therefore, through the learning of the machine learning model, after the image to be processed is subsequently input into the machine learning model, the machine learning model can directly output the current size of the target layer.

[0063] In this embodiment, the step of obtaining the data set includes: obtaining multiple test wafers, each of which has a target layer on its surface, and the current size values ​​of the target layers of the multiple test wafers are different; performing data preprocessing on each test wafer respectively, and the data preprocessing includes: selecting multiple sample points on the test wafer; obtaining the actual size of each of the sample points; imaging the test wafer to obtain a test image; and obtaining image parameters of the image points corresponding to the test image based on the relative positions of the sample points on the test wafer, so as to obtain image parameters including the actual size of the sample points on the wafer and the image parameters of the image points corresponding to the sample points.

[0064] By acquiring multiple test wafers with target layers, and the current size values ​​of the target layers of the multiple test wafers are different, the data diversity of the first data set is increased, thereby improving the training effect of the model.

[0065] The image corresponding to the test wafer has image points (for example, pixel points), and for any sample point, the relative position relationship of the sample point on the test wafer is the same as the relative position relationship of its corresponding image point in the image, and the coordinates of the sample point in the test wafer are available. Therefore, through the coordinates of each sample point in the test wafer, it is easy to find the corresponding image point in the image, thereby obtaining the image parameters corresponding to the sample point.

[0066] In this embodiment, in the step of selecting a plurality of sample points on the test wafer, the plurality of sample points are distributed in concentric circles on the test wafer, and the number of the concentric circles is one or more. The plurality of sample points are distributed in concentric circles on the test wafer, thereby improving the distribution uniformity of the sample points, which is conducive to improving the credibility of the model after training.

[0067] In this embodiment, the step of iteratively optimizing the trained initial analysis model using the first verification data includes: optimizing parameters using a back propagation neural network (BPNN).

[0068] Back propagation neural network is a multi-layer feedforward network trained by error back propagation (abbreviated as error back propagation). The basic idea is the gradient descent method, that is, the gradient search technology is used to minimize the mean square error between the actual output value and the expected output value of the network. Back propagation neural network is more suitable for multi-layer neural network. By selecting back propagation neural network for parameter optimization, the accumulated error can be obtained faster and the global minimum error can be obtained faster.

[0069] For example, the algorithm used by the back-propagation neural network may include one or more of a stochastic gradient descent (SGD) algorithm, an adaptive moment estimation (Adam) algorithm, and an adaptive gradient algorithm (Adagrad) algorithm.

[0070] Specifically, the method of iteratively optimizing the trained initial analysis model using the first verification data includes one or more of the following methods: adjusting the number of convolutional layers in the initial analysis model; adjusting the number of pooling layers in the initial analysis model.

[0071] The convolution layer can increase the dimension, which is beneficial for feature extraction; while the pooling layer can reduce the dimension, thereby preventing too many parameters from being extracted, which is beneficial for the model to extract a wider range of features and prevent overfitting.

[0072] like Figure 5 As shown, Figure 5 : is a schematic diagram of the structure of the convolutional neural network of this embodiment. As an example, the convolutional neural network model includes an input layer, a first convolutional layer, a first pooling layer, a second convolutional layer, a second pooling layer, a first fully connected layer, a linear rectifier function layer, a second fully connected layer and a normalized exponential layer.

[0073] It should be noted that, for the same wafer W, the wafer W that has not undergone the target operation is in a first state, and the wafer W that has undergone the target operation is in a second state. Therefore, after the steps of imaging the wafer W in the first state to obtain the image to be processed 400 and analyzing the image to be processed 400 to obtain the current size are sequentially performed on the wafer W in the first state, the current size of the target layer 300 on the surface of the wafer W in the first state is obtained.

[0074] For example, Figure 6 As shown, the wafers in the first state are incoming wafers Win1, Win2, etc., and the wafers in the second state are output wafers Wout1, Wout2, etc.

[0075] As an example, taking the specific process treatment being realized through a target operation as an example, the incoming wafer Win1 represents the current wafer in the first state, the output wafer Wout1 represents the current wafer in the second state, the incoming wafer Win2 represents the next wafer in the first state, and the output wafer Wout2 represents the next wafer in the second state.

[0076] Taking the target operation on the incoming wafer Win1 as an example, the steps of imaging the wafer W to obtain the image to be processed 400 and analyzing the image to be processed 400 to obtain the current size are sequentially performed on the incoming wafer Win1, thereby obtaining the current size of the target layer 300 on the surface of the incoming wafer Win1.

[0077] In other implementation rates, the specific process treatment can also be achieved through multiple target operations. Accordingly, the incoming wafer Win1 represents the current wafer in the first state when the first target operation is performed, the output wafer Wout1 represents the current wafer in the second state when the first target operation is performed, the incoming wafer Win2 represents the current wafer in the first state when the second target operation is performed, and the output wafer Wout2 represents the current wafer in the second state when the second target operation is performed.

[0078] Continue to refer Figure 1 It should be noted that, before subsequently determining the target parameters of the target operation based on the current size of the target layer 300, the semiconductor manufacturing method further includes: executing step S5 to obtain an estimated processing rate of the target operation.

[0079] After determining the estimated processing rate of the current target operation, the process parameters of the target operation may be subsequently adjusted based on the current size of the target layer and the estimated processing rate to obtain target parameters that meet process requirements.

[0080] In this embodiment, the method of obtaining the estimated processing rate of the target operation includes: obtaining the estimated processing rate using a virtual metrology (VM) model.

[0081] The virtual measurement model is established based on a large amount of historical process data in the factory. Specifically, the inherent connection between historical data is used to establish a virtual measurement model related to the actual data of the process equipment. Through the virtual measurement model, the processing rate of the process equipment can be quickly and reliably calculated.

[0082] In this embodiment, the virtual measurement model is obtained in the following manner: historical data of the target operation is obtained as a second data set, and the second data set includes a second training data set and a second verification data set; an initial measurement model is obtained; the initial measurement model is trained using the second training data set; the trained initial measurement model is iteratively optimized using the second verification data set to achieve parameter optimization of the initial measurement model, and the initial measurement model after parameter optimization is used as the virtual measurement model.

[0083] It should be noted that the historical data of the target operation is the offline data of the process equipment. As an example, the historical data includes process parameter information, wafer information and process equipment information, thereby increasing the diversity of data and making the intrinsic correlation between the virtual measurement model and the historical data stronger, which is conducive to improving the calculation accuracy of the virtual measurement model.

[0084] In a specific embodiment, taking the target operation as an etching operation, the data type of the historical data includes any multiple of process time, gas flow, chuck temperature, transformer coupled plasma (TCP) temperature, pressure, source power, RF power, RF hours, gas flow distribution, chamber ID, wafer ID, and sub-step (stage).

[0085] Among them, process time, gas flow, chuck temperature, transformer coupled plasma temperature, pressure, source power, RF power, RF time and gas flow distribution are all process parameter information, wafer ID is wafer information, chamber ID and sub-steps are all process equipment information.

[0086] In this embodiment, after acquiring the historical data of the target operation and before using the second training data set to train the initial measurement model, the method further includes: removing outliers in the historical data.

[0087] By removing the outliers in the historical data, the abnormal data in the historical data are eliminated, and accordingly, the remaining historical data is used to establish the model, which is conducive to improving the accuracy of the virtual measurement model finally obtained.

[0088] In this embodiment, before the initial measurement model is trained using the second training data, the method further includes: performing a feature extraction operation, wherein the extracted features include time neighbor features, statistical features, and usage neighbor features.

[0089] Correspondingly, in the step of training the initial measurement model using the second training data set, training is performed based on the temporal proximity features, statistical features and correlation weight proximity features.

[0090] As an example, after removing outliers in the historical data, a feature extraction operation is performed.

[0091] By extracting time proximity features, time series data features can be obtained so that higher weights can be given to adjacent historical data in chronological order.

[0092] The recent historical data can better characterize the current state of the process equipment. Giving higher weights to the recent historical data in chronological order makes the recent historical data have a greater impact on the results of model training, which correspondingly makes the final virtual measurement model more accurate.

[0093] By extracting correlation weighted neighboring features, higher weights are given to parameters that are more relevant to the process.

[0094] By extracting statistical features, the entire data is evaluated using statistical methods, and data that does not conform to the statistical distribution (for example, does not conform to the Gaussian distribution) is given a lower weight.

[0095] By extracting time proximity features, statistical features, and correlation weight proximity features, data can be processed and classified, which is helpful to improve the reliability of model training.

[0096] In this embodiment, the initial measurement model includes a plurality of sub-models of different types, and the plurality of sub-models can all output an estimated processing rate.

[0097] Correspondingly, the step of training the initial measurement model using the second training data includes: weighting the estimated processing rates output by multiple sub-models under different weight allocation schemes to obtain the estimated processing rate of the initial measurement model; selecting the weight allocation scheme corresponding to the estimated processing rate that is closest to the actual processing rate to obtain the target weight of each sub-model, and the target weight is used to characterize the estimated processing rate output by each sub-model, and its contribution rate to the estimated processing rate output by the initial measurement model.

[0098] Semiconductor manufacturing is a complex process. If only a single sub-model is used to establish a virtual measurement model, there may be a problem of incomplete information learned by the single sub-model, which will affect the prediction accuracy of the virtual measurement model. To this end, multiple sub-models are integrated into a virtual measurement model, and the weighted value of the estimated processing rate inferred by each sub-model is used as the estimated processing rate output by the initial measurement model. This is conducive to learning the impact of different factors on the prediction results during the model training process, thereby further improving the prediction accuracy of the virtual measurement model.

[0099] In this embodiment, the sub-models include any of a persistent model, a K-nearest neighbor regression model (K-Neighbors Regressor, K-nn regression) model, a linear regression (Linear Regression) model, a random forest (Random Forest, RF) model and a support vector regression (Support Vector Regression, SVR) model.

[0100] The persistence model is a prediction based on time series, which is simpler and faster to process.

[0101] The K nearest neighbor regression model is a model based on probability method, which is beneficial to improve prediction accuracy and find uncertainty information to support appropriate decision-making.

[0102] The linear regression model is a relatively simple mathematical model, which helps to reduce the complexity of the model.

[0103] Since semiconductor manufacturing is a complex process with nonlinear characteristics, the random forest model is selected to be able to make predictions under nonlinear conditions.

[0104] The support vector regression model adopts a learning mechanism based on statistical learning theory, which is conducive to improving the small sample, nonlinear, and high-dimensional problems in the modeling process and improving the generalization ability of the virtual measurement model.

[0105] It should be noted that, before the initial measurement model is trained using the second training data, a feature extraction operation is performed to extract various types of features. Therefore, suitable features can be selected for each sub-model for model training.

[0106] Continue to refer Figure 1 and Figure 6 , execute step S3 to determine the target parameters of the target operation based on the current size of the target layer 300.

[0107] The current size of the target layer 300 is acquired in advance, and the corresponding target parameters are determined based on the current size of the target layer 300. Accordingly, the operating device 40 performs a target operation (for example, etching processing) on ​​the target layer 300 based on the target parameters, thereby achieving operation uniformity (for example, etching uniformity) at each position on the incoming wafer Win1 in the feedforward direction.

[0108] Specifically, based on the current size of the target layer 300 and the estimated processing rate, the target parameters of the target operation are determined.

[0109] In a specific embodiment, the target parameters of the current target operation are determined based on the current size of the target layer 300 on the wafer surface in the first state and the estimated processing rate of the target operation.

[0110] For example, Figure 6 As shown, based on the current size of the target layer 300 on the surface of the incoming wafer Win1 and the estimated processing rate of the target operation, the target parameters when performing the target operation on the incoming wafer Win1 are determined.

[0111] Under the same current size, in order for the target operation to achieve the expected effect, different estimated processing rates require different target parameters; similarly, under the same estimated processing rate, in order for the target operation to achieve the expected effect, different current sizes also require different target parameters. Therefore, using the current size of the target layer 300 and the estimated processing rate as factors for determining the target parameters is beneficial to improving the accuracy of the target parameters.

[0112] In this embodiment, an advanced process control (APC) system is used to determine target parameters of the target operation based on the current size of the target layer 300 and the estimated processing rate.

[0113] The advanced process control system adopts a feedforward control system and a feedback control system, so that the processing effect of the current target operation can be fed back to the next target operation, which is conducive to improving the uniformity of the target operation.

[0114] In this embodiment, the target operation is an etching operation. Based on the current size of the target layer 300, in the step of determining the target parameters of the target operation, the target parameters include one or more of chuck temperature, gas flow distribution, process time, transformer coupled plasma temperature, gas flow, source power, RF power, RF hours and pressure.

[0115] For example, an electrostatic chuck (ESC) is usually used in an etching operation. The electrostatic chuck has a wafer chucking function and a temperature controlling function. The electrostatic chuck includes multiple heating zones. During the etching process, the wafer is uniformly heated to ensure process uniformity. Therefore, when the target parameter includes the chuck temperature, the chuck temperature is the temperature of each heating zone.

[0116] Continue to refer Figure 1 , execute step S4, and perform a target operation on the target layer 300 based on the target parameters.

[0117] like Figure 6 As shown, based on the target parameters corresponding to the incoming wafer Win1, the operating device 40 performs a target operation on the incoming wafer Win1.

[0118] In this embodiment, taking the target operation as an etching operation as an example, an etching operation is performed on the target layer 300 based on etching parameters.

[0119] In this embodiment, after performing the target operation on the target layer 300 on the surface of the wafer in the first state (i.e., the incoming wafer Win1), the manufacturing method also includes: performing imaging processing on the wafer again to obtain a processed image, and analyzing the processed image using an image analysis model to obtain the current size of the target layer on the surface of the wafer in the second state.

[0120] By again performing imaging processing on the wafer to obtain an image to be processed, and analyzing the image to be processed using an image analysis model, the result of the target operation based on the current target parameters can be verified, and the verification result can be fed back to the next target operation, so as to facilitate calibration of the parameters of the next target operation, thereby achieving uniformity between different target operations in the feedback direction (for example, etching uniformity).

[0121] Specifically, continue to refer to Figure 1 , execute step S6, perform imaging processing on the wafer (i.e., the incoming wafer Win1) again to obtain the image of the target layer 300 as the image to be processed; execute step S7, analyze the image to be processed to obtain the current size of the target layer according to the image parameters of the image to be processed, and the image parameters are related to the current size of the target parameters.

[0122] Continue to refer Figure 1 The manufacturing method further includes: executing step S8 to determine an estimated processing rate of the next target operation.

[0123] Specifically, in step S8 , based on the current size of the target layer 300 on the surface of the wafer (ie, the output wafer Wout1 ) in the second state, the estimated processing rate of the next target operation is determined.

[0124] By determining the estimated processing rate of the next target operation, after subsequently obtaining the current size of the target layer 300 corresponding to the next target operation, the target parameters can be determined based on the current size of the target layer and the estimated processing rate, thereby improving the uniformity of the target operation between wafers.

[0125] like Figure 6 As shown, in this embodiment, the specific process treatment is achieved through one target operation. In other words, after completing the target operation on the current wafer, the target operation will be performed on the next wafer. Then, based on the current size of the target layer on the surface of the wafer in the second state, in the step of determining the estimated processing rate of the next target operation, the estimated processing rate of the target operation of the next wafer (that is, the incoming wafer Win2) is determined.

[0126] Therefore, the steps of imaging the incoming wafer Win2 and analyzing the image to be processed are subsequently performed in sequence to obtain the current size of the target layer on the surface of the incoming wafer Win2 in the first state. Based on the current size of the target layer on the surface of the incoming wafer Win2 and the estimated processing rate obtained through feedback from the output wafer Wout1, the target parameters for the target operation on the incoming wafer Win2 can be determined.

[0127] Correspondingly, the incoming wafer Win2 is subsequently subjected to target processing based on the target parameters corresponding to the incoming wafer Win2 to obtain the output wafer Wout2.

[0128] In this embodiment, in order to improve the accuracy of the estimated processing rate of the next target operation, the estimated processing rate of the next target operation is determined based on the current size of the target layer on the surface of the wafer (i.e., the output wafer Wout1) in the second state, including: obtaining the actual processing rate of the current target operation based on the current size of the target layer on the surface of the wafer in the second state. ； An estimated processing rate when a target operation is performed on a target layer on the surface of the wafer in the first state is compared with an actual processing rate; wherein, when the difference between the estimated processing rate and the actual processing rate is within an acceptable range, the estimated processing rate is maintained as the estimated processing rate for the next target operation; when the difference between the estimated processing rate and the actual processing rate exceeds an acceptable range, the estimated processing rate is updated using the current actual processing rate to obtain an estimated processing rate for the next target operation.

[0129] The estimated processing rate is a rate extrapolated based on a large amount of historical data. Therefore, the actual processing rate of the previous target operation is used for verification, and the verification result is fed back to the next target operation to avoid the problem of excessive difference between the estimated processing rate and the actual processing rate, which can further improve the reliability of the next target operation.

[0130] Specifically, the actual processing rate of the current target operation is obtained, including: for the same wafer, calculating the difference between the current size of the target layer 300 on the surface of the wafer in the first state (for example, the incoming wafer Win1) and the current size of the target layer 300 on the surface of the wafer in the second state (for example, the output wafer Wout1) to obtain the size change; calculating the ratio of the size change to the process duration of the target operation to obtain the actual processing rate.

[0131] For example, taking the etching operation as an example, the difference between the thickness of the target layer 300 on the surface of the incoming wafer Win1 and the thickness of the target layer 300 on the surface of the output wafer Wout1 is calculated to obtain the thickness reduction. Then, the ratio of the thickness reduction to the etching time is calculated to obtain the etching rate (ER).

[0132] It should be noted that the estimated processing rate is obtained through a virtual measurement model. Therefore, when the difference between the estimated processing rate and the actual processing rate exceeds an acceptable range, the estimated processing rate is updated using the current actual processing rate, including: optimizing the virtual measurement model using the actual processing rate, and updating the estimated processing rate using the optimized virtual measurement model.

[0133] The virtual measurement model is optimized using the actual processing rate, so that the virtual measurement model can be optimized based on the adjacent process data, thereby improving the prediction accuracy of the virtual measurement model. For example, with the periodic shutdown maintenance (PM) of the process equipment, the etching rate of the equipment may drift, which easily leads to a difference between the estimated processing rate predicted by the virtual measurement model and the actual processing rate of the process equipment. Therefore, the estimated processing rate needs to be verified using the actual processing rate.

[0134] It should be noted that this embodiment is described by taking the specific process treatment being realized through one target operation as an example. In other embodiments, the specific process treatment can also be realized through multiple target operations; accordingly, in the step of determining the estimated processing rate of the next target operation based on the current size of the target layer on the surface of the wafer in the second state, the estimated processing rate of the next target operation of the current wafer is determined; that is, in the process of realizing the process treatment of the same wafer, imaging processing and analysis are performed in real time, and the target parameters are updated based on the real-time detection data, so as to further improve the uniformity of the target operation inside the wafer. For example, when the response speed of the imaging device and the response speed of the entire manufacturing system are fast enough, imaging processing, analysis, determination of target parameters and feedback operations can be performed in real time during the process treatment of the same wafer.

[0135] It should also be noted that in the traditional semiconductor manufacturing process, different semiconductor processing equipment is used to respectively perform the process of measuring the size of the target layer and the process of performing target processing on the target layer, and the wafers usually enter the semiconductor processing equipment in the form of batches (lots), which leads to a delay in information feedback and can only improve the uniformity between batches. In this embodiment, the step of imaging the wafer is implemented by an imaging device, and the imaging device can be integrated into the semiconductor processing equipment used for target processing, that is, the imaging device and the operating device 40 can be integrated into the same semiconductor processing equipment, therefore, the target parameters can be adjusted in the form of wafers, which improves the speed of information feedback, thereby improving the uniformity between wafers.

[0136] In addition, this embodiment uses a machine learning model to implement image analysis and a virtual measurement model to infer the etching rate, so that the process data can be used to adaptively obtain appropriate target parameters, which not only saves manpower but also reduces dependence on the operator's experience, which is beneficial to improving the reliability of target operations and manufacturing efficiency.

[0137] At the same time, the manufacturing method of this embodiment can omit the measurement steps in the prior art and reduce the number of transfers between different semiconductor processing equipment, thereby helping to save process costs and reduce the risk of defects.

[0138] Correspondingly, an embodiment of the present invention also provides a semiconductor manufacturing system. Figure 7 Schematic diagram of an embodiment of a semiconductor manufacturing system of the present invention

[0139] Combined with reference Figures 2 to 6 In this embodiment, the semiconductor manufacturing system is used to process a wafer W (such as Figure 2 The target layer 300 (as shown) on the surface Figure 2 As shown) perform target operations, which are used to achieve specific process processing.

[0140] The process is implemented by semiconductor processing equipment, which includes etching equipment, chemical mechanical polishing equipment or deposition equipment. In other words, the target operation may include etching operation, chemical mechanical polishing operation or deposition operation.

[0141] When the semiconductor processing equipment is an etching equipment (ie, the target operation is an etching operation), the semiconductor manufacturing system is used to perform etching treatment on the target layer 300 so that the etching amount of the target layer 300 can meet the requirements, and the process treatment is correspondingly an etching treatment.

[0142] When the semiconductor processing equipment is a chemical mechanical polishing equipment (that is, the target operation is a chemical mechanical polishing operation), the semiconductor manufacturing system is used to perform chemical mechanical polishing on the target layer 300 so that the removal amount of the target layer 300 and the surface flatness of the remaining target layer 300 can meet the requirements, and the process treatment is correspondingly a chemical mechanical polishing treatment.

[0143] When the semiconductor processing equipment is a deposition equipment (that is, the target operation is a deposition operation), the semiconductor manufacturing system is used to perform a deposition process on the surface of the target layer 300 to form a film layer on the surface of the target layer 300 that meets the thickness requirements and surface flatness requirements, and the process treatment is correspondingly a deposition process.

[0144] In this embodiment, the semiconductor processing equipment is an etching equipment.

[0145] In this embodiment, the target layer 300 is a non-patterned film layer that completely covers the top surface of the wafer W. In other embodiments, an opening may also be formed in the target layer.

[0146] In this embodiment, the semiconductor manufacturing system includes: an imaging device 10, which is used to perform imaging processing on the wafer W to obtain an image of the target layer 300 as a to-be-processed image 400 (eg, Figure 3 As shown); an image analyzing device 20, used for analyzing the image to be processed 400 to obtain the current size of the target layer 300 according to the image parameters of the image to be processed 400, wherein the image parameters are related to the current size of the target layer 300; a parameter setting device 30, used for determining the target parameters of the target operation based on the current size of the target layer 300; an operating device 40, used for performing a target operation on the target layer 300 based on the target parameters.

[0147] The image to be processed 400 is obtained by the imaging device 10 , and the image to be processed 400 is subsequently analyzed by the image analyzing device 20 to obtain the current size of the target layer 300 according to the image parameters of the image to be processed 400 .

[0148] It should be noted that imaging the wafer W reduces the difficulty of collecting status information of the surface of the wafer W. Moreover, the imaging processing method is convenient for analyzing the image to be processed 400 in combination with image processing technology, thereby improving the efficiency of subsequently obtaining the current size of the target layer 300.

[0149] In this embodiment, the imaging device 10 is a CCD image sensor. In other embodiments, the imaging device may also be a CMOS device image sensor.

[0150] like Figure 3 As an example, the type of the image to be processed 400 includes a grayscale image, and accordingly, the image parameter of the image to be processed 400 is grayscale. In other embodiments, other images to be processed that can be analyzed to obtain the current size of the target layer can also be selected. For example, when the hardware performance of the device is powerful enough (for example, the performance of the processor is powerful enough), a color image can also be used to further improve the accuracy of the results obtained after the subsequent analysis of the image to be processed.

[0151] The image analysis device 20 is used to analyze the image to be processed 400 to obtain the current size of the target layer 300 according to the image parameters of the image to be processed 400, and the current size can reflect the state of the surface of the wafer W before the target operation is performed. The current size of the target layer 300 is first obtained, and the current size is used as reference data for subsequent determination of target parameters, so that when the target operation is performed later, appropriate target parameters can be determined based on the current size of the target layer 300.

[0152] Among them, the image to be processed 400 is an image obtained by imaging wafer W, and the image to be processed 400 contains the status information of the entire surface of wafer W. Compared with the solution of detecting the wafer surface through optical detection technology such as optical emission spectroscopy technology or light signal reflection technology to obtain single-point signal strength, the information provided by the image to be processed 400 is richer, so that the current state of the target layer 300 on the surface of wafer W can be obtained more accurately. Then, after determining the target parameters of the target operation based on the current size of the target layer 300, the accuracy of the target parameters is also improved accordingly, and it is easy to match the current size of different positions on wafer W. Therefore, after performing the target operation on the target layer based on the target parameters, the uniformity of the target operation is improved, that is, the uniformity inside the wafer is improved, thereby improving the yield of semiconductor manufacturing.

[0153] In this embodiment, the current size includes the thickness of the target layer 300 .

[0154] like Figure 4 As shown, Figure 4 : is a relationship diagram of target layer thickness and grayscale according to an embodiment, wherein curve A composed of diamond points represents target layer thickness varying with radial position, and curve B composed of round points represents grayscale varying with radial position. It can be seen that the thickness of target layer 300 has a strong correlation with image grayscale, therefore, by analyzing the image to be processed 400, the thickness of target layer 300 can be obtained according to the grayscale of the image to be processed 400.

[0155] Taking the target operation as an etching operation as an example, the target layer 300 is the etched object, the thickness of the target layer 300 affects the etching amount of the etching operation, and the etching parameters affect the etching amount. Therefore, the thickness of the target layer 300 at different positions on the wafer W is first obtained, so that appropriate target parameters can be determined for the thickness of the target layer 300 at different positions.

[0156] In other embodiments, taking the target operation as a chemical mechanical polishing operation as an example, the target layer is the object to be polished. In order to improve the surface flatness of the remaining target layer after polishing, the thickness of the target layer 300 affects the polishing amount of the chemical mechanical polishing operation, and the polishing parameters affect the polishing amount. Therefore, the target layer thickness at different positions on the wafer is first obtained, so that appropriate target parameters can be determined for the target layer thickness at different positions.

[0157] In other embodiments, taking the target operation as an etching operation, and in the case where an opening is formed in the target layer, the current size may also be the line width of the opening in the target layer. The line width of the opening will also affect the etching effect, therefore, the line width of the opening at different positions on the wafer is first obtained, so that appropriate target parameters can be determined for the line width of the opening at different positions.

[0158] In this embodiment, the image analysis device 20 uses a machine learning model to analyze the image to be processed 400. Accordingly, the input of the machine learning model is the image to be processed 400, and the output is the current size of the target layer 300. Analyzing the image to be processed 400 by the machine learning model is conducive to improving the efficiency of obtaining the current size, and is conducive to obtaining the accurate current size, and is conducive to shortening the production cycle and saving manpower.

[0159] Specifically, the machine learning model includes a convolutional neural network model, which is used to extract image parameters of the image to be processed 400 and output the current size of the target layer 300 according to the image parameters. The convolutional neural network model has the advantages of self-adaptation, highly nonlinear approximation and self-learning. The use of the convolutional neural network is conducive to improving the accuracy of the current size.

[0160] In this embodiment, the convolutional neural network model includes an input layer, a convolutional layer, a pooling layer, a fully connected layer, a linear rectifier function layer and a normalized exponential layer, and the Softmax layer serves as the output layer of the convolutional neural network model. Specifically, in the Softmax layer, a regularization algorithm is used for calculation, which is beneficial to improving the generalization ability of the convolutional neural network and avoiding the problem of overfitting.

[0161] In this embodiment, the machine learning model is obtained in the following manner: obtaining a first data set, the first data set including a plurality of data pairs, each data pair including the actual size of a sample point on a wafer, and an image parameter of an image point corresponding to the sample point, and the first data set including a first training data set and a first verification data set; obtaining an initial analysis model; training the initial analysis model using the first training data set; iteratively optimizing the trained initial analysis model using the first verification data set to achieve parameter optimization of the initial analysis model, and using the initial analysis model that has completed parameter optimization as the machine learning model.

[0162] The first data set includes multiple data pairs, each data pair contains the actual size of a sample point on the wafer and the image parameters of the image point corresponding to the sample point. Therefore, through the learning of the machine learning model, after the image to be processed is subsequently input into the machine learning model, the machine learning model can directly output the current size of the target layer.

[0163] In this embodiment, the machine learning model achieves parameter optimization through back propagation neural network.

[0164] In this embodiment, the method of iteratively optimizing the trained initial analysis model using the first verification data includes one or more of the following methods: adjusting the number of convolutional layers in the initial analysis model; adjusting the number of pooling layers in the initial analysis model.

[0165] Among them, the algorithm adopted by the back propagation neural network may include one or more of a stochastic gradient descent algorithm, an adaptive matrix estimation algorithm, and an adaptive gradient algorithm.

[0166] like Figure 5 As shown, Figure 5 : is a schematic diagram of the structure of the convolutional neural network of this embodiment. As an example, the convolutional neural network model includes an input layer, a first convolutional layer, a first pooling layer, a second convolutional layer, a second pooling layer, a first fully connected layer, a linear rectifier function layer, a second fully connected layer and a normalized exponential layer.

[0167] It should be noted that, for the same wafer W, the wafer W that has not undergone the target operation is in a first state, and the wafer W that has undergone the target operation is in a second state. Therefore, after the wafer W in the first state is imaged by the imaging device 10 to obtain the image to be processed 400, and the image to be processed 400 is analyzed by the image analysis device 20 to obtain the current size, the current size of the target layer 300 on the surface of the wafer W in the first state is obtained.

[0168] For example, Figure 6As shown, the wafers in the first state are incoming wafers Win1, Win2, etc., and the wafers in the second state are output wafers Wout1, Wout2, etc.

[0169] As an example, taking the specific process treatment being realized through a target operation as an example, the incoming wafer Win1 represents the current wafer in the first state, the output wafer Wout1 represents the current wafer in the second state, the incoming wafer Win2 represents the next wafer in the first state, and the output wafer Wout2 represents the next wafer in the second state.

[0170] Taking the target operation on the incoming wafer Win1 as an example, the incoming wafer Win1 is imaged by the imaging device 10 to obtain the image to be processed 400, and the image analysis device 20 analyzes the image to be processed 400 to obtain the current size, thereby obtaining the current size of the target layer 300 on the surface of the incoming wafer Win1.

[0171] In other implementation rates, the specific process treatment can also be achieved through multiple target operations. Accordingly, the incoming wafer Win1 represents the current wafer in the first state when the first target operation is performed, the output wafer Wout1 represents the current wafer in the second state when the first target operation is performed, the incoming wafer Win2 represents the current wafer in the first state when the second target operation is performed, and the output wafer Wout2 represents the current wafer in the second state when the second target operation is performed.

[0172] Continue to refer Figure 1 It should be noted that the semiconductor manufacturing system further includes: an estimation module 50 for obtaining an estimated processing rate of the target operation before determining the target parameters of the target operation based on the current size of the target layer 300 .

[0173] After determining the estimated processing rate of the current target operation, the process parameters of the target operation may be subsequently adjusted based on the current size of the target layer and the estimated processing rate to obtain target parameters that meet process requirements.

[0174] In this embodiment, the estimation module 50 includes a virtual measurement model. The virtual measurement model is established based on a large amount of process history data in the factory. Specifically, by utilizing the inherent connection between the historical data, a virtual measurement model related to the actual data of the process equipment is established. Through the virtual measurement model, the processing rate of the process equipment can be quickly and reliably calculated.

[0175] In this embodiment, the virtual measurement model is obtained in the following manner: historical data of the target operation is obtained as a second data set, and the second data set includes a second training data set and a second verification data set; an initial measurement model is obtained; the initial measurement model is trained using the second training data set; the trained initial measurement model is iteratively optimized using the second verification data set to achieve parameter optimization of the initial measurement model, and the initial measurement model after parameter optimization is used as the virtual measurement model.

[0176] It should be noted that the historical data of the target operation is the offline data of the process equipment. As an example, the historical data includes process parameter information, wafer information and process equipment information, thereby increasing the diversity of data and making the inherent correlation between the virtual measurement model and the historical data stronger, which is conducive to improving the calculation accuracy of the virtual measurement model.

[0177] In a specific embodiment, taking the target operation as an etching operation, the data type of the historical data includes process time, gas flow, chuck temperature, transformer coupled plasma temperature, pressure, source power, RF power, RF hours, gas flow distribution, chamber ID, wafer ID and any multiple of the sub-steps.

[0178] Among them, process time, gas flow, chuck temperature, transformer coupled plasma temperature, pressure, source power, RF power, RF time and gas flow distribution are all process parameter information, wafer ID is wafer information, chamber ID and sub-steps are all process equipment information.

[0179] In this embodiment, the virtual measurement model includes multiple sub-models of different types, and the multiple sub-models can output estimated processing rates; the estimated processing rate output by the virtual measurement model is equal to the weighted value of the estimated processing rates output by each sub-model.

[0180] Semiconductor manufacturing is a complex process. If only a single sub-model is used to establish a virtual measurement model, there may be a problem of incomplete information learned by the single sub-model, thereby affecting the prediction accuracy of the virtual measurement model. To this end, multiple sub-models are integrated into a virtual measurement model, and the weighted value of the estimated processing rate inferred by each sub-model is used as the estimated processing rate output by the virtual measurement model, which is conducive to enabling the virtual measurement model to learn the impact of different factors on the prediction results, thereby further improving the prediction accuracy of the virtual measurement model.

[0181] The sub-models include any of a persistent model, a K-nearest neighbor regression model (K-NeighborsRegressor, K-nn regression) model, a linear regression model, a random forest (Random Forest, RF) model and a support vector regression (SVR) model.

[0182] In this embodiment, the sub-models include a persistence model, a K nearest neighbor regression model, a linear regression model, a random forest model and a support vector regression model.

[0183] The parameter setting device 30 determines the target parameter of the target operation based on the current size of the target layer 300 .

[0184] The current size of the target layer 300 is acquired in advance, and the corresponding target parameters are determined based on the current size of the target layer 300. Accordingly, the operating device 40 performs a target operation (for example, etching processing) on ​​the target layer 300 based on the target parameters, thereby achieving operation uniformity (for example, etching uniformity) at each position on the incoming wafer Win1 in the feedforward direction.

[0185] Specifically, the parameter setting device 30 determines the target parameters of the target operation based on the current size of the target layer 300 and the estimated processing rate. In a specific embodiment, the parameter setting device 30 determines the target parameters of the current target operation based on the current size of the target layer 300 on the wafer surface in the first state and the estimated processing rate of the target operation.

[0186] For example, Figure 6 As shown, the parameter setting device 30 determines the target parameters when performing the target operation on the incoming wafer Win1 based on the current size of the target layer 300 on the surface of the incoming wafer Win1 and the estimated processing rate of the target operation.

[0187] At the same time, taking the current size of the target layer 300 and the estimated processing rate as factors for determining the target parameters is conducive to improving the accuracy of the target parameters.

[0188] In this embodiment, the parameter setting device 30 includes an advanced process control (APC) module (ie, an APC system), and the APC system determines the target parameters of the target operation based on the current size of the target layer 300 and the estimated processing rate.

[0189] The APC system adopts a feedforward control system and a feedback control system, so that the processing effect of the current target operation can be fed back to the next target operation, which is conducive to improving the uniformity of the target operation.

[0190] In this embodiment, the target operation is an etching operation, and the target parameters include one or more of chuck temperature, gas flow distribution, process time, transformer coupled plasma temperature, gas flow, source power, RF power, RF hours and pressure.

[0191] After determining the target parameters, the operating device 40 performs a target operation on the target layer 300 based on the target parameters.

[0192] like Figure 6 As shown, the operating device 40 performs a target operation on the incoming wafer Win1 based on the target parameters corresponding to the incoming wafer Win1.

[0193] In this embodiment, taking the target operation as an etching operation as an example, the operating device 40 performs an etching operation on the target layer 300 based on the received etching parameters.

[0194] In this embodiment, the semiconductor manufacturing system includes a feedforward control system 100 and a feedback control system 200. The feedforward control system 100 and the feedback control system 200 both include the imaging device, the image analysis device and the parameter setting device 30, and share the parameter setting device 30.

[0195] Specifically, the feedforward control system 100 uses the imaging device 10 and the image analysis device 20 to respectively perform the steps of imaging the wafer in the first state and analyzing the image to be processed in sequence to obtain the current size of the target layer on the surface of the wafer in the first state. The feedforward control system 100 also uses the parameter setting device 30 to determine the target parameters of the current target operation based on the current size of the target layer on the surface of the wafer in the first state and the estimated processing rate of the target operation.

[0196] Therefore, in this embodiment, after performing the target operation on the target layer 300 on the surface of the wafer in the first state (i.e., the incoming wafer Win1), the feedback control system 200 uses the imaging device 60 and the image analysis device 70 to again perform the steps of imaging the wafer and analyzing the image to be processed on the wafer in the second state to obtain the current size of the target layer on the surface of the wafer in the second state. The feedback control system 200 also uses the parameter setting device 30 to determine the estimated processing rate of the next target operation based on the current size of the target layer on the surface of the wafer in the second state.

[0197] By again performing imaging processing on the wafer to obtain an image to be processed, and analyzing the image to be processed using an image analysis model, the result of the target operation based on the current target parameters can be verified, and the verification result can be fed back to the next target operation, so as to facilitate calibration of the parameters of the next target operation, thereby achieving uniformity between different target operations in the feedback direction (for example, etching uniformity).

[0198] Specifically, the imaging device 60 of the feedback control system 200 performs imaging processing on the wafer (i.e., the incoming wafer Win1) again to obtain the image of the target layer 300 as the image to be processed; the image analysis device 70 of the feedback control system 200 analyzes the image to be processed to obtain the current size of the target layer according to the image parameters of the image to be processed, and the image parameters are related to the current size of the target parameters.

[0199] After the image analysis device 70 of the feedback control system 200 analyzes the image to be processed, the estimation module 50 determines the estimated processing rate of the next target operation based on the current size of the target layer 300 on the surface of the wafer (ie, the output wafer Wout1) in the second state.

[0200] By determining the estimated processing rate of the next target operation, after subsequently obtaining the current size of the target layer 300 corresponding to the next target operation, the target parameters can be determined based on the current size of the target layer and the estimated processing rate, thereby improving the uniformity of the target operation between wafers.

[0201] It should be noted that the feedforward control system 100 and the feedback control system 200 can also share an imaging device and an image analysis device to simplify the semiconductor manufacturing system. That is, the imaging device 10 in the feedforward control system 100 and the imaging device 60 in the feedback control system 200 can be the same device, and the image analysis device 20 in the feedforward control system 100 and the image analysis device 70 in the feedback control system 200 can be the same device.

[0202] In other embodiments, the feedforward control system and the feedback control system may each use an independent imaging device, and the feedforward control system and the feedback control system may each use an independent image analysis device.

[0203] like Figure 6As shown, in this embodiment, the specific process treatment is achieved through one target operation. In other words, after completing the target operation on the current wafer, the target operation will be performed on the next wafer. Based on the current size of the target layer on the surface of the wafer in the second state, the estimated processing rate of the target operation of the next wafer (that is, the incoming wafer Win2) is determined.

[0204] Therefore, the incoming wafer Win2 is subsequently imaged and the image to be processed is analyzed in sequence to obtain the current size of the target layer on the surface of the incoming wafer Win2 in the first state. Based on the current size of the target layer on the surface of the incoming wafer Win2 and the estimated processing rate obtained through feedback from the output wafer Wout1, the target parameters for the target operation on the incoming wafer Win2 can be determined.

[0205] Correspondingly, the incoming wafer Win2 is subsequently subjected to target processing based on the target parameters corresponding to the incoming wafer Win2 to obtain the output wafer Wout2.

[0206] In this embodiment, in order to improve the accuracy of the estimated processing rate of the next target operation, the parameter setting device 30 of the feedback control system 200 includes: an operation module 80, which is used to obtain the actual processing rate of the current target operation based on the current size of the target layer on the surface of the wafer in the second state (that is, the output wafer Wout1); a verification module 90, which is used to compare the estimated processing rate when the target operation is performed on the target layer on the surface of the wafer in the first state (that is, the incoming wafer Win1) with the actual processing rate, and when the difference between the estimated processing rate and the actual processing rate is within an acceptable range, maintain the estimated processing rate as the estimated processing rate for the next target operation; when the difference between the estimated processing rate and the actual processing rate exceeds the acceptable range, the estimated processing rate is updated based on the current actual processing rate to obtain the estimated processing rate for the next target operation.

[0207] The estimated processing rate is a rate extrapolated based on a large amount of historical data. Therefore, the actual processing rate of the previous target operation is used for verification, and the verification result is fed back to the next target operation to avoid the problem of excessive difference between the estimated processing rate and the actual processing rate, which can further improve the reliability of the next target operation.

[0208] Specifically, for the same wafer, the operation module 80 calculates the difference between the current size of the target layer 300 on the surface of the wafer in the first state (for example, the incoming wafer Win1) and the current size of the target layer 300 on the surface of the wafer in the second state (for example, the output wafer Wout1) to obtain the size change; calculates the ratio of the size change to the process time of the target operation to obtain the actual processing rate.

[0209] For example, taking the etching operation as an example, the operation module 80 calculates the difference between the thickness of the target layer 300 on the surface of the incoming wafer Win1 and the thickness of the target layer 300 on the surface of the output wafer Wout1, and obtains the thickness reduction. Then, the ratio of the thickness reduction to the etching time is calculated to obtain the etching rate.

[0210] It should be noted that the estimation module 50 includes a virtual measurement model, and the estimated processing rate is obtained through the virtual measurement model. Therefore, when the difference between the estimated processing rate and the actual processing rate exceeds an acceptable range, the virtual measurement model uses the actual processing rate to perform model optimization and updates the estimated processing rate after the optimization is completed.

[0211] The virtual measurement model is optimized using the actual processing rate, so that the virtual measurement model can be optimized based on the adjacent process data, thereby improving the prediction accuracy of the virtual measurement model. For example, as the process equipment is shut down for maintenance periodically, the etching rate of the equipment may drift, which can easily lead to a difference between the estimated processing rate predicted by the virtual measurement model and the actual processing rate of the process equipment. Therefore, the estimated processing rate needs to be verified using the actual processing rate.

[0212] It should be noted that this embodiment is described by taking the specific process processing being implemented by one target operation as an example. In other embodiments, the specific process processing is implemented by multiple target operations; accordingly, the feedback control system is used to determine the estimated processing rate of the next target operation of the current wafer.

[0213] The feedback control system is used to determine the estimated processing rate of the next target operation of the current wafer, that is, in the process of implementing the process of the same wafer, imaging processing and analysis are performed in real time, and the target parameters are updated based on the real-time detection data, so as to further improve the uniformity of the target operation inside the wafer. For example, if the response speed of the imaging device and the response speed of the entire manufacturing system are fast enough, imaging processing, analysis, determination of target parameters and feedback operations can be performed in real time during the process of the same wafer.

[0214] In this embodiment, the imaging devices 10, 60, the image analyzing devices 20, 70, the parameter setting device 30, the operating device 40 and the estimation module 50 are integrated into the same semiconductor processing equipment, and the semiconductor processing equipment is the equipment used to implement the process treatment.

[0215] In the traditional semiconductor manufacturing process, different semiconductor processing equipment is used to respectively perform the process of measuring the size of the target layer and the process of performing target processing on the target layer, and the wafers usually enter the semiconductor processing equipment in the form of batches, which leads to a delay in information feedback and can only improve the uniformity between batches. In this embodiment, the step of imaging the wafer is implemented by an imaging device, and the imaging device can be integrated into the semiconductor processing equipment used for target processing. Therefore, the target parameters can be adjusted in the form of wafers, which improves the speed of information feedback and thus improves the uniformity between wafers.

[0216] In addition, the manufacturing system described in this embodiment uses a machine learning model to implement image analysis and a virtual measurement model to infer the etching rate, so that the process data can be used to adaptively obtain appropriate target parameters, which not only saves manpower but also reduces dependence on the operator's experience, which is conducive to improving the reliability of target operations and manufacturing efficiency.

[0217] At the same time, the manufacturing system of this embodiment can omit the measurement steps in the prior art and reduce the number of transfers between different semiconductor processing equipment, thereby helping to save process costs and reduce the risk of defects.

[0218] The semiconductor manufacturing method provided in the embodiment of the present invention can be executed by the semiconductor manufacturing system described in the above embodiment, or by other manufacturing systems. For the specific description of the semiconductor manufacturing system described in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment.

[0219] Correspondingly, an embodiment of the present invention further provides a device, which can implement the semiconductor manufacturing method provided by the embodiment of the present invention by loading the above-mentioned semiconductor manufacturing method in the form of a program.

[0220] refer to Figure 8 , shows a hardware structure diagram of a device provided by an embodiment of the present invention. The device of this embodiment includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0221] In this embodiment, the number of each of the processor 01 , the communication interface 02 , the memory 03 and the communication bus 04 is at least one, and the processor 01 , the communication interface 02 and the memory 03 communicate with each other via the communication bus 04 .

[0222] The communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module.

[0223] The processor 01 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the semiconductor manufacturing method of this embodiment.

[0224] The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory. The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the semiconductor manufacturing method provided in the above embodiment.

[0225] It should be noted that the above-mentioned electronic device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; since these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.

[0226] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the semiconductor manufacturing method provided by the aforementioned embodiment.

[0227] The above-mentioned embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment, and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the attached claims may be combined into embodiments of the present invention, or may be included as new claims in the amendment after submitting this application.

[0228] The embodiments of the present invention can be implemented by various means such as hardware, firmware, software or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0229] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, etc. The software code may be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and may send data to and receive data from the processor via various known means.

[0230] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0231] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor manufacturing method, characterized in that: Used to perform target operations on the target layer on the wafer surface. The target operation is used to implement a specific process, and the semiconductor manufacturing method includes: Performing imaging processing on the wafer to obtain an image of the target layer as an image to be processed; Analyzing the image to be processed to obtain the current size of the target layer according to image parameters of the image to be processed, wherein the image parameters are related to the current size of the target layer; Determining a target parameter for the target operation based on a current size of the target layer; Based on the target parameters, a target operation is performed on the target layer.

2. The semiconductor manufacturing method according to claim 1, wherein: Analyzing the graph to be processed using a machine learning model; The machine learning model includes a convolutional neural network model, which is used to extract image parameters of the image to be processed and output the current size of the target layer according to the image parameters.

3. The semiconductor manufacturing method according to claim 2, characterized in that: The machine learning model is obtained by: acquiring a first data set, the first data set comprising a plurality of data pairs, each data pair comprising a real size of a sample point on a wafer and an image parameter of an image point corresponding to the sample point, and the first data set comprising a first training data set and a first verification data set; Obtaining an initial analysis model; Using the first training data set to train the initial analysis model; The trained initial analysis model is iteratively optimized using the first validation data set to achieve parameter optimization of the initial analysis model, and the initial analysis model that has completed parameter optimization is used as a machine learning model.

4. The semiconductor manufacturing method according to claim 3, characterized in that: The step of iteratively optimizing the trained initial analysis model using the first verification data includes: optimizing parameters using a back propagation neural network.

5. The semiconductor manufacturing method according to claim 3, characterized in that: The method of iteratively optimizing the trained initial analysis model using the first verification data includes one or more of the following methods: adjusting the number of convolutional layers in the initial analysis model; adjusting the number of pooling layers in the initial analysis model.

6. The semiconductor manufacturing method according to claim 1, wherein: Before determining the target parameters of the target operation based on the current size of the target layer, the semiconductor manufacturing method further includes: obtaining an estimated processing rate of the target operation; Target parameters for the target operation are determined based on the current size of the target layer and the estimated processing rate.

7. The semiconductor manufacturing method according to claim 6, characterized in that: determining, by an advanced process control system, target parameters for the target operation based on a current size of the target layer and the estimated processing rate; The method of obtaining the estimated processing rate of the target operation includes: obtaining the estimated processing rate by using a virtual measurement model.

8. The semiconductor manufacturing method according to claim 7, characterized in that: The virtual measurement model is obtained by: acquiring historical data of the target operation as a second data set, wherein the second data set includes a second training data set and a second verification data set; Obtaining an initial measurement model; Using the second training data set to train the initial measurement model; The trained initial measurement model is iteratively optimized using the second verification data set to achieve parameter optimization of the initial measurement model, and the initial measurement model after parameter optimization is used as a virtual measurement model.

9. The semiconductor manufacturing method according to claim 8, characterized in that: The target operation is an etching operation, and the data types of the historical data include process time, gas flow, chuck temperature, transformer coupled plasma temperature, pressure, source power, RF power, RF hours, gas flow distribution, chamber ID, wafer ID and any multiple of sub-steps.

10. The semiconductor manufacturing method according to claim 8, wherein: Before using the second training data to train the initial measurement model, the method further includes: performing a feature extraction operation, wherein the extracted features include time proximity features, statistical features, and correlation weight proximity features; In the step of training the initial measurement model using the second training data set, the training is performed based on the temporal proximity features, statistical features and correlation weight proximity features.

11. The semiconductor manufacturing method according to claim 8, wherein: The initial measurement model includes a plurality of sub-models of different types, and the plurality of sub-models can output an estimated processing rate; The step of training the initial measurement model using the second training data includes: weighting the estimated processing rates output by the plurality of sub-models respectively under different weight allocation schemes to obtain the estimated processing rate of the initial measurement model; A weight distribution scheme corresponding to the estimated processing rate that is closest to the actual processing rate is selected to obtain the target weight of each sub-model. The target weight is used to characterize the contribution rate of the estimated processing rate output by each sub-model to the estimated processing rate output by the initial measurement model.

12. The semiconductor manufacturing method according to claim 11, wherein: The sub-models include any of a persistence model, a K nearest neighbor regression model, a linear regression model, a random forest model, and a support vector regression model.

13. The semiconductor manufacturing method according to claim 6, wherein: For the same wafer, the wafer that has not been subjected to the target operation is in a first state, and the wafer that has been subjected to the target operation is in a second state; The steps of performing imaging processing on the wafer and analyzing the image to be processed are sequentially performed on the wafer in the first state to obtain a current size of a target layer on the surface of the wafer in the first state; determining a target parameter for a current target operation based on a current size of a target layer on the surface of the wafer in the first state and an estimated processing rate of the target operation; After performing the target operation on the target layer on the surface of the wafer in the first state, performing the steps of imaging the wafer and analyzing the image to be processed again on the wafer in the second state to obtain a current size of the target layer on the surface of the wafer in the second state; Based on the current size of the target layer on the wafer surface in the second state, an estimated processing rate for the next target operation is determined.

14. The semiconductor manufacturing method according to claim 13, wherein: The specific process is implemented by a target operation; in the step of determining an estimated processing rate of the next target operation based on the current size of the target layer on the surface of the wafer in the second state, determining an estimated processing rate of the target operation of the next wafer; or, The specific process treatment is achieved through multiple target operations; In the step of determining an estimated processing rate for a next target operation based on a current size of a target layer on the surface of the wafer in the second state, an estimated processing rate for a next target operation of the current wafer is determined.

15. The semiconductor manufacturing method according to claim 13, wherein: Determining an estimated processing rate for a next target operation based on a current size of the target layer on the wafer surface in the second state, including: obtaining an actual processing rate for the current target operation based on the current size of the target layer on the wafer surface in the second state ； comparing an estimated processing rate when a target operation is performed on a target layer on the surface of the wafer in the first state with an actual processing rate; When the difference between the estimated processing rate and the actual processing rate is within an acceptable range, maintaining the estimated processing rate as the estimated processing rate for the next target operation; When the difference between the estimated processing rate and the actual processing rate exceeds an acceptable range, the estimated processing rate is updated using the current actual processing rate to obtain the estimated processing rate of the next target operation.

16. The semiconductor manufacturing method according to claim 15, characterized in that: The method of obtaining the estimated processing rate of the target operation includes: obtaining the estimated processing rate using a virtual measurement model; When the difference between the estimated processing rate and the actual processing rate exceeds an acceptable range, the estimated processing rate is updated using the current actual processing rate, including: optimizing the virtual measurement model using the actual processing rate, and updating the estimated processing rate using the optimized virtual measurement model.

17. The semiconductor manufacturing method according to any one of claims 1 to 16, characterized in that: The target operation includes an etching operation, a chemical mechanical polishing operation or a deposition operation ； In the step of obtaining the current size of the target layer according to the image parameters of the image to be processed, the current size includes the thickness of the target layer, or the line width of the opening in the target layer.

18. The semiconductor manufacturing method according to any one of claims 1 to 16, characterized in that: The target operation is an etching operation. Based on the current size of the target layer, in the step of determining target parameters of the target operation, the target parameters include one or more of chuck temperature, gas flow distribution, process time, transformer coupled plasma temperature, gas flow, source power, RF power, RF hours and pressure.

19. The semiconductor manufacturing method according to any one of claims 1 to 16, characterized in that: The type of the image to be processed includes a grayscale image, and the image parameter includes grayscale.

20. A semiconductor manufacturing system, characterized in that: Used to perform a target operation on a target layer on a wafer surface, wherein the target operation is used to implement a specific process, the semiconductor manufacturing system comprises: An imaging device, used for performing imaging processing on the wafer to obtain an image of the target layer as an image to be processed; An image analysis device, used for analyzing the image to be processed to obtain the current size of the target layer according to image parameters of the image to be processed, wherein the image parameters are related to the current size of the target layer; Parameter setting means, for determining a target parameter of the target operation based on a current size of the target layer; An operating device is used to perform a target operation on the target layer based on the target parameter.

21. The semiconductor manufacturing system according to claim 20, wherein: The image analysis device analyzes the image to be processed using a machine learning model; The machine learning model includes a convolutional neural network model, which is used to extract image parameters of the image to be processed and output the current size of the target layer according to the image parameters.

22. The semiconductor manufacturing system according to claim 20, wherein: The semiconductor manufacturing system further includes: an estimation module, configured to obtain an estimated processing rate of the target operation; The parameter setting device determines the target parameters of the target operation based on the current size of the target layer and the estimated processing rate.

23. The semiconductor manufacturing system according to claim 22, wherein: The parameter setting device includes an advanced process control module; The estimation module includes a virtual measurement model.

24. The semiconductor manufacturing system according to claim 23, wherein: The virtual measurement model includes a plurality of sub-models of different types, and the plurality of sub-models can output an estimated processing rate; The estimated processing rate output by the virtual measurement model is equal to the weighted value of the estimated processing rates output by each sub-model.

25. The semiconductor manufacturing system according to claim 24, wherein: The sub-models include any of a persistence model, a K nearest neighbor regression model, a linear regression model, a random forest model, and a support vector regression model.

26. The semiconductor manufacturing system according to claim 22, wherein: For the same wafer, the wafer that has not been subjected to the target operation is in a first state, and the wafer that has been subjected to the target operation is in a second state; The semiconductor manufacturing system includes a feedforward control system and a feedback control system, wherein the feedforward control system and the feedback control system both include the imaging device, the image analysis device and the parameter setting device, and share the parameter setting device; wherein, The feedforward control system uses the imaging device and the image analysis device to sequentially perform the steps of imaging the wafer and analyzing the image to be processed on the wafer in the first state, thereby obtaining a current size of a target layer on the surface of the wafer in the first state. The feedforward control system also uses the parameter setting device to determine a target parameter of a current target operation based on the current size of the target layer on the surface of the wafer in the first state and an estimated processing rate of the target operation. The feedback control system uses the imaging device and the image analysis device to again perform the steps of imaging the wafer and analyzing the image to be processed on the wafer in the second state to obtain the current size of the target layer on the surface of the wafer in the second state. The feedback control system also uses the parameter setting device to determine the estimated processing rate of the next target operation based on the current size of the target layer on the surface of the wafer in the second state.

27. The semiconductor manufacturing system according to claim 26, wherein: The specific process is achieved by a target operation; the feedback control system is used to determine the estimated processing rate of the target operation of the next wafer; or, The specific process is achieved through multiple target operations; the feedback control system is used to determine the estimated processing rate of the next target operation of the current wafer.

28. The semiconductor manufacturing system according to claim 26, wherein: The parameter setting device of the feedback control system includes: a calculation module for obtaining the actual processing rate of the current target operation; The inspection module is used to compare the estimated processing rate when the target operation is performed on the target layer on the surface of the wafer in the first state with the actual processing rate, and when the difference between the estimated processing rate and the actual processing rate is within an acceptable range, maintain the estimated processing rate as the estimated processing rate for the next target operation; when the difference between the estimated processing rate and the actual processing rate exceeds the acceptable range, update the estimated processing rate based on the current actual processing rate to obtain the estimated processing rate for the next target operation.

29. The semiconductor manufacturing system according to claim 28, wherein: The estimation module includes a virtual measurement model; When the difference between the estimated processing rate and the actual processing rate exceeds an acceptable range, the virtual measurement model uses the actual processing rate to perform model optimization, and updates the estimated processing rate after the optimization is completed.

30. The semiconductor manufacturing system according to any one of claims 20 to 29, characterized in that: The imaging device, image analyzing device, parameter setting device and operating device are integrated into the same semiconductor processing equipment, and the semiconductor processing equipment is the equipment used to implement the process treatment.

31. The semiconductor manufacturing system according to any one of claims 20 to 29, characterized in that: The process is implemented by semiconductor processing equipment, which includes etching equipment, chemical mechanical polishing equipment or deposition equipment.

32. A device, characterized in that The method comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the semiconductor manufacturing method according to any one of claims 1 to 19.

33. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the semiconductor manufacturing method as described in any one of claims 1-19.

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