Integrated circuit package and method of forming same

Abstract

Integrated circuit packages and methods of forming the same are provided. The integrated circuit package may include a first die having a first substrate over a package substrate; and a cover. The first channel may extend through the first substrate from a first sidewall of the first die to a second sidewall of the first die. The cap may include: a top portion over the first die; and a first bottom portion extending along a first sidewall of the first die. The first bottom portion may include a second channel connected to the first channel.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] Some embodiments of the present application provide an integrated circuit package, comprising: a first die located above a packaging substrate, wherein the first die includes a first substrate, and wherein a first channel extends through the first substrate from a first side wall of the first die to a second side wall of the first die; and a cover, comprising: a top portion located above the first die; and a first bottom portion extending along the first side wall of the first die, wherein the first bottom portion includes a second channel, and wherein the second channel is connected to the first channel.

[0004] Other embodiments of the present application provide an integrated circuit package, comprising: a first die located above a packaging substrate, wherein the first die includes a first substrate; and a cover, comprising: a top portion located above the first die; a first bottom portion extending along a first side wall of the first die, wherein the first bottom portion includes a first fluid channel; and a second bottom portion extending along a second side wall of the first die, wherein the second side wall of the first die is opposite to the first side wall of the first die, and wherein the second bottom portion includes a second fluid channel.

[0005] Still other embodiments of the present application provide a method for forming an integrated circuit package, the method comprising: bonding a first die to a package substrate; attaching a reinforcement ring to the package substrate, wherein the reinforcement ring surrounds the first die in a top view; and attaching a cover to the reinforcement ring, the cover comprising: a top portion located above the first die, wherein the top portion of the cover also includes a first fluid channel; a first bottom portion protruding from a bottom surface of the top portion, wherein the first bottom portion extends along a first side wall of the first die, wherein the first bottom portion includes a second fluid channel; and a second bottom portion protruding from the bottom surface of the top portion, wherein the second bottom portion extends along a second side wall of the first die, wherein the second side wall of the first die is opposite to the first side wall of the first die, and wherein the second bottom portion includes a third fluid channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E Cross-sectional and top view diagrams illustrate intermediate processing steps in the formation of an integrated circuit package in accordance with some embodiments.

[0008] Fig.14A , Fig. 14B and Fig. 14C A cross-sectional view of an integrated circuit package is shown in accordance with some embodiments.

[0009] Fig.15A and Fig. 15B A cross-sectional view of an integrated circuit package is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] An integrated circuit package having a lid and a method for forming the same are provided, wherein the lid has a coolant fluid channel. The integrated circuit package may include one or more integrated circuit dies and a lid. The lid may include a top portion located above the one or more integrated circuit dies and a bottom portion along the sidewalls of the one or more integrated circuit dies. The lid may also include coolant fluid channels in the top portion and the bottom portion. The coolant fluid channel in the bottom portion may be connected to the coolant fluid channel in the one or more integrated circuit dies. Because the coolant fluid may flow near hot spots (e.g., devices) in one or more integrated circuit dies, the heat generated in the one or more integrated circuit dies may be more effectively dissipated during operation of the integrated circuit package, thereby improving the heat dissipation of the integrated circuit package. Therefore, the performance and reliability of the integrated circuit package may be improved.

[0013] Figures 1A to 13E Intermediate processing steps in forming an integrated circuit package are shown. Figures 1A to 1C , a lower integrated circuit die 100 is shown. Figure 1A The cross-sectional view of the lower integrated circuit die 100 shown in FIG. Figure 1C The top view of the lower integrated circuit die 100 shown in FIG. 1 is obtained by referring to the reference cross section AA′. Figure 1BThe cross-sectional view of the lower integrated circuit die 100 shown in FIG. Figure 1C The reference cross section BB′ shown in the top view of the lower integrated circuit die 100 is obtained.

[0014] The lower integrated circuit die 100 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0015] The lower integrated circuit die 100 may have a semiconductor substrate 102, such as doped or undoped silicon, an active layer of a semiconductor-on-insulator (SOI) substrate, etc. The semiconductor substrate 102 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 102 may have an active surface (e.g., a front side) that may be referred to as a front side. Figure 1A and Figure 1B The surface facing downward in the middle) and the inactive surface which can be called the back side (e.g. Figure 1A and Figure 1B The back side of the semiconductor substrate 102 may also be referred to as the back side of the lower integrated circuit die 100 , and the front side of the semiconductor substrate 102 may face the front side of the lower integrated circuit die 100 .

[0016] Devices (not shown separately) may be disposed at the active surface of the semiconductor substrate 102. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The devices may generate a large amount of heat during operation of the lower integrated circuit die 100, and may generate hot spots in the lower integrated circuit die 100. An interconnect structure 104 may be disposed on the active surface of the semiconductor substrate 102. The interconnect structure 104 may interconnect the devices to form an integrated circuit. The interconnect structure 104 may include a metallization pattern (not shown separately) in a dielectric layer (not shown separately). The dielectric layer may be a low-k dielectric layer. The metallization pattern may include metal lines and vias, which may be formed in the dielectric layer by a damascene process, such as a single damascene process, a dual damascene process, etc. The metallization pattern may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc. The metallization pattern may be electrically coupled to the device. A seal ring 105 may extend through the interconnect structure 104 of the lower integrated circuit die 100. In the top view, the seal ring 105 may surround the metallization pattern corresponding to the interconnect structure 104. The seal ring 105 may be formed of the same or similar material and by the same or similar process as the metallization pattern. The seal ring 105 may be electrically isolated from the device.

[0017] Conductive vias 106 may be disposed in semiconductor substrate 102. Conductive vias 106 may be electrically coupled to a metallization pattern of interconnect structure 104. Conductive vias 106 may be referred to as through substrate vias (TSVs). Channels 107 may be disposed on the back side of semiconductor substrate 102. Channels 107 may be openings through which coolant fluid may flow to dissipate heat generated in lower integrated circuit die 100 during operation, as described in more detail below. For purposes of illustration, channels 107 are shown in FIG. Figure 1C It is shown by a dotted line. Figure 1A As shown in , the channel 107 is disposed between adjacent conductive vias 106. Figure 1B and Figure 1C As shown in FIG. 1 , the channel 107 may extend in parallel from one sidewall to an opposite sidewall through the semiconductor substrate 102. The channel 107 may be formed in the semiconductor substrate 102 by a suitable photolithography process. Figure 1A , Figure 1B and Figure 1C The number and arrangement of channels 107 in FIG. 1 are provided as examples. Other numbers and arrangements of channels 107 are also contemplated.

[0018] The cap 109 may be disposed on the back side of the semiconductor substrate 102 and cover the channel 107. The cap 109 may be bonded to the semiconductor substrate 102 by an adhesive (not separately shown), such as a thermal interface material (TIM), etc. The cap 109 may be formed of the same or similar material as the semiconductor substrate 102. In some embodiments, the conductive pad 103 extends through the cap 109 and is physically and electrically coupled to the conductive via 106, such as Figure 1A . External connections to the lower integrated circuit die 100 may be made through conductive pads 103. For such an embodiment, for illustrative purposes, Figure 1C Conductive pads 103 are omitted in the embodiment. In some embodiments, conductive vias 106 may extend through cap 109. External connections to the lower integrated circuit die 100 may be made through conductive vias 106. For such embodiments, for illustration purposes, Figure 1C The conductive via 106 is omitted.

[0019] The dielectric layer 108 may be disposed on the interconnect structure 104 at the front side of the lower integrated circuit die 100. The dielectric layer 108 may be formed of: an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), an oxide based on tetraethyl orthosilicate (TEOS), etc.; a nitride, such as silicon nitride, etc.; etc. The dielectric layer 108 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. One or more passivation layers (not separately shown) may be disposed between the dielectric layer 108 and the interconnect structure 104. A conductive pad 110 may extend through the dielectric layer 108 and be electrically coupled to a metallization pattern of the interconnect structure 104. External connections to the lower integrated circuit die 100 may be made through the conductive pad 110. The conductive pad 110 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The conductive pad 110 may be formed of a conductive material (such as copper, aluminum, etc.) through a suitable coating process (such as plating, etc.).

[0020] exist Figure 2 In the embodiment of the present invention, the lower integrated circuit die 100 is attached to the carrier 112 by the adhesive 114 , and a lower gap-fill layer 116 is formed around the lower integrated circuit die 100 . Figure 2The layout of the lower integrated circuit die 100 above the carrier 112 shown in FIG. is provided as an example. Other layouts of the lower integrated circuit die 100 are contemplated. The carrier 112 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 112 may be a wafer. In some embodiments, the adhesive 114 is a thermal release material, such as an epoxy-based light-to-heat conversion (LTHC) release material, which loses its viscosity when heated. In some embodiments, the adhesive 114 is a UV glue that loses its viscosity when exposed to UV light.

[0021] In the top view, the lower gap fill layer 116 may surround the lower integrated circuit die 100. The lower gap fill layer 116 may extend along the sidewalls of the lower integrated circuit die 100 (including the semiconductor substrate 102, the interconnect structure 104, and the dielectric layer 108). The lower gap fill layer 116 may be formed of a dielectric material, such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxide, polymer, etc., which may be formed by a suitable deposition process such as CVD, ALD, spin coating, etc. Initially, the lower gap fill layer 116 may cover the cap 109. One or more thinning processes may be performed to make the top surface of the lower gap fill layer 116 flush with the top surface of the cap 109 and to expose the conductive pad 103. The one or more thinning processes may be a chemical mechanical polishing (CMP) process, a grinding process, an etch back process, a combination thereof, etc. After one or more thinning processes, top surfaces of the lower gap-fill layer 116 , the cap 109 , and the conductive pad 103 may be substantially coplanar or flush (within process variations).

[0022] exist Figure 3In the embodiment of the present invention, a bonding layer 118 is formed on the lower gap filling layer 116, the cap 109 and the conductive pad 103, and a bonding pad 120 is formed in the bonding layer 118. The bonding layer 118 and the bonding pad 120 can be used to bond with the upper integrated circuit die in a subsequent process. The bonding pad 120 can extend through the bonding layer 118 to be physically and electrically coupled to the conductive pad 103. Some of the bonding pads 120 can be physically and electrically isolated from the conductive pad 103 and can be used for bonding purposes. The bonding layer 118 can be made of: oxides, such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxides, titanium oxide, etc.; or nitrides, such as silicon nitride, silicon oxynitride, silicon carbonitride, aluminum nitride, which can be formed by suitable deposition processes such as CVD, ALD, etc. The bonding pad 120 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The bonding pad 120 may be formed of a metal, such as copper, aluminum, etc., which may be formed by plating, etc. In some embodiments, a planarization process, such as a CMP process, a grinding process, an etch-back process, a combination thereof, etc., is performed on the bonding layer 118 and the bonding pad 120. After the planarization process, the top surfaces of the bonding layer 118 and the bonding pad 120 may be substantially coplanar or flush (within the process variation range).

[0023] exist FIG. 4A to FIG. 4C , an upper integrated circuit die 200 is shown. Figure 4A The cross-sectional view of the upper integrated circuit die 200 shown in FIG. Figure 4C The top view of the upper integrated circuit die 200 shown in FIG. 2 is obtained by referring to the reference cross section AA′. Figure 4B The cross-sectional view of the upper integrated circuit die 200 shown in FIG. Figure 4C The reference cross section BB′ shown in the top view of the upper integrated circuit die 200 is obtained.

[0024] The upper integrated circuit die 200 may be a logic die (e.g., a CPU, a GPU, a SoC, an AP, a microcontroller, etc.), a memory die (e.g., a DRAM die, an SRAM die, etc.), a power management die (e.g., a PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., a DSP die), a front-end die (e.g., an AFE die), etc., or a combination thereof. The materials and manufacturing processes of the components in the upper integrated circuit die 200 may be the same or similar to those of the similar components in the lower integrated circuit die 100. The upper integrated circuit die 200 may include a semiconductor substrate 202, which may have an active surface (e.g., a front side) that may be referred to as a front side. Figure 4A and Figure 4B The surface facing downward in the middle) and the inactive surface which can be called the back side (e.g. Figure 4A and Figure 4BThe back side of the semiconductor substrate 202 may also be referred to as the back side of the upper integrated circuit die 200 , and the front side of the semiconductor substrate 202 may face the front side of the upper integrated circuit die 200 .

[0025] Devices (not shown separately) may be disposed at the active surface of the semiconductor substrate 202. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The devices may generate a large amount of heat during operation of the upper integrated circuit die 200, and may generate hot spots in the upper integrated circuit die 200. An interconnect structure 204 may be disposed on the active surface of the semiconductor substrate 202. The interconnect structure 204 may interconnect the devices to form an integrated circuit. The interconnect structure 204 may include a metallization pattern (not shown separately) in a dielectric layer (not shown separately). The metallization pattern may be electrically coupled to the device. A seal ring 205 may extend through the interconnect structure 204 of the upper integrated circuit die 200. In a top view, the seal ring 205 may surround the metallization pattern of the corresponding interconnect structure 204. The seal ring 205 may be formed of the same or similar material as the metallization pattern and by the same or similar process as the metallization pattern. The seal ring 205 may be electrically isolated from the device.

[0026] A bonding layer 208 may be disposed on the interconnect structure 204 at the front side of the upper integrated circuit die 200. One or more passivation layers (not separately shown) may be disposed between the bonding layer 208 and the interconnect structure 204. The bonding layer 208 may include the same or similar material as the bonding layer 118. The bonding pads 210 may extend through the bonding layer 208 and may be electrically coupled to the metallization pattern of the interconnect structure 204. External connections to the upper integrated circuit die 200 may be made through the bonding pads 210. The bonding pads 210 may include the same or similar material as the bonding pads 120.

[0027] The channel 207 may be disposed on the back side of the semiconductor substrate 202. The channel 207 may be an opening through which a coolant fluid may flow to dissipate heat generated in the upper integrated circuit die 200 during operation, as described in more detail below. For purposes of illustration, the channel 207 may be disposed on the back side of the semiconductor substrate 202. The channel 207 may be an opening through which a coolant fluid may flow to dissipate heat generated in the upper integrated circuit die 200 during operation, as described in more detail below. Figure 4C It is shown by a dotted line. Figure 4B and Figure 4C As shown in FIG. 2 , the channel 207 may extend in parallel from one sidewall to an opposite sidewall through the semiconductor substrate 202. The channel 207 may be formed in the semiconductor substrate 202 by a suitable photolithography process. Figure 4A , Figure 4B and Figure 4CThe number and arrangement of channels 207 in FIG. 2 are provided as examples. Other numbers and arrangements of channels 207 are also contemplated. A cap 209 may be disposed on the back side of the semiconductor substrate 202 and cover the channels 207. The cap 209 may be bonded to the semiconductor substrate 202 by an adhesive (not separately shown), such as a TIM, etc. The cap 209 may be formed of the same or similar material as the semiconductor substrate 202.

[0028] exist Figure 5 In the embodiment, the upper integrated circuit die 200 is bonded to the bonding layer 118 and the bonding pad 120 , and an upper gap-fill layer 211 is formed around the upper integrated circuit die 200 . Figure 5 The layout of the upper integrated circuit die 200 on the bonding layer 118 shown in is provided as an example. Other layouts of the upper integrated circuit die 200 are contemplated. The upper integrated circuit die 200 can be bonded to the bonding layer 118 and the bonding pads 120 by: placing the upper integrated circuit die 200 using a pick and place process, etc.; and then bonding the upper integrated circuit die 200 to the bonding layer 118 and the bonding pads 120. The bonding layer 208 of the upper integrated circuit die 200 can be directly bonded to the bonding layer 118 by dielectric-to-dielectric bonding, and the bonding pads 210 of the upper integrated circuit die 200 can be directly bonded to the corresponding bonding pads 120 by metal-to-metal bonding. Figure 5 In the embodiment shown in , the size (eg, width) of the bonding pad 210 is the same as or similar to the corresponding bonding pad 120. In some embodiments, the size (eg, width) of the bonding pad 210 is smaller than the corresponding bonding pad 120.

[0029] The bonding process may include a pre-bonding process and an annealing process. During the pre-bonding process, a small pressure may be applied to press the upper integrated circuit die 200 against the bonding layer 118 and the bonding pad 120. The pre-bonding process may be implemented at low temperatures, such as room temperature. After the pre-bonding process, a direct bond, such as a dielectric to dielectric bond, may be formed between the bonding layer 208 and the bonding layer 118. The bonding strength between the bonding layer 208 and the bonding layer 118 may then be improved in a subsequent annealing process at a higher temperature. The bonding pad 210 may contact the bonding pad 120 after the pre-bonding process, or may expand to begin to contact the bonding pad 120 during the annealing process. During the annealing process, the material of the bonding pad 210 may be mixed or bonded with the material of the bonding pad 120, thereby forming a metal to metal bond. After the bonding process, the upper integrated circuit die 200 may be electrically coupled to the lower integrated circuit die 100 through the bonding pad 120.

[0030] In the top view, the upper gap filling layer 211 may surround the upper integrated circuit die 200. The upper gap filling layer 211 may extend along the sidewalls of the upper integrated circuit die 200 (including the semiconductor substrate 202, the interconnect structure 204, and the bonding layer 208). The upper gap filling layer 211 may be formed by the same or similar method as the lower gap filling layer 116 and by the same or similar dielectric material as the lower gap filling layer 116. A thinning process may be performed to remove a portion of the upper gap filling layer 211 and expose the cap 209. The thinning process may be a CMP process, a grinding process, an etch-back process, a combination thereof, or the like. After the thinning process, the top surfaces of the upper gap filling layer 211 and the cap 209 may be substantially coplanar or flush (within the process variation range).

[0031] Figure 5 A front-to-back bonding configuration is shown as an example, wherein, after bonding, the back side of the lower integrated circuit die 100 faces the front side of the upper integrated circuit die 200. Other bonding configurations may be used, such as a front-to-front bonding configuration or other bonding configurations. In a front-to-front bonding configuration, the front side of the lower integrated circuit die 100 may face the front side of the upper integrated circuit die 200.

[0032] exist Figure 6 , carrier 212 is bonded to the top surface of the upper integrated circuit die 200 and the upper gap filling layer 211. Carrier 212 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. Carrier 212 may be a wafer having the same or similar size as carrier 112. In some embodiments, carrier 212 is bonded to the upper integrated circuit die 200 and the upper gap filling layer 211 using bonding layers 213 and 214. Bonding layer 213 may be formed on cap 209 and upper gap filling layer 211, and bonding layer 214 may be formed on carrier 212. Bonding layer 213 and bonding layer 214 may each include a dielectric material, such as silicon dioxide, etc., and may be formed by a suitable deposition process such as CVD, ALD, etc. The structure above carrier 112 may be formed by a process for bonding a dielectric die 200 and an upper gap filling layer 211. Figure 5 The same or similar processes described for bonding layer 118 and bonding layer 208 are bonded to carrier 212 by bonding bonding layer 213 and bonding layer 214 .

[0033] exist Figure 7 In the process, the carrier 112 and the adhesive 114 are removed, and a dielectric layer 216 is formed on the lower gap fill layer 116 and the lower integrated circuit die 100. The removal process may include projecting a light beam (such as a laser beam or a UV beam) onto the adhesive 114 ( Figure 6) on the lower gap fill layer 116 so that the adhesive 114 can be decomposed when exposed to the light beam and the carrier 112 can be removed. In some embodiments, the dielectric layer 216 includes PBO, polyimide, BCB-based polymer, etc., and is formed by a suitable coating process such as spin coating, lamination, etc. In some embodiments, the dielectric layer 216 includes silicon dioxide, silicon nitride, etc., and is formed by a suitable deposition process such as CVD, ALD, etc. In some embodiments, before forming the dielectric layer 216, a redistribution structure (not separately shown) can be formed on the lower gap fill layer 116 and the lower integrated circuit die 100 to provide additional wiring.

[0034] exist Figure 8 In the process, an under bump metallization (UBM) 218 ​​and electrical connections 220 are formed. Figure 8 The structure shown in FIG. 2 may be referred to as wafer structure 250. UBM 218 may have a portion extending along the surface of dielectric layer 216 and a portion extending through dielectric layer 216 to be physically and electrically coupled to conductive pad 110. Thus, UBM 218 is electrically coupled to lower integrated circuit die 100. External connections to lower integrated circuit die 100 may be made through electrical connector 220.

[0035] In order to form UBM 218, dielectric layer 216 may first be patterned to form an opening that exposes conductive pad 110 below. Patterning may be accomplished by a suitable photolithography process, such as forming a mask and then performing anisotropic etching. The mask may be removed after patterning. A seed layer (not shown separately) may be formed on dielectric layer 216, in an opening through dielectric layer 216, and on an exposed portion of conductive pad 110. The seed layer may be formed using a suitable deposition process, such as physical vapor deposition (PVD), etc. A photoresist may then be formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist may correspond to UBM 218. Patterning may form an opening through the photoresist to expose the seed layer.

[0036] Conductive material may be formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as chemical plating, electroplating, etc. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed may then be removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the portion of the seed layer on which the conductive material is not formed may be removed by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material may form the UBM 218.

[0037] An electrical connector 220 may be formed on the UBM 218. The electrical connector 220 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel plating-electroless palladium plating-immersion gold technology (ENEPIG), etc. In some embodiments, the electrical connector 220 includes a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. The electrical connector 220 may be formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow may be implemented to shape the solder into a desired bump shape. In some embodiments, the electrical connector 220 includes a metal column, such as a copper column, formed by sputtering, printing, electroplating, chemical plating, CVD, etc., which has no solder and has substantially vertical sidewalls. A metal capping layer may be formed on the top of the metal column.

[0038] exist Fig. 9 In the embodiment of the present invention, the wafer structure 250 is divided to form independent integrated circuit package components 250'. The processes discussed above can be implemented using wafer level processing. The carrier 212 can be a wafer and can include a similar Figure 8 20 '. The wafer structure 250 may be placed on a belt 222 supported by a frame 224. The wafer structure 250 may then be segmented along the scribe lines 226 so that the wafer structure 250 may be separated into discrete integrated circuit package components 250'. After the segmentation process, the channel 107 in the semiconductor substrate 102 and the channel 207 in the semiconductor substrate 202 may be exposed again on the corresponding sidewalls of the semiconductor substrate 102 and the semiconductor substrate 202, as described in more detail below. The segmentation process may include a sawing process, a laser cutting process, and the like. Additional removal processes, such as etching, and the like may be implemented to remove excess lower gap filling layer 116 and / or excess upper gap filling layer 211 that may block the channel 107 and / or the channel 207. After the segmentation process, a cleaning process or a rinsing process may be implemented.

[0039] exist Fig.10, the integrated circuit package assembly 250' is bonded to the package substrate 228, and the bottom filler 234 is formed between the integrated circuit package assembly 250' and the package substrate 228. The package substrate 228 may include a body 229, a conductive pad 230, a conductive pad 232, and an electrical connector 233. The package substrate 228 may also include a conductive component (not shown separately) that electrically couples the conductive pad 230 and the conductive pad 232. In some embodiments, the body 229 includes a material such as a glass fiber reinforced resin, a bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials, etc. In some embodiments, the body 229 includes a material such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, etc. The electrical connector 233 may be made of the same or similar material as the electrical connector 220 and formed by the same or similar process as the electrical connector 220. External connections to the package substrate 228 may be made through the electrical connector 220.

[0040] In some embodiments, package substrate 228 includes active and / or passive devices (not shown separately), such as transistors, capacitors, resistors, combinations thereof, etc., and metallization layers (not shown separately) electrically couple the active and / or passive devices to conductive pads 230 and conductive pads 232. The metallization layers may be alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers. In some embodiments, package substrate 228 is free of active and / or passive devices.

[0041] During the bonding process, the electrical connector 220 can be reflowed to bond the integrated circuit package assembly 250' to the conductive pad 230. The electrical connector 220 can physically and electrically couple the package substrate 228 to the integrated circuit package assembly 250'. In some embodiments, a solder resist (not shown separately) is formed on the package substrate 228. The electrical connector 220 can be disposed in an opening in the solder resist to be physically and electrically coupled to the conductive pad 230. The solder resist can be used to protect the area of ​​the package substrate 228 from external damage. The bottom filler 234 can surround the electrical connector 220 and protect the joints generated by the reflow of the electrical connector 220. In the top view, the bottom filler 234 can surround the integrated circuit package assembly 250'. The bottom filler 234 can be formed by a capillary flow process after attaching the integrated circuit package assembly 250', or by a suitable deposition method before bonding the integrated circuit package assembly 250'. The bottom filler 234 can then be cured.

[0042] exist Fig.11In the embodiment of the present invention, the bonding layers 213 and 214 are removed, and an adhesive layer 236 is formed on the upper gap filling layer 211 and the upper integrated circuit die 200. The bonding layers 213 and 214 can be removed by a CMP process, a grinding process, an etch-back process, a combination thereof, etc. The adhesive layer 236 can be used to bond the cap to the upper gap filling layer 211 and the upper integrated circuit die 200. Fig.11 , while dissipating heat generated by the upper integrated circuit die 200 and the lower integrated circuit die 100 during operation to the cover. The adhesive layer 236 may include a thermal interface material (TIM), which may be a material with high thermal conductivity, such as thermal paste, gel-based thermal adhesive, graphite, graphene film, etc., or a combination thereof.

[0043] exist Fig. 12A , Fig. 12B and Fig. 12C , a stiffener ring 238 is attached to the package substrate 228 . Fig. 12A , Fig. 12B and Fig. 12C The structure shown in FIG. 3 may be referred to as an integrated circuit package assembly 300 . Fig. 12A The cross-sectional view of the integrated circuit package assembly 300 shown in FIG. Fig. 12C The top view of the integrated circuit package assembly 300 is shown in reference cross section AA′. Fig. 12B The cross-sectional view of the integrated circuit package assembly 300 shown in FIG. Fig. 12C The top view of the integrated circuit package assembly 300 shown in FIG. 2 is obtained by referring to the reference cross section BB'. For illustration purposes, the upper integrated circuit die 200 is Fig. 12C Shown by dotted lines.

[0044] The reinforcement ring 238 can be used to provide additional support to the package substrate 228 during subsequent manufacturing processes to reduce warping or other types of deformation of the package substrate 228. The reinforcement ring 238 can also be used to provide support to a cover that can be attached to the integrated circuit package assembly 300 in a subsequent process. The reinforcement ring 238 can be formed of a material with a large hardness, such as a metal, a metal alloy, etc. The reinforcement ring 238 can be attached to the package substrate 228 by an adhesive 240 (such as epoxy resin, glue, etc.). Fig. 12B As shown in , in the integrated circuit package assembly 300, the channel 107 in the semiconductor substrate 102 of the lower integrated circuit die 100 and the channel 207 in the semiconductor substrate 202 of the upper integrated circuit die 200 can be exposed on corresponding sidewalls of the semiconductor substrate 102 and the semiconductor substrate 202. The channel 107 and the channel 207 can be connected to corresponding channels in a cover, and the cover can be attached to the integrated circuit package assembly 300 in a subsequent process, as described in more detail below.

[0045] exist Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E , the cover 244 is attached to the integrated circuit package assembly 300 . Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E The structure shown in 350 may be referred to as an integrated circuit package 350 . Fig.13A The cross-sectional view of the integrated circuit package 350 shown in FIG. Fig.13E The reference cross section AA′ shown in the top view of the integrated circuit package 350 is obtained. Fig. 13B The cross-sectional view of the integrated circuit package 350 shown in FIG. Fig.13E The reference cross section BB′ shown in the top view of the integrated circuit package 350 is obtained. Fig. 13C The cross-sectional view of the integrated circuit package 350 shown in FIG. Fig.13E The reference cross section CC′ shown in the top view of the integrated circuit package 350 is obtained. Fig.13D The cross-sectional view of the integrated circuit package 350 shown in FIG. Fig.13E The top view of the integrated circuit package 350 in FIG. 3 is shown in FIG. 3 . For illustration purposes, the upper integrated circuit die 200 is Fig.13E Shown by dotted lines.

[0046] The cover 244 may include a top portion 244A and two bottom portions 244B. The top portion 244A may be attached to the upper integrated circuit die 200 and the upper gap fill layer 211 by an adhesive layer 236, and to the stiffening ring 238 by an adhesive 242 (such as epoxy, glue, etc.). The bottom portion 244B may protrude from the bottom surface of the top portion 244A and extend along the sidewalls of the upper integrated circuit die 200 (including the sidewalls of the semiconductor substrate 202) and the sidewalls of the lower integrated circuit die 100 (including the sidewalls of the semiconductor substrate 102). Fig. 13B and Fig.13D In the embodiment shown in , the bottom portion 244B contacts the sidewalls of the upper integrated circuit die 200 and the sidewalls of the lower integrated circuit die 100 .

[0047] The cover 244 may include a top channel 246A in the top portion 244A and a bottom channel 246B in the bottom portion 244B. The top channel 246A and the bottom channel 246B may be openings through which coolant fluid may flow to flow to the channel 107 of the lower integrated circuit die 100 and the channel 207 of the upper integrated circuit die 200, as described in more detail below. For purposes of illustration, the top channel 246A is Fig.13EFor the purpose of illustration, channels 107 and 207 are shown in dashed lines. Fig. 13C It is shown by a dotted line. Fig.13A , Fig. 13B , Fig. 13C and Fig.13D As shown in , the top channel 246A can extend horizontally in the top portion 244A of the cover 244. Fig.13E As shown in , each top channel 246A may have a double dagger shape with a main portion extending through the top portion 244A and side portions extending along the sidewalls of the upper integrated circuit die 200 .

[0048] like Fig. 13B , Fig. 13C and Fig.13D As shown in , each bottom channel 246B may have an inverted "F" shape and may extend vertically and horizontally in the bottom portion 244B of the cover 244. The vertical portion of the bottom channel 246B may be connected to the top channel 246A. The horizontal portion of the bottom channel 246B may extend through the inner sidewall of the bottom portion 244B and may be connected to the channel 107 of the lower integrated circuit die 100 and the channel 207 of the upper integrated circuit die 200. Fig. 13B , Fig. 13C and Fig.13D In the embodiment shown in , the number of bottom channels 246B may correspond to the total number of channels 107 and the total number of channels 207 , and each bottom channel 246B is connected to channel 107 and channel 207 .

[0049] The cover 244 may be formed of a metal or metal alloy, such as copper, stainless steel, etc. The top channel 246A and the bottom channel 246B may be formed by a suitable machining process. The cross section of the main portion or side portion of the top channel 246A may be a rectangle having a height H1 in the range of from about 5 mm to about 30 mm and a width W1 in the range of from about 5 mm to about 30 mm. The cross section of the vertical portion of the bottom channel 246B may be a rectangle having a height H2 in the range of from about 1 μm to about 100 μm and a width W2 in the range of from about 1 μm to about 100 μm. In some embodiments, the height H1 is greater than the height H2, and the width W1 is greater than the width W2. In some embodiments, the shape and size of the cross section of each horizontal portion of the bottom channel 246B is the same or similar to the shape and size of the cross section of the corresponding channel 107 or channel 207.

[0050] Fig. 13B and Fig.13DAn example of a flow path of a coolant fluid during operation of the integrated circuit package 350 is shown. The coolant fluid can flow from one end of each top channel 246A into the top portion 244A of the lid 244. The coolant fluid can flow through the main portion of the top channel 246A and out of the top portion 244A from the other end of the top channel 246A, and the heat transferred from the lower integrated circuit die 100 and the upper integrated circuit die 200 to the bonding layer 236 can be dissipated to the coolant fluid. The coolant fluid can also flow directly down to the bottom channel 246B connected to the main portion of the top channel 246A, or first flow into the side portion of the top channel 246A and then flow down to the bottom channel 246B connected to the side portion of the top channel 246A. Such a bottom channel 246B can be located in a bottom portion 244B of the lid 244. The coolant fluid may then flow through the corresponding channels 107 and 207 connected to the bottom channel 246B, and the heat generated in the lower integrated circuit die 100 and the upper integrated circuit die 200 may be dissipated to the coolant fluid. Thereafter, the coolant fluid may flow to the bottom channel 246B in the other bottom portion 244B of the cover 244, and flow back to the top channel 246A before flowing out of the top portion 244A.

[0051] Because the coolant fluid flowing through the bottom channel 246B, the channel 107, and the channel 207 is closer to the hot spots (e.g., devices) in the lower integrated circuit die 100 and the upper integrated circuit die 200, the heat generated in the lower integrated circuit die 100 and the upper integrated circuit die 200 can be more effectively dissipated during operation of the integrated circuit package 350, thereby improving the heat dissipation of the integrated circuit package 350. Therefore, the performance and reliability of the integrated circuit package 350 can be improved.

[0052] Fig.14A and Fig. 14B shows a method similar to that of Fig. 13B and Fig. 13C , wherein the same components refer to the same components formed by the same process. In the integrated circuit package 360, the cover 244 can include one or more pumps 252, such as an electrohydrodynamic (EHD) pump, in the top channel 246A and / or the bottom channel 246B. The pump 252 can promote the flow of the coolant fluid in the top channel 246A and / or the bottom channel 246B. The pump 252 can be powered by an external power source (not shown separately).

[0053] exist Fig.14A and Fig. 14BIn the embodiment shown in , pump 252 is an EHD pump, each of the pumps includes an electrode 252A and an electrode 252B, and the coolant fluid is a fluid including ions, such as water. An electric field can be generated between electrode 252A and electrode 252B, which can drive the flow of ionized coolant fluid in bottom channel 246B. Electrode 252A and electrode 252B can be electrically isolated from cover 244. As an example, Fig.14A and Fig. 14B One pump 252 is shown disposed in each bottom channel 246B. In some embodiments, more than one pump 252 may be disposed in each bottom channel 246B. Fig. 14C A top view of electrode 252A is shown with a portion of electrode 252A surrounding bottom portion 244B of cover 244. Electrode 252A may have the shape of a frame or ring with an opening in the center, which may be part of bottom channel 246B. Electrode 252A and electrode 252B may have the same or similar size and shape.

[0054] Fig.15A and Fig. 15B shows a diagram similar to Fig. 13B and Fig.13D , wherein the same components refer to the same components formed by the same process. In the integrated circuit package 370, the bottom portion 244B is bonded to the sidewalls of the upper integrated circuit die 200 and the sidewalls of the lower integrated circuit die 100 by the adhesive 248, and the adhesive 248 may include the same or similar material as the adhesive layer 236. Fig.14A , Fig. 14B and Fig. 14C The discussed pump 252 , such as an EHD pump, may also be added to the top channel 246A and / or the bottom channel 246B of the lid 244 in the integrated circuit package 370 .

[0055] Various embodiments are described above in the context of a system-on-integrated-chip (SoIC) packaging configuration. It should be understood that various embodiments may also be suitable for use in other packaging configurations, such as integrated fan-out on substrate (InFO), chip-on-wafer-on-substrate (CoWoS), etc.

[0056] Embodiments may have some advantageous features. By using a cover 244 including a top channel 246A and a bottom channel 246B in an integrated circuit package 350, heat generated in the lower integrated circuit die 100 and the upper integrated circuit die 200 may be more effectively dissipated during operation of the integrated circuit package 350, thereby improving heat dissipation of the integrated circuit package 350. Therefore, the performance and reliability of the integrated circuit package 350 may be improved.

[0057] In an embodiment, an integrated circuit package includes: a first die located above a packaging substrate, wherein the first die includes a first substrate, and wherein a first channel extends through the first substrate from a first sidewall of the first die to a second sidewall of the first die; and a cover including: a top portion located above the first die; and a first bottom portion extending along the first sidewall of the first die, wherein the first bottom portion includes a second channel, and wherein the second channel is connected to the first channel. In an embodiment, the top portion of the cover also includes a third channel, and wherein the third channel is connected to the second channel. In an embodiment, the third channel has a greater width than the second channel. In an embodiment, the cover also includes a second bottom portion extending along the second sidewall of the first die, wherein the second bottom portion includes a third channel, and wherein the third channel is connected to the first channel. In an embodiment, the integrated circuit package also includes: a second die located between the first die and the packaging substrate, wherein the second die is electrically connected to the first die and the packaging substrate, wherein the second die includes a second substrate, wherein the third channel extends through the second substrate from the first sidewall of the second die to the second sidewall of the second die, and wherein the first bottom portion of the cover extends along the first sidewall of the second die. In an embodiment, the second channel is connected to the third channel. In an embodiment, the cover further comprises an electrohydrodynamic (EHD) pump located in the second channel.

[0058] In an embodiment, an integrated circuit package includes: a first die located above a package substrate, wherein the first die includes a first substrate; and a cover including: a top portion located above the first die; a first bottom portion extending along a first sidewall of the first die, wherein the first bottom portion includes a first fluid channel; and a second bottom portion extending along a second sidewall of the first die, wherein the second sidewall of the first die is opposite to the first sidewall of the first die, and wherein the second bottom portion includes a second fluid channel. In an embodiment, the top portion of the cover also includes a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel. In an embodiment, the first substrate includes a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel. In an embodiment, the first die also includes a first cover located between the first substrate and the cover, and wherein the third fluid channel is located between a bottom surface of the first cover and an upper surface of the first substrate. In an embodiment, the integrated circuit package further comprises a second die located between the first die and the package substrate, wherein the second die is electrically connected to the first die and the package substrate, wherein the second die comprises a second substrate, wherein a first bottom portion of the cover extends along a first sidewall of the second die, wherein a second bottom portion of the cover extends along a second sidewall of the second die, and wherein the second sidewall of the second die is opposite to the first sidewall of the second die. In an embodiment, the second substrate comprises a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel. In an embodiment, the first bottom portion of the cover is bonded to the first sidewall of the first die by an adhesive.

[0059] In an embodiment, a method of forming an integrated circuit package includes: bonding a first die to a package substrate; attaching a stiffening ring to the package substrate, wherein the stiffening ring surrounds the first die in a top view; and attaching a cover to the stiffening ring, the cover including: a top portion located above the first die, wherein the top portion of the cover also includes a first fluid channel; a first bottom portion protruding from a bottom surface of the top portion, wherein the first bottom portion extends along a first sidewall of the first die, wherein the first bottom portion includes a second fluid channel; and a second bottom portion protruding from a bottom surface of the top portion, wherein the second bottom portion extends along a second sidewall of the first die, wherein the second sidewall of the first die is opposite to the first sidewall of the first die, and wherein the second bottom portion includes a third fluid channel. In an embodiment, the first fluid channel is connected to the second fluid channel and the third fluid channel. In an embodiment, the first die includes a first substrate, wherein a fourth fluid channel extends through the first substrate, and wherein the fourth fluid channel is connected to the second fluid channel and the third fluid channel. In an embodiment, the method further comprises: bonding a second die over the first die before attaching the cover, wherein the first die electrically connects the second die and the package substrate, wherein a first bottom portion of the cover extends along a first sidewall of the second die, wherein a second bottom portion of the cover extends along a second sidewall of the second die, wherein the second sidewall of the second die is opposite to the first sidewall of the second die. In an embodiment, the first die comprises a first substrate and the second die comprises a second substrate, wherein a fourth fluid channel extends through the first substrate and a fifth fluid channel extends through the second substrate, wherein the second fluid channel is connected to the fourth fluid channel and the fifth fluid channel, and wherein the third fluid channel is connected to the fourth fluid channel and the fifth fluid channel. In an embodiment, the cover further comprises one or more electrohydrodynamic (EHD) pumps located in the second fluid channel and one or more EHD pumps located in the third fluid channel.

[0060] Some embodiments of the present application provide an integrated circuit package, comprising: a first die located above a packaging substrate, wherein the first die includes a first substrate, and wherein a first channel extends through the first substrate from a first side wall of the first die to a second side wall of the first die; and a cover, comprising: a top portion located above the first die; and a first bottom portion extending along the first side wall of the first die, wherein the first bottom portion includes a second channel, and wherein the second channel is connected to the first channel.

[0061] In some embodiments, the top portion of the cover further comprises a third channel, and wherein the third channel is connected to the second channel. In some embodiments, the third channel has a width greater than the second channel. In some embodiments, the cover further comprises a second bottom portion extending along the second sidewall of the first die, wherein the second bottom portion comprises a third channel, and wherein the third channel is connected to the first channel. In some embodiments, the integrated circuit package further comprises: a second die located between the first die and the package substrate, wherein the second die is electrically connected to the first die and the package substrate, wherein the second die comprises a second substrate, wherein the third channel extends through the second substrate from the first sidewall of the second die to the second sidewall of the second die, and wherein the first bottom portion of the cover extends along the first sidewall of the second die. In some embodiments, the second channel is connected to the third channel. In some embodiments, the cover further comprises an electrohydrodynamic (EHD) pump located in the second channel.

[0062] Some other embodiments of the present application provide an integrated circuit package, comprising: a first die located above a package substrate, wherein the first die includes a first substrate; and a cover, comprising: a top portion located above the first die; a first bottom portion extending along a first sidewall of the first die, wherein the first bottom portion includes a first fluid channel; and a second bottom portion extending along a second sidewall of the first die, wherein the second sidewall of the first die is opposite to the first sidewall of the first die, and wherein the second bottom portion includes a second fluid channel. In some embodiments, the top portion of the cover also includes a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel. In some embodiments, the first substrate includes a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel. In some embodiments, the first die also includes a first cover located between the first substrate and the cover, and wherein the third fluid channel is located between a bottom surface of the first cover and an upper surface of the first substrate. In some embodiments, the integrated circuit package further comprises: a second die located between the first die and the package substrate, wherein the second die is electrically connected to the first die and the package substrate, wherein the second die comprises a second substrate, wherein the first bottom portion of the cover extends along a first sidewall of the second die, wherein the second bottom portion of the cover extends along a second sidewall of the second die, and wherein the second sidewall of the second die is opposite to the first sidewall of the second die. In some embodiments, the second substrate comprises a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel. In some embodiments, the first bottom portion of the cover is bonded to the first sidewall of the first die by an adhesive.

[0063] Still other embodiments of the present application provide a method for forming an integrated circuit package, the method comprising: bonding a first die to a package substrate; attaching a reinforcement ring to the package substrate, wherein the reinforcement ring surrounds the first die in a top view; and attaching a cover to the reinforcement ring, the cover comprising: a top portion located above the first die, wherein the top portion of the cover also includes a first fluid channel; a first bottom portion protruding from a bottom surface of the top portion, wherein the first bottom portion extends along a first side wall of the first die, wherein the first bottom portion includes a second fluid channel; and a second bottom portion protruding from the bottom surface of the top portion, wherein the second bottom portion extends along a second side wall of the first die, wherein the second side wall of the first die is opposite to the first side wall of the first die, and wherein the second bottom portion includes a third fluid channel.

[0064] In some embodiments, the first fluid channel is connected to the second fluid channel and the third fluid channel. In some embodiments, the first die comprises a first substrate, wherein a fourth fluid channel extends through the first substrate, and wherein the fourth fluid channel is connected to the second fluid channel and the third fluid channel. In some embodiments, the method further comprises: bonding a second die over the first die before attaching the cover, wherein the first die electrically connects the second die and the package substrate, wherein the first bottom portion of the cover extends along a first sidewall of the second die, wherein the second bottom portion of the cover extends along a second sidewall of the second die, wherein the second sidewall of the second die is opposite to the first sidewall of the second die. In some embodiments, the first die comprises a first substrate, and the second die comprises a second substrate, wherein a fourth fluid channel extends through the first substrate, and a fifth fluid channel extends through the second substrate, wherein the second fluid channel is connected to the fourth fluid channel and the fifth fluid channel, and wherein the third fluid channel is connected to the fourth fluid channel and the fifth fluid channel. In some embodiments, the cover further comprises one or more electrohydrodynamic (EHD) pumps located in the second fluid channel and one or more electrohydrodynamic pumps located in the third fluid channel.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated circuit package, comprising: a first die located above the package substrate, wherein the first die includes a first substrate, and wherein the first channel extends through the first substrate from a first sidewall of the first die to a second sidewall of the first die; and Cover, including: a top portion located above the first die; and A first bottom portion extends along the first sidewall of the first die, wherein the first bottom portion includes a second channel, and wherein the second channel is connected to the first channel.

2. The integrated circuit package according to claim 1, wherein: The top portion of the cover further includes a third channel, and wherein the third channel is connected to the second channel.

3. The integrated circuit package according to claim 2, wherein: The third channel has a greater width than the second channel.

4. The integrated circuit package according to claim 1, wherein: The cover also includes a second bottom portion extending along the second sidewall of the first die, wherein the second bottom portion includes a third channel, and wherein the third channel is connected to the first channel.

5. The integrated circuit package of claim 1 , further comprising: A second die is located between the first die and the packaging substrate, wherein the second die is electrically connected to the first die and the packaging substrate, wherein the second die includes a second substrate, wherein a third channel extends through the second substrate from a first side wall of the second die to a second side wall of the second die, and wherein the first bottom portion of the cover extends along the first side wall of the second die.

6. The integrated circuit package according to claim 5, wherein: The second channel is connected to the third channel.

7. The integrated circuit package according to claim 1, wherein: The cover also includes an electrohydrodynamic pump located in the second passage.

8. An integrated circuit package, comprising: A first die located above the package substrate, wherein the first die includes a first substrate; and Cover, including: a top portion located above the first tube core; a first bottom portion extending along a first sidewall of the first die, wherein the first bottom portion includes a first fluid channel; and A second bottom portion extends along a second sidewall of the first die, wherein the second sidewall of the first die is opposite to the first sidewall of the first die, and wherein the second bottom portion includes a second fluid channel.

9. The integrated circuit package according to claim 8, wherein: The top portion of the cover further includes a third fluid channel, and wherein the third fluid channel connects the first fluid channel and the second fluid channel.

10. A method of forming an integrated circuit package, the method comprising: bonding the first die to a package substrate; attaching a stiffener ring to the package substrate, wherein the stiffener ring surrounds the first die in a top view; and A cover is attached to the reinforcement ring, the cover comprising: a top portion located above the first die, wherein the top portion of the cover further comprises a first fluid channel; a first bottom portion protruding from a bottom surface of the top portion, wherein the first bottom portion extends along a first sidewall of the first die, wherein the first bottom portion includes a second fluid channel; and A second bottom portion protrudes from the bottom surface of the top portion, wherein the second bottom portion extends along a second sidewall of the first tube core, wherein the second sidewall of the first tube core is opposite to the first sidewall of the first tube core, and wherein the second bottom portion includes a third fluid channel.

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