Output complementary PWM (Pulse Width Modulation) wave circuit with dead zone setting and implementation method thereof

Abstract

The invention relates to an output complementary PWM (Pulse Width Modulation) wave circuit with dead zone setting and an implementation method thereof, and relates to the field of electronic information. According to the technical scheme, complementary PWM wave output can be realized by adopting a common MCU without depending on special IO resource or software dead zone configuration, so that the occupation of MCU resources is greatly reduced; different PWM frequency requirements can be flexibly matched by adjusting the proportion of the divider resistor R2, the divider resistor R3 and the divider resistor R4, and accurate control over hardware-level dead time is achieved; based on a pure hardware architecture of resistance voltage division, a half-bridge driving scheme with high cost performance is formed in combination with low-cost MCU model selection, and compared with a traditional method depending on MCU software to configure a dead zone, the half-bridge driving circuit has remarkable advantages in the aspects of resource consumption, cost control and application flexibility.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to an output complementary PWM wave circuit with a built-in dead zone setting and an implementation method thereof. Background Art

[0002] In the field of circuit design of modern electronic devices, PWM waves (pulse width modulation waves) are widely used, especially in scenarios such as full-bridge circuits that require precise power control. Most of the existing output complementary PWM wave solutions with built-in dead zone settings rely on the relevant functions of the MCU (microcontroller). Among them, the PWM complementary output function of the MCU seems convenient, but it has many disadvantages. It usually takes up two pins of the MCU, and in a complex circuit system, the pin resources of the MCU are already very precious. When occupied in this way, it will greatly limit the expansion of other functions. For example, in an intelligent control system that integrates a variety of sensors and actuators, the shortage of pin resources may make it impossible to connect more necessary devices. At the same time, the setting of the dead time also depends on the MCU, which further consumes the computing resources of the MCU, so that the MCU needs to be distracted by the dead zone setting while processing other key tasks, reducing the overall operating efficiency.

[0003] In the application of full-bridge circuits, due to the requirement for precise control of PWM waves, high-end MCUs are often used. Such MCUs are not only expensive, which greatly increases the cost of the product, but also have a lot of functions that are redundant for circuits that only need to implement simple PWM wave output and dead zone settings, resulting in a waste of resources.

[0004] In terms of voltage divider circuit applications, existing voltage divider circuits, whether using chip output or voltage regulator output, will occupy a large PCB area. In the current pursuit of miniaturization and integration, this is undoubtedly a serious problem, limiting the compact design of the product. In addition, the cost of existing voltage divider circuits is also relatively high, further increasing the cost burden of the product and reducing the competitiveness of the product in the market. Summary of the invention

[0005] The purpose of the present invention is to provide an output complementary PWM wave circuit with built-in dead zone setting and an implementation method thereof, so as to solve the problems existing in the above-mentioned prior art.

[0006] To achieve the above object, the technical solution adopted by the present invention is: In a first aspect, the present invention provides an output complementary PWM wave circuit with a built-in dead zone setting, comprising a comparison circuit and a voltage divider circuit connected to each other; The comparison circuit comprises: A resistor R1, a first end of which is connected to the PWM output end of the microcontroller MCU, and a second end of which is respectively connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2; The voltage divider circuit comprises: A resistor R2, a first end of which is connected to an output end of a low voltage drop linear regulator LDO; a resistor R3, a first end of which is connected to the second end of the resistor R2; and a resistor R4, a first end of which is connected to the second end of the resistor R3, and a second end of which is connected to GND; The cathode of the first comparator U1 is connected between the resistor R2 and the resistor R3 , and the anode of the second comparator U2 is connected between the resistor R3 and the resistor R4 .

[0007] In a possible implementation manner, the comparison circuit further includes: The capacitor C3 has a first end connected to the cathode of the second comparator U2, the anode of the first comparator U1, and the second end of the resistor R1, and a second end connected to GND.

[0008] In a possible implementation manner, the voltage divider circuit further includes: The capacitor C1 has a first end connected to the second end of the resistor R2 and the first end of the resistor R3 respectively, and a second end connected to GND.

[0009] In a possible implementation manner, the voltage divider circuit further includes: The capacitor C2 has a first end connected to the second end of the resistor R3 and the first end of the resistor R4 respectively, and a second end connected to GND.

[0010] In a possible implementation manner, a ground terminal of the low dropout linear regulator LDO is connected to GND.

[0011] In a possible implementation, the output end of the low dropout linear regulator LDO is a 5V power output.

[0012] In a possible implementation, the output voltage accuracy of the low dropout linear regulator LDO is ±2%.

[0013] In a possible implementation, the resistor R2, the resistor R3, and the resistor R4 are all high-precision resistors with a precision of ≤1%.

[0014] In a possible implementation, both the first comparator U1 and the second comparator U2 are high-speed comparators.

[0015] In a second aspect, the present invention provides an implementation method of an output complementary PWM wave circuit with a built-in dead zone setting, the method is applied to the output complementary PWM wave circuit with a built-in dead zone setting as described above, the method comprising: Based on the input resistance R of the first comparator U1 and the second comparator U2 in Much larger than the resistors R2, R3 and R4, the reference voltages Vref1 and Vref2 are determined by the formulas Vref1 = Vdc × R2 / (R2+R3+R4) and Vref2 = Vdc × (R2+R3) / (R2+R3+R4); In response to receiving the proportional coefficient adjustment instruction of the resistor R2, the resistor R3 and the resistor R4, changing the threshold value of the flipping of the first comparator U1 and the second comparator U2 to adjust the difference between the reference voltages Vref1 and Vref2; Based on the first end of the resistor R1 being connected to the PWM output end of the microcontroller MCU, and the second end being connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2 respectively, it is determined that the output phase difference between the first comparator U1 and the second comparator U2 is 180°; In view of the fact that the reference voltages Vref1 and Vref2 are not equal in magnitude and the flip levels of the first comparator U1 and the second comparator U2 are inconsistent, it is determined to generate a dead time on the waveforms of the first comparator U1 and the second comparator U2; In response to the rising and falling edge times of the PWM wave output signal being determined, when the difference between the reference voltages Vref1 and Vref2 increases, the dead time is correspondingly increased; when the difference between the reference voltages Vref1 and Vref2 decreases, the dead time is correspondingly decreased.

[0016] The beneficial effects brought about by the technical solution provided by the present invention include at least: This technical solution uses an ordinary MCU to achieve complementary PWM wave output without relying on special IO resources or software dead zone configuration, which greatly reduces the MCU resource usage; by adjusting the ratio of the voltage-dividing resistors R2, R3, and R4, it can flexibly match different PWM frequency requirements and achieve precise control of hardware-level dead zone time; the pure hardware architecture based on resistor voltage division, combined with low-cost MCU selection, has formed a cost-effective half-bridge drive solution. Compared with the traditional method that relies on MCU software to configure the dead zone, it has significant advantages in resource consumption, cost control and application flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0018] Figure 1 A structural block diagram of an output complementary PWM wave circuit with built-in dead zone setting provided by an exemplary embodiment of the present invention is shown.

[0019] Figure 2 A flow chart showing an implementation method of an output complementary PWM wave circuit with built-in dead zone setting provided by an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0022] Figure 1 The structure block diagram of an output complementary PWM wave circuit with a dead zone setting provided by an exemplary embodiment of the present invention is shown. The rear stage (i.e., the output ends of the first comparator U1 and the second comparator U2) of the output complementary PWM wave circuit with a dead zone setting is connected to a half-bridge pre-drive or a full-bridge drive circuit. The output complementary PWM wave circuit with a dead zone setting includes a comparison circuit and a voltage divider circuit connected to each other; the comparison circuit includes: a resistor R1, a first end of which is connected to the PWM output end of the microcontroller MCU, and a second end of which is respectively connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2; the voltage divider circuit includes: a resistor R2, a first end of which is connected to the output end of a low-dropout linear regulator LDO; a resistor R3, a first end of which is connected to the second end of the resistor R2; and a resistor R4, a first end of which is connected to the second end of the resistor R3, and a second end of which is connected to GND; wherein the negative electrode of the first comparator U1 is connected between the resistor R2 and the resistor R3, and the positive electrode of the second comparator U2 is connected between the resistor R3 and the resistor R4.

[0023] In the embodiment of the present application, the resistor R1 provides input impedance matching to prevent the MCU output from directly driving the comparator input to generate overcurrent or signal reflection. The first comparator U1 compares the PWM signal with Vref1 and outputs a high-end signal of complementary PWM. The second comparator U2 compares the PWM signal with Vref2 and outputs a low-end signal of complementary PWM. Resistors R2, R3, and R4 form a three-stage voltage divider network, and generate Vref1 and Vref2 reference voltages respectively through the voltage divider ratios R2 / (R2+R3+R4) and (R2+R3) / (R2+R3+R4).

[0024] Furthermore, the comparison circuit also includes: a capacitor C3, whose first end is respectively connected to the negative electrode of the second comparator U2, the positive electrode of the first comparator U1, and the second end of the resistor R1, and whose second end is connected to GND, for suppressing high-frequency interference of the input signal and improving the anti-noise ability of the comparator.

[0025] Furthermore, the voltage divider circuit also includes: a capacitor C1, a first end of which is respectively connected to the second end of the resistor R2 and the first end of the resistor R3, and a second end of which is connected to GND, for filtering out high-frequency noise of the voltage divider circuit and stabilizing the Vref1 reference voltage; and a capacitor C2, a first end of which is respectively connected to the second end of the resistor R3 and the first end of the resistor R4, and a second end of which is connected to GND, for filtering out high-frequency noise of the voltage divider circuit and stabilizing the Vref2 reference voltage.

[0026] In an embodiment of the present application, the ground terminal of the low-voltage dropout linear regulator LDO is connected to GND, the output terminal of the low-voltage dropout linear regulator LDO is a 5V power supply output, and the output voltage accuracy of the low-voltage dropout linear regulator LDO is ±2%, which is used to provide a stable reference voltage source for the voltage divider circuit and the comparator to ensure the stability of Vref1 / Vref2.

[0027] In the embodiment of the present application, resistor R2, resistor R3, and resistor R4 are all high-precision resistors with an accuracy of ≤1%, which are used to ensure that the voltage difference of Vref1 / Vref2 is consistent with the theoretical calculated value and realize precise control of the dead time.

[0028] In the embodiment of the present application, the first comparator U1 and the second comparator U2 are both high-speed comparators (response time <50ns), which are used to quickly respond to changes in the edge of the PWM signal, reduce dead time errors, and adapt to high-frequency application scenarios (>100kHz).

[0029] Figure 2 A flowchart showing an implementation method of an output complementary PWM wave circuit with a self-contained dead zone setting provided by an exemplary embodiment of the present invention is shown. The implementation method of the output complementary PWM wave circuit with a self-contained dead zone setting is applied to the output complementary PWM wave circuit with a self-contained dead zone setting as described above. The method comprises the following steps: Step 201: Based on the input resistance R of the first comparator U1 and the second comparator U2 in It is much larger than the resistors R2, R3 and R4, and the reference voltages Vref1 and Vref2 are determined by the formulas Vref1 = Vdc × R2 / (R2+R3+R4) and Vref2 = Vdc × (R2+R3) / (R2+R3+R4).

[0030] In the circuit, when the input resistance Rin of the first comparator U1 and the second comparator U2 is much larger than the resistance R2, the resistance R3 and the resistance R4, according to the voltage division principle, the influence of the input current of the comparator on the voltage division circuit can be ignored. The voltage division circuit is composed of the resistance R2, R3 and R4 in series, and the DC voltage Vdc output by the low voltage difference linear regulator LDO is added to this series resistor. For the reference voltage Vref1, it is the voltage division on the resistance R2. According to the voltage division formula of the series circuit, the total voltage Vdc is distributed to each resistor according to the resistance ratio, so Vref1=Vdc×R2 / (R2+R3+R4); for the reference voltage Vref2, it is the sum of the voltage division on the resistance R2 and R3, that is, Vref2=Vdc×(R2+R3) / (R2+R3+R4). Through these two formulas, the specific values ​​of the reference voltages Vref1 and Vref2 can be calculated according to the known Vdc and the resistance values ​​of R2, R3 and R4. These two reference voltages are important bases for subsequent comparator comparisons. They determine the threshold for comparator flipping, thereby affecting the characteristics of the final output PWM wave.

[0031] Step 202 , in response to receiving the proportional coefficient adjustment instruction of the resistors R2 , R3 and R4 , changing the thresholds of the first comparator U1 and the second comparator U2 flipping to adjust the difference between the reference voltages Vref1 and Vref2 .

[0032] In practical applications, it may be necessary to adjust the dead time according to different requirements, and the dead time is related to the difference between the reference voltages Vref1 and Vref2. When the proportional coefficient adjustment instruction of the resistor R2, the resistor R3 and the resistor R4 is received, it means that the resistance ratio of the three resistors needs to be changed. Since the reference voltages Vref1 and Vref2 are determined by the voltage division of the resistors R2, R3 and R4, changing their resistance ratio will directly affect the values ​​of Vref1 and Vref2. The flip thresholds of the first comparator U1 and the second comparator U2 are related to Vref1 and Vref2 respectively, so when the resistance ratio changes, the flip threshold of the comparator will also change accordingly. By changing the flip threshold of the comparator, the difference between the reference voltages Vref1 and Vref2 can be adjusted. For example, if the resistance of R2 is increased while keeping R3 and R4 unchanged, Vref1 will increase, and Vref2 will also increase, but the increase in Vref1 is relatively larger, so that the difference between Vref1 and Vref2 changes.

[0033] Step 203, based on the first end of the resistor R1 being connected to the PWM output end of the microcontroller MCU and the second end being connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2 respectively, it is determined that the output phase difference between the first comparator U1 and the second comparator U2 is 180°.

[0034] In the embodiment of the present application, the first end of the resistor R1 is connected to the PWM output end of the microcontroller MCU, and the second end is respectively connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2. The PWM signal output by the microcontroller MCU is transmitted to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2 at the same time through the resistor R1. For the comparator, when the input signal is compared with the reference voltage, since the positive electrode of the first comparator U1 receives the PWM signal, and the negative electrode of the second comparator U2 receives the PWM signal, their comparison methods for the same PWM signal are opposite. When the PWM signal rises, the first comparator U1 may flip from a low level to a high level, while the second comparator U2 flips from a high level to a low level; when the PWM signal falls, the situation is the opposite. Therefore, the output phase difference between the first comparator U1 and the second comparator U2 is 180°, so that the output of complementary PWM waves is achieved.

[0035] Step 204 , determining to generate a dead time on the waveforms of the first comparator U1 and the second comparator U2 in combination with the fact that the reference voltages Vref1 and Vref2 are unequal in magnitude and the flip levels of the first comparator U1 and the second comparator U2 are inconsistent.

[0036] In the embodiment of the present application, because the reference voltages Vref1 and Vref2 are not equal in size, and the flip levels of the first comparator U1 and the second comparator U2 are inconsistent. The first comparator U1 uses Vref1 as the flip threshold, and the second comparator U2 uses Vref2 as the flip threshold. When the PWM signal changes, the two comparators will not flip at the same time. There will be a period of time on the output waveforms of the first comparator U1 and the second comparator U2, during which the outputs of the two comparators are both low or high, which forms a dead time. The existence of dead time can prevent the power devices of the upper and lower bridge arms from being turned on at the same time in the circuit controlled by complementary PWM waves, thereby preventing the occurrence of problems such as short circuits.

[0037] Step 205, in response to the rising edge and falling edge time of the PWM wave output signal being determined, when the difference between the reference voltages Vref1 and Vref2 increases, the dead time is correspondingly increased; when the difference between the reference voltages Vref1 and Vref2 decreases, the dead time is correspondingly decreased.

[0038] In the embodiment of the present application, when the rising edge and falling edge time of the PWM wave output signal are determined, it means that the basic period and pulse width and other parameters of the PWM signal have been fixed. At this time, the dead time is mainly determined by the difference between the reference voltages Vref1 and Vref2. When the difference between the reference voltages Vref1 and Vref2 increases, the flip time interval of the first comparator U1 and the second comparator U2 will become larger, thereby increasing the dead time accordingly; conversely, when the difference between the reference voltages Vref1 and Vref2 decreases, the flip time interval of the two comparators will become smaller, and the dead time will be reduced accordingly. In this way, the size of the dead time can be flexibly adjusted according to actual needs to adapt to different circuit application scenarios.

[0039] In summary, this technical solution can realize complementary PWM wave output by using an ordinary MCU, without relying on special IO resources or software dead zone configuration, which greatly reduces the MCU resource occupation; by adjusting the ratio of the voltage-dividing resistors R2, R3, and R4, it can flexibly match different PWM frequency requirements and realize precise control of hardware-level dead zone time; the pure hardware architecture based on resistor voltage division, combined with the low-cost MCU selection, forms a cost-effective half-bridge drive solution, which has significant advantages in resource consumption, cost control and application flexibility compared to the traditional method that relies on MCU software to configure the dead zone.

[0040] It should be understood that the specific examples herein are only intended to help those skilled in the art to better understand the present disclosure, rather than to limit the scope of the present invention.

[0041] It is understood that in the various implementations of this specification, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the present disclosure.

[0042] It can be understood that the various implementation modes described in this specification can be implemented individually or in combination, and the present disclosure is not limited to this.

[0043] Unless otherwise stated, all technical and scientific terms used in this disclosure have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in this disclosure and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0044] The above is only a specific implementation of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An output complementary PWM wave circuit with built-in dead zone setting, characterized in that: It includes a comparison circuit and a voltage divider circuit connected to each other; The comparison circuit comprises: A resistor R1, a first end of which is connected to the PWM output end of the microcontroller MCU, and a second end of which is respectively connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2; The voltage divider circuit comprises: A resistor R2, a first end of which is connected to an output end of a low voltage drop linear regulator LDO; a resistor R3, a first end of which is connected to the second end of the resistor R2; and a resistor R4, a first end of which is connected to the second end of the resistor R3, and a second end of which is connected to GND; The cathode of the first comparator U1 is connected between the resistor R2 and the resistor R3 , and the anode of the second comparator U2 is connected between the resistor R3 and the resistor R4 .

2. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The comparison circuit further comprises: The capacitor C3 has a first end connected to the cathode of the second comparator U2, the anode of the first comparator U1, and the second end of the resistor R1, and a second end connected to GND.

3. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The voltage divider circuit further includes: The capacitor C1 has a first end connected to the second end of the resistor R2 and the first end of the resistor R3 respectively, and a second end connected to GND.

4. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The voltage divider circuit further includes: The capacitor C2 has a first end connected to the second end of the resistor R3 and the first end of the resistor R4 respectively, and a second end connected to GND.

5. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The ground terminal of the low dropout linear regulator LDO is connected to GND.

6. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The output end of the low voltage dropout linear regulator LDO is a 5V power output.

7. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The output voltage accuracy of the low dropout linear regulator LDO is ±2%.

8. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The resistor R2, the resistor R3, and the resistor R4 are all high-precision resistors with a precision of ≤1%.

9. The output complementary PWM wave circuit with built-in dead zone setting according to claim 1, characterized in that: The first comparator U1 and the second comparator U2 are both high-speed comparators.

10. An implementation method of an output complementary PWM wave circuit with a built-in dead zone setting, the method being applied to the output complementary PWM wave circuit with a built-in dead zone setting as claimed in any one of claims 1 to 9, characterized in that: The method comprises: Based on the input resistance R of the first comparator U1 and the second comparator U2 in Much larger than the resistors R2, R3 and R4, the reference voltages Vref1 and Vref2 are determined by the formulas Vref1 = Vdc × R2 / (R2+R3+R4) and Vref2 = Vdc × (R2+R3) / (R2+R3+R4); In response to receiving the proportional coefficient adjustment instruction of the resistor R2, the resistor R3 and the resistor R4, changing the threshold value of the flipping of the first comparator U1 and the second comparator U2 to adjust the difference between the reference voltages Vref1 and Vref2; Based on the first end of the resistor R1 being connected to the PWM output end of the microcontroller MCU, and the second end being connected to the positive electrode of the first comparator U1 and the negative electrode of the second comparator U2 respectively, it is determined that the output phase difference between the first comparator U1 and the second comparator U2 is 180°; In view of the fact that the reference voltages Vref1 and Vref2 are not equal in magnitude and the flip levels of the first comparator U1 and the second comparator U2 are inconsistent, it is determined to generate a dead time on the waveforms of the first comparator U1 and the second comparator U2; In response to the rising and falling edge times of the PWM wave output signal being determined, when the difference between the reference voltages Vref1 and Vref2 increases, the dead time is correspondingly increased; when the difference between the reference voltages Vref1 and Vref2 decreases, the dead time is correspondingly decreased.

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