Input / output interface circuit and driving method

Abstract

The invention discloses an input and output interface circuit and a driving method, the input and output interface circuit comprises an IO interface circuit and a target driving module connected with an output port of the IO interface circuit, the target driving module comprises a first level conversion circuit and a buffer driving circuit, the working voltage of the first level conversion circuit is 1.8 v, and the working voltage of the buffer driving circuit is 1.8 v. The working voltage of the buffer drive circuit is 1.8 v, when the target drive module is in a 1.8 v high-speed IO use state, the first level conversion circuit converts a high-speed signal from a core into a 1.8 v signal from core voltage, and the buffer drive module buffers and amplifies the 1.8 v signal and then transmits the 1.8 v signal to a post-stage drive module of the output port, so that the output port outputs the 1.8 v signal to the outside according to the 1.8 v signal. Therefore, under the condition that the layout area of a chip is limited, the high-speed working performance of the IO interface circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to an input-output interface circuit and a driving method. Background Art

[0002] Due to different application scenarios, the operating voltage of chip IO is sometimes 1.8v and sometimes 3.3v. In order to be compatible with 1.8vIO and 3.3vIO, and taking into account the voltage resistance of the device, the IO interface circuit usually uses a MOS tube with a voltage resistance of 3.3v to directly design it into a 1.8v / 3.3vcomboIO (which can be recorded as general IO) that is compatible with 1.8v and 3.3v operating voltages. In the pre-stage output drive scenario, the traditional design using a MOS tube with an operating voltage of 3.3v will increase the transmission delay of 1.8vIO, thereby reducing the data transmission speed of the IO interface circuit. In addition, in the level conversion scenario (used to convert the core voltage into a 1.8v or 3.3v signal), the traditional design using a MOS tube with a voltage resistance of 3.3v cannot meet the duty cycle requirements of the IO interface circuit when working at high speed.

[0003] In the existing technology, in order to shorten the transmission delay of 1.8vIO, the front-end output driver is usually kept working at 3.3v voltage. Alternatively, two independent IOs (i.e. 1.8vIO and 3.3vIO) are used instead of general IOs, and 1.8vIO and 3.3vIO are combined together using selection logic, which can not only solve the duty cycle of high-speed operation in the level conversion scenario, but also shorten the transmission delay of the front-end output driver.

[0004] However, even if the front-stage output driver keeps operating at 3.3V, the duty cycle of the IO interface circuit in the level conversion scenario may not meet the requirements of high-speed operation. In addition, the use of two independent IO combinations requires the design of ESD (Electro-Static Discharge) protection for two independent IOs at the same time, which will occupy additional chip layout area. Summary of the invention

[0005] The present application provides an input-output interface circuit and a driving method, which are used to improve the high-speed working performance of the IO interface circuit when the chip layout area is limited.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] An input-output interface circuit, comprising:

[0008] An IO interface circuit, and a target drive module connected to an output port of the IO interface circuit;

[0009] The target driving module includes a first level conversion circuit and a buffer driving circuit; the working voltage of the first level conversion circuit is 1.8v, and the working voltage of the buffer driving circuit is 1.8v;

[0010] Among them, when the target driving module is in the 1.8v high-speed IO use state, the first level conversion circuit converts the high-speed signal from the core from the core voltage into a 1.8v high-speed signal, and the buffer driving module buffers and amplifies the 1.8v high-speed signal and transmits it to the subsequent driving module of the output port, so that the output port outputs externally according to the 1.8v high-speed signal.

[0011] Optionally, when the IO interface circuit is in a 3.3vIO working state or a 1.8v low-speed IO working state, the target driver module is placed in an idle state; when the IO interface circuit is in a 1.8v high-speed IO working state, the target driver module is placed in a 1.8v high-speed IO use state.

[0012] Optionally, the output port includes a pre-stage driver module; when the IO interface circuit is in a 3.3v IO working state, the pre-stage driver module is in a 3.3v IO use state; when the IO interface circuit is in a 1.8v low-speed IO working state, the pre-stage driver module is in a 1.8v low-speed IO use state; when the IO interface circuit is in a 1.8v high-speed IO working state, the pre-stage driver module is in an idle state.

[0013] Optionally, when the front-stage driver module is in a 1.8v low-speed IO usage state, the front-stage driver module converts the signal from the core from the core voltage to a 1.8v low-speed signal, and amplifies the 1.8v low-speed signal through a corresponding buffer to obtain a corresponding first amplified voltage, so that the rear-stage driver module outputs externally according to the first amplified voltage; when the front-stage driver module is in a 3.3v IO usage state, the front-stage driver module converts the signal from the core from the core voltage to a 3.3v signal, and amplifies the 3.3v signal through a corresponding buffer to obtain a corresponding second amplified voltage, so that the rear-stage driver module outputs externally according to the second amplified voltage.

[0014] Optionally, the pre-stage driver module includes a second level conversion circuit, and the operating voltage of the second level conversion circuit is 3.3v or 1.8v; wherein, when the pre-stage driver module is in a 3.3v IO use state, the second level conversion circuit converts the signal from the core from the core voltage to a 3.3v signal; when the pre-stage driver module is in a 1.8v low-speed IO use state, the second level conversion circuit converts the signal from the core from the core voltage to a 1.8v low-speed signal.

[0015] Optionally, the input end of the rear-stage driving module is connected to the output of the front-stage driving module and the target driving module respectively, and the output end of the rear-stage driving module is connected to an external load.

[0016] Optionally, when the front-stage driver module is in 3.3vIO use state or 1.8v low-speed IO use state, the rear-stage driver module is isolated from the target driver module; when the front-stage driver module is in idle state, the rear-stage driver module is isolated from the front-stage driver module.

[0017] Optionally, the buffer driving circuit includes a first inverter with an operating voltage of 1.8V, and the pre-stage driving module includes a second inverter with an operating voltage of 1.8V or 3.3V.

[0018] Optionally, the first level conversion circuit includes a first switch tube with a withstand voltage of 1.8V, and the second level conversion circuit includes a second switch tube with a withstand voltage of 3.3V.

[0019] A driving method, the driving method is based on the input-output interface circuit, the driving method comprising:

[0020] Get the working status of the IO interface circuit;

[0021] When the IO interface circuit is in a 1.8v low-speed IO working state, the trigger target driver module is placed in an idle state, and the pre-stage driver module is placed in a 1.8v low-speed IO using state;

[0022] When the IO interface circuit is in a 3.3vIO working state, the target driver module is triggered to be placed in an idle state, and the pre-stage driver module is placed in a 3.3vIO using state;

[0023] When the IO interface circuit is in a 1.8V high-speed IO working state, the target drive module is triggered to be in a use state, and the pre-stage drive module is placed in an idle state.

[0024] The technical solution provided by the present application includes an IO interface circuit, and a target drive module connected to the output port of the IO interface circuit. The target drive module includes a first level conversion circuit and a buffer drive circuit. The working voltage of the first level conversion circuit is 1.8v, and the working voltage of the buffer drive circuit is 1.8v. Wherein, when the target drive module is in the 1.8v high-speed IO use state, the first level conversion circuit converts the signal from the core from the core voltage to a 1.8v signal, and the buffer drive module buffers and amplifies the 1.8v signal and transmits it to the post-stage drive module of the output port, so that the output port outputs externally according to the 1.8v signal. On the basis of the IO interface circuit, a target drive module with a simple circuit structure is added, and the first level conversion circuit in the target drive module is used to convert the high-speed signal from the core from the core voltage to a 1.8v high-speed signal, and the buffer drive module amplifies and outputs the 1.8v high-speed signal, so that the voltage difference between the core voltage and the IO voltage is maintained within a specified range, thereby improving the high-speed working performance of the IO interface circuit under the 1.8v working voltage state when the chip layout area is limited. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of the architecture of an input-output interface circuit provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of the architecture of another input-output interface circuit provided in an embodiment of the present application;

[0028] Figure 3 A schematic flow chart of a driving method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] In this application, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0031] The applicant found that the greater the voltage difference between the core voltage and the IO voltage, the more difficult it is to design a level conversion circuit for high-speed signals, especially when the core voltage is close to or less than the operating voltage of the internal devices of the IO interface circuit, the output of the front-stage driver module of the IO interface circuit cannot achieve a high-speed flip from high to low of the rear-stage driver module, resulting in the traditional design using a MOS tube with an operating voltage of 3.3v being unable to meet the duty cycle requirements of the IO interface circuit when it is working at high speed. To this end, it is only necessary to control the voltage difference between the core voltage and the IO voltage to be maintained within a specified range (for example, 1v) to meet the duty cycle requirements of the IO interface circuit when it is working at high speed, and achieve high-speed working performance of the IO interface circuit under the 1.8vIO working state.

[0032] Based on the above-mentioned discovery of the applicant, an embodiment of the present application provides an input-output interface circuit. On the basis of the IO interface circuit, the input-output interface circuit adds a target drive module with a simple circuit structure to control the voltage difference between the core voltage and the IO voltage, thereby improving the high-speed working performance of the IO interface circuit when the chip layout area is limited.

[0033] like Figure 1 As shown, it is a schematic diagram of the architecture of an input-output interface circuit provided in an embodiment of the present application, including the modules shown below.

[0034] The IO interface circuit 100 and the target driving module 200 connected to the output port 110 of the IO interface circuit 100 .

[0035] The target driving module 200 includes a first level conversion circuit 201 and a buffer driving circuit 202 . The operating voltage of the first level conversion circuit 201 is 1.8V, and the operating voltage of the buffer driving circuit 202 is 1.8V.

[0036] Among them, when the target driver module 200 is in the 1.8v high-speed IO use state, the first level conversion circuit 201 converts the high-speed signal from the core of the output port 110 from the core voltage into a 1.8v high-speed signal, and the buffer driver module buffers and amplifies the 1.8v high-speed signal and transmits it to the subsequent driver module of the output port 110 (usually used as the last stage 1.8v output driver), so that the output port 110 outputs externally according to the 1.8v high-speed signal.

[0037] In some examples, the core voltage may be understood as the voltage of the chip core. Specifically, the core voltage is typically 1V.

[0038] In some examples, the IO interface circuit 100 further includes an input port 120. The structure of the input port 120 can be seen in Figure 2 As shown, specifically, the input port 120 includes an independent third inverter, and the input port 120 can support a Pad bidirectional signal and a Pad input signal.

[0039] It should be noted that when the target driver module 200 is in the 1.8v high-speed IO use state, the IO interface circuit 100 is usually in the 1.8v high-speed IO working state, and the target driver module 200 converts the high-speed signal from the core of the output port 110 from the core voltage to a 1.8v high-speed signal, so that the voltage difference between the core voltage and the 1.8v signal (i.e., the IO voltage in the current state) is maintained within 1v.

[0040] Optionally, when the IO interface circuit 100 is in a 3.3v IO working state or a 1.8v low-speed IO working state, the target driver module 200 is placed in an idle state; when the IO interface circuit 100 is in a 1.8v high-speed IO working state, the target driver module 200 is placed in a 1.8v high-speed IO use state.

[0041] In some examples, the input port 120 is generally designed as a PSW18 control state, which is used to adapt the IO interface circuit 100 to switch between the 1.8v high-speed IO working state, the 1.8v low-speed IO working state, and the 3.3v IO working state. Specifically, when the IO interface circuit 100 is in the 3.3v IO working state or the 1.8v low-speed IO working state, the PSW18 control state is in a low-level state of 0, and when the IO interface circuit 100 is in the 1.8v high-speed IO working state, the PSW18 control state is in a high-level state of 1.

[0042] It is understandable that when the target driving module 200 is placed in an idle state, the first level conversion circuit 201 and the buffer driving circuit 202 stop running, that is, the first level conversion circuit 201 no longer performs voltage conversion, and the buffer driving circuit 202 no longer performs voltage amplification. The first level conversion circuit 201 and the buffer driving circuit 202 are not started until the target driving module 200 is placed in a 1.8V high-speed IO use state.

[0043] The circuit architecture shown above adds a target driver module with a simple circuit structure on the basis of the IO interface circuit. The first level conversion circuit in the target driver module is used to convert the signal from the core of the output port from the core voltage to a 1.8v high-speed signal. The buffer driver module buffers and amplifies the 1.8v high-speed signal and transmits it to the subsequent driver module of the output port, so that the voltage difference between the core voltage and the IO voltage is maintained within a specified range, thereby improving the high-speed working performance of the IO interface circuit under the 1.8v working voltage state when the chip layout area is limited.

[0044] like Figure 2 As shown, it is a schematic diagram of the architecture of another input-output interface circuit provided in an embodiment of the present application, including the modules shown below.

[0045] The IO interface circuit 100 and the target driving module 200, wherein the IO interface circuit 100 includes an output port 110 and an input port 120, the output port 110 includes a front-stage driving module 111 and a rear-stage driving module 112, the input end of the rear-stage driving module 112 is respectively connected to the output of the front-stage driving module 111 and the target driving module 200, and the output end of the rear-stage driving module 112 is connected to an external load.

[0046] Optionally, when the IO interface circuit 100 is in a 3.3v IO working state, the pre-stage driver module 111 is in a 3.3v IO use state; when the IO interface circuit 100 is in a 1.8v low-speed IO working state, the pre-stage driver module 111 is in a 1.8v low-speed IO use state; when the IO interface circuit 100 is in a 1.8v high-speed IO working state, the pre-stage driver module 111 is in an idle state.

[0047] Optionally, when the front-stage driver module 111 is in a 1.8v low-speed IO use state, the front-stage driver module 111 converts the signal from the core from the core voltage into a 1.8v low-speed signal, and amplifies the 1.8v low-speed signal through a corresponding buffer to obtain a corresponding first amplified voltage, so that the rear-stage driver module 112 outputs externally according to the first amplified voltage; when the front-stage driver module 111 is in a 3.3v IO use state, the front-stage driver module 111 converts the signal from the core from the core voltage into a 3.3v signal, and amplifies the 3.3v signal through a corresponding buffer to obtain a corresponding second amplified voltage, so that the rear-stage driver module 112 outputs externally according to the second amplified voltage.

[0048] Optionally, the front-stage driver module 111 includes a second level conversion circuit 1111, and the operating voltage of the second level conversion circuit 1111 is 1.8v or 3.3v. When the front-stage driver module 111 is in a 3.3v IO use state, the second level conversion circuit 1111 converts the signal from the core from the core voltage to a 3.3v signal. When the front-stage driver module 111 is in a 1.8v low-speed IO use state, the second level conversion circuit 1111 converts the signal from the core from the core voltage to a 1.8v low-speed signal.

[0049] It should be noted that when the front-stage driver module 111 is in 3.3vIO use state or 1.8v low-speed IO use state, the rear-stage driver module 112 is isolated from the target driver module 200; when the front-stage driver module 111 is in idle state, the rear-stage driver module 112 is isolated from the front-stage driver module 111.

[0050] Generally speaking, when the front-stage driver module 111 is in a .3vIO use state or a 1.8v low-speed IO use state, the rear-stage driver module 112 is isolated from the target driver module 200, and does not affect the normal output of the IO interface circuit 100 in the 3.3vIO working state or the 1.8v low-speed working state. When the front-stage driver module 111 is in an idle state, the rear-stage driver module 112 is isolated from the front-stage driver module 111, and does not affect the normal output of the IO interface circuit 100 in the 1.8v high-speed IO working state.

[0051] Specifically, the buffer driving circuit 202 includes a first inverter with an operating voltage of 1.8v, and the pre-stage driving module 111 includes a second inverter with an operating voltage of 1.8v or 3.3v.

[0052] Specifically, the first level conversion circuit 201 includes a first switch tube with a withstand voltage of 1.8V, and the second level conversion circuit 1111 includes a second switch tube with a withstand voltage of 1.8V or 3.3V.

[0053] Specifically, the post-stage driving module 112 includes a plurality of third switch tubes.

[0054] In a possible implementation manner, the ESD protection of the target driver module 200 and the subsequent driver module 112 are used together, which can effectively improve the performance of the ESD protection.

[0055] In some examples, the first switch tube, the second switch tube, and the third switch tube may be MOS tubes.

[0056] It should be emphasized that in the target driver module 200 added on the basis of the IO interface circuit 100, the voltage difference between the core voltage and the IO voltage is maintained within a specified range, so a high-speed level conversion circuit can be designed relatively easily, and at the same time, the high duty cycle requirement (e.g., 50%) required by the high-speed circuit of the chip memory can be guaranteed. Since the buffer driver circuit 202 uses a 1.8v device instead of a 3.3v device, the transmission delay of the output port 110 is effectively reduced, which is beneficial to the operation of the high-speed circuit.

[0057] In the circuit architecture shown above, the input end of the rear-stage driver module is connected to the output of the front-stage driver module and the target driver module respectively, and the output end of the rear-stage driver module is connected to the external load, so that the IO interface circuit maintains normal output under different working conditions, and the transmission delay will not be affected and extended.

[0058] like Figure 3 As shown, it is a flow chart of a driving method provided in an embodiment of the present application. The driving method is based on the above-mentioned input-output interface circuit and includes the following steps.

[0059] S301: Obtain the working status of the IO interface circuit.

[0060] Among them, the types of working states include 1.8v high-speed IO working state, 3.3vIO working state, and 1.8v low-speed working state.

[0061] S302: When the IO interface circuit is in the 1.8v low-speed IO working state, the target driver module is triggered to be placed in an idle state, and the pre-stage driver module is placed in the 1.8v low-speed IO using state.

[0062] Among them, when the front-stage driving module is placed in the 1.8v low-speed IO use state, the front-stage driving module converts the signal from the core from the core voltage to a 1.8v low-speed signal, and amplifies the 1.8v low-speed signal to obtain a corresponding first amplified voltage, so that the rear-stage driving module outputs externally according to the first amplified voltage.

[0063] In some examples, the front-stage driver module includes a second level conversion circuit, the operating voltage of the second level conversion circuit is 1.8v, wherein when the front-stage driver module is in a 1.8v low-speed IO usage state, the second level conversion circuit converts the signal from the core from the core voltage to a 1.8v low-speed signal.

[0064] It should be noted that when the IO interface circuit is in the 1.8v low-speed IO working state, the front-stage driver module in the 1.8v low-speed IO use state is used to convert the signal from the core from the core voltage to a 1.8v low-speed signal to ensure that the device is compatible with the working voltage, thereby shortening the transmission delay of the front-stage output driver in the IO interface circuit.

[0065] S303: When the IO interface circuit is in the 3.3vIO working state, the target driver module is triggered to be placed in an idle state, and the pre-stage driver module is placed in a 3.3vIO using state.

[0066] Among them, when the front-stage driving module is placed in the 3.3vIO use state, the front-stage driving module converts the signal from the core from the core voltage to a 3.3v signal, and amplifies the 3.3v signal to obtain a corresponding second amplified voltage, so that the rear-stage driving module outputs externally according to the second amplified voltage.

[0067] In some examples, the front-stage driver module includes a second level conversion circuit, the operating voltage of the second level conversion circuit is 3.3v, wherein when the front-stage driver module is in a 3.3vIO use state, the second level conversion circuit converts the signal from the core from the core voltage to a 3.3v signal.

[0068] It should be noted that when the IO interface circuit is in the 3.3vIO working state, the signal from the core is converted from the core voltage to a 3.3v signal using the pre-stage driver module in the 3.3vIO use state to ensure that the device is compatible with the working voltage.

[0069] S304: When the IO interface circuit is in the 1.8v high-speed IO working state, the target driver module is triggered to be placed in the 1.8v high-speed IO using state, and the pre-stage driver module is placed in the idle state.

[0070] Among them, the target driving module includes a first level conversion circuit and a buffer driving circuit. When the target driving module is placed in the 1.8v high-speed IO use state, the first level conversion circuit converts the signal from the core of the output port from the core voltage to a 1.8v high-speed signal, and the buffer driving module amplifies the 1.8v high-speed signal and transmits it to the subsequent driving module of the output port, so that the output port outputs externally according to the 1.8v high-speed signal.

[0071] In some examples, the operating voltage of the first level conversion circuit is 1.8V, and the operating voltage of the buffer driving circuit is 1.8V.

[0072] It should be noted that when the IO interface circuit is in the 1.8vIO working state, the target driver module in the 1.8v high-speed IO use state is used to convert the signal from the core from the core voltage to a 1.8v high-speed signal, ensuring that the device and the working voltage are compatible, and the voltage difference between the core voltage and the IO voltage is maintained within the specified range, thereby effectively improving the high-speed working performance of the IO interface circuit.

[0073] The process shown in S301-S303 above controls the use of the target driver module and the pre-stage driver module according to the working state of the IO interface circuit, so that the voltage difference between the core voltage and the IO voltage is maintained within a specified range, thereby improving the high-speed working performance of the IO interface circuit under different working voltage states (including 1.8vIO working state and 3.3vIO working state) when the chip layout area is limited.

[0074] Although several specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present application. Certain features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0075] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. An input-output interface circuit, characterized in that: include: An IO interface circuit, and a target drive module connected to an output port of the IO interface circuit; The target driving module includes a first level conversion circuit and a buffer driving circuit; the working voltage of the first level conversion circuit is 1.8v, and the working voltage of the buffer driving circuit is 1.8v; Among them, when the target driving module is in the 1.8v high-speed IO use state, the first level conversion circuit converts the high-speed signal from the core from the core voltage into a 1.8v high-speed signal, and the buffer driving module buffers and amplifies the 1.8v high-speed signal and transmits it to the subsequent driving module of the output port, so that the output port outputs externally according to the 1.8v high-speed signal.

2. The circuit according to claim 1, characterized in that When the IO interface circuit is in 3.3vIO working state or 1.8v low-speed IO working state, the target driver module is placed in idle state; when the IO interface circuit is in 1.8v high-speed IO working state, the target driver module is placed in 1.8v high-speed IO using state.

3. The circuit according to claim 1, characterized in that The output port includes a pre-stage driver module; when the IO interface circuit is in a 3.3v IO working state, the pre-stage driver module is in a 3.3v IO use state; when the IO interface circuit is in a 1.8v low-speed IO working state, the pre-stage driver module is in a 1.8v low-speed IO use state; when the IO interface circuit is in a 1.8v high-speed IO working state, the pre-stage driver module is in an idle state.

4. The circuit according to claim 3, characterized in that When the front-stage driver module is in the 1.8v low-speed IO use state, the front-stage driver module converts the signal from the core from the core voltage to the 1.8v low-speed signal, and amplifies the 1.8v low-speed signal through the corresponding buffer to obtain the corresponding first amplified voltage, so that the rear-stage driver module outputs externally according to the first amplified voltage; when the front-stage driver module is in the 3.3v IO use state, the front-stage driver module converts the signal from the core from the core voltage to the 3.3v signal, and amplifies the 3.3v signal through the corresponding buffer to obtain the corresponding second amplified voltage, so that the rear-stage driver module outputs externally according to the second amplified voltage.

5. The circuit according to claim 4, characterized in that The pre-stage driver module includes a second level conversion circuit, and the operating voltage of the second level conversion circuit is 3.3v or 1.8v; wherein, when the pre-stage driver module is in a 3.3vIO use state, the second level conversion circuit converts the signal from the core from the core voltage to a 3.3v signal; when the pre-stage driver module is in a 1.8v low-speed IO use state, the second level conversion circuit converts the signal from the core from the core voltage to a 1.8v low-speed signal.

6. The circuit according to claim 3, characterized in that The input end of the latter stage driving module is connected to the output of the former stage driving module and the target driving module respectively, and the output end of the latter stage driving module is connected to an external load.

7. The circuit according to claim 6, characterized in that When the front-stage driver module is in 3.3vIO use state or 1.8v low-speed IO use state, the rear-stage driver module is isolated from the target driver module; when the front-stage driver module is in idle state, the rear-stage driver module is isolated from the front-stage driver module.

8. The circuit according to claim 3, characterized in that The buffer driving circuit includes a first inverter with an operating voltage of 1.8V, and the pre-stage driving module includes a second inverter with an operating voltage of 1.8V or 3.3V.

9. The circuit according to claim 5, characterized in that The first level conversion circuit includes a first switch tube with a withstand voltage of 1.8V, and the second level conversion circuit includes a second switch tube with a withstand voltage of 3.3V.

10. A driving method, characterized in that: The driving method is based on the input-output interface circuit according to any one of claims 1 to 9, and the driving method comprises: Get the working status of the IO interface circuit; When the IO interface circuit is in a 1.8v low-speed IO working state, the trigger target driver module is placed in an idle state, and the pre-stage driver module is placed in a 1.8v low-speed IO using state; When the IO interface circuit is in a 3.3vIO working state, the target driver module is triggered to be placed in an idle state, and the pre-stage driver module is placed in a 3.3vIO using state; When the IO interface circuit is in a 1.8V high-speed IO working state, the target drive module is triggered to be in a use state, and the pre-stage drive module is placed in an idle state.

Images