Sampling Circuit with Clock Adjustment, Sampling Control Method, and Electronic Device

Abstract

The present application discloses a sampling circuit for clock adjustment, a sampling control method, and an electronic device. The sampling circuit includes: a first differential branch, a second differential branch, a phase detection circuit, a correction circuit, and an adjustment circuit; the first differential branch is connected between a first port and a first input end of the phase detection circuit; the second differential branch is connected between a second port and a second input end of the phase detection circuit; the correction circuit is connected between an output end of the phase detection circuit and the adjustment circuit, and is configured to output a control signal to the adjustment circuit based on a detection result of the phase detection circuit; the adjustment circuit is coupled to the first differential branch and the second differential branch, and is also coupled to a first clock signal source, and is configured to adjust a sampling clock of one or more differential branches in the first differential branch or the second differential branch based on the control signal. The present application has the technical effects of reducing the mismatch of differential input signals, reducing the energy of even harmonics, and improving the operation stability of the device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of circuit technologies, and particularly to a sampling circuit for clock regulation, a sampling control method, and an electronic device. Background Art

[0002] The development of wireless communication technologies has continuously increased the signal frequency requirements for high-speed and high-precision analog-to-digital converters. In analog-to-digital converters with high sampling rates, time-domain interleaved sampling is usually adopted to increase the sampling rate. The spectrum finally output by the analog-to-digital converter includes the high-order harmonics of each sub-channel analog-to-digital converter itself, and also includes the inter-channel spurs generated due to mismatches such as amplitude and phase between multiple channels. Moreover, due to non-ideal factors such as asymmetric traces and device mismatches, the influence of the even-order linearity of the differential signal becomes worse with frequency. Therefore, the harmonic problem of the differential signal input to the analog-to-digital converter deserves attention. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a sampling circuit for clock regulation, a sampling control method, and an electronic device, in order to reduce the harmonic influence in the differential signal input to the analog-to-digital converter. A sampling circuit includes: a first differential branch, a second differential branch, a phase detection circuit, a correction circuit, and an adjustment circuit; the first differential branch is connected between a first port and a first input end of the phase detection circuit; the second differential branch is connected between a second port and a second input end of the phase detection circuit; the correction circuit is connected between an output end of the phase detection circuit and the adjustment circuit, and is configured to output a control signal to the adjustment circuit based on the detection result of the phase detection circuit; the adjustment circuit is coupled to the first differential branch and the second differential branch, and is also coupled to a first clock signal source, and is configured to adjust the sampling clock of one or more differential branches in the first differential branch through a first adjustment branch or in the second differential branch through a second adjustment branch based on the control signal.

[0004] For the above sampling circuit for clock regulation, the phase error is determined based on the detection result of the phase detection circuit, and then the correction circuit generates a control signal according to the detection result to change the variation of the sampling clock in the differential branch through the adjustment circuit, so as to effectively adjust the phase error, reduce the mismatch of the differential input signal, thereby reducing the even-order harmonic energy of the entire analog-to-digital conversion chip, reducing the interference to sensitive devices, and improving the operation stability and reliability of the device.

[0005] Optionally, the first differential branch includes: a first sampling switch and a first sampling capacitor, and the first sampling switch is connected between the first port and the first end of the first sampling capacitor; the second differential branch includes: a second sampling switch and a second sampling capacitor, and the second sampling switch is connected between the second port and the first end of the second sampling capacitor.

[0006] Optionally, the first end of the first sampling capacitor is coupled to the first input terminal, and the second end of the first sampling capacitor is grounded; the first end of the second sampling capacitor is coupled to the second input terminal, and the second end of the second sampling capacitor is grounded.

[0007] Optionally, the adjustment circuit includes a first adjustment branch and a second adjustment branch; the first adjustment branch is connected between the correction circuit and the first sampling switch; the second adjustment branch is connected between the correction circuit and the second sampling switch.

[0008] Optionally, it further includes: a third sampling switch and a fourth sampling switch; the second end of the first sampling capacitor is coupled to the first input terminal; the second end of the second sampling capacitor is coupled to the second input terminal; the third sampling switch is connected between the first input terminal and the common-mode voltage source; the fourth sampling switch is connected between the second input terminal and the common-mode voltage source; the adjustment circuit is respectively coupled to the third sampling switch and the fourth sampling switch.

[0009] Optionally, the first sampling switch and the second sampling switch are respectively coupled to the second clock signal source.

[0010] Optionally, the phase detection circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, and an operational amplifier; the drain of the first switching transistor and the drain of the second switching transistor are coupled to the first power supply, the source of the first switching transistor and the source of the second switching transistor are coupled to the drain of the third switching transistor; the gate of the first switching transistor is coupled to the output terminal of the operational amplifier, the gate of the second switching transistor is coupled to the reference voltage source, the gate of the third switching transistor is coupled to the bias voltage source; the drain of the third switching transistor serves as the output terminal of the phase detection circuit, and the source of the third switching transistor is grounded.

[0011] Optionally, the phase detection circuit further includes: a first capacitor, a second capacitor, and a third capacitor; the first capacitor is connected between the input terminal of the operational amplifier and the first input terminal, the second capacitor is connected between the input terminal of the operational amplifier and the second input terminal; one end of the third capacitor is coupled to the output terminal of the phase detection circuit, and the other end is grounded.

[0012] Second aspect, a sampling control method is provided for controlling the sampling circuit provided in the first aspect, including: configuring the first adjustment branch and the second adjustment branch in the adjustment circuit to a first preset gear; obtaining a first output result of the phase detection circuit; adjusting the first adjustment branch to a second preset gear and adjusting the second adjustment branch to a third preset gear based on the first output result, where the phase adjustment value of the second preset gear is greater than that of the first preset gear, and the phase adjustment value of the third preset gear is less than that of the first preset gear; obtaining a second output result of the phase detection circuit; when the second output result is greater than the first output result, adjusting the first adjustment branch to a fourth preset gear and adjusting the second adjustment branch to a fifth preset gear, where the phase adjustment value of the fourth preset gear is less than that of the first preset gear, and the phase adjustment value of the fifth preset gear is greater than that of the first preset gear; when the second output result is less than the first output result, adjusting the first adjustment branch to a sixth preset gear and adjusting the second adjustment branch to a seventh preset gear until the second output result meets a preset output threshold, where the phase adjustment value of the sixth preset gear is greater than that of the second preset gear, and the phase adjustment value of the seventh preset gear is less than that of the third preset gear.

[0013] Third aspect, an electronic device is provided, including the sampling circuit provided in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following briefly introduces the drawings used in the description of the embodiments of the present disclosure:

[0015] Figure 1 It shows a schematic diagram of a conventional test scenario provided in some embodiments of the present application;

[0016] Figure 2 It shows a schematic circuit diagram of a sampling circuit with clock adjustment provided in some embodiments of the present application;

[0017] Figure 3 It shows a schematic circuit diagram of another sampling circuit with clock adjustment provided in some embodiments of the present application;

[0018] Figure 4 It shows a timing diagram of a sampling circuit with clock adjustment provided in some embodiments of the present application;

[0019] Figure 5 It shows a schematic circuit diagram of yet another sampling circuit with clock adjustment provided in some embodiments of the present application;

[0020] Figure 6 It shows a timing diagram of another sampling circuit with clock adjustment provided in some embodiments of the present application;

[0021] Figure 7The figure shows a schematic circuit diagram of a phase detection circuit provided in some embodiments of the present application;

[0022] Figure 8 The figure shows a schematic flowchart of a sampling control method provided in some embodiments of the present application;

[0023] Figure 9 The figure shows a schematic structural diagram of a sampling control device provided in some embodiments of the present application. Detailed implementation manners

[0024] To more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will describe the example embodiments of the present disclosure with reference to the accompanying drawings. The accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other embodiments can be obtained. Adjustments and improvements made without departing from the concept of the present disclosure all fall within the protection scope of the present disclosure.

[0025] To make the drawings concise, each drawing only schematically shows the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, parts with the same structure or function are only schematically shown partially, and there may actually be more or fewer parts with the same structure or function.

[0026] In the present disclosure, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order between related objects; in addition, they do not represent the quantity of related objects. "A plurality" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, which means the "or" relationship between related objects. "And / or" is used to describe the relationship between related objects, which includes any combination relationship between related objects. For example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" among multiple objects refers to any object or any combination of multiple objects. For example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0027] The development of wireless communication technology has continuously increased the signal frequency requirements for high-speed and high-precision analog-to-digital converters. In analog-to-digital converters with high sampling rates, time-domain interleaved sampling is usually adopted to improve the sampling rate. The spectrum finally output by the analog-to-digital converter contains the high-order harmonics of each sub-channel analog-to-digital converter itself, as well as the inter-channel spurs generated due to mismatches such as amplitude and phase between multiple channels. Moreover, due to non-ideal factors such as asymmetric traces and device mismatches, the influence of the even-order linearity of differential signals becomes worse with frequency. In the actual chip testing process, the phenomenon that the energy of even-order harmonics is much higher than that of other harmonics often occurs, and this problem is unacceptable in some special scenarios such as radar detection applications. Figure 1 FIG. shows a schematic diagram of a conventional test scenario provided in some embodiments of the present application. The high-frequency signal is provided by the signal source 10, converted into a differential signal through the external balun 20, and the differential signal is connected to the PCB board through two equal-length transmission lines respectively, and then sent to the chip under test 30 through a series of RC matching network devices. However, the differential signal generated by the balun 20 cannot completely achieve a phase difference of 180 degrees, and it is difficult for the two transmission lines of the differential signal to be completely symmetric. Therefore, a phase or amplitude difference will be generated in the differential signal sent into the chip under test 30. Inside the chip under test 30, the differential input is sent to the input port of the analog front-end circuit through symmetric traces, and then provided to each sub-analog-to-digital converter through tree-shaped traces respectively. In the actual layout, due to physical trace limitations, there are also mismatches in the differential input traces and the tree-shaped traces, and there may also be device mismatches in the analog front-end circuit. Therefore, there must be phase and amplitude mismatches in the signal actually sent to the sampling input end of the sub-analog-to-digital converter, which affects the final test result or causes unexpected failures. Therefore, a sampling circuit provided in the present application detects the phase difference of the differential input signal, adjusts the clock of the sampling switch according to the detection result, so as to achieve the minimum phase difference, reduce the mismatch of the differential input signal, and thus reduce the even-order harmonic energy of the entire analog-to-digital conversion chip.

[0028] Figure 2The figure shows a schematic circuit diagram of a sampling circuit for clock adjustment provided in some embodiments of the present application. The sampling circuit 200 for clock adjustment includes: a first differential branch 210, a second differential branch 220, a phase detection circuit 230, a correction circuit 240, and an adjustment circuit 250; the first differential branch 210 is connected between the first port IN1 and the first input end of the phase detection circuit 230; the second differential branch 220 is connected between the second port IN2 and the second input end of the phase detection circuit 230; the correction circuit 240 is connected between the output end of the phase detection circuit 230 and the adjustment circuit 250, and is configured to output a control signal to the adjustment circuit 250 based on the detection result of the phase detection circuit 230; the adjustment circuit 250 is coupled to the first differential branch 210 and the second differential branch 220, and is also coupled to the clock signal source, and is configured to adjust the sampling clock of one or more differential branches in the first differential branch 210 through the first adjustment branch or in the second differential branch 220 through the second adjustment branch based on the control signal.

[0029] In the above sampling circuit, the first differential branch 210 and the second differential branch 220 respectively obtain input signals from the connected signal source through the first port IN1 and the second port IN2. For example, the first differential branch 210 can control the on and off of the sampling switch according to a preset sampling period. When the sampling switch is on, the input signal is sampled through the sampling capacitor. When the sampling switch is off, obtaining the input signal is paused and the charge stored in the sampling capacitor is transferred to the subsequent circuit to complete the sampling. After sampling is completed, the differential signals provided by the first differential branch 210 and the second differential branch 220 can enter the phase detection circuit 230 from the first input terminal and the second input terminal respectively, detect the phase error between the two signals, and provide the detection result to the correction circuit 240. For example, when the phase error between the two differential ends is the smallest, the output value of the phase detection circuit 230 is the lowest. When the phase error increases, the output value of the phase detection circuit 230 increases accordingly. During the detection process, the output result can be further sent to the correction circuit 240 to generate a control signal for the control adjustment circuit 250 according to the specific parameters of the output result. For example, when the phase error is relatively large, the sampling period of one or all branches in the first differential branch 210 or the second differential branch 220 is adjusted. Correspondingly, the change in the sampling period can cause the on and off times of the sampling switch to change, thereby accumulating different amounts of charge in the sampling capacitor and reflecting different phase error results in the phase detection circuit 230. When the adjustment circuit 250 performs phase adjustment, for example, it can include a series of control gears. At the initial adjustment, the adjustment circuit 250 can be set to the middle gear. When the output value of the phase detection circuit 230 is relatively small, the control signals at both ends of the differential generated by the correction circuit 240 are relatively close to both sides of the middle gear. When the output value of the phase detection circuit 230 is relatively large, the difference between the control signals at both ends of its differential on both sides of the middle gear is relatively large, thereby realizing effective adjustment of the phase error. The above sampling circuit reduces the mismatch of the differential input signal by adjusting the sampling time, thereby reducing the even harmonic energy of the entire analog-to-digital conversion chip, reducing interference to sensitive devices, and improving the operation stability and reliability of the device.

[0030] Figure 3The figure shows a schematic circuit diagram of another clock-adjusted sampling circuit provided in some embodiments of the present application. In the clock-adjusted sampling circuit 300, the first differential branch includes: a first sampling switch Sc1 and a first sampling capacitor Cc1. The first sampling switch Sc1 is connected between the first port IN1 and the first end of the first sampling capacitor Cc1; the second differential branch includes: a second sampling switch and a second sampling capacitor Cc2. The second sampling switch is connected between the second port IN2 and the first end of the second sampling capacitor Cc2. The first sampling switch Sc1 and the second sampling switch can be turned on and off according to the sampling clock period provided by the first clock signal source CKS1. When the first sampling switch Sc1 and the second sampling switch are turned on, the input signals enter from the first port IN1 and the second port IN2 and are sampled by the first sampling capacitor Cc1 and the second sampling capacitor Cc2. When the sampling clock period indicates that the first sampling switch Sc1 and the second sampling switch are turned off, the charges stored in the first sampling capacitor Cc1 and the second sampling capacitor Cc2 can be transferred to the phase detection circuit 330, thereby completing the sampling within this period, and the phase difference between the input differential signals is detected via the phase detection circuit 330.

[0031] Continue to refer to Figure 3 , the first end of the first sampling capacitor Cc1 is coupled to the first input terminal, and the second end of the first sampling capacitor Cc1 is grounded; the first end of the second sampling capacitor Cc2 is coupled to the second input terminal, and the second end of the second sampling capacitor Cc2 is grounded. The above sampling circuit structure forms top-plate sampling and can be applicable to scenarios with relatively high requirements for sampling speed but relatively low requirements for accuracy. In Figure 3 the sampling circuit, when the clock signal provided by the first clock signal source CKS1 is at a high level, the first sampling switch Sc1 and the second sampling switch can be controlled to turn on, and the input signals charge the first sampling capacitor Cc1 and the second sampling capacitor Cc2. The input signal corresponding to the falling edge of the clock signal provided by the first clock signal source CKS1 is the signal level finally held in the first sampling capacitor Cc1 and the second sampling capacitor Cc2. When the clock signal provided by the first clock signal source CKS1 is at a low level, the phase detection circuit 330 compares the phase differences between VSP and VSN of the signal holding nodes to determine the detection result. Figure 4The timing schematic diagram of a sampling circuit for clock adjustment provided in some embodiments of the present application is shown. The input signals VINp and VINn enter from the first port IN1 and the second port IN2 respectively. The first clock signal source CKS1 provides the clock signal waveform. Фp or Фn represents the conduction and turn-off timing of the first sampling switch Sc1 or the second sampling switch. The shaded part represents the possible turn-off interval of the first sampling switch Sc1 or the second sampling switch. When the phase error at both ends of the differential is minimized, the output value of the phase detection circuit 330 is the lowest. On the contrary, when the phase difference increases, the output value of the phase detection circuit 330 will increase accordingly. The detection result is further sent to the correction circuit 340, and a control signal for controlling the adjustment circuit is generated based on the detection result, thereby adjusting the sampling period of the clock signal provided to the first sampling switch Sc1 and the second sampling switch to reduce the overall even harmonic energy.

[0032] Continuing to refer to Figure 3 , the adjustment circuit may include a first adjustment branch 351 and a second adjustment branch 352; the first adjustment branch 351 is connected between the correction circuit 340 and the first sampling switch Sc1; the second adjustment branch 352 is connected between the correction circuit 340 and the second sampling switch. The first adjustment branch 351 and the second adjustment branch 352 in the adjustment circuit can be implemented by adjusting the inverter of the tail current source, the inverter load plus the DAC capacitor, etc. The adjustment accuracy can be the minimum value of the phase error correction.

[0033] Figure 5 The circuit structure schematic diagram of another sampling circuit for clock adjustment provided in some embodiments of the present application is shown. The sampling circuit 500 further includes: a third sampling switch Sc3 and a fourth sampling switch Sc4; the second end of the first sampling capacitor Cc1 is coupled to the first input terminal; the second end of the second sampling capacitor Cc2 is coupled to the second input terminal; the third sampling switch Sc3 is connected between the first input terminal and the common-mode voltage source; the fourth sampling switch Sc4 is connected between the second input terminal and the common-mode voltage source; the adjustment circuit is respectively coupled to the third sampling switch Sc3 and the fourth sampling switch Sc4.

[0034] In some embodiments, the first sampling switch and the second sampling switch are respectively coupled to the second clock signal source.

[0035] The sampling method of the above sampling circuit is bottom-plate sampling. The bottom-plate charge of the sampling capacitor is not easily affected by the switch control and the input current, and the requirements for the switch are relatively low, which can improve the stability of the circuit and is suitable for scenarios with high requirements for sampling accuracy and acceptable more complex circuit designs. Different from the top-plate sampling, the adjustment object of the adjustment circuit can be the control timing of the third sampling switch Sc3 and the fourth sampling switch Sc4 at the bottom plate of the sampling capacitor. Figure 6The timing schematic diagram of another clock adjustment sampling circuit provided in some embodiments of the present application is shown. Refer to Figure 6 , in the bottom plate sampling, the falling edge of the sampling clock provided by the first clock signal source CKS1 is earlier than that of the sampling clock provided by the second clock signal source CKS2. Therefore, in this sampling circuit, when the sampling clock delay is adjusted to the maximum gear, the falling edges of and in the turn-on and turn-off timings of the third sampling switch Sc3 and the fourth sampling switch Sc4 can be made earlier than the falling edge of the second clock signal source CKS2.

[0036] Figure 7 The circuit structure schematic diagram of a phase detection circuit provided in some embodiments of the present application is shown. The phase detection circuit includes: a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and an operational amplifier A1; the drain of the first switching transistor M1 and the drain of the second switching transistor M2 are coupled to a first power supply VDD, the source of the first switching transistor M1 and the source of the second switching transistor M2 are coupled to the drain of the third switching transistor M3; the gate of the first switching transistor M1 is coupled to the output terminal of the operational amplifier A1, the gate of the second switching transistor M2 is coupled to a reference voltage source VREF, and the gate of the third switching transistor M3 is coupled to a bias voltage source VBIAS; the drain of the third switching transistor M3 serves as the output terminal of the phase detection circuit, and the source of the third switching transistor M3 is grounded.

[0037] The phase detection circuit further includes: a first capacitor C1, a second capacitor C2, and a third capacitor C3; the first capacitor C1 is connected between the input terminal of the operational amplifier A1 and the first input terminal, and the second capacitor C2 is connected between the input terminal of the operational amplifier A1 and the second input terminal; one end of the third capacitor C3 is coupled to the output terminal of the phase detection circuit, and the other end is grounded.

[0038] The above sampling circuit accesses signals from the sampling and holding nodes VSP and VSN, and the two first capacitors C1 and C2 with the same size are connected in series for AC coupling to remove the DC component in the input signal and transmit the AC part to prevent the DC bias from affecting the operation of the subsequent circuit and avoid too high or too low DC level in the input signal. After forming an intermediate node in series, the signal amplitude is increased by the operational amplifier A1 and output through the operational amplifier A1. The output is connected to the drains of the first switching transistor M1 and the second switching transistor M2 respectively with the reference voltage source VREF. After the sources of the first switching transistor M1 and the second switching transistor M2 are short-circuited, the magnitude of the output voltage represents the magnitude of the phase of the input differential signal. When the phase difference between the two ends of the differential input is 0, its output is a common-mode level.

[0039] Figure 8The flowchart of a sampling control method provided in some embodiments of the present application is shown. The sampling control method is used to control the sampling circuit provided in the above embodiments, and at least includes the steps:

[0040] S810: Configure the first adjustment branch and the second adjustment branch in the adjustment circuit to the first preset gear;

[0041] S820: Obtain the first output result of the phase detection circuit;

[0042] S830: Based on the first output result, adjust the first adjustment branch to the second preset gear, and adjust the second adjustment branch to the third preset gear, where the phase adjustment value of the second preset gear is greater than that of the first preset gear, and the phase adjustment value of the third preset gear is less than that of the first preset gear;

[0043] S840: Obtain the second output result of the phase detection circuit;

[0044] S850: When the second output result is greater than the first output result, adjust the first adjustment branch to the fourth preset gear, and adjust the second adjustment branch to the fifth preset gear, where the phase adjustment value of the fourth preset gear is less than that of the first preset gear, and the phase adjustment value of the fifth preset gear is greater than that of the first preset gear;

[0045] S860: When the second output result is less than the first output result, adjust the first adjustment branch to the sixth preset gear, and adjust the second adjustment branch to the seventh preset gear until the second output result meets the preset output threshold, where the phase adjustment value of the sixth preset gear is greater than that of the second preset gear, and the phase adjustment value of the seventh preset gear is less than that of the third preset gear.

[0046] In the above sampling control method, when obtaining the first output result, if it is determined that the output of the phase detection circuit increases, the phase adjustment control gear of the adjustment circuit corresponding to the first differential branch or the second differential branch in the sampling circuit can be increased. For example, the control gear of the first adjustment branch is increased, and the control gear of the second adjustment branch is decreased. Then, the sampling result after adjustment for a certain number of times is detected by the phase detection circuit again. If the output value of the phase detection circuit increases compared with the previous time, the adjustment direction is reversed. For example, the control gear of the first adjustment branch is decreased from the middle gear, and the phase adjustment control of the control gear of the second adjustment branch is increased from the middle gear. If the output value of the phase detection circuit decreases compared with the previous time, the adjustment amplitude is further increased. For example, the control gear of the first adjustment branch is further increased, and the control gear of the second adjustment branch is decreased. When the output of the phase detection circuit falls within the range of the preset output threshold, the correction is completed, and the control gear no longer changes.

[0047] Based on the same inventive concept, an electronic device is provided, including the sampling circuit provided in the above embodiments.

[0048] Based on the same inventive concept, Figure 9 The structural schematic diagram of a sampling control device provided in some embodiments of the present application is shown. The sampling control device 900 includes: a configuration unit 910, configured to configure the first adjustment branch and the second adjustment branch in the adjustment circuit to a first preset gear; an acquisition unit 920, configured to acquire a first output result of the phase detection circuit; an adjustment unit 930, configured to adjust the first adjustment branch to a second preset gear based on the first output result, and adjust the second adjustment branch to a third preset gear, where the phase adjustment value of the second preset gear is greater than that of the first preset gear, and the phase adjustment value of the third preset gear is less than that of the first preset gear; the acquisition unit 920 is further configured to acquire a second output result of the phase detection circuit;

[0049] The adjustment unit 930 is further configured to, when the second output result is greater than the first output result, adjust the first adjustment branch to a fourth preset gear, and adjust the second adjustment branch to a fifth preset gear, where the phase adjustment value of the fourth preset gear is less than that of the first preset gear, and the phase adjustment value of the fifth preset gear is greater than that of the first preset gear; and is configured to, when the second output result is less than the first output result, adjust the first adjustment branch to a sixth preset gear, and adjust the second adjustment branch to a seventh preset gear until the second output result meets a preset output threshold, where the phase adjustment value of the sixth preset gear is greater than that of the second preset gear, and the phase adjustment value of the seventh preset gear is less than that of the third preset gear.

[0050] The division of each of the above units is only a division of logical functions. In actual implementation, they can be fully or partially integrated into a physical entity, or physically separated. In addition, each of the above units can be implemented in the form of a processor calling software. For example, the photovoltaic module roller brush cleaning control device includes a processor, the processor is connected to a memory, and instructions are stored in the memory. The processor calls the instructions stored in the memory to implement any of the above methods or the functions of each unit. The processor is, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory is a memory inside or outside the device. Alternatively, each of the above units can be implemented in the form of a hardware circuit, and the functions of some or all of the units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, in some embodiments, the hardware circuit is an application specific integrated circuit (ASIC), and the functions of some or all of the above units are implemented through the design of the logical relationship between the components in the circuit. Again, in another implementation, the hardware circuit can be implemented by a programmable logic device (PLD), which can include a large number of logic gate circuits, and the logical relationship between the logic gate circuits is configured through a configuration file to implement the functions of some or all of the above units. All the units of the above device can be fully implemented in the form of a processor calling a program, or fully implemented in the form of a hardware circuit, or partially implemented in the form of a processor calling a program, and the remaining part is implemented in the form of a hardware circuit.

[0051] In some embodiments of the present disclosure, a processor is a circuit with signal processing capabilities. In some embodiments, a processor can be a circuit with instruction reading and running capabilities, such as a CPU, a microprocessor, a graphics processing unit (GPU), or a digital signal processor (DSP), etc.; in another implementation, a processor can achieve certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit is fixed or can be reconfigured. For example, the processor is a hardware circuit implemented by an ASIC or a PLD, such as a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of a processor loading a configuration document to implement the configuration of the hardware circuit can be understood as the process of a processor loading instructions to implement the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc. It can be seen that each unit in the above device can be one or more processors (or processing circuits) configured to implement the above methods. For example: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms. In addition, each unit in the above device can be integrated in whole or in part, or can be independently implemented. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC). The SOC can include at least one processor for implementing any of the above methods or implementing the functions of each unit of the above device.

[0052] In the above embodiments, the descriptions of each embodiment have their own focuses. For parts not detailedly described or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A clock-regulated sampling circuit, characterized in that: The analog front end applied to the analog-to-digital conversion chip includes: a first differential branch, a second differential branch, a phase detection circuit, a correction circuit and an adjustment circuit; The first differential branch is connected between the first port and the first input terminal of the phase detection circuit; The second differential branch is connected between the second port and the second input terminal of the phase detection circuit; The phase detection circuit comprises: a first switch tube, a second switch tube, a third switch tube and an operational amplifier; The drain of the first switch tube and the drain of the second switch tube are coupled to a first power source, and the source of the first switch tube and the source of the second switch tube are coupled to the drain of the third switch tube; The gate of the first switch tube is coupled to the output terminal of the operational amplifier, the gate of the second switch tube is coupled to a reference voltage source, and the gate of the third switch tube is coupled to a bias voltage source; The drain of the third switch tube serves as the output end of the phase detection circuit, and the source of the third switch tube is grounded; The correction circuit is connected between the output terminal of the phase detection circuit and the adjustment circuit, and is configured to output a control signal to the adjustment circuit based on the detection result of the phase detection circuit; The regulating circuit is coupled to the first differential branch and the second differential branch, and is coupled to a first clock signal source, and is configured to adjust the sampling clock of the first differential branch through the first regulating branch or adjust the sampling clock of one or more differential branches in the second differential branch through the second regulating branch based on the control signal, specifically comprising: configuring the first regulating branch and the second regulating branch to a first preset gear position; The correction circuit obtains a first output result of the phase detection circuit; The correction circuit adjusts the first adjustment branch to a second preset gear position based on the first output result, and adjusts the second adjustment branch to a third preset gear position, wherein the phase adjustment value of the second preset gear position is greater than the first preset gear position, and the phase adjustment value of the third preset gear position is less than the first preset gear position; The correction circuit obtains a second output result of the phase detection circuit; when the second output result is greater than the first output result, the first adjustment branch is adjusted to a fourth preset gear, and the second adjustment branch is adjusted to a fifth preset gear, wherein the phase adjustment value of the fourth preset gear is less than the first preset gear, and the phase adjustment value of the fifth preset gear is greater than the first preset gear; when the second output result is less than the first output result, the first adjustment branch is adjusted to a sixth preset gear, and the second adjustment branch is adjusted to a seventh preset gear, until the second output result meets a preset output threshold, wherein the phase adjustment value of the sixth preset gear is greater than the second preset gear, and the phase adjustment value of the seventh preset gear is less than the third preset gear.

2. The sampling circuit according to claim 1, characterized in that: The first differential branch includes: a first sampling switch and a first sampling capacitor, wherein the first sampling switch is connected between the first port and a first end of the first sampling capacitor; The second differential branch includes: a second sampling switch and a second sampling capacitor, wherein the second sampling switch is connected between the second port and a first end of the second sampling capacitor.

3. The sampling circuit according to claim 2, characterized in that: A first terminal of the first sampling capacitor is coupled to the first input terminal, and a second terminal of the first sampling capacitor is grounded; A first terminal of the second sampling capacitor is coupled to the second input terminal, and a second terminal of the second sampling capacitor is grounded.

4. The sampling circuit according to claim 3, characterized in that: The first regulating branch is connected between the correction circuit and the first sampling switch; The second regulating branch is connected between the correction circuit and the second sampling switch.

5. The sampling circuit according to claim 2, characterized in that: Also includes: a third sampling switch and a fourth sampling switch; The second terminal of the first sampling capacitor is coupled to the first input terminal; The second terminal of the second sampling capacitor is coupled to the second input terminal; The third sampling switch is connected between the first input terminal and the common mode voltage source; The fourth sampling switch is connected between the second input terminal and the common mode voltage source; The regulating circuit is coupled to the third sampling switch and the fourth sampling switch respectively.

6. The sampling circuit according to claim 5, characterized in that: The first sampling switch and the second sampling switch are respectively coupled to a second clock signal source.

7. The sampling circuit according to claim 1, characterized in that: The phase detection circuit further includes: a first capacitor, a second capacitor and a third capacitor; The first capacitor is connected between the input terminal of the operational amplifier and the first input terminal, and the second capacitor is connected between the input terminal of the operational amplifier and the second input terminal; One end of the third capacitor is coupled to the output end of the phase detection circuit, and the other end of the third capacitor is grounded.

8. An electronic device, characterized in that: The sampling circuit comprises the sampling circuit described in any one of claims 1 to 7.

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