Power time service method, system and device based on SW processor and storage medium

Abstract

The invention relates to an electric power time service method, system and device based on a SW processor and a storage medium, and the method comprises the steps: receiving time message information of a plurality of time sources, and carrying out the analysis, and obtaining the time information and second signals of each time source; performing time difference measurement on the second signal of each time source and the second signal generated locally to obtain time difference measurement information; acquiring a time source priority set by a user, selecting a time source according to the time information and the time source priority, and outputting a source selection result; estimating the time frequency deviation of the corresponding time source according to the time difference measurement information, the source selection result and a preset time compensation parameter, and outputting a time frequency calibration parameter; and performing time information synchronization and second signal phase synchronization on the available time source according to the source selection result and the time frequency calibration parameter, and outputting the synchronized time information and second signal. The precision and the response speed of the time service device can be remarkably improved through the high-performance computing power of the SW processor.

Description

Technical Field

[0001] The present application relates to the field of electric power timing technology, and in particular to an electric power timing method, system, device and storage medium based on a Shenwei processor. Background Art

[0002] At present, the commonly used methods for power timing are: GPS timing, which uses the time information transmitted by the Global Positioning System (GPS) satellite. Due to its high precision and global coverage, it is widely used in the synchronous clock system of the power grid; IEEE 1588 timing (PTP, Precision Time Protocol), which transmits time information through the network and is suitable for local area networks and wide area networks; IRIG-B code timing, which uses pulse code modulation to transmit time information, is usually transmitted through a dedicated communication link, has high reliability, and is widely used in industrial control and metering and protection equipment of power systems; power line carrier communication (PLC), which transmits time information through power lines, uses the existing power network, does not require additional communication infrastructure, and is suitable for measurement and control of remote and remote areas of power systems; Network Time Protocol (NTP), which transmits time information through the Internet or local area network, is easy to implement, and is widely used in computer networks.

[0003] However, the accuracy of the existing Beidou-based power timing solution cannot meet the high-precision requirements of the power system. For example, some traditional timing methods may have large time deviations, resulting in inconsistent equipment time in the power system, affecting the stable operation of the system. At the same time, the existing power grid-wide time synchronization accuracy monitoring means are single and have low monitoring accuracy. It is impossible to effectively manage and monitor the timing status of various clock devices, which may lead to time synchronization anomalies at critical moments, thus affecting the normal operation of the power system. Summary of the invention

[0004] The embodiments of the present application provide a power timing method, system, device and storage medium based on the Shenwei processor, so as to at least solve the problem in the related technology that the accuracy of the existing Beidou-based power timing solution cannot meet the high-precision requirements of the power system.

[0005] In a first aspect, an embodiment of the present application provides a power timing method based on a Shenwei processor, comprising:

[0006] Receive time message information from multiple time sources and parse them to obtain the time information and second signal of each time source;

[0007] The time difference between the second signal of each time source and the second signal generated locally is measured to obtain the time difference measurement information;

[0008] Obtain the time source priority set by the user, select a time source according to the time information and the time source priority, and output the source selection result;

[0009] According to the time difference measurement information, the source selection result and the preset time compensation parameters, the time frequency deviation of the corresponding time source is estimated, and the time frequency calibration parameters are output;

[0010] The time information and second signal phase of the available time source are synchronized according to the source selection result and the time frequency calibration parameters, and the synchronized time information and second signal are output.

[0011] In one embodiment, the receiving and parsing of time message information from multiple time sources to obtain time information and a second signal from each time source includes:

[0012] Receive satellite message information sent by a satellite time source, identify the validity of the satellite time source according to the satellite message information, and parse out the first year, month, day, hour, minute, second information and position information;

[0013] Receive IRIG_B time code signal and perform decoding operation to obtain code element information and second time edge;

[0014] The code element information is parsed to obtain the second year, month, day, hour, minute, and second information and time validity status information of the IRIG_B time code signal.

[0015] In one embodiment, the time difference measurement information includes a first second difference measurement value, a second second difference measurement value, and a third second difference measurement value, and the time difference measurement of the second signal of each time source and the second signal generated locally to obtain the time difference measurement information includes:

[0016] Extract two BDS second signals from the first year-month-day hour-minute-second information, and perform time difference measurement based on the two BDS second signals to obtain a first second difference measurement value;

[0017] Extract two IRIG_B code second signals from the second year-month-day-hour-minute-second information, and perform time difference measurement based on the two IRIG_B code second signals to obtain a second second difference measurement value;

[0018] The phase difference between the second signals generated by the FPGA and the CPU is calculated to obtain the third second difference measurement value.

[0019] In one embodiment, the method further comprises:

[0020] If there is no available time source, the time information is maintained based on the locally generated seconds, which are maintained by the device's built-in frequency source, and the device enters a punctual state.

[0021] In one embodiment, the outputting of synchronized time information and second signal comprises:

[0022] Obtaining the configuration requirements of the user, and compiling the synchronized time information into relevant serial time codes according to the configuration requirements to obtain the time information code;

[0023] The time information is encoded and superimposed on the second punctual edge, and modulated according to the pulse modulation requirements of the serial time code, and the modulated signal is distributed to output modules with different electrical characteristics;

[0024] The calibrated time information and second information are encoded and synchronized according to the NTP and SNTP protocol requirements.

[0025] In a second aspect, an embodiment of the present application provides a power timing system based on a Shenwei processor, including:

[0026] A time analysis unit is used to receive and analyze time message information from multiple time sources to obtain time information and second signals from each time source;

[0027] A time difference measurement unit is used to measure the time difference between the second signal of each time source and the second signal generated locally to obtain time difference measurement information;

[0028] A time source selection unit, configured to obtain a time source priority set by a user, select a time source according to the time information and the time source priority, and output a source selection result;

[0029] A calibration parameter calculation unit, configured to estimate the time frequency deviation of the corresponding time source according to the time difference measurement information, the source selection result and the preset time compensation parameter, and output the time frequency calibration parameter;

[0030] The time synchronization unit is used to synchronize the time information and the second signal phase of the available time source according to the source selection result and the time frequency calibration parameter, and output the synchronized time information and second signal.

[0031] In one embodiment, the system further comprises a BDS decoding module and a B code decoding module, wherein:

[0032] The BDS decoding module is used to receive and decode satellite message information sent by the satellite time source;

[0033] The B code decoding module is used to receive the IRIG_B time code signal and perform decoding operations to obtain code element information and second punctual edge;

[0034] The time parsing unit is used to identify the validity of the satellite time source according to the satellite message information, and parse out the first year, month, day, hour, minute, second information and position information; and parse the code element information to obtain the second year, month, day, hour, minute, second information and time validity status information of the IRIG_B time code signal.

[0035] In one embodiment, the time synchronization unit includes a time generation and synchronization unit and a second signal generation and synchronization unit, wherein:

[0036] The time is generated by the synchronization unit for correcting the deviation of the time information according to the source selection result and the time frequency calibration parameter;

[0037] The second signal is phase-synchronized by the second signal generation and synchronization unit.

[0038] In one embodiment, the system further comprises a management and configuration unit, a serial time encoding unit, a serial time signal generating unit and a network timing service unit, wherein:

[0039] The management and configuration unit is used to obtain parameters and configuration requirements set by the user;

[0040] The serial time encoding unit is used to compile the synchronized time information into relevant serial time codes according to the configuration requirements to obtain time information codes;

[0041] The serial time signal generating unit is used to encode the time information and superimpose the second punctual edge, and modulate it according to the pulse modulation requirements of the serial time code, and distribute the modulated signal to output modules with different electrical characteristics;

[0042] The network timing service unit is used to encode and time the calibrated time information and second information according to the NTP and SNTP protocol requirements.

[0043] In a third aspect, an embodiment of the present application provides a power timing device based on a Shenwei processor, comprising:

[0044] A CPU board equipped with a Shenwei processor and an FPGA is used to execute the power timing method based on the Shenwei processor in any of the above embodiments;

[0045] A BOARD with two Beidou receiving modules is deployed to receive satellite message information sent by the Beidou system;

[0046] Display control panel, used to display time information, power system status data and alarm data, and realize human-computer interaction function;

[0047] The time output board is used to provide RS485, RS232, TTL, BAC, OC electrical interfaces and FIBER optical interfaces.

[0048] In one embodiment, the device further comprises:

[0049] The extended interface unit is used to convert the time information according to the type of the connected interface and output the time serial code in a corresponding format to the power system.

[0050] In one embodiment, the extension interface unit includes at least one time output module, and the time output module is an IRIG-B signal generating module, a pulse signal generating module, a DCF77 signal generating module, an NTP signal generating module or a PTP signal generating module.

[0051] In one embodiment, the CPU board further includes two Ethernet ports, an alarm contact, two optical signal input interfaces, and a serial port for communicating with a display control board.

[0052] In one embodiment, the BORAD board further comprises a plurality of slots for plugging various serial coded time output boards and a plurality of fixed programmable optical B code output interfaces.

[0053] In one embodiment, the display control panel includes a status indicator light, an LED liquid crystal, a button and an MCU.

[0054] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the power timing method based on the Shenwei processor as described in the first aspect above.

[0055] The power timing method, system, device and storage medium based on the Shenwei processor provided in the embodiments of the present application have at least the following technical effects:

[0056] By using the Shenwei processor to implement a single Beidou SBAS (Satellite-Based Augmentation System) timing system solution, the timing accuracy can be improved to a higher level: the high-performance computing capability of the Shenwei processor can significantly improve the accuracy and response speed of the timing device; improve system security and autonomous controllability. The Shenwei processor is combined with the Beidou SBAS system to form a completely autonomous and controllable hardware and software platform, which can effectively avoid external dependence and improve the security of the power system. By providing an autonomous and controllable computing platform, the Shenwei processor can avoid potential security threats and ensure that the power timing system always runs smoothly and reliably.

[0057] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0059] Figure 1It is a structural frame of a power timing device based on a Shenwei processor in an embodiment of the present application;

[0060] Figure 2 It is a functional design diagram of a power timing device based on a Shenwei processor in one embodiment of the present application;

[0061] Figure 3 It is a flow chart of a power timing method based on a Shenwei processor in an embodiment of the present application;

[0062] Figure 4 It is a structural block diagram of a power timing system based on a Shenwei processor in an embodiment of the present application;

[0063] Figure 5 This is a flowchart of time synchronization in one embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0065] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0066] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0067] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0068] Shenwei processor is a special research and development project of my country's "core high-tech" project. Its processor is different from the core authorization or instruction set authorization mode. Shenwei processor adopts SW64 independent instruction set architecture, with fully controllable intellectual property rights, higher autonomy and stronger security. The core technology can be independently iterated and developed. It is the only domestic processor manufacturer with a completely independent and controllable instruction set in China. Beidou timing device uses the characteristics of Shenwei processor to optimize the use of existing CPUs: ① Improve computing performance: Through efficient parallel computing capabilities and rich instruction sets, the computing performance of the algorithm is significantly improved, especially for the current large-scale data processing and solution in high-precision timing. The multi-core and multi-threaded capabilities of Shenwei processors are used to rewrite and optimize existing programs so that they can better utilize parallel computing resources, and the program operation efficiency is significantly improved; ② Low-power design can maintain high performance while reducing energy consumption and extending the service life of the equipment. Using the power management characteristics of Shenwei processors, the voltage and frequency of the processor are dynamically adjusted under different loads to achieve energy saving; ③ Using the security features provided by the SW64 instruction set, key data and systems are protected from various attacks, improving the security of the overall system.

[0069] Based on the above situation, the embodiment of the present application provides a power timing device based on the Shenwei processor, specifically referring to Figure 1 , the device of this embodiment includes:

[0070] The CPU board is equipped with a Shenwei processor and FPGA, and the BOARD board is equipped with two Beidou receiving modules (BDS1 and BDS2). It receives satellite message information sent by the Beidou system through antenna 1 and sends information to the navigation system through antenna 2; the display control board is used to display time information, power system status data and alarm data, and realize human-computer interaction functions; the time output board is used to provide RS485, RS232, TTL, BAC, OC electrical interfaces and FIBER optical interfaces.

[0071] The device also includes an extended interface unit, which is used to convert the time information according to the type of the connected interface and output the time serial code in the corresponding format to the power system. In this embodiment, the extended interface unit includes at least one time output module, which is an IRIG-B signal generation module, a pulse signal generation module, a DCF77 signal generation module, an NTP signal generation module or a PTP signal generation module.

[0072] In addition, the CPU board also includes two Ethernet ports (NET1, NET2), alarm contacts, two optical signal input interfaces (FIBER), and a serial port for communicating with the display control board. The BORAD board also includes multiple slots for plugging various serial coded time output boards and multiple fixed programmable optical B code output interfaces. The display control board includes status indicator lights, LED liquid crystal, buttons and MCU.

[0073] In a specific embodiment, reference Figure 1 , CPU and FPGA are deployed on the CPU board, where the CPU is Shenwei's Weiyan 831+ICH3, and the FPGA is Gaoyun's GW2A-LV18. The CPU board provides two Ethernet ports NET1 and NET2, alarm contacts and 2 optical signal input interfaces, as well as a serial port for communicating with the display board. Two Beidou receiving modules (BDS) are deployed on the BORAD board, and 6 slots are provided to plug in various types of serially coded time output boards. According to user needs, different types and quantities of time serial coded time output boards can be flexibly configured. In addition, 5 fixed programmable optical B code output interfaces are deployed on the BOARD board, and the display board is equipped with status indicators, LED liquid crystals, and buttons, a serial port for communicating with the display board, and an MCU responsible for display and button processing; the serially coded time output board provides RS485, RS232, TTL, BAC, OC electrical interfaces and FIBER optical interfaces.

[0074] More specifically, the core processor module of the Beidou high-precision timing device is mainly composed of the Shenwei 831 processor, FPGA, constant temperature crystal oscillator / rubidium clock, etc. Figure 2, the functions mainly include time analysis and measurement, time synchronization and time synchronization. Among them, the time analysis and measurement function includes operations such as time source validity identification, time information and second punctual edge and time difference measurement; in the time synchronization process, it is necessary to first determine the source selection strategy, and then perform phase and frequency synchronization; when the time is output, the serial time code will be output, and the time will be synchronized through the network timing server, and the synchronization status alarm and self-test information alarm can also be output. In addition, the device of the present application also has a configuration and management module, which can configure and manage operating parameters, as well as remote upgrade management. The configuration and management module is connected to the output module so that the output module outputs status information for management.

[0075] The timing device provided in the embodiment of the present application can realize functions such as time training, multi-task management, local punctuality, time coding, time generation, status and human-computer interaction, system configuration, local log, etc., and can also monitor and control the status of various expansion boards, expand the time signal output, etc., to realize the management, calculation processing, time training, etc. of the Beidou high-precision timing device.

[0076] The expansion interface unit provides various time signal generation and encoding modules, including IRIG-B signal generation module, pulse signal generation module, DCF77 signal generation module, NTP signal generation module, and PTP signal generation module. It can flexibly configure different types and quantities of time serial encoding time output modules according to user needs.

[0077] The CPU board mainly completes the time taming algorithm, including BDS decoding module, B code decoding module, time difference measurement module, time calibration module and second signal generation and synchronization module. The taming unit judges the validity of Beidou satellite signals and obtains the year, month, day, hour, minute and second information, position information and second punctual edge of Beidou satellite according to the external input time source and the satellite time received by the BD module; judges the validity of the IRIG_B code time source and obtains the year, month, day, hour, minute and second information and second punctual edge in the IRIG_B code. Measure the time difference between the input source time and the device output time for device time synchronization. The synchronization process includes phase synchronization and frequency synchronization. According to the source selection strategy, select one of the valid time sources according to priority to perform time phase and frequency synchronization. Calibrate the local clock and phase to complete the taming of the local constant temperature crystal oscillator / rubidium clock time.

[0078] The display control unit provides LED liquid crystal and buttons, providing system status data display, alarm data display, human-computer interaction and button processing functions. The output of status information includes alarm node output and indicator light for intuitive display. The time message and PPS signal output provide coded time output function. The output of time information includes year, month, day, hour, minute, second and second pulse data. The coding format includes IRIG-B, DCF77, IEC-61850, etc. The Ethernet time output includes NTP and SNTP network timing servers.

[0079] In the second aspect, with respect to the above-mentioned power timing device, the embodiment of the present application provides a power timing method based on the Shenwei processor, which is applied in a power timing system with a Shenwei processor, referring to Figure 3 , the method comprising:

[0080] Step S1, receiving time message information of multiple time sources and parsing them to obtain time information and second signals of each time source. Specifically, receiving satellite message information sent by a satellite time source, identifying the validity of the satellite time source according to the satellite message information, and parsing out the first year, month, day, hour, minute, second information and position information; receiving an IRIG_B time code signal and performing a decoding operation to obtain symbol information and second punctual edge; parsing the symbol information to obtain the second year, month, day, hour, minute, second information and time validity status information of the IRIG_B time code signal.

[0081] Step S2, measuring the time difference between the second signal of each time source and the second signal generated locally, and obtaining the time difference measurement information. Specifically, the time difference measurement information includes a first second difference measurement value, a second second difference measurement value, and a third second difference measurement value, and the time difference measurement between the second signal of each time source and the second signal generated locally, and obtaining the time difference measurement information, includes: extracting two BDS second signals from the first year-month-day hour-minute-second information, and measuring the time difference according to the two BDS second signals, and obtaining the first second difference measurement value; extracting two IRIG_B code second signals from the second year-month-day hour-minute-second information, and measuring the time difference according to the two IRIG_B code second signals, and obtaining the second second difference measurement value; calculating the phase difference between the second signals generated by the FPGA and the CPU, and obtaining the third second difference measurement value.

[0082] Step S3, obtaining the time source priority set by the user, selecting a time source according to the time information and the time source priority, and outputting a source selection result.

[0083] Step S4, estimating the time frequency deviation of the corresponding time source according to the time difference measurement information, the source selection result and the preset time compensation parameters, and outputting the time frequency calibration parameters.

[0084] Step S5, according to the source selection result and the time frequency calibration parameters, the available time sources are synchronized with the time information and the second signal phase, and the synchronized time information and second signal are output. Specifically, the user's configuration requirements are obtained, and the synchronized time information is compiled with the relevant serial time code according to the configuration requirements to obtain the time information code; the time information code is superimposed with the second punctual edge, and modulated according to the pulse modulation requirements of the serial time code, and the modulated signal is distributed to the output modules with different electrical characteristics; the calibrated time information and second information are encoded and timed according to the NTP and SNTP protocol requirements.

[0085] In addition, in an embodiment of the present application, if there is no available time source at present, the time information is maintained based on the locally generated seconds, and the locally generated seconds are maintained by the frequency source built into the device, and the device enters a punctual state.

[0086] In summary, the timing device provided by this application has the following advantages:

[0087] (1) The enhanced design of autonomous and controllable time base can access two Beidou satellite signals;

[0088] (2) Use high-precision satellite receivers with an accuracy better than 10ns;

[0089] (3) Rich output interface types: network interface, RS232, RS485, TTL, AC signal, switch signal output;

[0090] (4) The output time type can be selected as hour, minute, second pulse, DCF77, IRIG-B, etc.

[0091] (5) It provides both optocoupler OC gate and RS485 bus output pulses, which can meet the time synchronization requirements of up to 128 sets of devices for hour, minute and second pulses;

[0092] (6) Provides a network timing server that supports NTP and SNTP protocols. Popular network host systems / devices can automatically and accurately synchronize time without the need for additional programming;

[0093] (7) After satellite synchronization is lost, the system can continuously, stably and accurately output substitute (timekeeping) hour, minute and second pulses that are synchronized with the original second pulses of the satellite receiver and maintain the accuracy of the internal clock (i.e., internal timekeeping function);

[0094] (8) It has strong pulse, serial port, and IRIG-B expansion capabilities to meet the expansion needs of high-precision and large-capacity interfaces;

[0095] (9) Provide device working status alarm contact output: power failure alarm, satellite synchronization loss alarm;

[0096] (10) The status indicator on the front panel visually indicates the device's operating, fault, advanced, and synchronization status;

[0097] (11) Network interface, supports UDP host point-to-point mode, broadcast mode and multicast mode, with no limit on the number of receiving hosts;

[0098] (12) Support web configuration function, support network remote upgrade, and reduce production and maintenance links in each link;

[0099] (13) There are no jumpers or adjustable components inside the device. The baud rate, IRIG-B and other related parameters are all set by software, which facilitates application and improves the reliability of the device.

[0100] (14) Support multiple network management protocols: support WEB management, support 61850, 104 and SNMPV1 / V2 / 3.

[0101] refer to Figure 4 The embodiment of the present application provides a power timing system based on the Shenwei processor on the basis of the power timing device. The system is applied in Figure 1 The CPU board specifically includes:

[0102] A time parsing unit is used to receive and parse time message information from multiple time sources to obtain time information and second signals of each time source; a time difference measurement unit is used to measure the time difference between the second signal of each time source and the locally generated second signal to obtain time difference measurement information; a time source selection unit is used to obtain the time source priority set by the user, select a time source according to the time information and the time source priority, and output a source selection result; a calibration parameter calculation unit is used to estimate the time frequency deviation of the corresponding time source according to the time difference measurement information, the source selection result and the preset time compensation parameters, and output the time frequency calibration parameters; a time synchronization unit is used to synchronize the time information and the second signal phase of the available time sources according to the source selection result and the time frequency calibration parameters, and output the synchronized time information and second signal.

[0103] Preferably, the system further comprises a BDS decoding module and a B code decoding module, wherein the BDS decoding module is used to receive and decode satellite message information sent by a satellite time source; the B code decoding module is used to receive an IRIG_B time code signal and perform a decoding operation to obtain symbol information and a second punctual edge; the time parsing unit is used to identify the validity of the satellite time source according to the satellite message information, and parse out the first year, month, day, hour, minute, and second information and position information; and parse the symbol information to obtain the second year, month, day, hour, minute, and second information and time validity status information of the IRIG_B time code signal.

[0104] More specifically, the time synchronization unit includes a time generation and synchronization unit and a second signal generation and synchronization unit, wherein the time generation and synchronization unit is used to correct the deviation of the time information according to the source selection result and the time frequency calibration parameter; and the second signal generated is phase synchronized by the second signal generation and synchronization unit.

[0105] Preferably, the system also includes a management and configuration unit, a serial time encoding unit, a serial time signal generating unit and a network timing service unit, wherein the management and configuration unit is used to obtain parameters and configuration requirements set by the user; the serial time encoding unit is used to compile the synchronized time information into relevant serial time codes according to the configuration requirements to obtain the time information code; the serial time signal generating unit is used to superimpose the time information code with the second punctual edge, and modulate it according to the pulse modulation requirements of the serial time code, and distribute the modulated signal to output modules with different electrical characteristics; the network timing service unit is used to encode and time the calibrated time information and second information according to the NTP and SNTP protocol requirements.

[0106] In one embodiment, this embodiment combines Figure 3 and Figure 4 To explain, the time analysis function is completed by the CPU and FPGA together. The FPGA analyzes the code element information and second time edge of IRIG_B, and sends the analyzed code element information of IRIG_B code to the time analysis unit of the CPU. Finally, the time analysis unit of the CPU obtains the time information such as year, month, day, hour, minute, and second in the code element as well as the time validity status information.

[0107] The time difference measurement function is realized by the time difference measurement unit embedded in the FPGA (field programmable gate array). This unit is responsible for measuring the phase difference between two IRIG_B code second signals, one FPGA second signal and the second signal generated by the synchronization unit. After obtaining the three-way second difference measurement data, the FPGA sends these data to the CPU's time frequency calibration parameter calculation unit to ensure that the CPU's time frequency calibration parameter calculation unit can provide accurate calibration parameters for the time frequency, which is an important data basis for device time synchronization.

[0108] refer to Figure 5Time synchronization includes the synchronization of year, month, day, hour, minute, and second time information and the phase synchronization of the second signal. The year, month, day, hour, minute, and second information that needs to be synchronized is generated by the CPU time generation and synchronization unit; the second signal that needs phase synchronization is generated by the FPGA second signal generation and synchronization unit. The synchronization process is to select the source first, and then realize the synchronization of time information and second signal according to the time frequency deviation estimation result. First, the CPU time source selection unit comprehensively evaluates and selects the time source according to the validity of the time source, the measurement information of the time difference measurement unit, and the time source priority provided by the CPU management and configuration unit. After the time source is selected, the CPU time frequency deviation estimation unit has three reference second difference information and two external time base time information (time source status information, such as: whether the satellite is synchronized, whether the time source is valid, and UTC time information). The mathematical calculation method can be used to obtain the determined relationship between the two time bases. The system uses standard deviation to estimate the deviation of multiple measurement values, corrects the deviation of year, month, day, hour, minute, and second through the CPU time generation and synchronization unit, and uses interpolation to give the deviation estimation value to the FPGA second signal generation and synchronization unit to perform phase synchronization on the generated second.

[0109] When high precision is required, a better crystal oscillator is configured. The system can use the Kalman filter to smooth the jitter of the standard signal. The coherent complementation of each time reference can obtain a time parameter with better performance. The phase synchronization accuracy is controlled by ultra-fine frequency fine-tuning to overcome the jitter of the output signal phase when the phase shift mode time synchronization is used.

[0110] The time output function is performed by the serial time encoding unit of the CPU according to the configuration requirements of the management configuration unit to compile the calibrated time information into relevant serial time codes, such as serial port times in different formats, B code information in different specifications, and DCF77 encoding. The time information is encoded and given to the serial time signal generation unit of the FPGA, superimposed on the second punctual edge and modulated according to the pulse modulation requirements of the serial time code, and the modulated signal is distributed to output modules with different electrical characteristics. The network timing service unit of the CPU encodes and synchronizes the calibrated time information and the second signal according to the requirements of the NTP and SNTP protocols.

[0111] Status information output and parameter configuration are realized by the management and configuration unit of the CPU through the serial port and the network port to realize local management and remote management. Local management realizes parameter configuration and status display by controlling the LCD display and the on and off of the status light through the corresponding buttons of the human-machine interaction board. Remote management realizes remote parameter configuration and status display through 61850 or WEB or SNMP protocol, and can also realize the upgrade function.

[0112] In summary, the timing device, system and method provided by this application have the following technical effects:

[0113] 1. Improve timing accuracy to a higher level

[0114] With its powerful computing power and parallel processing performance, the Shenwei processor can significantly improve the computing efficiency and processing accuracy of the Beidou SBAS timing system. In terms of fast signal processing capabilities, the multi-core architecture and high main frequency operation capabilities of the Shenwei processor enable it to quickly process timing data from Beidou satellites and ground augmentation stations, and correct errors in real time. In terms of high-precision algorithm implementation, compared with traditional processors, Shenwei can more efficiently process complex time synchronization algorithms and reduce timing errors. ① High-precision algorithm implementation. The Shenwei system can support the implementation of high-precision timing algorithms. The improvement of timing accuracy depends on the execution of complex differential calibration algorithms. These algorithms can more accurately calculate time synchronization errors and make corresponding corrections through complex mathematical calculations and model optimization. The implementation of this high-precision algorithm depends on the powerful computing power and accuracy guarantee of the Shenwei processor. ② Adaptive algorithm implementation. In actual applications, timing signals may be affected by many factors, such as electromagnetic interference, atmospheric propagation delay, etc. The Shenwei system supports the implementation of adaptive algorithms, which can automatically adjust parameters and calculation models according to real-time conditions to adapt to different timing environments and conditions, thereby improving timing accuracy and stability. Specifically, the signal delay and in the Beidou SBAS system are monitored and corrected in real time, and various error sources such as atmospheric delay, ionospheric influence, and receiving equipment deviation are quickly corrected through complex timing algorithms. In traditional systems, due to limited computing resources, error correction has a certain delay. The high-performance parallel computing of the Shenwei processor can reduce this delay to an extremely low level, thereby effectively reducing the timing deviation. ③ Algorithm optimization. The Shenwei processor supports a variety of algorithm optimization technologies, such as loop unrolling, memory access optimization, and instruction reordering. These optimization technologies can further improve the execution efficiency of the timing algorithm, and can accurately control and correct the clock drift through the algorithm to ensure that the clocks between different timing devices remain consistent, avoiding system uncertainty caused by the accumulation of time errors after long-term operation. In summary, the high-performance computing power of the Shenwei system has shown significant advantages in fast signal processing and precise algorithm implementation. These advantages enable the Shenwei system to provide more accurate and stable time synchronization services in SBAS timing applications to meet various high-precision timing requirements.

[0115] 2. Improve system security and autonomous control

[0116] ①Autonomy and controllability: Shenwei processor is a high-performance processor independently developed by China. Combined with the Beidou SBAS system, it has formed a completely autonomous and controllable hardware and software platform, getting rid of dependence on foreign processors and timing systems, and ensuring the independence and security of the power system timing.

[0117] ②Prevent external risks: Traditional power timing systems rely on imported processors and foreign timing services such as GPS, which may face risks such as signal interruption, malicious attacks or data leakage. By using Shenwei processors, the Beidou SBAS timing system can achieve stable and reliable time synchronization without external dependence, ensuring the security of critical infrastructure, especially in the national power system, where this autonomous controllability is particularly important.

[0118] ③ High-security design: The Shenwei processor adopts multiple encryption and security protection measures, which can effectively prevent network attacks and data tampering, ensure the safe operation of the timing device in a complex power environment, and further enhance the credibility of the timing system. The "Trusted Computing Module" (TCM) of the Shenwei processor is one of the important components in the Shenwei processor architecture for enhancing system security. Through the combination of hardware and software, the Shenwei processor is provided with security functions such as data integrity verification, identity authentication, and encrypted storage to ensure the autonomous controllability of the computing platform and its ability to resist external attacks.

[0119] The trusted computing module of the Shenwei processor usually has an independent security chip built in, which has independent processing capabilities for performing encryption operations, key management and authentication operations. By placing key security operations (this system puts key algorithms such as the time source validity verification algorithm and the differential calibration high-precision algorithm into it to prevent the time source from being tampered with or maliciously attacked at will) in an independent hardware chip, the TCM can reduce the possibility of the main processor being attacked or tampered with by malicious code, thereby improving the overall security of the system. The core of the trusted computing module is the root of trust, which is a highly trusted and tamper-proof hardware component. The root of trust ensures that the hardware and software started are verified by executing a trusted boot process when the system starts. The root of trust of the Shenwei processor generates and stores keys through an independent hardware module to prevent unauthorized access.

[0120] 3. Further enhance the device's anti-interference ability

[0121] ① Anti-interference design: The Sunway processor is optimized for complex power environments and has strong anti-interference capabilities. In power systems, timing devices are often affected by adverse factors such as electromagnetic interference and environmental changes, resulting in time synchronization errors. The hardware design and algorithm optimization of the Sunway processor can resist electromagnetic interference in the power system, ensuring that the accuracy of the timing system can be maintained in harsh environments.

[0122] ② Stability in complex environments: Beidou SBAS signals may be interfered by natural environment, electromagnetic fields and other factors during transmission, resulting in signal instability or time deviation. The design of the Sunway processor enhances the signal processing capability of the timing device under these complex conditions, and can perform error correction and dynamic adjustment in real time to ensure that the timing system always operates stably, and can still provide accurate time signals even in power facilities or remote areas with severe electromagnetic interference.

[0123] Through these three aspects, the application of Shenwei processors has enabled the Beidou SBAS power timing system to achieve significant advantages in accuracy, security and anti-interference capabilities, and can well meet the strict requirements of modern power systems for high-precision timing.

[0124] Can

[0125] It should be noted that the timing system and device provided in the present embodiment are used to implement the above-mentioned implementation mode, and those that have been described will not be repeated. As used above, the terms "module", "unit", "subunit" and the like can implement a combination of software and / or hardware of a predetermined function. Although the device described in the above embodiment is preferably implemented with software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0126] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a program stored thereon, and when the program is executed by a processor, the power timing method based on the Shenwei processor provided in the first aspect is implemented.

[0127] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0128] In a possible implementation, the present invention can also be implemented in the form of a program product, which includes a program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of the power timing method based on the Shenwei processor provided in the first aspect.

[0129] The program code for executing the present invention may be written in any combination of one or more programming languages, and may be executed entirely on a user device, partially on a user device, as an independent software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0130] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A power timing method based on Shenwei processor, characterized in that: Applications in power timing systems with Sunway processors include: Receive time message information from multiple time sources and parse them to obtain the time information and second signal of each time source; The time difference between the second signal of each time source and the second signal generated locally is measured to obtain the time difference measurement information; Obtain the time source priority set by the user, select a time source according to the time information and the time source priority, and output the source selection result; According to the time difference measurement information, the source selection result and the preset time compensation parameters, the time frequency deviation of the corresponding time source is estimated, and the time frequency calibration parameters are output; The available time source is synchronized with the time information and the second signal phase according to the source selection result and the time frequency calibration parameter, and the synchronized time information and second signal are output.

2. The electric power timing method according to claim 1, characterized in that: The receiving and parsing of time message information from multiple time sources to obtain time information and second signals from each time source includes: Receive satellite message information sent by a satellite time source, identify the validity of the satellite time source according to the satellite message information, and parse out the first year, month, day, hour, minute, second information and position information; Receive IRIG_B time code signal and perform decoding operation to obtain code element information and second time edge; The code element information is parsed to obtain the second year, month, day, hour, minute, and second information and time validity status information of the IRIG_B time code signal.

3. The electric power timing method according to claim 2, characterized in that: The time difference measurement information includes a first second difference measurement value, a second second difference measurement value, and a third second difference measurement value. The time difference measurement is performed on the second signal of each time source and the second signal generated locally to obtain the time difference measurement information, including: Extract two BDS second signals from the first year-month-day hour-minute-second information, and perform time difference measurement based on the two BDS second signals to obtain a first second difference measurement value; Extract two IRIG_B code second signals from the second year-month-day-hour-minute-second information, and perform time difference measurement based on the two IRIG_B code second signals to obtain a second second difference measurement value; The phase difference between the second signals generated by the FPGA and the CPU is calculated to obtain the third second difference measurement value.

4. The electric power timing method according to claim 1, characterized in that: The method further comprises: If there is no available time source, the time information is maintained based on the locally generated seconds, which are maintained by the device's built-in frequency source, and the device enters a punctual state.

5. The electric power timing method according to claim 1, characterized in that: The output synchronized time information and second signal include: Obtaining the configuration requirements of the user, and compiling the synchronized time information into relevant serial time codes according to the configuration requirements to obtain the time information code; The time information is encoded and superimposed on the second punctual edge, and modulated according to the pulse modulation requirements of the serial time code, and the modulated signal is distributed to output modules with different electrical characteristics; The calibrated time information and second information are encoded and synchronized according to the NTP and SNTP protocol requirements.

6. A power timing system based on Shenwei processor, characterized in that: include: A time analysis unit is used to receive and analyze time message information from multiple time sources to obtain time information and second signals from each time source; A time difference measurement unit is used to measure the time difference between the second signal of each time source and the second signal generated locally to obtain time difference measurement information; A time source selection unit, configured to obtain a time source priority set by a user, select a time source according to the time information and the time source priority, and output a source selection result; A calibration parameter calculation unit, configured to estimate the time frequency deviation of the corresponding time source according to the time difference measurement information, the source selection result and the preset time compensation parameter, and output the time frequency calibration parameter; The time synchronization unit is used to synchronize the time information and the second signal phase of the available time source according to the source selection result and the time frequency calibration parameter, and output the synchronized time information and second signal.

7. The electric power timing system according to claim 6, characterized in that: The system also includes a BDS decoding module and a B code decoding module, wherein: The BDS decoding module is used to receive and decode satellite message information sent by the satellite time source; The B code decoding module is used to receive the IRIG_B time code signal and perform decoding operations to obtain code element information and second punctual edge; The time parsing unit is used to identify the validity of the satellite time source according to the satellite message information, and parse out the first year, month, day, hour, minute, second information and position information; and parse the code element information to obtain the second year, month, day, hour, minute, second information and time validity status information of the IRIG_B time code signal.

8. The electric power timing system according to claim 6, characterized in that: The time synchronization unit includes a time generation and synchronization unit and a second signal generation and synchronization unit, wherein: The time is generated by the synchronization unit for correcting the deviation of the time information according to the source selection result and the time frequency calibration parameter; The second signal is phase-synchronized by the second signal generation and synchronization unit.

9. The electric power timing system according to claim 6, characterized in that: The system also includes a management and configuration unit, a serial time encoding unit, a serial time signal generating unit and a network timing service unit, wherein: The management and configuration unit is used to obtain parameters and configuration requirements set by the user; The serial time encoding unit is used to compile the synchronized time information into relevant serial time codes according to the configuration requirements to obtain time information codes; The serial time signal generating unit is used to encode the time information and superimpose the second punctual edge, and modulate it according to the pulse modulation requirements of the serial time code, and distribute the modulated signal to output modules with different electrical characteristics; The network timing service unit is used to encode and time the calibrated time information and second information according to the NTP and SNTP protocol requirements.

10. A power timing device based on the Shenwei processor, characterized in that: include: A CPU board equipped with a Shenwei processor and an FPGA, used to execute the power timing method based on the Shenwei processor in any one of claims 1 to 5; A BOARD with two Beidou receiving modules is deployed to receive satellite message information sent by the Beidou system; Display control panel, used to display time information, power system status data and alarm data, and realize human-computer interaction function; The time output board is used to provide RS485, RS232, TTL, BAC, OC electrical interfaces and FIBER optical interfaces.

11. The electric timing device according to claim 10, characterized in that: The device also includes: The extended interface unit is used to convert the time information according to the type of the connected interface and output the time serial code in a corresponding format to the power system.

12. The electric timing device according to claim 11, characterized in that: The extended interface unit includes at least one time output module, and the time output module is an IRIG-B signal generating module, a pulse signal generating module, a DCF77 signal generating module, an NTP signal generating module or a PTP signal generating module.

13. The electric timing device according to claim 10, characterized in that: The CPU board also includes two Ethernet ports, an alarm contact, two optical signal input interfaces, and a serial port for communicating with a display control board.

14. The electric timing device according to claim 10, characterized in that: The BOARD also includes multiple slots for plugging various serial coded time output boards and multiple fixed programmable optical B code output interfaces.

15. The electric power timing device according to claim 10, characterized in that: The display control panel includes a status indicator light, an LED liquid crystal, buttons and an MCU.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by the processor, the power timing method based on the Shenwei processor as described in any one of claims 1 to 5 is implemented.

Images