Algorithm-agile post quantum cryptography system and working method thereof

Abstract

The invention provides an algorithm-agile post quantum cryptography system and a working method thereof.The system comprises a hardware platform and a software system, the hardware platform comprises a main processor, the main processor comprises a multi-core CPU, a GPU and a PCIe interface, and the software system comprises a password master control module, a PCIe-EP driving module, a PQC algorithm module, a GPU acceleration module and an algorithm upgrading module. The password master control module receives a PQC algorithm request message of an external host through the PCIe-EP driving module, sends the PQC algorithm request message to the PQC algorithm module and the GPU acceleration module for multi-thread asynchronous acceleration processing, and returns a processing result to the external host through the PCIe interface. According to the algorithm-agile post quantum cryptography system and the working method provided by the invention, the problems that a traditional password card cannot quickly support the PQC algorithm and cannot be quickly reconstructed when the PQC algorithm is updated in the process that the password system migrates to the post quantum cryptography can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of cryptographic cards, and more specifically, to an algorithmically agile post-quantum cryptographic system and a working method thereof. Background Art

[0002] With the rapid development of quantum computing technology, the quantum computing-based Shor algorithm can theoretically crack the currently widely used RSA (Rivest–Shamir–Adleman) and elliptic curve public key cryptography algorithms, which poses a huge challenge to traditional public key cryptography. On August 13, 2024, NIST (National Institute of Standards and Technology) released the first three PQC (Post-quantum cryptography) encryption standards to defend against network attacks from quantum computers. NIST is also continuing to evaluate and formulate other PQC algorithm standards. On November 12, 2024, NIST released a draft strategy for "transitioning to post-quantum cryptography standards", emphasizing the urgency of protecting the security of critical systems before the emergence of quantum computing capabilities. At the same time, my country's cryptographic standardization agencies are also actively evaluating and formulating their own PQC algorithm standards and migration plans.

[0003] The cryptographic industry urgently needs to migrate to the PQC standard. However, the current international and domestic PQC cryptographic standards are still in the process of standard formulation and revision experiments. Therefore, cryptographic equipment (including cryptographic cards) is required to support emerging PQC algorithms as soon as possible and have agile characteristics, that is, to quickly implement new algorithms and be able to quickly revise and reconstruct them when the algorithms change.

[0004] In the cryptographic equipment industry, the solutions for implementing a new cryptographic algorithm in a cryptographic card include: (1) first developing a dedicated algorithm chip, and then designing a new cryptographic card based on the dedicated algorithm chip; (2) designing a new algorithm module based on FPGA hardware programming; (3) designing a new algorithm module through software development based on the programmability of general-purpose CPUs and GPUs. Solution (1) includes chip development and cryptographic card development, and the product development cycle is usually more than 2 years; Solution (2) is essentially a programmable hardware development, involving algorithm logic programming in hardware description language, parallel processing of complex logic, performance tuning, and hardware simulation. Each link has high barriers and low efficiency, and the product development cycle is usually more than half a year; Solution (3) is software programming based on high-level languages, and the development efficiency is more than 3 times that of Solution (2), and the product development cycle is usually about 1-2 months.

[0005] Through the software programming method based on general-purpose CPUs and GPUs in solution (3), it is possible to quickly develop and deploy emerging PQC algorithms, allowing cryptographic cards to respond more quickly to changes in standards and ensure information security in the quantum era.

[0006] In summary, in order to cope with the security challenges brought by quantum computing, an efficient and flexible method is urgently needed to implement and support the PQC algorithm to meet the needs of cryptographic equipment to quickly adapt to new standards. Summary of the invention

[0007] In view of this, the present invention provides an algorithm-agile post-quantum cryptographic system and a working method thereof, aiming to solve the problem that traditional cryptographic cards cannot quickly support the PQC algorithm and cannot be quickly reconstructed when the PQC algorithm is updated during the migration of the cryptographic system to post-quantum cryptography.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A working method of an algorithm-agile post-quantum cryptographic system, characterized in that the working method of the algorithm-agile post-quantum cryptographic system comprises:

[0010] Step S1, the main processor receives a service request message sent by an external host through a PCIe interface through a PCIe-EP driver module;

[0011] Step S2, the main processor parses the service request message through the password main control module and determines the message type; if the message is a PQC algorithm request, the message is sent to the PQC algorithm module for multi-threaded asynchronous processing, the PQC algorithm module accelerates the calculation process through the GPU acceleration module, the password main control module asynchronously obtains the processing result from the PQC algorithm module, and then constructs a service response message; if the message is a key management request, the key management operation logic is completed to form a key result, and the key result is updated to the storage unit through the peripheral interface module, and then a service response message is constructed;

[0012] Step S3: After receiving the service response message through the cryptographic main control module, the main processor returns the service response message to the external host through the PCIe interface via the PCIe-EP driver module.

[0013] Further, if the message is a PQC algorithm request, the multi-threaded asynchronous processing in step S2 includes:

[0014] Step S21, after receiving the PQC algorithm request message, the PQC algorithm module analyzes the PQC algorithm request message and selects a specific PQC algorithm logic to perform algorithm calculation;

[0015] Step S22, the PQC algorithm module splits the sub-logic process that consumes the most computing power in the PQC algorithm logic, and calls multiple concurrent acceleration requests to send them to the GPU acceleration module;

[0016] Step S23, the GPU acceleration module converts the acceleration request into an acceleration instruction based on the opencl kernel algorithm function, and sends it to the GPU for calculation through an asynchronous concurrent mode;

[0017] Step S24, the GPU returns the opencl calculation result to the GPU acceleration module through an asynchronous event;

[0018] Step S25, the GPU acceleration module returns the accelerated calculation result to the PQC algorithm module, and the PQC algorithm module completes the complete PQC algorithm calculation process;

[0019] Step S26: The PQC algorithm module sends the final calculation result back to the password main control module.

[0020] Furthermore, the step S2 includes: if the message is a classic algorithm request, sending the message to the classic algorithm chip for processing through the peripheral interface module, obtaining the processing result and constructing a business response message.

[0021] Furthermore, the working method of the algorithm-agile post-quantum cryptographic system includes: when a new PQC algorithm is released, the external host sends an algorithm upgrade request message to the main processor through the PCIe interface, and the main processor implements online upgrade of the software algorithm of the PQC algorithm module through the algorithm upgrade module.

[0022] An algorithm-agile post-quantum cryptographic system, used to implement the working method of the algorithm-agile post-quantum cryptographic system provided by the present invention, characterized in that it includes: a hardware platform and a software system; the hardware platform includes a main processor, a storage unit and a random number chip; the main processor includes a multi-core CPU, a GPU and a PCIe interface;

[0023] The software system includes an operating system and a control program, and the control program includes a cryptographic master control module, a PCIe-EP driver module, a peripheral interface module, a PQC algorithm module, a GPU acceleration module and an algorithm upgrade module; the cryptographic master control module is used to receive and process business requests from an external host to implement key management and cryptographic operation control logic; the PCIe-EP driver module is used to implement data communication between the cryptographic master control module and the external host based on the PCIe interface; the peripheral interface module is used to manage the drive of the storage unit, the random number chip and the external USB device; the PQC algorithm module is used to implement various PQC algorithms and support multi-threaded operation; the GPU acceleration module is connected to the GPU inside the main processor through a high-speed communication interface and shared memory, and is used to implement parallel acceleration of the most computing-intensive sub-logic processes in various PQC algorithms; the algorithm upgrade module is used to implement online upgrades of the software algorithms of the PQC algorithm module.

[0024] Furthermore, the main processor adopts a processor with model RK3588 or RK3568.

[0025] Furthermore, the hardware platform also includes a USB interface for connecting an external USB KEY or USB card reader to implement login, management, and key backup and recovery of the password card.

[0026] Furthermore, the hardware platform also includes a classic algorithm chip, which is a special algorithm chip that has passed the review of the National Cryptography Bureau and is used to implement classic national cryptography and international algorithms. The peripheral interface module is also used to drive and manage the classic algorithm chip.

[0027] The algorithm-agile post-quantum cryptographic system and its working method provided by the present invention have the following beneficial effects:

[0028] 1. The cost-effective main processor's self-integrated PCIe interface simply and efficiently implements the external PCIe interface function of the password card, reducing hardware costs, shortening the development cycle, and improving development efficiency.

[0029] 2. Software programming based on high-level languages, such as C / C++ programming and opencl programming, shortens the development cycle of the emerging PQC algorithm in the cryptographic card, improves development efficiency, and enables rapid development or reconstruction of the cryptographic card to support the PQC algorithm.

[0030] 3. The algorithm operation speed is improved through the multi-core high-performance CPU and GPU acceleration of the main processor, combined with multi-threading and asynchronous processing.

[0031] 4. The algorithm upgrade module enables online real-time updates of emerging PQC algorithms, allowing the cryptographic card to respond more quickly to changes in PQC standards to ensure information security in the quantum era.

[0032] 5. Compatibility with traditional classic cryptographic algorithms is achieved through external classic algorithm chips.

[0033] Accordingly, the present invention provides an algorithm-agile post-quantum cryptographic system and its working method, which can solve the problem that traditional cryptographic cards cannot quickly support PQC algorithms and cannot be quickly reconstructed when the PQC algorithm is updated during the migration of cryptographic systems to post-quantum cryptography, so that cryptographic cards can respond to changes in PQC standards more quickly to ensure information security in the quantum era. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a logic block diagram of an algorithm-agile post-quantum cryptographic system provided by an embodiment of the present invention;

[0035] Figure 2 Schematic diagram of a working method of an algorithm-agile post-quantum cryptographic system provided by an embodiment of the present invention;

[0036] Figure 3 It is a schematic diagram of the PQC algorithm business process provided by an embodiment of the present invention;

[0037] Figure 4 The figure is a schematic diagram of the interaction process of the PQC algorithm module, the GPU acceleration module and the GPU provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] The cryptographic industry urgently needs to migrate to the PQC standard. However, the current international and domestic PQC cryptographic standards are still in the process of standard formulation and revision experiments. The embodiment of the present invention provides an algorithm-agile post-quantum cryptographic system and a working method thereof, which are intended to support emerging PQC algorithms as quickly as possible and have agile characteristics, that is, to quickly implement new algorithms and be able to quickly revise and reconstruct them when the algorithms change.

[0040] like Figure 1As shown, an embodiment of the present invention provides an algorithm-agile post-quantum cryptographic system, including a hardware platform and a software system; the hardware platform includes a main processor, a storage unit and a random number chip; the main processor includes a multi-core CPU, a GPU and a PCIe interface, and the PCIe interface is used to realize data communication between the main processor and an external host, and the external host is a general host, such as a server, an industrial computer, an office computer, etc. In actual scenarios, a password card is usually inserted into the external host through the PCIe interface, and data communication is performed with the password card through the SDK-API on the external host. The main processor is mainly used for external interface control, key management and PQC algorithm implementation, and is the main function implementation carrier of the password card. In an embodiment of the present invention, the main processor adopts a processor of model RK3588 or RK3568, or other similar processors including a multi-core CPU, a GPU and a PCIe interface. Among them, RK3588 includes an 8-core high-performance ARM CPU (4-core A76 and 4-core A55, CPU computing power is 9300DMIPS) and a Mali-G610 MC4 GPU (GPU floating point computing power is 512G FLOPS-FP32). RK3588 uses PCIe3.0 PHY0+PCIe3.0 PHY1 to form a 4Lane PCIe3.0 X4 EP mode interface to realize the data communication channel with the external host.

[0041] The storage unit includes a high-speed dynamic memory, a program boot memory and a main memory. The storage unit is connected to the main processor through a storage signal port. The high-speed dynamic memory can be implemented with dual-channel DDR4, the program boot memory can be implemented with QSPI NOR-FLASH, and is used to store bootloader and uboot. The main memory can be implemented with eMMC, and is used to store system kernel / file system and key data. In an embodiment of the present invention, the random number chip is a two-channel TRNG hard random number chip, which is connected to the main processor through GPIO, such as RK3588, and is used to generate random numbers. The random numbers are transmitted back to the main processor for PQC algorithm or classic algorithm operation.

[0042] Traditional PCIe cryptographic cards mostly use relatively complex FPGA or dedicated chip solutions to implement PCIe interfaces, which have long development cycles and low development efficiency. The above-mentioned main processor, such as RK3588, simply and efficiently implements the external PCIe interface function of the cryptographic card through the PCIe interface, reducing hardware costs, shortening development cycles, and improving development efficiency.

[0043] The software system includes an operating system and a control program, and the control program includes a password master control module, a PCIe-EP driver module, a peripheral interface module, a PQC algorithm module, a GPU acceleration module, and an algorithm upgrade module. In some embodiments of the present invention, a tailored Linux system and a password card control program are run on the main processor RK3588, including an external interface (PCIe / USB), key management, PQC algorithm implementation, etc.

[0044] The cryptographic master control module is used to receive and process the service request of the external host, and implement key management and cryptographic operation control logic; the PCIe-EP driver module is used to implement data communication between the cryptographic master control module and the external host based on the PCIe interface. In some embodiments of the present invention, the PCIe-EP driver module and the external host realize efficient data reception and transmission through IO memory mapping and DMA data movement, synchronize the receiving and transmitting cache addresses of both parties through the PCIe-BAR0 register, and realize real-time and efficient data processing through a dedicated polling thread.

[0045] The peripheral interface module is used for driver management of the storage unit, the random number chip and the external USB device. The PQC algorithm module is used to implement various PQC algorithms such as CRYSTALS-Kyber, CRYSTALS-Dilithium, Sphincs+, etc., and supports multi-threaded operation. The GPU acceleration module is connected to the GPU inside the main processor through a high-speed communication interface and shared memory, and controls and schedules the GPU through a standard opencl API interface in software, so as to realize parallel acceleration of the most computing-intensive sub-logic processes in various PQC algorithms. In an embodiment of the present invention, the high-speed communication interface is the AXI (Advanced eXtensible Interface) high-speed bus and DMA in RK3588, and the sub-logic process is polynomial multiplication, NTT transformation, etc. The algorithm upgrade module is used to realize online upgrade of the software algorithm of the PQC algorithm module.

[0046] The above software system is based on high-level language programming, such as C / C++ programming and opencl programming, which shortens the development cycle of emerging PQC algorithms in password cards, improves development efficiency, and realizes rapid development or reconstruction of the password card to support the PQC algorithm; through the high-performance CPU and GPU acceleration of the main processor, the algorithm operation speed is improved; through the algorithm upgrade module, the online real-time update of the emerging PQC algorithm is realized.

[0047] In some embodiments of the present invention, the hardware platform further includes a USB interface for connecting an external USB KEY or USB card reader to implement login, management, and key backup and recovery of the password card. For example, a USB KEY or USB card reader is connected to the USB2.0 interface on RK3588.

[0048] In some embodiments of the present invention, the hardware platform also includes a classic algorithm chip, that is, a dedicated algorithm chip that has been reviewed by the National Cryptography Bureau, for implementing classic national cryptography and international algorithms, and the peripheral interface module is also used to drive and manage the classic algorithm chip. For example, the classic algorithm chip is connected to RK3588 through a PCIe2.0 or USB interface to implement classic national cryptography such as SM1, SM2, SM3, SM4 and international algorithms such as AES, SHA, and RSA.

[0049] The present invention supports the PQC algorithm and also achieves compatibility with traditional classical cryptographic algorithms by externally connecting a classical algorithm chip.

[0050] like Figure 2 FIG. 1 is a schematic diagram of a working method of an algorithm-agile post-quantum cryptographic system provided by an embodiment of the present invention. The method of this embodiment may include the following steps:

[0051] Step S1, the main processor receives a service request message sent by an external host through a PCIe interface through a PCIe-EP driver module; the service request message is an instruction including key management, data encryption, data decryption, etc. transmitted between the password card and the external host;

[0052] Step S2, the main processor parses the service request message through the password main control module and determines the message type; if the message is a PQC algorithm request, the message is sent to the PQC algorithm module for multi-threaded asynchronous processing, the PQC algorithm module accelerates the calculation process through the GPU acceleration module, the password main control module asynchronously obtains the processing result from the PQC algorithm module, and then constructs a service response message; if the message is a key management request, the key management operation logic is completed to form a key result, the key management operation logic includes key generation, modification, deletion, query, and the key result is updated to the storage unit, that is, the eMMC main memory chip, through the peripheral interface module, and then a service response message is constructed;

[0053] Step S3: After receiving the service response message through the cryptographic main control module, the main processor returns the service response message to the external host through the PCIe interface via the PCIe-EP driver module.

[0054] Figure 3 is a schematic diagram of the PQC algorithm business process provided by an embodiment of the present invention, Figure 4 1 is a schematic diagram of the interaction process of the PQC algorithm module, the GPU acceleration module and the GPU provided in an embodiment of the present invention. If the message is a PQC algorithm request, the multi-threaded asynchronous processing in step S2 further includes:

[0055] Step S21, after receiving the PQC algorithm request message, the PQC algorithm module analyzes the PQC algorithm request message and selects a specific PQC algorithm logic to perform algorithm calculation;

[0056] Step S22, the PQC algorithm module splits the most computationally intensive sub-logic processes in the PQC algorithm logic, such as NTT and inverse NTT transformations, and calls multiple concurrent NTT / inverse NTT transformation acceleration requests to send to the GPU acceleration module;

[0057] Step S23, the GPU acceleration module converts the NTT / inverse NTT transformation acceleration request into an acceleration instruction based on an opencl kernel algorithm function, and sends it to the GPU for calculation through an asynchronous concurrent mode;

[0058] Step S24, the GPU returns the opencl calculation result to the GPU acceleration module through an asynchronous event;

[0059] Step S25, the GPU acceleration module returns the NTT / inverse NTT transformation acceleration calculation result to the PQC algorithm module, and the PQC algorithm module completes the complete PQC algorithm calculation process;

[0060] Step S26: The PQC algorithm module sends the final calculation result back to the password main control module.

[0061] Asynchronous processing allows the program to perform other tasks while waiting for encryption or decryption, which can improve overall computing efficiency; GPU parallel acceleration can quickly process computing-intensive tasks; multi-threading can optimize data processing and GPU interaction. The combination of multi-core CPU and multi-threading, as well as the coordination of multi-threading and asynchronous processing, provides powerful computing support for the PQC algorithm, which can achieve significant performance improvements in computing-intensive tasks and large-scale parallel processing.

[0062] In an embodiment of the present invention, the step S2 includes: if the message is a classic algorithm request, sending the message to the classic algorithm chip for processing through the peripheral interface module, obtaining the processing result and constructing a business response message.

[0063] In the embodiment of the present invention, when a new PQC algorithm is released, the external host sends an algorithm upgrade request message to the main processor through the PCIe interface, and the main processor implements online upgrade of the software algorithm of the PQC algorithm module through the algorithm upgrade module.

[0064] The online upgrade of the software algorithm of the above-mentioned PQC algorithm module further includes: the upgrade request message is sent to the algorithm upgrade module for processing through the PCIe-EP driver module, and the algorithm upgrade module and the external host complete the acquisition of the new PQC algorithm module file through multiple interactions, replace the previous PQC algorithm module and make it run again. In the embodiment of the present invention, the upgrade packages of the PQC algorithm module and the password master control module are usually binary executable files. The algorithm file of the GPU acceleration module is usually an opencl file, which can be dynamically loaded through the PQC algorithm module. If the newly added PQC algorithm is significantly different from the existing data structure, the interface between the password master control module and the PQC algorithm module may also need to be modified accordingly. At this time, the password master control module can be upgraded synchronously. Because the embodiment of the present invention adopts a general CPU+GPU architecture and is developed in a high-level language, after the PQC algorithm is upgraded, the existing code can be quickly reconstructed to adapt to the new algorithm.

[0065] The algorithm-agile post-quantum cryptographic system and its working method provided by the present invention have the following beneficial effects:

[0066] 1. The cost-effective main processor's self-integrated PCIe interface simply and efficiently implements the external PCIe interface function of the password card, reducing hardware costs, shortening the development cycle, and improving development efficiency.

[0067] 2. Software programming based on high-level languages, such as C / C++ programming and opencl programming, shortens the development cycle of the emerging PQC algorithm in the cryptographic card, improves development efficiency, and enables rapid development or reconstruction of the cryptographic card to support the PQC algorithm.

[0068] 3. The algorithm operation speed is improved through the multi-core high-performance CPU and GPU acceleration of the main processor, combined with multi-threading and asynchronous processing.

[0069] 4. The algorithm upgrade module enables online real-time updates of emerging PQC algorithms, allowing the cryptographic card to respond more quickly to changes in PQC standards to ensure information security in the quantum era.

[0070] 5. Compatibility with traditional classic cryptographic algorithms is achieved through external classic algorithm chips.

[0071] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for operating an algorithmically agile post-quantum cryptographic system, characterized in that: The working method of the algorithm-agile post-quantum cryptographic system includes: Step S1, the main processor receives a service request message sent by an external host through a PCIe interface through a PCIe-EP driver module; Step S2, the main processor parses the service request message through the password main control module and determines the message type; if the message is a PQC algorithm request, the message is sent to the PQC algorithm module for multi-threaded asynchronous processing, the PQC algorithm module accelerates the calculation process through the GPU acceleration module, the password main control module asynchronously obtains the processing result from the PQC algorithm module, and then constructs a service response message; if the message is a key management request, the key management operation logic is completed to form a key result, and the key result is updated to the storage unit through the peripheral interface module, and then a service response message is constructed; Step S3: After receiving the service response message through the cryptographic main control module, the main processor returns the service response message to the external host through the PCIe interface via the PCIe-EP driver module.

2. The method for operating an algorithm-agile post-quantum cryptographic system according to claim 1, characterized in that: If the message is a PQC algorithm request, the multi-thread asynchronous processing in step S2 further includes: Step S21, after receiving the PQC algorithm request message, the PQC algorithm module analyzes the PQC algorithm request message and selects a specific PQC algorithm logic to perform algorithm calculation; Step S22, the PQC algorithm module splits the sub-logic process that consumes the most computing power in the PQC algorithm logic, and calls multiple concurrent acceleration requests to send them to the GPU acceleration module; Step S23, the GPU acceleration module converts the acceleration request into an acceleration instruction based on the opencl kernel algorithm function, and sends it to the GPU for calculation through an asynchronous concurrent mode; Step S24, the GPU returns the opencl calculation result to the GPU acceleration module through an asynchronous event; Step S25, the GPU acceleration module returns the accelerated calculation result to the PQC algorithm module, and the PQC algorithm module completes the complete PQC algorithm calculation process; Step S26: The PQC algorithm module sends the final calculation result back to the password main control module.

3. The method for operating an algorithm-agile post-quantum cryptographic system according to claim 1, characterized in that: The step S2 further includes: if the message is a classic algorithm request, sending the message to the classic algorithm chip for processing through the peripheral interface module, obtaining the processing result and constructing a business response message.

4. The method for operating an algorithm-agile post-quantum cryptographic system according to claim 1, characterized in that: The working method of the algorithm-agile post-quantum cryptographic system further includes: when a new PQC algorithm is released, the external host sends an algorithm upgrade request message to the main processor through the PCIe interface, and the main processor implements online upgrade of the software algorithm of the PQC algorithm module through the algorithm upgrade module.

5. An algorithm-agile post-quantum cryptographic system, used to implement the working method of the algorithm-agile post-quantum cryptographic system described in any one of claims 1 to 4, characterized in that: include: Hardware platform and software system; the hardware platform includes a main processor, a storage unit and a random number chip; the main processor includes a multi-core CPU, a GPU and a PCIe interface; The software system includes an operating system and a control program, and the control program includes a cryptographic master control module, a PCIe-EP driver module, a peripheral interface module, a PQC algorithm module, a GPU acceleration module and an algorithm upgrade module; the cryptographic master control module is used to receive and process business requests from an external host and implement key management and cryptographic operation control logic; the PCIe-EP driver module is used to implement data communication between the cryptographic master control module and the external host based on the PCIe interface; the peripheral interface module is used to manage the drive of the storage unit, the random number chip and the external USB device; the PQC algorithm module is used to implement various PQC algorithms and support multi-threaded operation; the GPU acceleration module is connected to the GPU inside the main processor through a high-speed communication interface and a shared memory, and is used to implement parallel acceleration of the most computing-intensive sub-logic processes in various PQC algorithms; The algorithm upgrade module is used to implement online upgrade of the software algorithm of the PQC algorithm module.

6. The algorithm-agile post-quantum cryptographic system according to claim 5, characterized in that: The main processor adopts a processor of model RK3588 or RK3568.

7. The algorithm-agile post-quantum cryptographic system according to claim 5, characterized in that: The hardware platform also includes a USB interface for connecting an external USB KEY or USB card reader to implement login, management, and key backup and recovery of the password card.

8. The algorithm-agile post-quantum cryptographic system according to claim 5, characterized in that: The hardware platform also includes a classic algorithm chip, which is a special algorithm chip that has passed the review of the National Cryptography Bureau and is used to implement classic national cryptography and international algorithms. The peripheral interface module is also used to drive and manage the classic algorithm chip.

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