Low-complexity ocdm modulation and demodulation implementation method based on FPGA

Abstract

The application relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA, and belongs to the technical field of electronic communication. The DFnT or IDFnT is split into twice rotation factor multiplication, FFT or IFFT transformation, phase and amplitude adjustment steps to realize OCDM modulation and demodulation. The IQ data module is used to input IQ data to be subjected to DFnT or IDFnT transformation; the first rotation factor multiplication module is used to multiply the first rotation factor after phase rotation with the input data; the FFT or IFFT module is used to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; then, the data is subjected to second rotation factor multiplication; finally, the phase and amplitude are adjusted to complete OCDM modulation or demodulation. The application provides an OCDM modulation and demodulation scheme based on FPGA, and the storage capacity is reduced under the condition of invariable complexity.

Description

Technical Field

[0001] This invention belongs to the field of electronic communication technology and relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA. Background Technology

[0002] OCDM (Orthogonal Chirp Division Multiplexing) is a multi-carrier modulation scheme proposed in recent years. OCDM constructs a multi-carrier waveform with linear frequency modulated signals as subcarriers using the Discrete Fresnel Transform (DFnT). By selecting appropriate parameters, orthogonality between subcarriers is ensured, achieving error-free information transmission. Compared to the current mainstream Orthogonal Frequency Division Multiplexing (OFDM), OCDM exhibits stronger robustness to frequency-selective channels, lower bit error rates under various equalization methods, and better performance against multipath propagation, inter-symbol interference, and narrowband interference. Therefore, OCDM has become one of the representative new technologies in the physical layer of wireless communication in recent years. Research on OCDM modulation and demodulation is not only of great significance to current 5G communication, but also provides guidance for future 6G and non-terrestrial network communication towards higher spectral efficiency, higher reliability, and lower latency.

[0003] Currently, most research on OCDM technology, both domestically and internationally, is still in the software theoretical simulation stage. There is no satisfactory solution yet for its hardware implementation in modulation and demodulation. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a low-complexity OCDM modulation and demodulation implementation method based on FPGA. This invention considers complexity and structural optimization, prioritizing the implementation of OCDM modulation and demodulation using the more efficient FPGA (Field Programmable Gate Array) tool, and encapsulates its interface, allowing external configuration of the number of OCDM subcarriers. As a semi-custom circuit in integrated circuits, FPGA has advantages such as low cost and high flexibility, making it suitable as a hardware simulation and verification platform in the early stages of wireless communication prototype research, thus bringing greater convenience to the design of digital communication circuits.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A low-complexity OCDM modulation and demodulation implementation method based on FPGA is proposed. This method decomposes the Discrete Fresnel Transform (DFnT) or Inverse Discrete Fresnel Transform (IDFnT) into two steps of rotation factor multiplication, Fast Fourier Transform (FFT) or Inverse Fast Fourier Transform (IFFT), and phase and amplitude adjustment to achieve OCDM modulation and demodulation. The method includes the following steps:

[0007] S1. Input the IQ data to be transformed by DFnT or IDFnT through the input IQ data module;

[0008] S2. Set up the first rotation factor multiplication module, select the rotation factor, perform phase rotation on the rotation factor, and then multiply the first rotation factor after phase rotation with the input data to obtain the output result;

[0009] S3. Set up the FFT or IFFT module to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication.

[0010] S4. Set up a second rotation factor multiplication module to perform a second rotation factor multiplication on the data after FFT or IFFT transformation;

[0011] S5. Set the phase and amplitude adjustment module to adjust the phase and amplitude of the data after the second rotation factor multiplication, and complete OCDM modulation or demodulation.

[0012] Furthermore, in step S1, for OCDM modulation, the data input to the input IQ data module is the received IQ time domain data sampled by the receiver, and its amplitude is normalized; for OCDM demodulation, the data input to the input IQ data module is the in-phase and quadrature component data of the modulation symbol after the transmitter has been mapped by the constellation points.

[0013] For N IQ data points to be transformed by DFnT or IDFnT, the input IQ data module is represented as follows:

[0014] in_signal[n]=i_insgn[n]+jq_insign[n]

[0015] In the formula, n represents the index of the input data, ranging from 0 to N-1; i_insgn[n] and q_insgn[n] are signed fixed-point numbers or floating-point numbers.

[0016] Furthermore, in step S2, the first rotation factor multiplication module includes a conjugate extraction submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule, and a complex number multiplication combination output submodule, wherein...

[0017] The conjugate submodule determines whether to take the conjugate of the input IQ data based on the DFnT_flag flag.

[0018] The counter submodule is used to generate two signals, namely the index counter (index) and the address counter (addr_cnt).

[0019] The RAM submodule stores the twitch factor IQ data and retrieves the twitch factor for the corresponding address based on the value of the address counter addr_cnt.

[0020] The phase rotation selection submodule uses an index counter (index) to obtain the phase adjustment mode (phase_mode) of the rotation factor through combinational logic.

[0021] The complex multiplication and combination output submodule performs complex multiplication of the input IQ data with the rotation factor according to the phase adjustment mode (phase_mode) to obtain the calculation result.

[0022] Furthermore, the conjugate submodule of the first rotation factor multiplication module determines whether conjugation of the input IQ data is necessary based on the DFnT_flag flag.

[0023] For the DFnT transform, setting DFnT_flag to 1 enables direct pass-through of input IQ data to the output.

[0024] in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n]

[0025] For the IDFnT transform, DFnT_flag is set to 0, and the conjugate output is taken from the input IQ data:

[0026] in_DFnT[n]=i_din[n]+jq_din[n]=i_insgn[n]-jq_insgn[n]

[0027] The index counter generated by the counter submodule increments by 1 when the input IQ data in_signal is valid, with a counting range of 0 to N-1. Therefore, the index counter has log2(N) bits. The address counter addr_cnt counts in ascending order when the log2(N)-2th bit of the index counter is 0, and in descending order when the log2(N)-2th bit of the index counter is 1, with a counting range of 0 to N / 8-1. This yields the address data for the rotation factor RAM table.

[0028] The RAM submodule stores N / 8 rotation factor IQ data and retrieves the rotation factor θ1(n) = i_dw[n] + jq_dw[n] at the corresponding address based on the value of the address counter addr_cnt.

[0029] Furthermore, the phase adjustment mode (phase_mode) obtained by the phase rotation selection submodule of the first rotation factor multiplication module has four possibilities:

[0030] Case 1: When the high 3 bits of the index counter are 000 or 111, phase_mode is always 0;

[0031] Case 2: When the high 3 bits of the index counter are 001 or 010, let m be the value of index after removing the high 3 bits, and phase_mode = m%4;

[0032] Case 3: When the high 3 bits of the index counter are 011 or 100, let m be the value of the index after removing the high 3 bits, and phase_mode = (m%2)*2;

[0033] Case 4: When the high 3 bits of the index counter are 101 or 110, let m be the value of index after removing the high 3 bits, and phase_mode = 3 - (m%2)*2.

[0034] Furthermore, the complex multiplication combination output submodule of the first rotation factor multiplication module obtains four output results based on the four phase adjustment modes of the phase rotation selection submodule:

[0035] Case 1: When phase_mode is 0, the calculated result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n], q_dout[n]=i_din[n]*q_dw[n]+q_din[n]*i_dw[n];

[0036] Case 2: When phase_mode is 1, the calculated result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n]+q_din[n]*q_dw[n]), q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0037] Case 3: When phase_mode is 2, the calculated result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n]+q_din[n]*q_dw[n]), q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0038] Case 4: When phase_mode is 3, the calculated result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n], q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n].

[0039] Furthermore, in the first rotation factor multiplication module, for the DFnT transform, the input IQ data is multiplied by the required rotation factor to obtain the output result; for the IDFnT transform, the input IQ data is conjugate and then multiplied by the required rotation factor to obtain the output result.

[0040] The input IQ data of the DFnT transform are represented as follows:

[0041] in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n]

[0042] The input IQ data of the IDFnT transform, after taking the conjugate, is represented as:

[0043] in_DFnT[n]=i_din[n]+jq_din[n]=i_insgn[n]-jq_insgn[n]

[0044] The twiddle factor is expressed as:

[0045]

[0046] The output result is represented as follows:

[0047] Out_DFnT[n]=i_dout[n]+jq_dout[n].

[0048] Furthermore, in step S3, the FFT or IFFT module performs an FFT transformation on DFnT and an IFFT on IDFnT; the number of points in the FFT or IFFT transformation is N, which is the same as the number of points in the DFnT or IDFnT transformation.

[0049] Furthermore, in step S4, the second rotation factor multiplication module also includes a conjugate submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule, and a complex multiplication combination output submodule, which performs a second rotation factor multiplication on the output data of the FFT or IFFT module.

[0050] Furthermore, in step S5, the phase and amplitude adjustment module adjusts the phase and amplitude of the data output by the second rotation factor multiplication module, wherein...

[0051] For the DFnT transform, the IQ data output from the second rotation factor multiplication module is multiplied by exp(-j*pi / 4), and the result is reduced by right shift. times;

[0052] For IDFnT, the conjugate of the IQ data is multiplied by exp(-j*pi / 4), and the result is amplified by left shift. times;

[0053] The output phase and amplitude are adjusted to complete OCDM modulation or demodulation.

[0054] The beneficial effects of this invention are as follows:

[0055] This invention utilizes the inherent properties of OCDM modulation to design a method for rapidly implementing DFnT / IDFnT using FFT / IFFT. Specifically, the rotation factor multiplication module, by observing the properties of the rotation factor, reduces the storage capacity by a factor of 8 by adding only some control circuitry while maintaining the same computational complexity.

[0056] This invention provides an interface compatible with different DFnT modulation point numbers, at the cost of only adding some control circuitry. Furthermore, by employing a pipelined FFT, the entire DFnT can be pipelined, and its data rate can be compatible with some high-speed application scenarios.

[0057] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0058] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0059] Figure 1This is a schematic diagram of the overall design of the FPGA-based low-complexity OCDM modulation and demodulation implementation method of the present invention;

[0060] Figure 2 This is a schematic diagram of the design structure of the first rotation factor multiplication module of the present invention;

[0061] Figure 3 This is an overall flowchart of the FPGA-based low-complexity OCDM modulation and demodulation implementation method of the present invention;

[0062] Figure 4 This is a schematic diagram of the verification platform structure for the FPGA-based low-complexity OCDM modulation and demodulation implementation method in the embodiment.

[0063] Figure 5 This is a block diagram of the 1024-point IDFnT design in the example embodiment;

[0064] Figure 6 This is a schematic diagram illustrating the OCDM bit error probability in an embodiment.

[0065] Figure 7 This is a schematic diagram comparing FPGA and MATLAB waveforms in the example, where... Figure 7 (a) is a schematic diagram comparing the real part waveforms. Figure 7 (b) is a schematic diagram comparing the waveforms of the imaginary part. Detailed Implementation

[0066] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0067] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures, and should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0068] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0069] Please see Figures 1 to 7 This is a low-complexity OCDM modulation and demodulation implementation method based on FPGA.

[0070] Example

[0071] The purpose of this invention is to provide a low-complexity OCDM modulation and demodulation implementation method based on FPGA. OCDM modulation and demodulation are implemented using the Discrete Fresnel Transform (DFnT) and the Inverse Discrete Fresnel Transform (IDFnT), respectively. The DFnT transformation formula is shown below:

[0072]

[0073] In the formula, s(n) represents the OCDM time-domain signal, x(k) represents the Fresnel domain signal after DFnT transformation, n, k∈[0,N=1], and N is the number of points of DFnT transformation.

[0074] Therefore, this invention decomposes the Discrete Fresnel Transform (DFnT) and Inverse Discrete Fresnel Transform (IDFnT) into four steps: two twitch factor multiplications, Fast Fourier Transform (FFT) / Inverse Fast Fourier Transform (IFFT), and phase / modulus adjustment. Utilizing the properties of the twitch factor and combining it with FPGA, a low-memory, low-complexity OCDM modulation and demodulation implementation method is proposed. The design block diagram of this invention is shown below. Figure 1 As shown.

[0075] like Figure 1 The FPGA design block diagram of DFnT / IDFnT shown consists of an input IQ data module, a double rotation factor multiplication module, an FFT / IFFT module, and a phase and amplitude adjustment module.

[0076] Input IQ data module: For IDFnT conversion, the input IQ data is the in-phase and quadrature component data of the modulation symbols after constellation point mapping by the transmitter (abbreviated as: IQ data), which needs to be converted by IDFnT to generate OCDM time-domain waveform. For DFnT conversion, the input IQ data is the received IQ time-domain data sampled by the receiver, which is normalized in amplitude before being input for DFnT conversion. Input IQ data in_signal[n] = i_insgn[n] + jq_insign[n], where n represents the index of the input data, ranging from 0 to N-1; i_insgn[n] and q_insgn[n] are signed fixed-point numbers or floating-point numbers.

[0077] First rotation factor multiplication module: For the DFnT transform, the input IQ data in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n] is multiplied by the required rotation factor. The output is: Out_DFnT[n] = i_dout[n] + jq_dout[n]. For the IDFnT transform, the input IQ data needs to be conjugate first: in_DFnT[n] = i_din[n] + jq_din[n] = i_insgn[n] - jq_insgn[n], and then multiplied by the required rotation factor. The output result is: Out_DFnT[n].

[0078] The first rotation factor multiplication module consists of five sub-modules: a conjugate extraction sub-module, a counter sub-module, a RAM sub-module, a phase rotation selection sub-module, and a complex number multiplication combination output sub-module. For example... Figure 2 As shown.

[0079] The conjugate submodule determines whether conjugation of the input IQ data is needed based on the DFnT_flag flag. For DFnT transform, DFnT_flag is set to 1, and the input IQ data is passed directly to the output in_DFnT[n] = i_din[n] + jq_din[n] = in_signal[n] = i_insgn[n] + jq_insgn[n]. For IDFnT transform, DFnT_flag is set to 0, and the input IQ data is conjugated to the output in_DFnT[n] = i_din[n] + jq_din[n] = i_insgn[n] - jq_insgn[n].

[0080] The counter submodule generates two signals: an index counter (index) and an address counter (addr_cnt). The index counter increments by 1 when the input IQ data `in_signal` is valid (when `data_valid` is 1), with a counting range of 0 to N-1, thus having log2(N) bits. The address counter `addr_cnt` counts in ascending order when the (log2(N)-2)th bit of the index counter is 0, and in descending order when the (log2(N)-2)th bit of the index counter is 1, with a counting range of 0 to N / 8-1. This is used to generate the address data for the rotation factor RAM table.

[0081] RAM submodule: Stores N / 8 rotation factor IQ data, and retrieves the rotation factor θ1(n) = i_dw[n] + jq_dw[n] at the corresponding address based on the value of the address counter addr_cnt.

[0082] Phase rotation selection submodule: Based on the properties of the DFnT / IDFnT transform, the rotation factor data intervals of N / 8 points will be the same or have a fixed phase offset. Therefore, the phase adjustment mode (phase_mode) of the rotation factor is obtained through combinational logic using the index counter (index). There are ultimately four possible phase adjustment modes (phase_mode): 0, 1, 2, and 3. The method of calculating phase_mode using the index counter (index) will be described below for each case.

[0083] Case 1: When the high 3 bits of the index counter are 000 or 111, phase_mode is always 0;

[0084] Case 2: When the high 3 bits of the index counter are 001 or 010, let m be the value of index after removing the high 3 bits, and phase_mode = m%4;

[0085] Case 3: When the high 3 bits of the index counter are 011 or 100, let m be the value of index after removing the high 3 bits, and phase_mode = (m%2)*2;

[0086] Case 4: When the high 3 bits of the index counter are 101 or 110, let m be the value of the index after removing the high 3 bits, and phase_mode = 3 - (m%2)*2;

[0087] The complex multiplication and combination output submodule performs complex multiplication of the input IQ data in_DFnT[n] = i_din[n] + jq_din[n] with the rotation factor θ1(n) = i_dw[n] + jq_dw[n] using only four phase adjustment modes, while maintaining the same complexity of multiplication operations. This results in the calculated output: Out_DFnT[n] = i_dout[n] + jq_dout[n]. The results of the complex multiplication and combination output submodule will be detailed below, considering different scenarios.

[0088] Case 1: When phase_mode is 0, the calculated result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n];

[0089] Case 2: When phase_mode is 1, the calculated result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0090] Case 3: When phase_mode is 2, the calculated result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0091] Case 4: When phase_mode is 3, the calculated result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n]q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n];

[0092] The FFT / IFFT module employs a radix-2 2048-64 point Fast Fourier Transform / Inverse Fast Fourier Transform (FFT / IFFT) to perform FFT on DFnT and IFFT on IDFnT. The number of FFT / IFFT transformation points is N, the same as the number of transformation points in DFnT / IDFnT.

[0093] Second Rotation Factor Multiplication Module: This module has the same structure as the first rotation factor multiplication module, and it performs a second rotation factor multiplication on the output data of the FFT / IFFT module. In non-pipelined scenarios, it can be reused with the first rotation factor multiplication module to save resources; in pipelined scenarios, only one identical module needs to be instantiated.

[0094] Phase and amplitude adjustment module: For DFnT, the IQ data output by the second rotation factor multiplication module is multiplied by exp(-j*pi / 4) using a complex number multiplication, and the result is reduced by right shift. For IDFnT, the conjugate of the IQ data is multiplied by exp(-j*pi / 4), and the result is amplified by left shift. times.

[0095] The process of DFnT / IDFnT implemented in this invention is as follows: Figure 3 As shown.

[0096] Step 1: Input N IQ data points that need to be used to complete DFnT or IDFnT. For example... Figure 3 Step 1.

[0097] Step 2: Retrieve the required rotation factor from the RAM table using a counter, perform phase rotation of the rotation factor, and complex multiplication with the input data to complete the first rotation factor multiplication. For example... Figure 3 Step 2.

[0098] Step 3: Perform FFT / IFFT on the data after the first phase rotation. For example... Figure 3 Three steps.

[0099] Step 4: Perform a second multiplication of the FFT / IFFT data using the rotation factor, the process being the same as in Step 2. For example... Figure 3 The middle 4 steps.

[0100] Step 5: After adjusting the phase and amplitude of the data that has undergone the second phase rotation, output the data to complete the entire DFnT / IDFnT transformation. For example... Figure 3 Five steps.

[0101] To verify the feasibility of this invention, a theoretical analysis is first conducted. OCDM modulation and demodulation are implemented using DFnT and IDFnT respectively, and the formulas for DFnT and IDFnT are shown below.

[0102]

[0103] Where x(k) represents the IQ data of the constellation points mapped to the Fresnel domain, and s(n) represents the OCDM time-domain signal data after IDFnT modulation. The difference between odd and even N, and the subsequent implementation will use FFT, will be used as an example for designing the OCDM modulation and demodulation scheme, since even N is used. Although DFnT has a complete definition, there is no fast DFnT algorithm. Using matrix multiplication would result in excessive computational complexity and cost. Therefore, derivation shows that DFnT can be implemented quickly using FFT.

[0104]

[0105] DFnT can be obtained by appending two quadratic phases to an FFT. The two diagonal twisting factors are: and Therefore, DFnT can be quickly implemented in three steps using the Fast Fourier Transform (FFT) algorithm:

[0106] (1) The signal is multiplied by the second phase θ1;

[0107] (2) Perform an N-point FFT;

[0108] (3) Multiply by another quadratic phase θ2

[0109] The fast implementation of DFnT reduces the computational complexity of the Discrete Fresnel Transform, allowing Fresnel Transform-based communication systems to be better integrated into Fourier Transform-based systems. IDFnT is very similar to DFnT and can be quickly implemented in three steps using IFFT:

[0110] (1) Signal multiplied by the second phase

[0111] (2) Perform an N-point IFFT;

[0112] (3) Multiply by another quadratic phase

[0113] The key optimization point of this invention lies in the multiplication module of the rotation factor. This is achieved by observing the rotation factor. Discover When the number of modulation points is greater than 4, we get θ1(n+N / 2)=θ1(n)exp(jπn). Similarly, we can get θ1(n+N / 4)=θ1(n)exp(jπn / 2) and θ1(N / 4-n)=θ1(n)exp(-jπn / 2). Therefore, it can be seen that the rotation factor data interval of N / 8 points will be the same as the original data or have a fixed phase shift. At the same time, to ensure compatibility with DFnT at different points, it was observed that… Therefore, for DFnT with a smaller number of points, rotation factors can be directly retrieved from a DFnT table with a larger number of points at intervals. This invention uses this method to ensure compatibility with DFnTs of different points, thus avoiding the drawback of conventional methods that require different RAM tables for DFnTs of different points.

[0114] Next, we verify the practicality of this invention in a real-world environment. For example... Figure 4 As shown, simulations are performed using Vivado and MATLAB platforms. The input data to the IDFnT uses a number of bits randomly generated by the MATLAB platform. After QPSK modulation, the generated IQ data signal is sent to the IDFnT module. The OCDM data modulated by the IDFnT is then sent to the DFnT module for demodulation, followed by QPSK demodulation. Finally, the data is written back to MATLAB for comparison and verification. Simultaneously, the OCDM data generated by the MATLAB software and the OCDM data generated by the FPGA are compared to examine the magnitude of the error. The simulation platform for a specific embodiment is as follows: Figure 6 As shown.

[0115] In this embodiment, N is specified as 1024 and 256 points. The following detailed explanation uses N=1024 points as an example. First, a random number function in MATLAB is used to generate 2048*1000 bits and write them to a txt file. Then, a testbench is written on the Vivado platform to read the bit data from the txt file and instantiate each module.

[0116] The QPSK modulation module modulates the input bit data into QPSK IQ data and inputs it into the IDFnT module. The quantization width of the IQ data is 12 bits (signed). Along with the IQ data in_mod[n] = i_mod[n] + jq_mod[n], a valid output signal data_valid is also output.

[0117] The IDFnT modulation module is mainly divided into four modules: first rotation factor multiplication, IFFT, second rotation factor multiplication, and phase and amplitude adjustment module.

[0118] The first rotation factor multiplication module consists of five sub-modules: a conjugate extraction sub-module, a counter sub-module, a RAM sub-module, a phase rotation selection sub-module, and a complex number multiplication combination output sub-module. The module's design block diagram is shown below. Figure 5 As shown. Take the conjugate submodule: Set the input DFnT_flag to 0, so the input IQ data takes the conjugate output in_DFnT[n]=i_din[n]+jq_din[n]=i_mod[n]-jq_mod[n], where n is 0 to 1023;

[0119] The counter submodule generates two control signals: the index counter (index) and the address counter (addr_cnt). The index counter increments by 1 when the input IQ data `in_signal` is valid (when `data_valid` is 1), with a counting range of 0 to 1023. The index counter has 10 bits. The address counter `addr_cnt` counts in forward order when the 8th bit of the index is 0, and in reverse order when the 8th bit of the index is 1, with a counting range of 0 to 127. This is used to generate the address data for the rotation factor RAM table.

[0120] RAM submodule: Stores 128 rotation factor IQ data, and retrieves the rotation factor θ1(n) = i_dw[n] + jq_dw[n] of the corresponding address according to the value of the address counter addr_cnt.

[0121] The phase rotation selection submodule uses an index counter (index) to obtain the actual phase adjustment mode (phase_mode) through combinational logic. There are four possible phase adjustment modes (phase_mode): 0, 1, 2, and 3. The method for calculating phase_mode from the index counter (index) will be described below for each case. Operations such as taking the high-order bit, taking the low-order bit, and taking the remainder can all be performed using bit truncation.

[0122] Case 1: When the 10th, 9th, and 8th bits of the index counter are 000 or 111, phase_mode is always 0;

[0123] Case 2: When the 10th, 9th, and 8th bits of the index counter are 001 or 010, record m as the value of the 7th bit of the index, and phase_mode = m%4;

[0124] Case 3: When the 10th, 9th, and 8th bits of the index counter are 011 or 100, record m as the value of the 7th bit of the index, and phase_mode = (m%2)*2;

[0125] Case 4: When the 10th, 9th, and 8th bits of the index counter are 101 or 110, record m as the value of the 7th bit of the index, and phase_mode = 3 - (m%2)*2;

[0126] The complex multiplication and combination output submodule performs a complex multiplication of the input IQ data in_DFnT[n] = i_din[n] + jq_din[n] with the rotation factor θ1(n) = i_dw[n] + jq_dw[n] based on the phase adjustment mode phase_mode. This module can perform phase adjustment of the rotation factor and complex multiplication with the IQ data using only four phase adjustment results while maintaining the same complexity of the multiplication operation, thus obtaining the calculation result Out_DFnT[n] = i_dout[n] + jq_dout[n]. The results of the complex multiplication and combination output submodule will be detailed below for different cases.

[0127] Case 1: When phase_mode is 0, the calculated result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n];

[0128] Case 2: When phase_mode is 1, the calculated result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0129] Case 3: When phase_mode is 2, the calculated result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0130] Case 4: When phase_mode is 3, the calculated result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n]q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n];

[0131] IFFT module: Employs radix-2 2048-64 point inverse fast Fourier transform (IFFT), with the IFFT transformation configured to have 1024 points.

[0132] Second rotation factor multiplication module: The IQ data after IFFT needs to be multiplied by rotation factors a second time. The specific process is similar to the above and will not be described in detail.

[0133] Phase and amplitude adjustment module: After the second phase rotation, the IQ data is conjugate, multiplied by exp(jpi / 4) in a complex number, and the result is shifted left by 6 bits to complete IDFnT modulation;

[0134] DFnT module: Similar to the IDFnT module mentioned above, you only need to set the DFnT_flag flag to 1 and replace the FFT module with the IFFT module.

[0135] The QPSK demodulation module normalizes the IQ data output by the DFnT module, demodulates it into bit data through phase detection, and writes it into a txt file.

[0136] This example compares the performance of FPGA and MATLAB data under different data conditions. (See the graph.) Figure 6 As shown, after continuously performing 1000 frames of OCDM data IDFnT modulation and then DFnT demodulation, the bit error rate of each frame is 0%. Simultaneously, a frame of data was captured and compared with the data modulated by MATLAB. It was found that the data modulated by the FPGA can completely cover the data modulated by MATLAB, with only a small deviation in the integer part. Furthermore, the data modulated by the FPGA is amplitude-limited. The waveforms of the real and imaginary parts are shown below. Figure 7 (a) and Figure 7 As shown in (b), this verifies the effectiveness of the present invention.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for implementing low-complexity OCDM modulation and demodulation based on FPGA, characterized in that: The method splits a discrete Fresnel transform DFnT or an inverse discrete Fresnel transform IDFnT into twice rotation factor multiplication, fast Fourier transform FFT or inverse fast Fourier transform IFFT, phase and amplitude adjustment steps to realize OCDM modulation and demodulation, which comprises the following steps: S1, inputting IQ data to be subjected to DFnT or IDFnT transform through an input IQ data module; S2, setting a first rotation factor multiplication module, selecting a rotation factor, and performing phase rotation on the rotation factor, and then multiplying the phase-rotated rotation factor with the input data to obtain an output result; S3, setting an FFT or IFFT module to perform FFT or IFFT transform on the output result of the first rotation factor multiplication; S4, setting a second rotation factor multiplication module to perform second rotation factor multiplication on the data after FFT or IFFT transform; S5, setting a phase and amplitude adjustment module to perform phase and amplitude adjustment on the data after second rotation factor multiplication to complete OCDM modulation or demodulation; In step S1, for OCDM modulation, the data input by the input IQ data module is the received IQ time domain data obtained by sampling the receiver, and the amplitude normalization processing is performed thereon; for OCDM demodulation, the data input by the input IQ data module is the in-phase and quadrature component data of the modulation symbol after the constellation point mapping of the transmitter; Wherein, for N IQ data to be subjected to DFnT or IDFnT transform, the input IQ data module is represented in the following manner: in_signal[n]=i_insgn[n]+jq_insign[n] In the formula, n represents the index of the input data, ranging from 0 to N-1; i_insgn[n], q_insgn[n] are signed fixed-point numbers or floating-point numbers.

2. The method according to claim 1, wherein the method is characterized in that: In step S2, the first rotation factor multiplication module includes a conjugate taking submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule and a complex multiplication combination output submodule, wherein, The conjugate taking submodule determines whether to take the conjugate of the input IQ data according to the DFnT flag DFnT_flag; The counter submodule is used to generate two signals index and addr_cnt respectively; The RAM submodule stores the rotation factor IQ data, and takes out the rotation factor at the corresponding address according to the value of the address counter addr_cnt; The phase rotation selection submodule obtains the phase adjustment mode phase_mode of the rotation factor through combination logic by using the index counter index; The complex multiplication combination output submodule completes the complex multiplication of the input IQ data and the rotation factor according to the phase adjustment mode phase_mode to obtain the calculation result.

3. The method according to claim 2, wherein the method is characterized in that: The conjugate taking submodule of the first rotation factor multiplication module determines whether the conjugate of the input IQ data is needed according to the DFnT flag DFnT_flag, wherein, For DFnT transform, DFnT_flag is set to 1, and the input IQ data is directly outputted: in_DFnT[n] = i_din[n] + jq_din[n] = in_signal[n] = i_insgn[n] + jq_insgn[n] For IDFnT transform, DFnT_flag is set to 0, and the input IQ data is conjugated as output: in_DFnT[n] = i_din[n] + jq_din[n] = i_insgn[n] - jq_insgn[n] The index counter index generated by the counter sub-module is incremented by 1 when the input IQ data in_signal is valid, and the counting range is 0 to N-1, so the index counter index has log2(N) bits; the address counter addr_cnt is counted in positive order when the first log2(N)-2 bits of the index counter index are 0; and counted in reverse order when the first log2(N)-2 bits of the index counter index are 1, and the counting range is 0 to N / 8-1; and the address data of the rotation factor RAM table is obtained; The RAM sub-module stores N / 8 rotation factor IQ data, and takes out the rotation factor of the corresponding address according to the value of the address counter addr_cnt .

4. The method according to claim 3, wherein the method is characterized in that: The phase adjustment mode phase_mode obtained by the phase rotation selection sub-module of the first rotation factor multiplication module has four cases: Case 1: When the high 3 bits of the index counter index are 000 or 111, phase_mode is always 0; Case 2: When the high 3 bits of the index counter index are 001 or 010, let m be the value of index after removing the high 3 bits, and phase_mode = m%4; Case 3: When the high 3 bits of the index counter index are 011 or 100, let m be the value of index after removing the high 3 bits, and phase_mode = (m%2)*2; Case 4: When the high 3 bits of the index counter index are 101 or 110, let m be the value of index after removing the high 3 bits, and phase_mode = 3-(m%2)*2.

5. The method according to claim 4, wherein the method is characterized in that: The complex multiplication combination output sub-module of the first rotation factor multiplication module obtains four output results according to the four phase adjustment modes of the phase rotation selection sub-module: Case 1: When phase_mode is 0, the calculation result Out_DFnT[n] is i_dout[n] = i_din[n]*i_dw[n] + q_din[n]*q_dw[n], q_dout[n] = i_din[n]*q_dw[n] + q_din[n]*i_dw[n]; Case 2: When phase_mode is 1, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n] + q_din[n]*q_dw[n]), q_dout[n] = i_din[n]*q_dw[n] - q_din[n]*i_dw[n]; Case 3: when phase_mode is 2, the calculation result Out_DFnT[n] is i_dout[n]=-(i_din[n]*i_dw[n] +q_din[n]*q_dw[n]), q_dout[n]=i_din[n]*q_dw[n]-q_din[n]*i_dw[n]; Case 4: when phase_mode is 3, the calculation result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n] +q_din[n]*q_dw[n], q_dout[n]= q_din[n]*i_dw[n]-i_din[n]*q_dw[n].

6. The method according to claim 5, wherein the method is characterized in that: In the first rotation factor multiplication module, for DFnT transformation, the input IQ data is multiplied by the required rotation factor to obtain the output result; for IDFnT transformation, the input IQ data is conjugated and then multiplied by the required rotation factor to obtain the output result. Wherein, the input IQ data of DFnT transformation is represented as: in_DFnT[n] =i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n] The input IQ data of IDFnT transformation is conjugated and represented as: in_DFnT[n]=i_din[n]+jq_din[n]= i_insgn[n]-jq_insgn[n] The rotation factor is represented as: The output result is represented as: Out_DFnT[n]=i_dout[n]+jq_dout[n].

7. The method according to claim 6, wherein the method is characterized in that: In step S3, the FFT or IFFT module performs FFT transformation on DFnT and IFFT on IDFnT; the number of points of FFT or IFFT transformation is N, which is the same as the number of points of DFnT or IDFnT transformation.

8. The method according to claim 7, wherein the method is characterized in that: In step S4, the second rotation factor multiplication module set also includes a conjugate sub-module, a counter sub-module, a RAM sub-module, a phase rotation selection sub-module and a complex multiplication combination output sub-module, which performs second rotation factor multiplication on the output data of the FFT or IFFT module.

9. The method according to claim 8, wherein the method is characterized in that: In step S5, the phase and amplitude adjustment module adjusts the phase and amplitude of the data output by the second rotation factor multiplication module, wherein, For the DFnT transform, the IQ data output from the second rotation factor multiplication module is complex multiplied by exp(-j*pi / 4) and the result is down-scaled by right shifting by 2 times; For IDFnT, the IQ data is conjugated and multiplied by exp(-j*pi / 4) and the result is up-sampled by left shifting times; The output phase and amplitude adjusted results complete OCDM modulation or demodulation.

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