Airplane power supply system test data processing gateway and data processing method

Abstract

The invention belongs to the technical field of data processing, and relates to an aircraft power supply system test data processing gateway and a data processing method. The gateway comprises an industrial personal computer, a high-speed data processing board card and an expanded 1588 network port, the high-speed data processing board card is formed by heterogeneous FPGA chips and ARM chips, the board card and the network port are integrated in the industrial personal computer through PCIe expansion slots, and the gateway is connected with test equipment through an industrial personal computer interface and an ARM chip interface; the industrial personal computer is used for receiving a test data processing algorithm of the upper computer and sending processed and analyzed test data to the upper computer; the industrial personal computer dynamically transmits an algorithm file sent by the upper computer into the high-speed data processing board card, the ARM chip unpacks test data received from the test equipment based on an unpacking algorithm, and the FPGA chip processes and analyzes the unpacked data based on a processing algorithm. According to the invention, the algorithm in the FPGA can be flexibly configured, the dynamic loading of the gateway is realized, and the data acquisition and processing capability is improved.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and specifically relates to an aircraft power supply system test data processing gateway and a data processing method. Background Art

[0002] In the process of power supply system integration verification test in the aviation field, various types of test equipment are involved, including various types of shelf-type equipment and non-standard customized test equipment. The test equipment has no unified communication protocol or communication specification, and no unified control center. At the same time, the data generated by each test equipment is stored locally in the equipment, and there is no unified data management center, which makes data management complicated and confusing.

[0003] For the above problems, the general industrial IoT gateway can achieve multi-protocol conversion and unified data collection and upload management. However, due to the particularity of aviation field experiments, there are still the following problems:

[0004] 1) Each test device uploads a large amount of data, and a single device can collect hundreds of MB of data per second;

[0005] 2) A large amount of collected data needs to be processed and analyzed in real time based on different algorithms. For example, the analysis of aircraft power supply characteristic parameters needs to be within milliseconds according to the requirements of relevant national military standards and real-time monitoring requirements of the test.

[0006] Therefore, this scenario requires high-performance data processing capabilities and the ability to load dedicated algorithms. The current existing gateways and their technical paths do not support the requirements of such scenarios. Summary of the invention

[0007] In order to solve the above problems, the present application provides an aircraft power supply system test data processing gateway and data processing method to meet the needs of aviation structure testing and verification.

[0008] In a first aspect, the present application provides an aircraft power supply system test data processing gateway, comprising an industrial computer, a high-speed data processing board card heterogeneous with an FPGA chip and an ARM chip, and an extended 1588 network port, wherein the high-speed data processing board card and the extended 1588 network port are integrated into the industrial computer through a PCIe expansion slot, and the gateway is connected to a test device through an industrial computer interface and an ARM chip interface;

[0009] The industrial computer is connected to the host computer through the extended 1588 network port to communicate with the host computer, receive the test data processing algorithm of the host computer, and send the processed and analyzed test data to the host computer;

[0010] The industrial computer dynamically transfers the algorithm file sent by the host computer to the high-speed data processing board through the PCIe bus, the ARM chip unpacks the test data received from the test equipment based on the unpacking algorithm in the algorithm file, and the FPGA chip performs data processing and analysis on the unpacked data based on the processing algorithm in the algorithm file.

[0011] Preferably, the industrial computer further includes a network port, a USB port, an RS232 port, and an RS458 port.

[0012] Preferably, the ARM chip interface is an Ethernet port.

[0013] Preferably, each of the data processing gateways is connected to a test device via an ARM chip therein, and the 1588V2 protocol is used for clock synchronization between multiple data processing gateways.

[0014] Preferably, the FPGA chip is divided into a dynamically reconfigurable resource area and a static logic area. The dynamically reconfigurable resource area is used to dynamically reconfigure according to the processing algorithm transmitted from the industrial computer. The static logic area includes an XDMA module, a MIG module, and a ZYNQ module. The XDMA module is used to receive the processing algorithm sent by the industrial computer, and the MIG module is used to mount the memory. The interaction of the processing algorithm and data between the CPU of the industrial computer and the FPGA chip is realized through the memory. The ZYNQ module is used to manage the peripheral resources of the high-speed processing board.

[0015] A second aspect of the present application provides an aircraft power supply system test data processing method, using the aircraft power supply system test data processing gateway as described above to process aircraft power supply system test data, the method comprising:

[0016] Step S1, transferring the algorithm file of the CPU end of the industrial computer into the memory of the high-speed data processing board through the PCIe bus, and overwriting and replacing the data in the original resource area of ​​the FPGA chip through the PCAP interface of the FPGA chip;

[0017] Step S2, collecting test data based on the Ethernet port of the ARM chip, and unpacking the test data by the ARM chip;

[0018] Step S3, transferring the unpacked test data to the FPGA chip;

[0019] Step S4, the processing algorithm of the FPGA chip processes the unpacked test data, and the processing result is transmitted to the CPU of the industrial computer via the PCIe bus;

[0020] In step S5, the CPU of the industrial computer packages the processing and analysis results and reports them to the host computer.

[0021] Preferably, in step S3, the test data unpacked by the ARM chip is transmitted to the FPGA chip via the AXI bus inside the high-speed data processing board.

[0022] Preferably, in step S5, the processing and analysis results are pushed to a host computer based on the MQTT protocol.

[0023] Preferably, step S5 further comprises:

[0024] For low-speed data, the remote insertion module of the host computer writes it into the distributed time series database of the host computer; for high-speed data, the industrial computer writes it into the local high-compression ratio time series database, and after compression, it is periodically imported into the distributed time series database of the host computer;

[0025] The low-speed data refers to data with a transmission rate less than or equal to 1 MB / s, and the high-speed data refers to data with a transmission rate greater than 1 MB / s.

[0026] Preferably, for test data uploaded by the test equipment that needs to be processed, the test data is collected through the Ethernet port of the ARM chip and transmitted to the FPGA chip for analysis; for test data uploaded by the test equipment that only needs to be collected and stored, the test data is collected through the interface of the industrial computer.

[0027] This application can flexibly configure the algorithm in the FPGA, realize dynamic loading of the gateway, and improve data collection and processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a system architecture diagram of a preferred embodiment of the aircraft power supply system test data processing gateway of the present application.

[0029] Figure 2 This application Figure 1 Schematic diagram of the connection between the gateway, test equipment and the cloud in the illustrated embodiment.

[0030] Figure 3 It is a flow chart of a preferred embodiment of the aircraft power supply system test data processing method of the present application.

[0031] Figure 4 This application Figure 3 The algorithm file update flow chart of the illustrated embodiment. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the implementation of this application clearer, the technical scheme in the implementation of this application will be described in more detail in combination with the drawings in the implementation of this application. In the drawings, the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The described implementation is a part of the implementation of this application, not all of the implementations. The implementation described below with reference to the drawings is exemplary and is intended to be used to explain this application, and cannot be understood as a limitation on this application. Based on the implementation in this application, all other implementations obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The implementation of this application is described in detail below in combination with the drawings.

[0033] The first aspect of the present application provides an aircraft power supply system test data processing gateway, such as Figure 1 and Figure 2 As shown, it includes an industrial computer, a high-speed data processing board card with heterogeneous FPGA chip and ARM chip, and an extended 1588 network port. The high-speed data processing board card and the extended 1588 network port are integrated into the industrial computer through a PCIe expansion slot, and the gateway is connected to the test equipment through the industrial computer interface and the ARM chip interface;

[0034] The industrial computer is connected to the host computer through the extended 1588 network port to communicate with the host computer, receive the test data processing algorithm of the host computer, and send the processed and analyzed test data to the host computer;

[0035] The industrial computer dynamically transfers the algorithm file sent by the host computer to the high-speed data processing board through the PCIe bus, the ARM chip unpacks the test data received from the test equipment based on the unpacking algorithm in the algorithm file, and the FPGA chip performs data processing and analysis on the unpacked data based on the processing algorithm in the algorithm file.

[0036] The gateway of the present application is configured with an industrial computer. On the one hand, it communicates with the host computer arranged in the cloud, receives the instructions and configuration files of the host computer, and can dynamically configure the heterogeneous boards and cards according to the configuration files. On the other hand, it connects with the test equipment to collect and process the test data of the test equipment through the heterogeneous boards and cards. The software level of the industrial computer includes multiple adapter components, such as resource management components, data reporting components, instruction issuing components, communication protocol configuration components, time synchronization components, etc., among which the data reporting component mainly feeds back the collected data to the host computer, and the instruction issuing component and the communication protocol configuration component mainly receive the instructions and algorithm files / configuration files of the host computer, and configure the processing logic or communication protocol of the internal heterogeneous boards. The hardware level of the industrial computer is connected to the host computer through an extended 1588 network port.

[0037] In some optional implementations, the industrial computer further includes a network port, a USB port, an RS232 port, and an RS458 port.

[0038] In some optional implementations, the interface of the ARM chip is an Ethernet port.

[0039] The gateway of the present application is connected to the test equipment through the industrial computer interface and the ARM chip interface. For the test data uploaded by the test equipment that needs to be processed, the test data is collected through the Ethernet port of the ARM chip and transmitted to the FPGA chip for analysis; for the test data uploaded by the test equipment that only needs to be collected and stored, the test data can be collected through the interface of the industrial computer.

[0040] Inside the industrial computer, the ARM chip is mainly used for data acquisition and high-speed data unpacking, dynamic algorithm loading, data acquisition and unpacking through the Gigabit Ethernet port and dynamically configured unpacking algorithm. After unpacking, the data is processed and calculated by the FPGA chip for real-time processing of large amounts of data and specific data processing.

[0041] In some optional implementations, each of the data processing gateways is connected to a test device via an ARM chip therein, and the 1588V2 protocol is used for clock synchronization between multiple data processing gateways.

[0042] In this embodiment, reference Figure 2 This application adopts a distributed deployment mode, and 1588v2 is used for clock synchronization between gateways. The host computer sends test cases to different gateways, and the clock synchronization accuracy can reach ±30ns.

[0043] In some optional implementations, the FPGA chip is divided into a dynamically reconfigurable resource area and a static logic area. The dynamically reconfigurable resource area is used to dynamically reconfigure according to the processing algorithm transmitted by the industrial computer. The static logic area includes an XDMA module, a MIG module, and a ZYNQ module. The XDMA module is used to receive the processing algorithm sent by the industrial computer, and the MIG module is used to mount the memory. The interaction of the processing algorithm and data between the CPU of the industrial computer and the FPGA chip is realized through the memory. The ZYNQ module is used to manage the peripheral resources of the high-speed processing board.

[0044] In this embodiment, the peripheral resources may be, for example, memory, HP (high performance interface), GP (general purpose interface), EMMC FLASH (embedded multimedia card integrating FLASH memory and controller), clock resources, etc.

[0045] This application has a wider scope of application and can be applied to data collection in general industrial fields and aviation test fields at the same time; the data collection capability is stronger, and for a single data collection point, the maximum test data that can be processed is more than 40MB / s; the integrated FPGA chip is used for real-time data analysis, and the data processing delay is no more than 10ms; this application can flexibly configure the algorithm in the FPGA, realize dynamic loading of the gateway, improve data collection and processing capabilities, and at the same time have 1588v2 time synchronization capabilities, supporting time synchronization between gateways.

[0046] The second aspect of the present application provides an aircraft power supply system test data processing method, using the aircraft power supply system test data processing gateway as described above to process the aircraft power supply system test data, such as Figure 3 As shown, the method includes:

[0047] Step S1, transferring the algorithm file of the CPU end of the industrial computer into the memory of the high-speed data processing board through the PCIe bus, and overwriting and replacing the data in the original resource area of ​​the FPGA chip through the PCAP interface of the FPGA chip;

[0048] Step S2, collecting test data based on the Ethernet port of the ARM chip, and unpacking the test data by the ARM chip;

[0049] Step S3, transferring the unpacked test data to the FPGA chip;

[0050] Step S4, the processing algorithm of the FPGA chip processes the unpacked test data, and the processing result is transmitted to the CPU of the industrial computer via the PCIe bus;

[0051] In step S5, the CPU of the industrial computer packages the processing and analysis results and reports them to the host computer.

[0052] In step S1, as mentioned above, the static logic area of ​​the FPGA chip has a ZYNQ module, in which the logic configuration of the PS of the FPGA chip to the PL is realized through the PCAP (Processor Configuration Access Port) configuration interface, such as Figure 3As shown, it is periodically checked whether there is an algorithm file / configuration file to be updated in the memory of the FPGA chip. If so, the data in the dynamically reconfigurable resource area of ​​the FPGA chip is reconfigured based on the PCAP interface to realize the logical processing of different test data. The algorithm file / configuration file here includes analysis channel configuration, analysis algorithm configuration, analysis result upload configuration, etc. In step S4, the processing algorithm of the FPGA chip performs processing and analysis of the test data, and the analysis result is written into the specified calculation result address area in the memory, and is read by the CPU of the industrial computer through the PCIe bus.

[0053] In some optional implementations, in step S3, the test data unpacked by the ARM chip is transmitted to the FPGA chip via the AXI bus inside the high-speed data processing board.

[0054] In some optional implementations, in step S5, the processing and analysis results are pushed to a host computer based on the MQTT protocol.

[0055] In this embodiment, it is a client-server based message publishing / subscribing transmission protocol, which works on the TCP / IP protocol.

[0056] In some optional implementations, step S5 further includes:

[0057] For low-speed data, the remote insertion module of the host computer writes it into the distributed time series database of the host computer; for high-speed data, the industrial computer writes it into the local high-compression ratio time series database, and after compression, it is periodically imported into the distributed time series database of the host computer;

[0058] The low-speed data refers to data with a transmission rate less than or equal to 1 MB / s, and the high-speed data refers to data with a transmission rate greater than 1 MB / s.

[0059] like Figure 2 As shown, a certain test management system requires simultaneous storage of high-speed time series data and low-speed time series data in a test scenario. The test system establishes an industrial Internet of Things platform, including a cloud, a network, the gateway described in this application, and test equipment. The database body is deployed in a server in the cloud, and the embedded components are deployed on the high-speed data processing board in the gateway to control the test equipment and collect data. The low-speed data generated by the gateway is directly written into the distributed time series database through the remote insertion API of the time series database. High-speed data, such as the data stream generated by the test-specific test equipment, is first written into the local high-compression ratio time series database, and then periodically imported into the distributed time series database by the local high-compression ratio time series database.

[0060] Although the present application has been described in detail above with general descriptions and specific implementation schemes, it is obvious to those skilled in the art that some modifications or improvements may be made to the present application. Therefore, these modifications or improvements made without departing from the spirit of the present application all fall within the scope of protection claimed in the present application.

Claims

1. An aircraft power supply system test data processing gateway, characterized in that: It includes an industrial computer, a high-speed data processing board card with heterogeneous FPGA chip and ARM chip, and an extended 1588 network port. The high-speed data processing board card and the extended 1588 network port are integrated into the industrial computer through a PCIe expansion slot. The gateway is connected to the test equipment through the industrial computer interface and the ARM chip interface. The industrial computer is connected to the host computer through the extended 1588 network port to communicate with the host computer, receive the test data processing algorithm of the host computer, and send the processed and analyzed test data to the host computer; The industrial computer dynamically transfers the algorithm file sent by the host computer to the high-speed data processing board through the PCIe bus, the ARM chip unpacks the test data received from the test equipment based on the unpacking algorithm in the algorithm file, and the FPGA chip performs data processing and analysis on the unpacked data based on the processing algorithm in the algorithm file.

2. The aircraft power supply system test data processing gateway according to claim 1, characterized in that: The industrial computer also includes a network port, a USB port, a RS232 port, and a RS458 port.

3. The aircraft power supply system test data processing gateway according to claim 1, characterized in that: The ARM chip interface is an Ethernet port.

4. The aircraft power supply system test data processing gateway according to claim 1, characterized in that: Each of the data processing gateways is connected to a test device via the ARM chip therein, and the 1588V2 protocol is used for clock synchronization between multiple data processing gateways.

5. The aircraft power supply system test data processing gateway according to claim 1, characterized in that: The FPGA chip is divided into a dynamically reconfigurable resource area and a static logic area. The dynamically reconfigurable resource area is used to dynamically reconfigure according to the processing algorithm transmitted by the industrial computer. The static logic area includes an XDMA module, a MIG module, and a ZYNQ module. The XDMA module is used to receive the processing algorithm sent by the industrial computer, and the MIG module is used to mount the memory. The interaction of the processing algorithm and data between the CPU of the industrial computer and the FPGA chip is realized through the memory. The ZYNQ module is used to manage the peripheral resources of the high-speed processing board.

6. A method for processing test data of an aircraft power supply system, characterized in that: Using the aircraft power supply system test data processing gateway according to any one of claims 1 to 5 to process aircraft power supply system test data, the method comprising: Step S1, transferring the algorithm file of the CPU end of the industrial computer into the memory of the high-speed data processing board through the PCIe bus, and overwriting and replacing the data in the original resource area of ​​the FPGA chip through the PCAP interface of the FPGA chip; Step S2, collecting test data based on the Ethernet port of the ARM chip, and unpacking the test data by the ARM chip; Step S3, transferring the unpacked test data to the FPGA chip; Step S4, the processing algorithm of the FPGA chip processes the unpacked test data, and the processing result is transmitted to the CPU of the industrial computer via the PCIe bus; In step S5, the CPU of the industrial computer packages the processing and analysis results and reports them to the host computer.

7. The aircraft power supply system test data processing method according to claim 6, characterized in that: In step S3, the test data unpacked by the ARM chip is transmitted to the FPGA chip through the AXI bus inside the high-speed data processing board.

8. The aircraft power supply system test data processing method according to claim 6, characterized in that: In step S5, the processing and analysis results are pushed to the host computer based on the MQTT protocol.

9. The aircraft power supply system test data processing method according to claim 6, characterized in that: Step S5 further comprises: For low-speed data, the remote insertion module of the host computer writes it into the distributed time series database of the host computer; for high-speed data, the industrial computer writes it into the local high-compression ratio time series database, and after compression, it is periodically imported into the distributed time series database of the host computer; The low-speed data refers to data with a transmission rate less than or equal to 1 MB / s, and the high-speed data refers to data with a transmission rate greater than 1 MB / s.

10. The aircraft power supply system test data processing method according to claim 7, characterized in that: Step S5 further comprises: For test data uploaded by the test equipment that need to be processed, the test data is collected through the Ethernet port of the ARM chip and transmitted to the FPGA chip for analysis; for test data uploaded by the test equipment that only needs to be collected and stored, the test data is collected through the interface of the industrial computer.

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