Method of operation to mitigate high-k metal-insulator-metal (MIM) capacitor hysteresis problems

Abstract

Disclosed herein are methods of operation to mitigate hysteresis problems of high-k metal-insulator-metal (MIM) capacitors. In one embodiment, a method for reducing image hysteresis associated with a pixel included in a plurality of pixels is described. The pixel includes a photodiode, a first floating diffusion coupled to the photodiode through a transfer transistor, a second floating diffusion coupled to the first floating diffusion through a dual floating diffusion transistor, and a lateral overflow integrating capacitor coupled between the second floating diffusion and a bias voltage source. The lateral overflow integrating capacitor is further coupled to a pixel reference voltage source through a reset transistor. The operation of the pixel includes an idle period and an integration period following the idle period. The method also includes configuring the lateral overflow integrating capacitor to be zero biased or forward biased during the idle period.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors and, in particular, but not exclusively, to pixel cells having a reduced time lag after the pixel cells are exposed to light. Background Art

[0002] CMOS image sensors (CIS) have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and in medical, automotive, and other applications. Image sensors operate in response to image light from an external scene that is incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate a corresponding charge in response. The charge of an individual pixel can be measured as the output voltage of each photosensitive element. In general, the output voltage varies as a function of the intensity and duration of the incident light. The output voltages of the individual photosensitive elements are used to generate a digital image (i.e., image data) representing the external scene.

[0003] Image sensor technology continues to advance rapidly. The demand for higher resolution and lower power consumption has promoted the further miniaturization and integration of these devices with high dynamic range and low light sensitivity. For example, image sensors in some automotive products use high-k (high dielectric constant) metal-to-metal (MIM) capacitor processes to improve the capacitance of the high lateral overflow integration capacitor (LOFIC). As a result, the dynamic range of the image sensor is improved. However, the use of high-k capacitors can cause image lag (for example, after a bright image is captured by the image sensor), which negatively affects the performance of the image sensor. Therefore, there is a need for systems and methods for reducing image lag of image sensors that employ high-k capacitors as LOFICs to achieve high dynamic performance. Summary of the invention

[0004] One aspect of the present disclosure relates to a method for reducing image lag associated with a pixel included in a plurality of pixels, the pixel comprising a photodiode, a first floating diffusion coupled to the photodiode via a transfer transistor, a second floating diffusion coupled to the first floating diffusion via a double floating diffusion transistor, and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source, and the lateral overflow integration capacitor is further coupled to a pixel reference voltage source via a reset transistor, wherein operation of the pixel comprises an idle period and an integration period following the idle period, the method comprising: configuring the lateral overflow integration capacitor to be zero biased or forward biased during the idle period; and configuring the lateral overflow integration capacitor to be reverse biased at least at the beginning of the integration period when the photodiode is exposed to light.

[0005] Another aspect of the present disclosure relates to an image sensor, comprising: a plurality of pixels arranged in rows and columns of a pixel array, each pixel comprising: a photodiode; a first floating diffusion connected to the photodiode; a transfer transistor connecting the photodiode to the first floating diffusion; a second floating diffusion; a double floating diffusion transistor coupled between the first floating diffusion and the second floating diffusion; and a lateral overflow integration capacitor coupled between the second floating diffusion and a bias voltage source, wherein the photodiode is configured to generate charge during an integration period, and wherein the integration period is preceded by an idle period, wherein operation of the pixel includes: configuring the lateral overflow integration capacitor to be zero biased or forward biased during the idle period; and configuring the lateral overflow integration capacitor to be reverse biased at least at the beginning of the integration period when the photodiode is exposed to light. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 An imaging system according to an embodiment of the present disclosure is illustrated.

[0008] Figure 2 is a graph of dielectric relaxation according to an embodiment of the present disclosure.

[0009] Figure 3 is an electrical schematic diagram of a pixel according to an embodiment of the present disclosure.

[0010] Figure 4 is a timing diagram illustrating various stages of image sensor operation according to an embodiment of the present disclosure.

[0011] Figure 5A and 5B is a timing diagram of high lateral overflow integrator capacitor (LOFIC) voltage bias according to an embodiment of the present disclosure.

[0012] Fig. 6A is an electrical schematic diagram of a pixel according to an embodiment of the present disclosure.

[0013] Figure 6B is a timing diagram illustrating various stages of image sensor operation according to an embodiment of the present disclosure.

[0014] Figures 7A to 7C Illustrated are sample voltages of a high-k (high dielectric constant) metal-to-metal (MIM) capacitor according to an embodiment of the disclosure.

[0015] Fig. 8A and 8B is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure.

[0016] Fig. 9 is a timing diagram illustrating various stages of image sensor operation according to an embodiment of the present disclosure.

[0017] Fig. 10A and 10B is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure.

[0018] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to help improve understanding of the various embodiments of the present invention, the sizes of some of the elements in the various figures may be exaggerated relative to other elements. Moreover, common and well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention. DETAILED DESCRIPTION

[0019] Apparatus and methods for lag time effects of image sensors are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, one skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details or can be practiced with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0020] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the appearances of the phrase "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0021] Spatially relative terms (e.g., "below," "below," "lower," "below," "above," "upper," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the various figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device when in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the various figures is turned over, then the elements described as being "below" or "below" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or one or more intervening layers may also be present.

[0022] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context in which they are used clearly implies otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, the two have the same meaning.

[0023] In short, an image sensor may use a high-k metal-insulator-metal (MIM) capacitor process to form a lateral overflow integration capacitor (LOFIC) with higher capacitance, thereby increasing the dynamic range of the image sensor. For example, such image sensors are used in the automotive industry, where a high dynamic range is required to span usage scenarios from driving during nighttime with very little external light to driving during very bright daytime. However, high-k MIM capacitors may suffer from high image lag, which means that after a pixel is exposed to light, the high-k MIM capacitor requires a relatively long time to discharge to its initial value and thus be ready for the next exposure of the pixel to light. For example, during a pixel integration period under bright lighting conditions, due to the hysteresis characteristics and slow relaxation behavior of the high-k material, the image lag caused by the high-k MIM capacitor may be caused by trapping charge within a material with a high dielectric constant (or high-k material) included in the insulating material of the high-k MIM capacitor, which then takes a relatively long time (e.g., a long idle time) to discharge during material relaxation before starting acquisition of the next frame during the next integration period. In some embodiments, the discharge time of the high-k MIM can be about 400 ms, which is significantly longer than the typical frame time of 33 ms of the image sensor itself, thus causing image lag artifacts. Moreover, in many practical applications, the lag time should be reduced even further, for example, to less than 20 ms. Therefore, as the capacitance of the LOFIC in the pixel circuit increases, the image lag increases, which can result in a slower frame rate.

[0024] In general, the high-k MIM LOFIC capacitor hysteresis time is such that a longer idle time is required to discharge the capacitor. In some embodiments of the inventive technology, during the idle period, the high-k MIM LOFIC capacitor is biased to a voltage bias of opposite sign to the voltage bias at the end of the integration time. This reversal of the voltage bias can reduce the accumulated charge, which speeds up the discharge process of the high-k MIM LOFIC capacitor, thus achieving shorter idle times and, conversely, higher frame rates for the image sensor. However, this approach can result in deteriorated dark image non-uniformity (DINU) that interferes with machine vision applications, for example.

[0025] For some embodiments of the inventive technology, the high-k MIM LOFIC capacitor progresses through negative bias and positive bias during the integration period to mitigate the image lag problem. In addition, since the voltage bias of the high-k MIM LOFIC capacitor can start from a negative bias and then transition to a positive bias as more charge is photogenerated by the photodiode and overflows to the high-k MIM LOFIC capacitor during the integration period, the reduced final voltage bias of the high-k MIM LOFIC reduces the image lag. Therefore, the image sensor can operate at a higher frame rate because only a shorter idle time needs to be allocated to discharge the high-k MIM LOFIC capacitor.

[0026] Figure 1 An exemplary imaging system 100 according to an embodiment of the present disclosure is illustrated. Imaging system 100 includes a pixel array 102, a control circuit system 104, a readout circuit system 106, and functional logic 110. In one example, pixel array 102 is a two-dimensional (2D) array of photodiodes or image sensor pixels 112 (e.g., pixels P1, P2..., Pn). As illustrated, the photodiodes are arranged into rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx). In operation, the photodiodes or image sensor pixels 112 acquire image data of an external scene in response to detected incident light, which can then be used to reproduce a 2D image of a person, place, object, etc. However, in other embodiments, the photodiodes or image sensor pixels 112 may be arranged in configurations other than rows and columns.

[0027] As will be discussed, in various embodiments, one or more photodiodes or image sensor pixels 112 may also be configured to provide HDR image signals, in which case image charge generated by one or more photodiodes or image sensor pixels 112 in bright lighting conditions may also be transferred to coupled LOFICs and / or additional floating diffusions in each pixel circuit associated with the one or more photodiodes or image sensor pixels 112 to store image charge. For example, each of the pixel circuits associated with the one or more photodiodes or image sensor pixels 112 may include a LOFIC (e.g., a high-k based MIM capacitor) configured to store overflow image charge received from the coupled one or more photodiodes. In various embodiments, readout circuitry 106 may be configured to read out image signals through column bit lines 118 at different conversion gains.

[0028] In an embodiment, after each photodiode or image sensor pixel 112 in pixel array 102 acquires its image charge, the image data is read out by readout circuitry 106 via bit lines 118 and then transferred to function logic 110. In various embodiments, readout circuitry 106 may include signal amplifiers, analog-to-digital (ADC) conversion circuitry, and data transmission circuitry. Function logic 110 may store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or other). In some embodiments, control circuitry 104 and function logic 110 may be combined into a single functional block to control image capture of photodiodes or image sensor pixels 112 and read out image data from readout circuitry 106. For example, function logic 110 may be a digital processor. In one embodiment, readout circuitry 106 may read out image data one row at a time along readout column lines (bit lines 118) or may read out the image data using various other techniques, such as serial readout or full parallel readout of all pixels simultaneously (not illustrated).

[0029] In one example, the control circuit system 104 is coupled to the pixel array 102 to control the operation of the plurality of photodiodes or image sensor pixels 112 in the pixel array 102. For example, the control circuit system 104 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal for simultaneously enabling all photodiodes or image sensor pixels 112 within the pixel array 102 to simultaneously capture their respective image data during a single data acquisition window. In another embodiment, the shutter signal is a rolling shutter signal such that each row, column, or group of pixels is sequentially enabled during consecutive acquisition windows. In another example, image acquisition is synchronized with a lighting effect such as a flash. In one or more embodiments, the control circuit 104 may include circuitry for modulating or adjusting the voltage level of a bias voltage provided to a LOFIC associated with the plurality of photodiodes or image sensor pixels 112.

[0030] In one embodiment, readout circuitry 106 includes an analog-to-digital converter (ADC) that converts analog image data received from pixel array 102 into a digital representation. The digital representation of the image data may be provided to function logic 110. In some embodiments, data transfer circuitry 108 may receive the digital representation of the image data from the ADC in parallel and may provide the image data to function logic 110 serially.

[0031] In one example, the imaging system 100 is implemented on a single semiconductor wafer. In another example, the imaging system 100 is located on a stacked semiconductor wafer. For example, the pixel array 102 may be implemented on a pixel wafer, while the readout circuit system 106, the control circuit 104, and the functional logic 110 may be implemented on an application specific integrated circuit (ASIC) wafer, wherein the pixel wafer and the ASIC wafer are interconnected by bonding (hybrid bonding, oxide bonding, etc.) or one or more through substrate vias (TSVs). In another example, the pixel array 102 and the control circuit 104 are implemented on a pixel wafer, while the readout circuit 106 and the functional logic 110 are implemented on an ASIC wafer, wherein the pixel wafer and the ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, etc.) or one or more TSVs.

[0032] In various embodiments, the imaging system 100 may be incorporated into an imaging device of a digital camera, a mobile phone, a laptop computer, an endoscope, a security camera, a head mounted display device, or an imaging device for an automobile, etc. In addition, the imaging system 100 may be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other pieces of hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0033] Figure 2 is a graph of dielectric relaxation according to an embodiment of the present disclosure. The horizontal axis indicates the relaxation time in milliseconds (ms) for a high-k MIM LOFIC capacitor, and the vertical axis indicates the relaxation current in amperes. In general, for the same charge accumulated or stored in the high-k MIM LOFIC, a higher relaxation current requires a shorter relaxation time. For example, when the relaxation current is reduced from about 7E-11A to about 3E-12A, the relaxation time of the illustrated high-k MIM LOFIC capacitor increases to significantly above 33ms, making the idle period required for the image sensor to avoid image lag impractically long, i.e., the frame rate of the image sensor is reduced to an unacceptably small value. As discussed above, for many applications, the target relaxation time may be below 33ms or even below 20ms. Some embodiments of the inventive technology for reducing lag time are discussed below.

[0034] Figure 32 is an electrical schematic diagram of a pixel 210 according to an embodiment of the present disclosure. Pixel 210 may be coupled to a bit line 218, such as to provide a readout column of image data to a readout circuitry, such as readout circuitry 106. In operation, pixel 210 may receive control signals from a control circuitry, such as control circuitry 104, to control the operation of a plurality of transistors included in pixel 210. The control circuitry may control the operation of the plurality of transistors in a desired sequence with relative timing that ensures an orderly readout of the image data. The voltages provided to the different elements of pixel 210 are listed on the left hand side of the circuit, however, the differently labeled voltages may have the same or different values ​​in different embodiments.

[0035] The illustrated embodiment of the pixel 210 includes a photodiode (PD) 211, a first floating diffusion (FD1) 213, a transfer transistor 212, a double floating diffusion transistor 216, a second floating diffusion (FD2) 217 ​​connected to a lateral overflow integrating capacitor (LOFIC) 215, a lateral overflow gate transistor 234, a reset (RST) transistor 214, a row select transistor 221, and a source follower (SF) transistor 220. The transfer transistor 212 (which may also be referred to as a transfer gate 212) is coupled between the photodiode 211 and the first floating diffusion FD1 213 to control the charge transfer operation between the photodiode 211 and the first floating diffusion FD1 213. The transfer transistor 212 operates based on a transfer control signal TX applied to its gate terminal. The transfer transistor 212 is configured to be switched in response to the received transfer control signal TX. In the illustrated embodiment, the first floating diffusion FD1 213 is switched between the first floating diffusion FD1 213 and the second floating diffusion FD1 213. Figure 3 213 is depicted in the schematic diagram of as a capacitor coupled to transfer transistor 212, and dual floating diffusion transistor 216 selectively couples first floating diffusion FD1 213 to capacitor 219. In some embodiments, capacitor 219 is coupled to receive an optional floating diffusion capacitance control signal FDC and is coupled to first floating diffusion FD1 213 through dual floating diffusion transistor 216. In one example, floating diffusion capacitance control signal FDC can be used to provide a boost control signal to capacitor 219 coupled to first floating diffusion FD1 213. In embodiments, the combination of first floating diffusion FD1 213 and second floating diffusion FD2 (or floating node FD2) can also be collectively referred to as a floating diffusion associated with pixel 210. It should be appreciated that capacitor 219 can be formed by a junction capacitor metal-oxide-metal capacitor or a metal-insulator-metal capacitor.

[0036] While the dual floating diffusion transistor 216 is enabled (e.g., turned on), the coupling of the second floating diffusion FD2 217 with the first floating diffusion FD1 213 may provide additional capacitance to store charge photogenerated by the photodiode 211 and modulate the conversion gain of the pixel 210. For example, when the transfer transistor 212 is enabled to transfer the image charge accumulated by the photodiode 211 to the first floating diffusion FD1 213, the dual floating diffusion transistor 216 may be enabled to couple the LOFIC 215 to the first floating diffusion FD1 213, thereby providing additional capacitance to increase the overall charge capacity of the first floating diffusion FD1 213. In some embodiments, the bias voltage VCAP may be provided by a bias voltage source and configured to provide different voltage levels depending on the operation of the pixel 210 (e.g., whether the pixel 210 has been selected to be active during an integration period or a readout period).

[0037] RST transistor 214 may be coupled to receive a pixel reference voltage (e.g., voltage AVDD) and may be coupled to receive a reset control signal RSTG on its gate terminal. Reset transistor RST 214 is configured to be switched in response to reset control signal RSTG and is configured to reset pixel 210 during, for example, an idle period, a precharge period, and a readout period between an image signal readout and a reset signal readout.

[0038] LOFIC 215 may be coupled between bias voltage VCAP and second floating diffusion FD2 217. In the context of the present application, bias voltage VCAP may be implemented by a variable voltage source, by a combination of multiple voltage sources (in which individual voltage sources may be non-variable), or by other methods known to those skilled in the art. In an embodiment, a pixel reference voltage (e.g., voltage AVDD) is supplied by a pixel reference voltage source, which may be configured to provide a fixed voltage. In some embodiments, LOFIC 215 may be fabricated as a metal-to-metal (MIM) capacitor having an insulating material (e.g., a high-k dielectric) with a high dielectric constant sandwiched between a first metal electrode or plate and a second metal electrode or plate. In some embodiments, LOFIC 215 may be fabricated as a trench capacitor or a stacked MIM capacitor within a metal layer disposed on a substrate or wafer. For ease of reference, the first metal electrode or plate of the LOFIC 215 may be designated as the A side or CTM (capacitor top metal) side, and the second metal electrode or plate of the LOFIC 215 may be designated as the B side or CBM (capacitor bottom metal) side. The A side or CTM side of the LOFIC 215 is coupled to receive a bias voltage VCAP. The A side or CTM side of the LOFIC 215 is also coupled to receive a pixel reference voltage (e.g., voltage AVDD) through a second reset transistor 232. The second reset transistor 232 is configured to selectively couple the LOFIC 215 to a reference or pixel reference voltage (e.g., voltage AVDD) in response to a second reset control signal RST2. The B side or CBM of the LOFIC 215 is coupled to the first floating diffusion FD1 213 (first floating diffusion). The B side or CBM of the LOFIC 215 is coupled to the source of the reset transistor 214 and the drain of the lateral overflow gate transistor 234. In an exemplary operation, during a reset or precharge cycle, the reset control signal RSTG is configured to turn on the reset transistor 214 and the second reset control signal RST2 is configured to turn on the second reset transistor 232, so that both the A side or CTM side of the LOFIC 215 and the B side or CBM side of the LOFIC 215 are coupled to receive, for example, a pixel reference voltage (e.g., voltage AVDD) from a pixel reference voltage source to ensure zero bias across the LOFIC 215, thereby initiating a discharge process of the LOFIC 215. In various embodiments, the insulating material disposed between the first metal electrode or plate and the second metal electrode or plate of the LOFIC 215 may be a single layer of high-k material or a multi-layer stack, depending on the desired LOFIC capacitance. In various examples, the high-k material may include one of aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or a combination thereof. In different embodiments, the LOFIC 215 may be biased by a bias voltage VCAP 236.Additionally, the A side of the LOFIC 215 may be reset to a pixel reference voltage, such as voltage AVDD (or other voltage provided to the source side of the second reset transistor 232 ).

[0039] For later reference Figures 4 to 9 As explained, the bias voltage VCAP coupled to the LOFIC 215 may be modulated during an idle period (before the integration period). In some embodiments, the bias voltage VCAP may be modulated between a high bias voltage VCAPHi (e.g., 2.8V) and a low bias voltage VCAPLo (e.g., approximately 0V). In embodiments, other voltage levels may be implemented depending on, for example, the design and operating requirements of the image sensor. By controlling the voltage level of the bias voltage VCAP, the voltage across the LOFIC 215 may be adjusted. In various embodiments, the bias voltage VCAP may be supplied by a bias voltage source included in a control circuit (e.g., control circuit system 104) coupled to the pixel 210. It should also be appreciated that in various examples, the VCAPLO and VCAPHI bias voltage levels may be determined taking into account the stable range of the high-k material.

[0040] Continuing with the discussion of the circuitry of pixel 210, dual floating diffusion transistor 216 may be coupled between first floating diffusion FD1 213 and second floating diffusion FD2 217, and further coupled to receive dual floating diffusion control signal DFD on its gate terminal. That is, dual floating diffusion transistor 216 is configured to be turned on in response to dual floating diffusion control signal DFD and is configured to transfer image charge from first floating diffusion FD1 213 to second floating diffusion FD2 217, thereby allowing image charge to overflow from photodiode 211 through first floating diffusion FD1 213 to second floating diffusion FD217, for example, when photodiode 211 is saturated or when the generated charge exceeds the full well capacity (FWC) of photodiode 211. Lateral overflow gate transistor 234 may be coupled between FD2 217 and LOFIC 215, and further coupled to receive lateral overflow gate control signal LFG on its gate terminal. 218. Lateral overflow gate transistor 234 is configured to be switched in response to lateral overflow gate control signal LFG. In addition, a gate terminal of source follower transistor SF 220 is coupled to floating diffusion node FD1 213. A source / drain terminal of source follower transistor SF 220 is coupled between a reference or pixel voltage (e.g., voltage AVDD) and a row select transistor. Row select transistor 221 may be coupled between bit line 218 and source follower SF transistor 220. Row select transistor 221 is configured to be switched in response to row select control signal RS and is configured to selectively transmit a signal from source follower transistor SF 220 to bit line 218. It should be appreciated that pixel 210 may include fewer, additional, and / or alternative components (e.g., transistors, capacitors, buffers, switches) depending on the specific requirements of the imaging system.

[0041] In operation, the transfer transistor 212 receives a transfer control signal TX to enable, for example, charge transfer from the photodiode 211 to the first floating diffusion FD1 213 during a charge transfer period following an integration period. In general, the amount of charge transfer depends on the exposure of the photodiode 211 and the operation of the pixel 210. In some embodiments, the capacitor 219 may be formed by metallization present in the physical layout of the device. The transfer transistor 212, the dual floating diffusion transistor 216, and the lateral overflow gate transistor 234 are configured to allow excess photogenerated charge (e.g., generated in strong light conditions) to overflow from the photodiode 211 to the LOFIC 215. In some embodiments, the LOFIC 215 may increase the charge storage capacity, such as capacitance, of the second floating diffusion FD2 217. For example, in response to high intensity illumination, the photodiode 211 may generate more charge than the first floating diffusion FD1 213 can store. The additional or excess charge may be stored by the LOFIC 215. In some embodiments, the bias voltage VCAP modulates how much charge can be stored by the LOFIC 215. In general, the first floating diffusion FD1 213 is read in conjunction with the high conversion gain (HCG) portion of the data readout, while the second floating diffusion FD2 217 and the floating diffusion 213 are read in conjunction with the low conversion gain (LCG) portion of the readout. Collectively, the HCG and LCG readouts constitute a dual conversion gain (DCG) data readout.

[0042] In some embodiments, the operation of the RST transistor 214 and the double floating diffusion transistor 216 can reset the floating diffusion FD1 213 to a high voltage representing a dark state because the photogenerated electrons, when transferred to the first floating diffusion FD1 213, cause the voltage to decrease in proportion to the intensity of the charge of the photodiode PD 211. In order to reset the first floating diffusion FD1 213, the RST transistor 214, the lateral overflow gate transistor 234, and the double floating diffusion transistor 216 are enabled (turned on) by their respective control signals. In some embodiments, the RST transistor 214 can be in an on state while the double floating diffusion transistor 216 remains in an off state, thereby resetting the second floating diffusion FD2 217 but not resetting the first floating diffusion FD1 213. In an embodiment, the second reset transistor 232 is configured to provide a local reset to the coupled LOFIC 215, reduce the load effect, and improve the stabilization time of the LOFIC 215.

[0043] Example 1

[0044] Figure 4 is a diagram illustrating an embodiment of the present disclosure (eg, Figure 3) is an exemplary timing diagram of the operation of an image sensor. The different periods of the pixel operation cycle associated with the pixel - readout, idle, precharge, integration, next readout of the next frame, etc. are shown in the LOFIC (e.g., Figure 3 215) and the voltage at the top metal electrode or plate of the capacitor (referred to as the CTM side or A side) and the bottom metal electrode or plate of the capacitor (referred to as the CBM side or B side). These different time periods are not drawn to scale. For example, in many embodiments, the integration period may be significantly longer than other illustrated periods of the pixel operation cycle. The illustrated bias voltage range across the LOFIC 215 may be from 0V to 2.8V, however, in different embodiments, different operating voltage ranges may be applied to the CTM and CBM sides of the LOFIC 215 by configuration of the bias voltage VCAP applied to the CTM side or by charge accumulation on the CBM side (e.g., charge overflowing from the photodiode 211). A row of capacitor images at the bottom of the figure represent voltage bias states across the LOFIC 215 at different periods of the pixel operation cycle. As explained above, LOFIC 215 may be a high-k MIM capacitor, ie, a high-k dielectric sandwiched between a capacitor top metal electrode or plate (first metal electrode or plate) and a capacitor bottom metal electrode or plate (second metal electrode or plate).

[0045] It should be understood that the bias voltage VCAP applied to the top metal electrode (or first metal electrode) of the capacitor can be configured to forward bias, zero bias, or reverse bias the LOFIC 215 by adjusting the voltage value at the top metal electrode (or first metal electrode) of the capacitor to be higher, equal to, or lower than the voltage value at the bottom metal electrode (or second metal electrode) of the capacitor applied to the floating node between the reset transistor 214 and the lateral overflow gate transistor 234, respectively. The voltage applied to the top metal electrode (or first metal electrode) of the capacitor can be referred to as the first bias voltage value and the voltage applied to the bottom metal electrode (or second metal electrode) of the capacitor can be referred to as the second bias voltage value. The first bias voltage value at the top metal electrode of the capacitor can be configured to be higher, equal to, or lower than the second bias voltage value at the bottom metal electrode of the capacitor.

[0046] For example, when the first bias voltage value at the CTM side exceeds the second bias voltage value at the CBM side, the LOFIC 215 is configured to be forward biased. Conversely, when the first bias voltage value at the CTM side is less than the second voltage value at the CBM side, the LOFIC 215 is configured to be reverse biased. When the first bias voltage value at the CTM side is equal to the second bias voltage value at the CBM side, the LOFIC 215 is configured to be zero biased.

[0047] In some embodiments, the control circuit (e.g., Figure 1 The control circuit 104 illustrated in FIG. 1 may include circuitry that modulates the voltage level supplied by the bias voltage VCAP. In some embodiments, the bias voltage VCAP may be included on an ASIC die, while the control circuit is included on a pixel die. In other embodiments, the bias voltage VCAP may be included on an ASIC die with the control circuit.

[0048] In some embodiments, during an idle period, for example, by configuring the bias voltage to be adjusted and closing the switch 236 coupling the CTM side (side A) of the LOFIC 215 to receive the bias voltage VCAP, applying a first bias voltage value to the CTM side (side A) Figure 3 214). As shown in FIG. 215 , the CTM side (Side A) of the LOFIC 215 is set to a first bias voltage value (e.g., 1.4V) while the CBM side (Side B) is at a second bias voltage value (e.g., 2.8V), which may be supplied by a pixel reference voltage (e.g., voltage AVDD) through the reset transistor 214. As previously described, the voltage bias across the LOFIC 215 is defined as the difference between the voltage at the CTM side (e.g., from the bias voltage VCAP) and the voltage at the CBM plate (e.g., the voltage at the node between the reset transistor 214 and the lateral overflow gate transistor 234). Thus, during the idle period, the LOFIC 215 may be reverse biased to compensate for the residual charge accumulated from the previous frame. For example, the LOFIC 215 may be biased with a voltage of -1.4V.

[0049] In a pre-charge cycle following an idle period, the LOFIC 215 may be configured to be zero biased to begin the discharge process.

[0050] At the beginning of the integration period, after the precharge (reset) period is complete, both the CTM side (Side A) and the CBM side (Side B) of the LOFIC may be set to a common bias voltage, such as 1.4 V. The bias voltage at the CTM side (Side A) may be set by the action of switch 236, where the bias voltage VCAP is configured accordingly, and a second bias voltage value at the CBM side (Side B) may be set by the pixel reference voltage (e.g., by the voltage AVDD of reset transistor 214). Thus, at the beginning of the integration period, there is a 0V voltage bias across the plates of the LOFIC 215 (i.e., the LOFIC 215 is zero biased at the beginning of the integration period). As charge accumulates during the integration period (e.g., as excess photogenerated charge overflows from photodiode PD 211 to LOFIC 215), the second bias voltage value at the CBM side of LOFIC 215 decreases to a lower voltage value, such as 0 V (for bright light), at the end of the integration period due to the accumulation of negative charge generated by photodiode PD 211 at LOFIC 215. Thus, in this example representing relatively bright external conditions, at the end of the integration period, LOFIC 215 may be forward biased to 1.4 V.

[0051] The above voltage numbers are given as non-limiting examples. For example, the integration period does not necessarily end exactly with the CBM side of the LOFIC 215 at 1.4V, resulting in a 0V bias. In different embodiments, the illustrated voltage values ​​may vary while still embodying the principles that characterize the operation of these different embodiments.

[0052] The integration period is followed by a readout period, which may be followed by another idle period of the next frame, and so on. Depending on the value of the second bias voltage at the CBM side of LOFIC 215 at the end of the integration period corresponding to the amount of charge accumulated in LOFIC 215, the next idle period may require a longer or shorter time to properly discharge the LOFIC (e.g., high-k MIM capacitor), thus potentially resulting in a high lag time between pixel exposures. Figure 5A and 5B Describe some lag time scenarios. For ease of reference and without loss of generality, Figure 5A , 5B The bias voltage of the LOFIC 215 illustrated in the figures in 8A and 8B is shown as being normalized to 1V to -1V.

[0053] Figure 5A and 5B is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure. Specifically, Figure 5A The diagram illustrates the crossover of the LOFIC (e.g., Figure 3215) is an exemplary representation of the voltage change of the LOFIC 215, while Figure 5B The diagram illustrates the crossover of the LOFIC (e.g., Figure 3 215). In both cases, the horizontal axis represents time: the idle period to the left of the coordinate origin and the integration period to the right of the coordinate origin. The vertical axis represents the voltage change across the LOFIC (e.g., Figure 3 The voltage bias of the top and bottom metal electrodes or plates of the LOFIC 215) is such that a negative bias corresponds to a positive bias of the LOFIC (e.g., Figure 3 The CTM side of the LOFIC 215) has a lower voltage value than the voltage value of the CBM side of the LOFIC (e.g., the LOFIC is reverse biased), and a positive bias corresponds to the CTM side of the LOFIC having a higher value than the CBM side of the LOFIC (e.g., the LOFIC is forward biased). These voltage biases are represented in a range from about -1V (bias low or BL) to about +1V (bias high or BH), however, these values ​​should be understood to be merely representative voltage values ​​and other values ​​are possible in different embodiments, depending on the design of the image sensor and the voltages provided to different nodes of the image sensor circuitry. In addition, in the context of the present disclosure, the terms "about," "approximately," and similar terms mean + / - 5% of the stated value.

[0054] Figure 5A The diagram illustrates the LOFIC during the integration process under relatively bright (bright) conditions (e.g., Figure 3 At the beginning of the integration period, the voltage bias BL across the top and bottom metal plates of the LOFIC is approximately 0V. When the LOFIC (e.g., Figure 3 When the LOFIC 215 of FIG. 1 accumulates the charge generated by the photodiode PD 211 during the integration period in response to the amount of incident light, the LOFIC (eg, Figure 3 LOFIC 215) is positively biased or forward biased, for example, at the end of the integration period, the final voltage bias BH is positive 1V. The integration period is followed by the readout period, and then followed by the next idle period of the next frame. Figure 3 The LOFIC 215 of FIG. 215 is negatively biased to -1V at the beginning of the idle period, so this negative bias actually speeds up the positively biased LOFIC (eg, Figure 3 LOFIC 215), thereby reducing the discharge of the LOFIC (e.g., a high-k MIM LOFIC capacitor, such as Figure 3 LOFIC 215) associated image lag and improve the frame rate of the image sensor.

[0055] Figure 5B The diagram illustrates the crossover of the LOFIC (e.g., Figure 3 The voltage of the top and bottom metal electrodes or plates of the LOFIC 215) changes. Figure 5A In the case shown in FIG. , the integration period is spanned by LOFIC (eg, Figure 3 The LOFIC 215 is started with a 0V voltage bias (BL) on the top and bottom metal electrodes or plates. Figure 3 LOFIC 215) has been negatively biased (reverse biased), so during the idle period, the LOFIC (e.g., Figure 3 Therefore, even if the photodiode PD 211 remains exposed to a dark field during the integration period, and the voltage of the photodiode remains at or near 0V at the end of the integration period, the charge accumulated in the LOFIC 215 may not be fully discharged. Figure 5A ), during the negative voltage bias (reverse bias) operation in the idle period at the LOFIC (e.g., Figure 3 The photogenerated charge accumulated in the LOFIC 215) may not be offset by the charge accumulated during the positive voltage bias operation in the integration period. Figure 3 The problem of image lag associated with the LOFIC 215) due to residual charge remaining in the LOFIC may still exist, as explained above, which may affect the overall image quality or operation of the image sensor due to the need for longer idle periods and the inability to have a frame rate.

[0056] Example 2

[0057] Fig. 6A is an electrical schematic diagram of a pixel according to an embodiment of the present disclosure. The schematic diagram illustrates a pixel circuit system with a LOFIC. The voltage bias operation applied to the LOFIC can be relatively easily incorporated into existing image sensor products because it is similar to Figure 3 Compared to the pixel schematic shown in FIG. 1 (for example, an additional transistor for local reset needs to be added), here only the bias operation of the bias voltage VCAP needs to be configured. In some embodiments, this update can be achieved by tuning the pixel control circuit system (for example, Figure 1 The control circuit system 104 is implemented by designing an existing application-specific integrated circuit (ASIC).

[0058] Figure 6Bis a timing diagram illustrating various stages of image sensor operation according to an embodiment of the present disclosure. Figure 6B Can be displayed with Fig. 6A . The bottom row of capacitor symbols illustrates the voltages at the top metal electrode of the capacitor (CTM side or A side) and the bottom metal electrode of the capacitor (CBM side or B side) during different periods of the pixel operation cycle - readout, idle, precharge, integration, turn to next readout, etc. As previously mentioned, the illustrated voltage range is from 0V to 2.8V, however, in different embodiments, different voltage ranges may be applied.

[0059] In an embodiment, during an idle period, both the CTM side (Side A) and the CBM side (Side B) of the LOFIC 215 in the pixel 210B are configured to receive a common bias voltage value that causes the LOFIC 215 to be zero biased, thereby allowing the LOFIC to discharge. Figure 6B , the CTM side (A side) of the LOFIC 215 is set to 2.3 V by closing the switch 236 that couples the bias voltage VCAP to the CTM side (A side) of the LOFIC 215, thereby providing a first bias voltage value of 2.3 V to the CTM side (A side) of the LOFIC 215, while the CBM side (B side) is also set to a second bias voltage value of 2.3 V by enabling the reset transistor 214. In this embodiment, during the idle period, the LOFIC 215 is zero biased, so that the LOFIC 215 begins the discharge process.

[0060] During the precharge or reset cycle, the CTM side (Side A) of the LOFIC 215 is set to a first bias voltage value lower than a second bias voltage value applied to the CBM side (Side B) of the LOFIC 215, so that the LOFIC 215 is reverse biased. For example, the CTM side (Side A) of the LOFIC 215 is set to a first bias voltage value of 2.3V by configuring the bias voltage VCAP, and the CBM side (Side B) of the LOFIC is set to a second bias voltage value of 2.8V by configuring the voltage level of the pixel reference voltage (e.g., voltage AVDD). At the beginning of the integration period, the CTM side (Side A) of the LOFIC 215 is set to a first bias voltage value lower than the second bias voltage value applied to the CBM side (Side B) of the LOFIC 215, so that the LOFIC 215 continues to be reverse biased. For example, at the beginning of the integration period, after precharge (reset) is completed, the CTM side (A side) of the LOFIC 215 is set to a first bias voltage value of 0.9V by configuring the bias voltage VCAP, and the CBM side (B side) of the LOFIC is set to a second bias voltage value of 1.4V by configuring the pixel reference voltage (e.g., voltage AVDD). Thereafter, at the beginning of the integration period, there is a -0.5V voltage bias across the LOFIC 215, that is, the LOFIC 215 is configured to be reverse biased at the beginning of the integration period. In the illustrated embodiment, the bias voltage VCAP can be configured in a manner such that the first bias voltage value applied to the CTM side (A side) of the LOFIC 215 during the integration period is lower than the first bias voltage value applied to the CTM side (A side) of the LOFIC 215 during the precharge period to ensure a target bias voltage across the LOFIC 215 and a required voltage swing range for the LOFIC readout voltage.

[0061] When the photodiode PD photogenerates charge in response to incoming light (e.g., under bright light conditions), the charge may begin to accumulate in the LOFIC 215 during the integration period, and the voltage value (e.g., the second bias voltage value) at the CBM side of the LOFIC 215 may begin to decrease to a lower value (e.g., 0.4V) such that the LOFIC 215 may be forward biased at the end of the integration period due to the accumulation of negative charge at the LOFIC 215. Thus, the LOFIC 215 changes its voltage bias from -0.5V (BL) at the beginning of the integration period to 0.5V (BH) at the end of the integration period. That is, the LOFIC 215 may be reverse biased at the beginning of the integration period and become forward biased as the LOFIC 215 accumulates charge overflowing from the photodiode PD 211. This may compensate or counteract residual charge accumulated in the LOFIC 215 (e.g., charge accumulated and trapped by the insulating material of the LOFIC 215 during the current or previous frame), thus reducing the LOFIC 215 discharge time and thereby reducing image lag associated with the LOFIC 215. For example, image charge accumulated during an idle period and discharged from the LOFIC 215 and accumulated during a forward bias operation and discharged from the LOFIC 215 have opposite polarity and may compensate each other during a subsequent readout operation. In this way, trapped charge released from the insulating material of the LOFIC may be reduced or eliminated in a manner such that those trapped charges will not affect the readout voltage (signal) of the LOFIC 215 being read during a readout operation.

[0062] On the other hand, under dark field conditions, little or no charge is generated by the photodiode PD, and the LOFIC 215 maintains its initial voltage bias of -0.5 V. It should be understood that the amount of charge that can be stored in the LOFIC 215 is related to the bias voltage applied across the LOFIC 215, so by reducing the bias voltage across the LOFIC 215, the charge can be stored in the LOFIC 215. Figure 5B Compared to the illustration in FIG. 1 , the amount of charge accumulated and stored in the LOFIC 215 under dim light conditions can be reduced accordingly. In this way, the discharge time of the LOFIC 215 can be shortened and the image lag problem associated with the LOFIC 215 can be reduced during subsequent readout operations.

[0063] Figures 7A to 7C Graph illustrating a sample signal voltage of a high-k (high dielectric constant) metal-to-metal (MIM) LOFIC versus the amount of charge accumulated in the LOFIC during an integration period according to an embodiment of the present disclosure. Figures 7A to 7C The diagram shows Fig. 6AAs explained above, the above voltage values ​​are given as non-limiting examples, and in different embodiments, the illustrated voltage values ​​may vary while still embodying the principles that characterize the operation of these different embodiments.

[0064] Fig. 7A The diagram illustrates that in a low signal (relatively low light condition) scenario, at the end of the integration period, LOFIC (eg, Fig. 6A The voltages on the CTM side (side A) and the CBM side (side B) of the LOFIC (e.g., LOFIC 215) are measured. In this scenario, the CTM side of the LOFIC (e.g., LOFIC 215) is maintained at its initial value of 0.9V (first bias voltage value) throughout the integration period. Since a relatively small amount of charge is generated by the photodiode PD during the integration period, the voltage on the CBM side of the LOFIC (e.g., LOFIC 215) (second bias voltage value) also remains unchanged at or close to 1.4V. Therefore, the LOFIC (e.g., LOFIC 215) continues to be reverse biased.

[0065] Figure 7B The diagram illustrates the voltages on the CTM side (side A) and CBM side (side B) of the LOFIC (e.g., LOFIC 215) at the end of the integration period in the scenario of a medium level signal (medium brightness field). Here, a considerable amount of charge is generated by the photodiode PD (e.g., photodiode PD 211) during the integration period, thus causing the second bias voltage value at the CBM side of the LOFIC (e.g., LOFIC 215) to change from 1.4 V to 0.9 V, which is equivalent to changing the bias voltage of the LOFIC (e.g., LOFIC 215) from -0.5 V to 0 V. That is, the LOFIC (e.g., LOFIC 215) is configured to operatively transition from reverse bias operation to zero bias operation.

[0066] Figure 7C The diagram illustrates the voltage values ​​on the CTM side (side A) and the CBM side (side B) of the LOFIC (e.g., LOFIC 215) at the end of the integration period in the scenario of a high level signal (bright field). Here, a relatively high amount of charge generated by the photodiode PD (e.g., photodiode PD 211) overflows to the coupled LOFIC (e.g., LOFIC 215) during the integration period, resulting in a second bias voltage value at the CBM side of the LOFIC (e.g., LOFIC 215) changing from 1.4V to 0.4V, which is equivalent to changing the voltage bias of the LOFIC (e.g., LOFIC 215) from -0.5V to 0.5V. That is, the LOFIC (e.g., LOFIC 215) is configured to operatively transition from reverse bias operation to forward bias operation. Referring to FIG. 2 and FIG. 3 , the charge generated by the photodiode PD (e.g., photodiode PD 211) overflows to the coupled LOFIC (e.g., LOFIC 215) during the integration period, resulting in a second bias voltage value at the CBM side of the LOFIC (e.g., LOFIC 215) changing from 1.4V to 0.4V, which is equivalent to changing the voltage bias of the LOFIC (e.g., LOFIC 215) from -0.5V to 0.5V. That is, the LOFIC (e.g., LOFIC 215) is configured to operatively transition from reverse bias operation to forward bias operation. Fig. 8A and 8B The relevance of these end bias operations of LOFIC is discussed.

[0067] Fig. 8A and 8B is a timing diagram associated with an exemplary pixel (eg, pixel 210B) according to an embodiment of the present disclosure. Specifically, Fig. 8A Graphical instructions are above Figure 7C The change in LOFIC voltage bias during the integration process under relatively bright conditions, while Figure 8B Graphical instructions are above Fig. 7A The voltage change of the LOFIC during the integration process under relatively dark (low light) conditions. In both figures, the horizontal axis represents time: the idle time is to the left of the coordinate origin and the integration time is to the right of the coordinate origin. The vertical axis represents the voltage bias across the LOFIC, with a negative bias corresponding to the CTM side of the LOFIC having a bias voltage value lower than the bias voltage value of the CBM side of the LOFIC, and a positive bias corresponding to the CTM side of the LOFIC having a higher value than the CBM side of the LOFIC. These voltage biases are represented as ranging from about -0.5V (BL) to about 0.5V (BH), however, these values ​​should be understood to be merely representative voltage values ​​and other values ​​are possible in different embodiments, depending on the design of the image sensor and the voltages provided to different nodes of the image sensor circuit system.

[0068] Fig. 8A Graphical instructions are above Figure 7C The voltage bias of LOFIC changes during the integration process under relatively bright (bright) conditions. At the beginning of the integration process, the voltage across LOFIC (e.g., Fig. 6A The voltage bias of the electrode or plate of the LOFIC 215 of the pixel 210B in FIG. 2 is about -0.5 V. With the LOFIC (e.g., Fig. 6A The LOFIC 215 of the pixel 210B in FIG. 2 accumulates the charge generated by the photodiode PD, and at the end of the integration period, the final voltage bias is about 0.5 V. By allowing the LOFIC (e.g., Fig. 6A Transitioning the LOFIC 215 of pixel 210B in FIG. 2 from a reverse bias to a forward bias may compensate or cancel the residual charge in the LOFIC, thereby reducing image lag associated with the LOFIC.

[0069] Figure 8B Graphical instructions are above Fig. 7A Under relatively dark (low light) conditions, the LOFIC is crossed during the integration process (e.g., Fig. 6A The voltage of the electrode or plate of the LOFIC 215 of the pixel 210B in FIG. Fig. 8AIn the case shown in , the integration process begins with a -0.5 V bias across the electrodes or plates of the LOFIC. However, since the photodiode is still exposed to a dark field during the integration process, the photodiode generates little or no charge, so at the end of the integration period, the voltage bias of the LOFIC remains unchanged at -0.5 V.

[0070] Since LOFIC returns to its 0V bias at the beginning of the next idle period, Fig. 8A In either of the scenarios in 8B (bright light) and 8B (dark field), the voltage bias across the plates of the LOFIC is maintained within a maximum range of -0.5V to 0.5V. In many embodiments, limiting the voltage bias across the CTM and CBM electrodes or plates of the LOFIC results in a smaller amount of charge being accumulated on the electrodes or plates because the charge (Q) of a capacitor is the product of the capacitance (C) of the capacitor and the magnitude of the bias voltage (V), i.e., Q=CV. When the voltage bias across the CTM and CBM electrodes or plates of the LOFIC is limited to approximately + / -0.5V, the charge Q of the capacitor is also reduced, thereby reducing the lag time of the capacitor. Therefore, at the start of the next idle process, the amount of lag accumulated by the LOFIC (e.g., high-k MIM capacitor) is smaller, thereby achieving a shortened idle time and improved frame rate. Furthermore, since the LOFIC voltage bias during the idle period is approximately 0V, there is no need for a complex bias voltage VCAP control that sets the voltage bias to a specific predetermined value for a specific amount of time during the idle period.

[0071] Example 3

[0072] Fig. 9 is a timing diagram illustrating various stages of image sensor operation according to an embodiment of the present disclosure. Fig. 9 Display for Fig. 6A The bottom row of capacitors illustrates the LOFICs (e.g., Fig. 6A 210B in FIG. 214 . The illustrated voltage range during the integration period ranges from 2.8V to 0V, however, in different embodiments, different voltages may be used.

[0073] In some embodiments, during an idle period, the LOFIC (e.g., Fig. 6AThe CTM side of the LOFIC 215 of FIG. 6 is coupled to a switch (eg, switch 236 of FIG. 6 ) of a bias voltage VCAP (supplied from a bias voltage source) and the LOFIC (eg, Fig. 6A The CTM side (side A) of the LOFIC 215 of the pixel 210B in FIG. 2 is set to a first bias voltage value of 1.4 V, while the CBM side (side B) of the LOFIC is set to a second bias voltage value of approximately 0 V by enabling the reset transistor, thereby allowing the CBM side (side B) of the LOFIC to be coupled to a pixel reference voltage source (e.g., a voltage source that provides a pixel reference voltage (e.g., voltage AVDD)). Thus, during the idle period, the LOFIC (e.g., Fig. 6A LOFIC 215) is biased to about 1.4 V. That is, the LOFIC (e.g., Fig. 6A During the precharge cycle, the LOFIC (e.g., Fig. 6A The CTM side (Side A) of the LOFIC 215 of FIG. 214 may continue to be set at 1.4V while the CBM side (Side B) is set to approximately 2.8V, thereby causing the LOFIC (eg, Fig. 6A The LOFIC 215) is reverse biased to compensate or cancel the LOFIC (e.g., Fig. 6A A portion of the residual charge accumulated in LOFIC 215).

[0074] At the beginning of the integration period, after precharge (reset) is completed, the CTM side (A side) of LOFIC is set to 0V (e.g., by configuring the bias voltage VCAP) and LOFIC (e.g., Fig. 6A The CBM side (B side) of the LOFIC 215 is set to 1.4 V. That is, at the beginning of the integration period, the voltage across the LOFIC (e.g., Fig. 6A The plates of the LOFIC 215 are biased at -1.4V, causing the LOFIC to be reverse biased. When the photodiode PD is exposed to bright light, as charge accumulates during the integration period, the LOFIC (e.g., Fig. 6A The voltage value (eg, the second bias voltage value) at the CBM side of the LOFIC 215) is due to the negative charge generated by the PD 211 in the LOFIC (eg, Fig. 6A The accumulation at LOFIC 215 of FIG. 215 decreases to a lower value, such as about 0 V, at the end of the integration period. Therefore, LOFIC (e.g., Fig. 6AThe voltage bias of the LOFIC 215 changes from about -1.4V (reverse bias) at the beginning of the integration period to about 0V (zero bias) at the end of the integration period. However, in a dark field scenario, little or no charge is generated by the photodiode PD, and the LOFIC (e.g., Fig. 6A The LOFIC 215 maintains its initial bias of -1.4V. Fig. 10A and 10B Explain the two scenarios (bright field and dark field).

[0075] Fig. 10A and 10B is a timing diagram of LOFIC voltage bias according to an embodiment of the present disclosure. Fig. 10A Graphical instructions are above Fig. 9 During the integration process, LOFIC (e.g., Fig. 6A The voltage of LOFIC 215) changes, while Fig. 10B Graphical instructions are above Fig. 9 The voltage change of the LOFIC during the integration process under relatively dark (low light) conditions. In both figures, the horizontal axis represents time: the idle period to the left of the coordinate origin and the integration period to the right of the coordinate origin. The vertical axis represents the voltage change across the LOFIC (e.g., Fig. 6A The voltage biases of the CTM and CBM electrodes or plates of the LOFIC 215 are shown as ranging from -1V to 1V across the LOFIC, however, these values ​​should be understood to be representative voltage values ​​only and other values ​​are possible in different embodiments.

[0076] Fig. 10A The diagram illustrates the LOFIC (e.g., Fig. 6A During the idle period before the integration period, the voltage of the LOFIC (e.g., Fig. 6A The LOFIC 215 is configured to have positive 1V across the plates of the LOFIC, causing the LOFIC to be forward biased. At the beginning of the integration period, the voltage bias across the plates of the LOFIC is about -1V (BL). As the LOFIC (e.g., Fig. 6A The LOFIC 215 of the embodiment of the present invention accumulates the charge generated by the photodiode PD, and at the end of the integration period, the final bias across the LOFIC can be reduced to about 0V (BH). That is, the LOFIC is configured to be biased in the opposite direction across the plates of the LOFIC during the idle period and the subsequent integration period, so that the LOFIC (e.g., Fig. 6AThe residual charge in LOFIC 215) can be stably compensated, thereby maintaining the LOFIC read voltage at the CBM side (B side) of the LOFIC (or the junction node between the reset transistor (e.g., reset transistor 214) and the lateral overflow gate transistor (e.g., lateral overflow gate transistor 234)) during the read cycle.

[0077] Fig. 10B The diagram illustrates the crossover of the LOFIC (e.g., Fig. 6A During the idle period, the LOFIC (e.g., Fig. 6A LOFIC 215) is configured to span across LOFIC (e.g., Fig. 6A The plates of the LOFIC 215) have positive 1V, causing the LOFIC (e.g., Fig. 6A The LOFIC215) is forward biased. Fig. 10A In the case (integration period) shown in FIG. , LOFIC (e.g., Fig. 6A LOFIC215) is configured to span LOFIC (e.g., Fig. 6A The electrodes or plates of the LOFIC 215 are reverse biased at -1 V. However, since the photodiode remains exposed to the dark field during the integration period, the photodiode generates little or no charge, so at the end of the integration period, the LOFIC (e.g., Fig. 6A The voltage bias of the LOFIC 215 is maintained constant at approximately -1 V. Thus, the charge accumulated during the idle period and the charge accumulated during the integration period have opposite polarity and can compensate for each other, for example, canceling out the charge accumulated from the LOFIC (e.g., Fig. 6A The trapped charge is released by the insulating material of the LOFIC 215, thereby reducing image lag during a subsequent readout cycle in relatively dark landscape conditions.

[0078] Due to LOFIC (e.g. Fig. 6A The voltage bias of the LOFIC 215 returns to -1V at the beginning of the idle period. Fig. 10B In the case of dark conditions, the voltage bias of the LOFIC is reversed from -1V at the end of the integration period to 1V at the beginning of the idle period, which accelerates the discharge process of the LOFIC and thus reduces the lag time of the LOFIC. Fig. 10A Under relatively bright (bright) conditions, this reversal of the voltage bias of the LOFIC does not exist. As a result, under bright field conditions, Fig. 10B Compared with the situation described in , the minimum idle period can still be kept relatively long.

[0079] The above description of the illustrated examples of the present invention including the contents described in the Abstract of the Invention is not intended to be exhaustive or limited to the precise form disclosed. Although specific embodiments and examples of the present invention are described herein for illustrative purposes, various equivalent modifications may be made without departing from the broader spirit and scope of the present invention. In fact, it should be understood that specific exemplary voltages, currents, frequencies, power range values, times, etc. are provided for explanation purposes, and other values ​​may also be adopted in other embodiments and examples according to the teachings of the present invention. In the context of the present disclosure, the terms "about", "approximately" and similar terms mean + / -5% of the stated value.

[0080] These modifications may be made to examples of the present invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A method for reducing image lag associated with a pixel included in a plurality of pixels, the pixel comprising a photodiode, a first floating diffusion coupled to the photodiode through a transfer transistor, a second floating diffusion coupled to the first floating diffusion through a double floating diffusion transistor, and a lateral overflow integrating capacitor coupled between the second floating diffusion and a bias voltage source, and the lateral overflow integrating capacitor is further coupled to a pixel reference voltage source through a reset transistor, wherein the operation of the pixel includes an idle period and an integration period after the idle period, The method comprises: configuring the lateral overflow integration capacitor to be zero biased or forward biased during the idle period; and When the photodiode is exposed to light, the lateral overflow integration capacitor is configured to be reverse biased at least at the beginning of the integration period.

2. The method of claim 1 , wherein the lateral overflow integrating capacitor comprises an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is selectively coupled to receive a first bias voltage from the bias voltage source, wherein the second metal electrode is selectively coupled to the pixel reference voltage source to receive a second bias voltage; wherein configuring the lateral overflow integration capacitor to be zero biased during the idle period comprises: coupling the bias voltage source to the first metal electrode of the lateral overflow integrating capacitor to provide the first bias voltage to the first metal electrode of the lateral overflow integrating capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integrating capacitor to the pixel reference voltage source, thereby providing the second bias voltage to the second metal electrode of the lateral overflow integrating capacitor; The first bias voltage and the second bias voltage are configured to be the same.

3. The method of claim 2, wherein configuring the lateral spillover integration capacitor to be reverse biased at the beginning of the integration period comprises: The first bias voltage is configured to be lower than the second bias voltage at the beginning of the integration period.

4. The method according to claim 3, comprising: configuring the transfer transistor and the dual floating diffusion transistor such that image charge photogenerated by the photodiode overflows into the lateral overflow integration capacitor during the integration period, thereby causing the second bias voltage at the second metal electrode to decrease; and The first bias voltage of the bias voltage source is configured so that the lateral overflow integration capacitor is reverse biased at the beginning of the integration period and becomes forward biased at a later time during the integration period as the second bias voltage at the second metal electrode of the lateral overflow integration capacitor decreases to less than the first bias voltage provided to the first metal electrode, wherein the forward bias voltage between the first metal electrode and the second metal electrode is set based on the amount of overflow image charge received from the photodiode. The method of claim 4 , wherein the forward bias voltage is configured to be equal to a reverse bias voltage at the beginning of the integration period. The method according to claim 5 , wherein the forward bias voltage is 0.5V.

7. The method of claim 1, wherein the lateral overflow integrating capacitor comprises an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is selectively coupled to the bias voltage source, wherein the second metal electrode is selectively coupled to the pixel reference voltage source; Wherein configuring the lateral overflow integration capacitor to be forward biased during the idle period comprises: coupling the bias voltage source to the first metal electrode of the lateral overflow integrator capacitor to provide a first bias voltage to the first metal electrode of the lateral overflow integrator capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integrating capacitor to the pixel reference voltage source, thereby providing a second bias voltage to the second metal electrode of the lateral overflow integrating capacitor, The first bias voltage is greater than the second bias voltage.

8. The method of claim 7, wherein when the lateral overflow integration capacitor is configured to be forward biased during the idle period, the lateral overflow integration capacitor is configured to be reverse biased during the integration period, so that charges accumulated in the lateral overflow integration capacitor during the idle period and during the integration period compensate each other, thereby maintaining the read voltage at the second metal electrode during the read period occurring after the integration period.

9. The method of claim 1 , wherein the operation of the pixel further comprises a pre-charge period between the idle period and the integration period, comprising configuring the first bias voltage of the bias voltage source to be less than the second bias voltage of the pixel reference voltage source during the pre-charge period so that the lateral overflow integration capacitor is reverse biased.

10. The method according to claim 9, further comprising: The first bias voltage in the integration period is configured to be smaller than the first bias voltage in the pre-charge period.

11. An image sensor, comprising: A plurality of pixels are arranged in a plurality of rows and a plurality of columns of a pixel array, each pixel comprising: Photodiode; a first floating diffusion connected to the photodiode; a transfer transistor connecting the photodiode to the first floating diffusion; a second floating diffusion; a dual floating diffusion transistor coupled between the first floating diffusion and the second floating diffusion; and a lateral overflow integrating capacitor coupled between the second floating diffusion and a bias voltage source, wherein the photodiode is configured to generate charge during an integration period, and wherein the integration period is preceded by an idle period, The pixel operations include: configuring the lateral overflow integration capacitor to be zero biased or forward biased during the idle period; and When the photodiode is exposed to light, the lateral overflow integration capacitor is configured to be reverse biased at least at the beginning of the integration period.

12. The image sensor of claim 11, wherein the lateral overflow integrating capacitor comprises an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is selectively coupled to receive a first bias voltage from the bias voltage source, wherein the second metal electrode is selectively coupled to a pixel reference voltage source to receive a second bias voltage; wherein configuring the lateral overflow integration capacitor to be zero biased during the idle period comprises: coupling the first metal electrode of the lateral overflow integrating capacitor to the bias voltage source to receive the first bias voltage; and turning on a reset transistor to couple the second metal electrode of the lateral overflow integration capacitor to the pixel reference voltage source, thereby enabling the second metal electrode of the lateral overflow integration capacitor to receive the second bias voltage; The first bias voltage and the second bias voltage are configured to have the same voltage.

13. The image sensor of claim 12, wherein configuring the lateral overflow integration capacitor to be reverse biased at the beginning of the integration period comprises: The first bias voltage is configured to be lower than the second bias voltage at the beginning of the integration period.

14. The image sensor of claim 11, wherein the lateral overflow integrating capacitor is a high-k dielectric constant metal-to-metal MIM capacitor.

15. The image sensor of claim 11, wherein the lateral overflow integrating capacitor comprises an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is selectively coupled to receive a first bias voltage from the bias voltage source, wherein the second metal electrode is selectively coupled to a pixel reference voltage source to receive a second bias voltage, wherein the operation of the pixel comprises: configuring the transfer transistor and the dual floating diffusion transistor to allow image charge photogenerated by the photodiode to overflow into the lateral overflow integration capacitor during the integration period, thereby causing the second bias voltage at the second metal electrode to decrease; and The first bias voltage of the bias voltage source is configured so that the lateral overflow integration capacitor is reverse biased at the beginning of the integration period and becomes forward biased at a later time during the integration period when the second bias voltage at the second metal electrode of the lateral overflow integration capacitor decreases to less than the first bias voltage at the first metal electrode, wherein the forward bias voltage between the first metal electrode and the second metal electrode of the lateral overflow integration capacitor is set based on the amount of overflow image charge received from the photodiode. 16 . The image sensor of claim 15 , wherein the forward bias voltage is configured to be equal to a reverse bias voltage at the beginning of the integration period.

17. The image sensor of claim 11, wherein the lateral overflow integrating capacitor comprises an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is selectively coupled to the bias voltage source, wherein the second metal electrode is selectively coupled to a pixel reference voltage source, wherein the image sensor further comprises a reset transistor coupled between the lateral overflow integrating capacitor and the pixel reference voltage source; Wherein configuring the lateral overflow integration capacitor to be forward biased during the idle period comprises: coupling the bias voltage source to the first metal electrode of the lateral overflow integrator capacitor to provide a first bias voltage to the first metal electrode of the lateral overflow integrator capacitor; and causing the reset transistor to turn on to couple the second metal electrode of the lateral overflow integrating capacitor to the pixel reference voltage source, thereby providing a second bias voltage to the second metal electrode of the lateral overflow integrating capacitor, The first bias voltage is greater than the second bias voltage.

18. An image sensor according to claim 17, wherein when the lateral overflow integration capacitor is configured to be forward biased during the idle period, the lateral overflow integration capacitor is configured to be reverse biased during the integration period, so that the image charges accumulated in the lateral overflow integration capacitor during the idle period and during the integration period compensate each other, thereby maintaining the read voltage at the second metal electrode of the lateral overflow integration capacitor during the readout period.

19. An image sensor according to claim 18, wherein the operation of the pixel further includes a pre-charge period between the idle period and the integration period, including configuring the first bias voltage of the bias voltage source applied to the first metal electrode of the lateral overflow integration capacitor to be less than the second bias voltage of the pixel reference voltage source during the pre-charge period, so that the lateral overflow integration capacitor is reverse biased.

20. The image sensor according to claim 19, further comprising: The bias voltage source is configured such that the first bias voltage provided by the bias voltage source during the integration period is less than the first bias voltage provided by the bias voltage source during the pre-charge period.

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