Self-biased CTIA pixel reading circuit, image sensor and electronic equipment

Abstract

The invention discloses a self-biased CTIA pixel reading circuit, an image sensor and electronic equipment, and relates to the technical field of integrated circuits, the key points of the technical scheme are that the self-biased CTIA pixel reading circuit comprises a pixel and an integrator composed of an integral operational amplifier and an integral capacitor, the integral operational amplifier is a single-ended input inverting amplifier, and the self-biased CTIA pixel reading circuit further comprises a bias voltage storage module and a control module, the storage circuit is used for storing the bias voltage of the integral operational amplifier in the reset stage of the pixel reading circuit and outputting the bias voltage to the bias end of the integral operational amplifier in the integral stage of the pixel reading circuit so as to eliminate the offset voltage; and the load pre-charging module is used for adjusting the initial voltage of the output end of the integral operational amplifier to the reference voltage at the reset stage of the pixel reading circuit. According to the invention, through the combination of self-bias integration and load capacitor pre-charging, the offset of the pixel reading circuit and the output mismatch between pixel circuits are eliminated, the FPN of the pixel array of the image sensor caused by the circuit offset and mismatch is suppressed and eliminated, and the uniformity of pixels is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a self-biased CTIA pixel readout circuit, an image sensor and an electronic device. Background Art

[0002] As a key component of digital imaging technology, image sensors are responsible for converting optical information into electronic information. In recent years, image sensors have been widely used in many fields such as mobile communications, security monitoring, autonomous driving, low-light night vision, industrial control, biomedicine, and aerospace. With the rapid development of sensor technology, higher requirements have been put forward for image sensor performance such as image quality, system size, weight and power consumption (SWaP), and the development trend of image sensors with high imaging quality and small pixels has become increasingly prominent.

[0003] As a key link in image sensor technology, the structure and performance of the pixel readout integrated circuit (ROIC) are also constantly improving with the development of image sensors. The image sensor readout circuit is a digital-analog hybrid system, which is mainly composed of pixel readout circuit, signal processing circuit, timing circuit and analog-to-digital conversion circuit. The image sensor directly converts the detected weak photocurrent signal into a voltage signal through the front-stage pixel readout circuit, and reconstructs and presents the image information through the subsequent readout circuit and image processing algorithm. Therefore, the performance of the pixel readout circuit directly affects the quality of the image sensor imaging signal. With the reduction of the pixel area, the size of the pixel readout unit circuit is also gradually reduced. The smaller device size brings greater mismatch, and the mismatch of the pixel readout unit circuit and the mismatch between the pixel readout circuits are becoming more and more serious (for example, a larger fixed pattern noise FPN). Therefore, in the design of the readout circuit for small pixels (for example, pixel spacing of 15μm and below), it is necessary to minimize the impact of the readout circuit mismatch and mismatch on the ROIC image signal.

[0004] Depending on the material and working mode of the pixels used in the sensor, the structure of ROIC is also different. Common pixel readout circuits mainly include direct injection (DI), gate modulated injection (GMI), source follower (SFD) and capacitive transimpedance amplifier (CTIA). Among them, DI and SFD readout methods cannot guarantee high linearity when processing wide dynamic range input signals; the current gain and injection efficiency of the GMI readout method are very sensitive to the MOS tube threshold voltage, so there is a large offset voltage between different pixels; the CTIA readout method can obtain good linearity and high injection efficiency under a wide dynamic range, and is a readout method with a wider range of applications.

[0005] Therefore, how to study and design a self-biased CTIA pixel readout circuit, image sensor and electronic equipment that can overcome the above-mentioned defects is a problem that we urgently need to solve. Summary of the invention

[0006] In order to address the deficiencies in the prior art, the purpose of the present invention is to provide a self-biased CTIA pixel readout circuit, an image sensor and an electronic device, which eliminates the offset of the pixel readout circuit and the output mismatch between pixel circuits through a combination of self-bias integration and load capacitor precharging, suppresses and eliminates the FPN of the image sensor pixel array caused by circuit offset and mismatch, and improves the uniformity of pixels.

[0007] The above technical objectives of the present invention are achieved through the following technical solutions:

[0008] In a first aspect, a self-biased CTIA pixel readout circuit is provided, comprising a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a single-ended input inverting amplifier, and further comprising:

[0009] A bias voltage storage module is used to store the bias voltage of the integrating operational amplifier in the reset phase of the pixel readout circuit, and output the bias voltage to the bias terminal of the integrating operational amplifier in the integration phase of the pixel readout circuit to eliminate the offset voltage;

[0010] The load pre-charging module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0011] Furthermore, the bias voltage storage module realizes bias voltage storage and bias voltage output by connecting an offset storage capacitor in series between the bias terminal and the ground terminal of the integrating operational amplifier;

[0012] And / or, the load pre-charging module realizes load pre-charging by connecting a load capacitor in series between the output terminal of the integrating operational amplifier and the ground terminal.

[0013] Furthermore, the pixel readout circuit further includes a reset switch S1, a reset switch S2 and a reset switch S3;

[0014] The two ends of the reset switch S1 are respectively connected to the output end and the bias end of the integrating operational amplifier;

[0015] The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage end;

[0016] The two ends of the reset switch S3 are connected to the integration capacitor and the reference voltage terminal respectively.

[0017] Furthermore, at time t0 in the reset phase, the reset switch S1 , the reset switch S2 , and the reset switch S3 are all closed, and the working cycle of the pixel readout circuit begins.

[0018] Furthermore, the pixel readout circuit further includes a reset switch S4, and two ends of the reset switch S4 are respectively connected to the reference voltage end and the output port.

[0019] Furthermore, at time t1 in the reset phase, the reset switch S4 is closed to pre-charge the integrator output.

[0020] Furthermore, the pixel readout circuit further includes an integration control switch S5, and two ends of the integration control switch S5 are respectively connected to the connection point between the integration capacitor and the reset switch S3 and the output end of the integration amplifier.

[0021] Furthermore, at time t2 in the reset phase, the reset switches S2, S3 and S4 are opened, and the integration control switch S5 is closed, and the pixel readout circuit enters an integration state.

[0022] In a second aspect, an image sensor is provided, comprising at least one self-biased CTIA pixel readout circuit as described in any one of the first aspects.

[0023] According to a third aspect, an electronic device is provided, comprising at least one image sensor as described in the second aspect.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The self-biased CTIA pixel readout circuit provided by the present invention has a self-biased integration module that eliminates the influence of the integrator offset on the pixel bias voltage by means of adaptive integration; the load pre-charging module eliminates the influence of the integrator offset on the output voltage by means of pre-charging the output at the end of reset, and can suppress and eliminate the FPN of the image sensor readout circuit caused by circuit offset and mismatch. The circuit structure can be used for various image sensor readout circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0027] Figure 1 It is a schematic diagram of the structure of a CTIA type pixel readout circuit in the prior art;

[0028] Figure 2 It is a schematic diagram of the working timing of the CTIA type pixel readout circuit in the prior art;

[0029] Figure 3 It is a schematic diagram of an equivalent circuit of a reset state of a CTIA type pixel readout circuit in the prior art;

[0030] Figure 4 It is a schematic diagram of an equivalent circuit of an integral state of a CTIA type pixel readout circuit in the prior art;

[0031] Figure 5 It is a schematic diagram of the structure of a CTIA type pixel readout circuit in the prior art under the condition of misalignment;

[0032] Figure 6 It is a schematic diagram of the working timing of the CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0033] Figure 7 It is a schematic diagram of an equivalent circuit of a reset state of a CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0034] Figure 8 It is a schematic diagram of an equivalent circuit of an integral state of a CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0035] Fig. 9 is a schematic diagram of a self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0036] Fig.10 is a schematic diagram of the structure of a self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0037] Fig.111 is a schematic diagram of the working timing of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0038] Fig.12 is an equivalent schematic diagram of a reset phase 1 of a self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0039] Fig.13 is an equivalent schematic diagram of the reset stage 2 of the self-biased CTIA pixel readout circuit in an embodiment of the present invention;

[0040] Fig.14 1 is an equivalent schematic diagram of the integration stage of the self-biased CTIA pixel readout circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary implementation modes of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0042] Example

[0043] As the pixel area decreases, the offset and mismatch effects of the pixel-level CTIA readout circuit become more serious, as analyzed below.

[0044] Taking a photovoltaic image sensor as an example, its pixel is a photodiode (PD). The current-voltage relationship of PD can be expressed as

[0045]

[0046] In formula (1), I d (t) is the total current generated by the photodiode at time t, I p (t) is the photocurrent generated by the photodiode at time t, I o is the saturation leakage current, V b is the bias voltage of the photodiode. If the external radiation power is constant, the light intensity received by the PD will remain unchanged, so I p (t) remains unchanged, I d (t) is a constant value I d .

[0047] In the design of ROIC of small pixel infrared focal plane sensor, due to the limited pixel area, the pixel readout circuit must use the least number of devices. One benefit of this is that it can reduce power consumption and noise. Figure 1As shown, in order to reduce area and power consumption, the amplifier constituting CTIA does not use a differential input operational amplifier (OpAmp), but a single-ended input inverting amplifier, such as a single-ended input inverting amplifier Amp composed of field effect transistors MP1 and MN2. It can also be a single-ended input inverting amplifier composed of other devices, and the number of devices is not limited.

[0048] Figure 1 The right side of the middle part is the pixel readout circuit; the left side is the pixel array bias circuit that provides bias. In the pixel readout circuit, PD is the pixel; the single-ended input inverting amplifier Amp, the integral capacitor C int Together with the integral reset switch S1, they form a CTIA type integral amplifier to integrate and amplify the input PD current. MP5, MP3 and MP1 in the bias circuit form a mirror relationship, and MN2 and MN4 form a current mirror. Ideally, Figure 1 The voltage V of A A =V ref Therefore, the bias voltage of the PD is V ref and V BIAS_PDN When V BIAS_PDN ≥V ref When , the PD is in the reverse bias or zero bias state required for normal operation.

[0049] like Figure 2 As shown, S1 and V B They respectively represent the control timing of the reset switch S1 and the curve of the voltage at point B changing with time. Figure 2 A medium-high level represents a closed switch, and a low level represents an open switch.

[0050] At time t0, the integral reset switch S1 is closed, and the pixel readout circuit is reset. The equivalent circuit of the reset state is as follows: Figure 3 shown. Figure 1 The gate of MP1 is shorted to the drain of MN2. The current of the single-ended input inverting amplifier in CTIA is proportional to the current flowing through MP5 in the pixel array bias circuit (refer to Figure 1 ), for the current I flowing through MP1 and MN2 D1_MP1 and I D1_MN2 have:

[0051]

[0052] In formulas (2) and (3), μ p and μ n are the mobility of P-channel and N-channel MOSFET devices, C ox is the gate oxide capacitance per unit area of ​​the MOSFET device, W is the channel width, L is the channel length, is the ratio of the channel width to length of MP1, is the ratio of the channel width to the length of MN2, V THP 、V THN The absolute value of the threshold voltage of the P-channel and N-channel MOSFETs, V SG*_MP1 is the source-gate voltage difference of MP1, V GS*_MN2 is the gate-source voltage difference of MN2, V b3 is the gate voltage of MN2.

[0053] The charge of node A during the reset phase is:

[0054] Q1=(V A -V B )C int +(V A -V BIAS_PDN )C PD (4).

[0055] In formula (4), V BIAS_PDN for Figure 2 The cathode bias voltage of the PD.

[0056] At time t1, the integral reset switch S1 is disconnected, and the readout circuit enters the integral state. Figure 4 As shown, at this time, the circuit integrates and amplifies the weak photocurrent generated by the pixel until the reset switch S1 is closed, and the integration period ends. Figure 4 The gate of MP1 is floating. Ideally, there is no influence of other factors such as offset, so the current flowing through MP1 and MN2 remains I bias If the PD does not generate photocurrent, the output voltage V out Maintain the voltage V at the end of reset ref ; If the PD generates a photocurrent input, the current of the PD flows into point A during the integration phase, and the output voltage V out From V ref It starts to change linearly with the integration time, so the charge at point A at time t2 is Q2 = Q1 + I int ×t int , that is, the charge at node A is:

[0057] Q2=(V A -V out )C int +(V A -V BIAS_PDN )C PD (5);

[0058] In formula (5), V out for Figure 4 The output voltage of CTIA is Figure 4 Medium V B =Vout For V in formula (5) A , ideally by I D1_MP5 =I D1_MP3 =I D1_MN4 have:

[0059]

[0060] In formula (6), V ref is the gate voltage of MP5, so:

[0061]

[0062] byI D1_MP1 =I D1_MN2 have:

[0063]

[0064] Therefore:

[0065]

[0066] Substituting formula (7) into formula (9), we can get:

[0067]

[0068] For formula (10), if Then for V in formula (5) A have:

[0069] V A =V ref (11);

[0070] In formula (5), let the integration time t int =t2-t1. Combining equations (4) and (5), according to the law of conservation of charge, Q2=Q1+I int ×t int It can be obtained that, ideally, the output voltage V of the traditional CTIA pixel readout circuit is out have:

[0071]

[0072] In formula (12), t int is the integration time, I int is the integral current, C int At time t4, the reset switch S1 is closed, a working cycle of the readout circuit ends, and the pixel readout circuit outputs the integrated voltage result to the subsequent system, which will output the corresponding image information according to the integrated result and perform imaging.

[0073] Formula (12) shows that under ideal conditions, the output voltage V of the traditional CTIA pixel readout circuit is out However, ideal readout circuits and pixel units do not exist. Due to manufacturing process limitations (process deviations of oxide layer thickness, diffusion doping, etching, etc.), the device parameters of the transistors in the op amp in the CTIA circuit (such as current gain, threshold voltage, etc.) cannot be completely matched. These mismatching factors will lead to the generation of offset voltage. In addition, temperature changes will also cause changes in offset voltage. Assume that the offset voltage caused by device and current mirror mismatch is V os The equivalent circuit of the CTIA pixel readout circuit and its pixel array bias circuit under the condition of misalignment is as follows: Figure 5 shown.

[0074] like Figure 6 As shown, at time t0, the integral reset switch S1 is closed, and the pixel readout circuit is reset (as shown in FIG. Figure 7 As shown in the figure, due to the circuit offset, it is assumed that the equivalent bias voltage of MN2 is V b3 becomes V b3 -V os , for the current I flowing through MP1 and MN2 D2_MP1 and I D2_MN2 have:

[0075]

[0076] The charge at point A is:

[0077] Q1=(V A -V B )C int +(V A -V BIAS_PDN )C PD (15).

[0078] Subsequently, the integration reset switch S1 is disconnected, and the readout circuit enters the integration state, such as Figure 8 As shown, the circuit integrates and amplifies the current generated by the pixel PD until the reset switch S1 is closed, and the integration period ends. During the integration phase, the current of the PD flows into point A, and the output voltage V out From V ref It starts to change linearly with the integration time, and the charge at node A at time t2 is:

[0079] Q2=(V A -V B )C int +(V A -V BIAS_PDN )C PD (16);

[0080] For V in formula (16)A , by I D2_MP1 =I D2_MN2 have:

[0081]

[0082] Therefore:

[0083]

[0084] Substituting formula (7) into formula (18), we have:

[0085]

[0086] For formula (19), if Then for V in formula (19) A have:

[0087]

[0088] Therefore, in formula (16), V A As shown in formula (20), V B =V out , integration time t int =t2-t1. In formula (20) Combining equations (15) and (16), according to the charge conservation law, Q2 = Q1 + I int ×t int It can be obtained that, in the actual imbalance condition, the output voltage V of the traditional CTIA type pixel readout circuit is out have:

[0089]

[0090] From the previous analysis, we can see that the offset of the op amp will cause the bias voltage of the PD to change from the ideal (V BIAS_PDN -V ref ) becomes (V BIAS_PDN -V A ). Therefore, from formula (1), it can be seen that the change in PD current caused by the change in PD bias voltage is:

[0091]

[0092] Combining equations (21) and (12) yields the CTIA output voltage deviation ΔV caused by op amp misregulation: out for:

[0093]

[0094] In formula (23), ΔI int =ΔI d, substituting formula (22) into formula (23), we can see that in the case of imbalance, the output voltage deviation ΔV generated by the i-th pixel unit CTIA in the pixel array out _ i It can be expressed as:

[0095]

[0096] In the above formula (24), the first term is the output voltage change caused by the pixel readout circuit offset; the second term is the integrator output change caused by the dark current offset caused by the pixel reverse bias voltage offset. Since the offsets of each pixel in the pixel array are different, the output of any pixel readout circuit is different. These offsets ultimately cause non-uniformity in the pixel array output, namely fixed pattern noise (FPN).

[0097] The self-biased CTIA pixel readout circuit described in the present invention is as follows: Fig. 9 As shown, it includes a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor. The integrating operational amplifier is a single-ended input inverting amplifier. It also includes a bias voltage storage module and a load pre-charging module.

[0098] Among them, the bias voltage storage module is used to store the bias voltage of the integrating operational amplifier in the reset phase of the pixel readout circuit, and output the bias voltage to the bias end of the integrating operational amplifier in the integration phase of the pixel readout circuit to eliminate the offset voltage; the load pre-charging module is used to adjust the initial voltage of the output end of the integrating operational amplifier to the reference voltage in the reset phase of the pixel readout circuit.

[0099] The bias voltage storage module and the load pre-charging module can be executed independently in the reset phase without any timing sequence restriction.

[0100] In addition, the bias voltage storage module and the load pre-charging module can be implemented by circuits or devices independent of the existing pixel readout circuit, such as configuring a controllable power supply terminal to achieve real-time regulation. The bias voltage storage module and the load pre-charging module can also be integrated into the existing pixel readout circuit.

[0101] Take the CTIA pixel readout circuit as an example. Fig.10 As shown, the CTIA pixel readout circuit consists of an integrator (Amp+C int ), reset switches S1-S4, integral control switch S5, offset storage capacitor C az , load capacitance C load And the output port V out The integrator includes an integrating operational amplifier Amp and an integrating capacitor. The integrating operational amplifier Amp is a single-ended input inverting amplifier composed of MP1 and MN2.

[0102] It should be noted that the load capacitor may be a parasitic capacitor of the integrator or a newly added capacitor device.

[0103] like Fig.11 As shown, it is the working timing of the self-biased CTIA pixel readout circuit, wherein S1, S2, and S3 represent the working timing of the reset switches S1, S2, and S3 respectively, and S4 and S5 represent the working timing of the output reset switch S4 and the integral control switch S5 respectively, wherein a high level represents that the switch is closed, and a low level represents that the switch is open.

[0104] like Fig.10 and Fig.11 As shown, at time t0, the reset switches S1, S2, and S3 are closed, the readout circuit working cycle begins, and the readout circuit is in reset phase 1. Its equivalent schematic diagram is shown in Fig.12 As shown. At this time, the voltages at points A, B, C and D are: V A1 =V D1 =V ref , V B1 =V D1 =V GS_MN2 The current I flowing through MP1 and MN2 D3_MP1 and I D3_MN2 have:

[0105]

[0106] After the circuit stabilizes, the current flowing through MP1 and MN2 is:

[0107] I D4_MP1 =I D4_MN2 (27).

[0108] At time t1, the reset switch S1 is opened, and the output reset switch S4 is closed to pre-charge the integrator output. Fig.13 As shown, at this time, the voltage V B Reset to V ref , and then reset phase 2 ends. The current I flowing through MP1 and MN2 D5_MP1 and I D5_MN2 have:

[0109]

[0110] The charge of points A and B at this stage is:

[0111] Q A2 =(V A2 -V ref )C int +(V A2 -V BIAS_PDN )C PD (29);

[0112] Q B2 =Q D2 =(V B2 -V ref )C int +(V B2 -0)C load (30);

[0113] The voltages at points A, B, and D in equations (29) and (30) are: V A2 =V B2 =V D2 =V ref Because there is no current path, the voltage at point C (i.e. C az The voltage on the upper side of the circuit maintains the V GS_MN2 constant.

[0114] At time t2, the reset switches S2, S3, and S4 are disconnected, and the integral control switch S5 is closed. Fig.14 As shown in the figure, the self-biased CTIA pixel readout circuit enters the integration state. At this time, the readout circuit integrates and amplifies the integrated current until the integration control switch S5 is disconnected at time t4, and the entire readout circuit working cycle ends. During the integration phase, the current of PD flows into point A, so the charge amount Q at point A at time t2 is A3 =Q A2 +I int ×t int , so the charge at points A and B is:

[0115] Q A3 =(V A3 -V B3 )C int +(V A3 -V BIAS_PDN )C PD (31);

[0116] Q B3 =Q D3 =(V B3 -V A3 )C int +(V B3 -0)C load (32);

[0117] In formula (31) and (32), V B3 =V out .

[0118] For point C, due to the moment when the reset switch S1 is disconnected at time t1, the storage capacitor C at point C is offset. az The charge stored on point C cannot mutate suddenly. At the same time, after time t1, there is no charge discharge path at point C.az The charge stored on the output terminal remains constant during the pre-charge and reset stages. From equations (27) and (28), we have:

[0119] I D4_MP1 =I D4_MN2 =I D5_MP1 =I D5_MN2 (33);

[0120] At t2, the reset switch S2 is disconnected, and the voltage at point A is V A3 It is in floating state. Since the current I flowing through MP1 and MN2 is D6_MP1 ,I D6_MN2 The current I flowing through MP1 and MN2 before disconnecting S2 D5_MP1 ,I D5_MN2 remain unchanged, so:

[0121] I D6_MP1 =I D6_MN2 (34);

[0122] From formula (28), we can get the voltage V at point A during the integration phase: A3 The voltage V at point A during reset phase 2 A2 Equal, that is:

[0123] V A3 =V A2 =V ref (35).

[0124] contrast Figure 8 The equivalent circuit of the integration state of the CTIA type pixel readout circuit under the condition of imbalance. The self-bias integration technology proposed in the present invention can make the voltage V of each pixel A point in the pixel array equal to 0.01V in the process of integration and amplification of the pixel readout circuit. A Keep V A =V ref It is known from formulas (22) and (24) that at this time, the reverse bias voltage difference V of each pixel photodiode in the circuit pixel array is b Fixed, so the integrated current change ΔI produced by each pixel photodiode in the pixel array compared to the case without offset int =ΔI d =0, the influence of inconsistent PD dark current caused by input mismatch between pixel circuits in the pixel array is eliminated.

[0125] For point B, at time t2, the reset switch S4 is disconnected, the integral control switch S5 is closed, and the readout circuit enters the integral stage. A3 、V B2 、V B3 Substituting into equations (30) and (32), we can obtain:

[0126] Q B2 =V ref C load (36);

[0127] Q B3 =(V out -V ref )C int +V out C load (37).

[0128] Considering that there is no charge injected into point B at the moment when the integral control switch S5 is closed, the charge Q at point B at the moment when the integral control switch S5 is closed can be known from the law of charge conservation. B3_0 Q B2 =Q B3_0 , the combined equations (36) and (37) are:

[0129] (V out -V ref )(C load +C int )=0(38).

[0130] Because C load , C int All are actual capacitances, (C load +C int )>0, so from (38) we can know that V out =V ref , that is, the initial voltage V at point B during the integration phase B3_0 have:

[0131] V B3_0 =V out_0 =V ref (39);

[0132] Among them, V out_0 Outputs the initial voltage at the beginning of integration.

[0133] Therefore, the initial output voltage V of the self-biased CTIA pixel readout circuit embodiment proposed in the present invention is out =V B3_0 , that is, the initial value of point B in the integration phase remains unchanged. The mismatch error calibration combined readout method of the self-bias integration technology and the load capacitor pre-charging technology proposed in the present invention can simultaneously eliminate the mismatch between the outputs of the pixel circuits and reduce the pixel array FPN.

[0134] Substituting the above values ​​into formulas (29) and (31), we can obtain:

[0135] Q A2 =(V ref -V BIAS_PDN )CPD -V os C az (40);

[0136]

[0137] Combining equations (40) and (41), let the integration time t int =t3-t2, according to the charge conservation theorem Q A3 =Q A2 +I int ×t int have:

[0138]

[0139] Substituting the values ​​in equations (35) and (39) into equation (42), it can be seen that the output voltage V of the self-biased CTIA pixel readout circuit embodiment proposed in the present invention is out for:

[0140]

[0141] It can be seen that the expression of formula (43) is the same as the output expression (12) of the CTIA pixel readout circuit under the above ideal condition without misalignment, and has nothing to do with the MOSFET device parameters in the CTIA. Therefore, an embodiment of the combined readout method of the pixel circuit self-bias integration technology and the load capacitor pre-charging technology proposed in the present invention: the self-biased CTIA pixel readout circuit can eliminate the output mismatch between pixel circuits, the mismatch of the PD reverse bias voltage, and eliminate the pixel array FPN.

[0142] like Fig.10 An embodiment of a self-biased CTIA type pixel readout circuit is shown in the figure. The combined readout method of the pixel circuit self-bias integration technology and the load capacitor pre-charging technology proposed by the present invention ensures that the voltage V of the pixel bias node A during the integration period of the CTIA readout circuit is A Always keep the reference voltage V ref , while making the output voltage V at the output node B out The initial value is the reference voltage V ref During the integration amplification process of the self-biased CTIA pixel readout circuit, the reverse bias voltage difference V b remains unchanged. From formulas (22) and (24), we can see that the integral current change of each pixel photodiode in the pixel array ΔI int =ΔI d=0, so the combined readout method of the self-biased integration technology and the load capacitor pre-charging technology proposed in the present invention can effectively suppress the phenomenon of inconsistent PD dark current caused by the mismatch between pixel circuits in the pixel array. At the same time, the combined readout method of the pixel circuit self-biased integration technology and the load capacitor pre-charging technology proposed in the present invention effectively fixes the output starting voltage of each pixel unit during the integration process, eliminating the influence of the mismatch between pixel circuits on the integration output. Therefore, the combined readout method of the pixel circuit self-biased integration technology and the load capacitor pre-charging technology proposed in the present invention can effectively eliminate the pixel array FPN and reduce the non-uniformity of the image sensor readout circuit.

[0143] The present invention also describes an image sensor, comprising at least one self-biased CTIA type pixel readout circuit as described above.

[0144] The present invention also describes an electronic device, comprising at least one image sensor as described above.

[0145] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0146] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A self-biased CTIA pixel readout circuit, comprising a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a single-ended input inverting amplifier, and wherein: include: A bias voltage storage module is used to store the bias voltage of the integrating operational amplifier in the reset phase of the pixel readout circuit, and output the bias voltage to the bias terminal of the integrating operational amplifier in the integration phase of the pixel readout circuit to eliminate the offset voltage; The load pre-charging module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

2. The self-biased CTIA pixel readout circuit according to claim 1, wherein: The bias voltage storage module realizes bias voltage storage and bias voltage output by connecting the offset storage capacitor in series between the bias terminal and the ground terminal of the integrating operational amplifier; And / or, the load pre-charging module realizes load pre-charging by connecting a load capacitor in series between the output terminal of the integrating operational amplifier and the ground terminal.

3. The self-biased CTIA pixel readout circuit according to claim 2, wherein: The pixel readout circuit also includes a reset switch S1, a reset switch S2 and a reset switch S3; The two ends of the reset switch S1 are respectively connected to the output end and the bias end of the integrating operational amplifier; The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage end; The two ends of the reset switch S3 are connected to the integration capacitor and the reference voltage terminal respectively.

4. The self-biased CTIA pixel readout circuit according to claim 3, wherein At time t0 in the reset phase, the reset switch S1, the reset switch S2 and the reset switch S3 are all closed, and the working cycle of the pixel readout circuit begins.

5. The self-biased CTIA pixel readout circuit according to claim 3, wherein: The pixel readout circuit further includes a reset switch S4, and two ends of the reset switch S4 are respectively connected to the reference voltage end and the output port.

6. The self-biased CTIA pixel readout circuit according to claim 5, wherein At time t1 in the reset phase, the reset switch S4 is closed to pre-charge the integrator output.

7. The self-biased CTIA pixel readout circuit according to claim 5, wherein: The pixel readout circuit further includes an integration control switch S5, and two ends of the integration control switch S5 are respectively connected to a connection point between the integration capacitor and the reset switch S3 and an output end of the integration amplifier.

8. The self-biased CTIA pixel readout circuit according to claim 7, wherein At time t2 of the reset phase, the reset switches S2, S3 and S4 are opened, and the integration control switch S5 is closed, and the pixel readout circuit enters an integration state.

9. An image sensor, characterized in that: Comprising at least one self-biased CTIA pixel readout circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that: Comprising at least one image sensor as claimed in claim 9.

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