Novel CTIA pixel reading circuit, image sensor and electronic equipment

Abstract

The invention discloses a novel CTIA pixel readout circuit, an image sensor and electronic equipment, and relates to the technical field of integrated circuits, the key points of the technical scheme are that the novel CTIA pixel readout circuit comprises a pixel and an integrator composed of an integral operational amplifier and an integral capacitor, and the novel CTIA pixel readout circuit is characterized by further comprising an imbalance pre-storage module used for pre-storing imbalance in a reset stage of the pixel readout circuit, pre-storing the offset voltage obtained by the integral operational amplifier to an inverted input end of the integral operational amplifier; and the load pre-charging module is used for adjusting the initial voltage of the output end of the integral operational amplifier to the reference voltage at the reset stage of the pixel reading circuit. Through the combination of offset voltage pre-storage and load capacitor pre-charging, the offset of the pixel circuits and the output mismatch between the pixel circuits are eliminated, the FPN of the pixel array of the image sensor caused by the circuit offset and mismatch is inhibited and eliminated, and the uniformity of pixels is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a novel CTIA pixel readout circuit, an image sensor and an electronic device. Background Art

[0002] As a key component of digital imaging technology, image sensors are responsible for converting optical information into electronic information. In recent years, image sensors have been widely used in many fields such as mobile communications, security monitoring, autonomous driving, low-light night vision, industrial control, biomedicine, and aerospace. With the rapid development of sensor technology, higher requirements have been put forward for image sensor performance such as image quality, system size, weight and power consumption (SWaP), and the development trend of image sensors with high imaging quality and small pixels has become increasingly prominent.

[0003] As a key link in image sensor technology, the structure and performance of the pixel readout integrated circuit (ROIC) are also constantly improving with the development of image sensors. The image sensor readout circuit is a digital-analog hybrid system, which is mainly composed of pixel readout circuit, signal processing circuit, timing circuit and analog-to-digital conversion circuit. The image sensor directly converts the detected weak photocurrent signal into a voltage signal through the front-stage pixel readout circuit, and reconstructs and presents the image information through the subsequent readout circuit and image processing algorithm. Therefore, the performance of the pixel readout circuit directly affects the quality of the image sensor imaging signal. With the reduction of the pixel area, the size of the pixel readout unit circuit is also gradually reduced. The smaller device size brings greater mismatch, and the mismatch of the pixel readout unit circuit and the mismatch between the pixel readout circuits are becoming more and more serious (for example, a larger fixed pattern noise FPN). Therefore, in the design of the readout circuit for small pixels (for example, pixel spacing of 15μm and below), it is necessary to minimize the impact of the readout circuit mismatch and mismatch on the ROIC image signal.

[0004] Depending on the material and working mode of the pixels used in the sensor, the structure of ROIC is also different. Common pixel readout circuits mainly include direct injection (DI), gate modulated injection (GMI), source follower (SFD) and capacitive transimpedance amplifier (CTIA). Among them, DI and SFD readout methods cannot guarantee high linearity when processing wide dynamic range input signals; the current gain and injection efficiency of the GMI readout method are very sensitive to the MOS tube threshold voltage, so there is a large offset voltage between different pixels; the CTIA readout method can obtain good linearity and high injection efficiency under a wide dynamic range, and is a readout method with a wider range of applications.

[0005] Therefore, how to research and design a new CTIA pixel readout circuit, image sensor and electronic equipment that can overcome the above-mentioned defects is a problem that we urgently need to solve. Summary of the invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a novel CTIA pixel readout circuit, image sensor and electronic device, which eliminates the offset of the pixel circuit and the output mismatch between the pixel circuits through a combination of offset voltage pre-storage and load capacitor pre-charging, suppresses and eliminates the FPN of the image sensor pixel array caused by circuit offset and mismatch, and improves the uniformity of pixels.

[0007] The above technical objectives of the present invention are achieved through the following technical solutions:

[0008] In a first aspect, a novel CTIA pixel readout circuit is provided, comprising a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a differential input operational amplifier, and further comprising:

[0009] An offset pre-storage module is used to pre-store the offset voltage obtained for the integrating operational amplifier to the inverting input terminal of the integrating operational amplifier during the reset phase of the pixel readout circuit;

[0010] The load pre-charging module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0011] Furthermore, the offset pre-storage module realizes offset voltage pre-storage by connecting an offset storage capacitor in series between the bias node of the pixel and the inverting input terminal of the integrating operational amplifier;

[0012] And / or, the load pre-charging module realizes load pre-charging by connecting a load capacitor in series between the output terminal of the integrating operational amplifier and the ground terminal.

[0013] Furthermore, the pixel readout circuit further includes a reset switch S1, a reset switch S2 and a reset switch S3;

[0014] The two ends of the reset switch S1 are respectively connected to the output end and the inverting input end of the integrating operational amplifier;

[0015] The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage end;

[0016] The two ends of the reset switch S3 are connected to the integration capacitor and the reference voltage terminal respectively.

[0017] Furthermore, at time t0 in the reset phase, the reset switch S1 , the reset switch S2 , and the reset switch S3 are all closed, so that the voltage at the inverting input terminal of the integrating operational amplifier is equal to the sum of the reference voltage and the offset voltage.

[0018] Furthermore, the pixel readout circuit further includes a reset switch S4, and two ends of the reset switch S4 are respectively connected to the reference voltage end and the output port.

[0019] Furthermore, at time t1 in the reset phase, the reset switch S1 is opened and the reset switch S4 is closed to pre-charge the integrator output.

[0020] Furthermore, the pixel readout circuit further includes an integration control switch S5, and two ends of the integration control switch S5 are respectively connected to the connection point between the integration capacitor and the reset switch S3 and the output end of the integration amplifier.

[0021] Furthermore, at time t2 in the reset phase, the reset switches S2, S3 and S4 are opened, and the integration control switch S5 is closed, and the pixel readout circuit enters an integration state.

[0022] In a second aspect, an image sensor is provided, comprising at least one novel CTIA pixel readout circuit as described in any one of the first aspects.

[0023] According to a third aspect, an electronic device is provided, comprising at least one image sensor as described in the second aspect.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] A novel CTIA pixel readout circuit provided by the present invention ensures that the voltage of the pixel bias node A is always maintained at the reference voltage during the integration period of the CTIA pixel readout circuit through a combination of offset voltage pre-storage and load capacitor pre-charging, and at the same time makes the initial value of the output voltage at the output node the reference voltage, thereby eliminating the offset of the pixel circuit and the output mismatch between the pixel circuits, suppressing and eliminating the FPN of the image sensor pixel array caused by the circuit offset and mismatch, and improving the uniformity of the pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings:

[0027] Figure 1 It is a schematic diagram of the structure of a CTIA type pixel readout circuit in the prior art;

[0028] Figure 2 It is a schematic diagram of the working timing of the CTIA type pixel readout circuit in the prior art;

[0029] Figure 3 It is a schematic diagram of an equivalent circuit of a reset state of a CTIA type pixel readout circuit in the prior art;

[0030] Figure 4 It is a schematic diagram of an equivalent circuit of an integral state of a CTIA type pixel readout circuit in the prior art;

[0031] Figure 5 is a schematic diagram of an equivalent circuit of a CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0032] Figure 6 It is a schematic diagram of the working timing of the CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0033] Figure 7 It is a schematic diagram of an equivalent circuit of a reset state of a CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0034] Figure 8 It is a schematic diagram of an equivalent circuit of an integral state of a CTIA type pixel readout circuit in the prior art when there is an imbalance;

[0035] Fig. 9 is a schematic diagram of a novel CTIA pixel readout circuit in an embodiment of the present invention;

[0036] Fig.10 is a schematic diagram of the structure of a novel CTIA pixel readout circuit in an embodiment of the present invention;

[0037] Fig.111 is a schematic diagram of the working timing of the novel CTIA pixel readout circuit in an embodiment of the present invention;

[0038] Fig.12 Schematic diagram of offset elimination of a novel CTIA pixel readout circuit in an embodiment of the present invention;

[0039] Fig.13 is an equivalent schematic diagram of a reset phase 1 of a novel CTIA pixel readout circuit in an embodiment of the present invention;

[0040] Fig.14 is an equivalent schematic diagram of the reset stage 2 of the novel CTIA pixel readout circuit in an embodiment of the present invention;

[0041] Fig.15 1 is an equivalent schematic diagram of the integration stage of the novel CTIA pixel readout circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0043] Example

[0044] As the pixel area decreases, the offset and mismatch effects of the pixel-level CTIA readout circuit become more serious, as analyzed below.

[0045] Taking a photovoltaic image sensor as an example, its pixel is a photodiode (PD), and the current-voltage relationship of the PD can be expressed as:

[0046]

[0047] In formula (1), I d (t) is the total current generated by the photodiode at time t, I p (t) is the photocurrent generated by the photodiode at time t, I o is the saturation leakage current, V b is the bias voltage of the photodiode. If the external radiation power is constant, the light intensity received by the PD will remain unchanged, so I p (t) remains unchanged, I d (t) is a constant value I d .

[0048] like Figure 1 As shown, the photodiode (PD) is the pixel, the integrating operational amplifier Amp and the integrating capacitor C int Together they form an integrator, S1 is the integral reset switch, V outFor the output port, the integrating operational amplifier Amp and the integrating capacitor C int The most basic unit of CTIA structure. The voltage at point A is V A and V BIAS_PDN The voltage provides the required reverse bias voltage for PD. Under their action, the current generated on the sensor pixel is input to the integrator for integration, and a voltage signal related to the light intensity is output.

[0049] It should be noted that the integrating operational amplifier is a differential input operational amplifier.

[0050] like Figure 2 As shown, S1 and V B They represent the control timing of the reset switch S1 and the curve of the voltage at point B changing with time. Figure 2 A medium-high level represents a closed switch, and a low level represents an open switch.

[0051] At time t0, the reset switch S1 is closed, and the pixel readout circuit is reset. The equivalent circuit of the reset state is as follows: Figure 3 As shown. The charge of node A in the reset phase is:

[0052] Q1=(V A -V B )C int +(V A -V BIAS_PDN )C PD (2);

[0053] In formula (2), V A =V B =V ref , V ref is the reference voltage of the positive input terminal of the integrating operational amplifier, C PD is the PD capacitor.

[0054] At time t1, the reset switch S1 is disconnected, and the pixel readout circuit enters the integration state. The equivalent circuit of the pixel readout circuit in the integration state is as follows: Figure 4 As shown in FIG. 1 , the circuit integrates and amplifies the weak photocurrent generated by the pixel until the reset switch S1 is closed and the integration period ends. Figure 2 As shown. The charge amount of node A at time t2 is:

[0055] Q2=(V A -V out )C int +(V A -V BIAS_PDN )C PD (3);

[0056] In formula (3), V A =V ref , Vout for Figure 4 The voltage at point B of the CTIA shown in the figure is also the output voltage of the CTIA, that is, V B =V out . Let the integration time t int =t2-t1. According to the law of conservation of charge, Q2=Q1+I int ×t int , so combining equations (1) and (2) we can get that, ideally, the output voltage V of the traditional CTIA pixel readout circuit is out have:

[0057]

[0058] In formula (4), V ref is the reference voltage, t int is the integration time, I int is the integral current, C int At time t3, the reset switch S1 is closed, a working cycle of the readout circuit ends, and the pixel readout circuit outputs the integrated voltage result to the subsequent system, which will output the corresponding image information according to the integrated result and perform imaging.

[0059] Formula (4) shows that under ideal conditions, the output voltage V of the traditional CTIA pixel readout circuit is out However, ideal readout circuits and pixel units do not exist. Due to manufacturing process limitations (process deviations of oxide layer thickness, diffusion doping, etching, etc.), the device parameters of the transistors in the op amp in the CTIA circuit (such as current gain, threshold voltage, etc.) cannot be completely matched. This mismatch factor will cause the op amp to produce an offset voltage. In addition, temperature changes will also cause changes in the offset voltage. Assume that the op amp offset voltage caused by device mismatch is V os The equivalent circuit of the CTIA pixel readout circuit in the case of misalignment is as follows: Figure 5 shown.

[0060] like Figure 6 As shown, at time t0-t1, the reset switch S1 is closed, and the pixel readout circuit is reset. Figure 7 As shown, the charge at point A is:

[0061] Q1=(V A -V B )C int +(V A -V BIAS_PDN )C PD (5);

[0062] In formula (5), the voltage V at points A and B is A =V B =V ref+V os .

[0063] Then, the reset switch S1 is disconnected, and the pixel readout circuit enters the integration state, such as Figure 8 As shown, the circuit integrates and amplifies the current generated by the pixel PD until the reset switch S1 is closed, and the integration period ends. Figure 6 As shown, the charge of node A at time t2 is:

[0064] Q2=(V A -V B )C int +(V A -V BIAS_PDN )C PD (6);

[0065] In formula (6), the voltage V at points A and B is A =V ref +V os , V B =V out , integration time t int =t2-t1. According to the charge conservation principle, Q2=Q1+I int ×t int , combining equations (1) and (2), we can get that, in the actual misalignment condition, the output voltage V of the conventional CTIA pixel readout circuit is out have:

[0066]

[0067] From the previous analysis, we can see that the offset of the op amp will cause the bias voltage of the PD to change from the ideal (V BIAS_PDN -V ref ) changes to (V BIAS_PDN -V ref -V os ). From formula (1), we can know that the change in the current of the photodiode caused by the change in PD bias voltage is:

[0068]

[0069] Combining equations (7) and (4) yields the CTIA output voltage deviation ΔV caused by op amp misregulation: out for:

[0070]

[0071] In formula (9), ΔI int =ΔI d , substituting formula (8) into formula (9), we can see that in the case of misalignment, the output voltage deviation ΔV generated by the i-th pixel unit CTIA in the pixel array is out_i It can be expressed as:

[0072]

[0073] In the above formula (10), V os_i is the equivalent input offset voltage of the CTIA op amp of the i-th pixel in the pixel array; the first term is the output voltage change caused by the pixel readout circuit offset; the second term is the dark current offset caused by the photodiode reverse bias voltage offset, which causes the integrator output change. Since the offsets of each pixel in the pixel array are different, the output of any pixel readout circuit is different, and these offsets ultimately cause the non-uniformity of the pixel array output, namely fixed pattern noise (FPN).

[0074] A new type of CTIA pixel readout circuit, such as Fig. 9 As shown, it includes a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, and also includes an offset pre-storage module and a load pre-charging module.

[0075] Among them, the offset pre-storage module is used to pre-store the offset voltage obtained for the integrating operational amplifier to the inverting input terminal of the integrating operational amplifier during the reset phase of the pixel readout circuit; the load pre-charging module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

[0076] It should be noted that the offset voltage can be acquired from an integrating operational amplifier using a negative feedback technique, and can also be acquired by acquisition and analysis from an integrator using a detection circuit or device.

[0077] In addition, the offset pre-storage module and the load pre-charging module can be executed independently during the reset phase without any timing sequence restriction.

[0078] In addition, the offset pre-storage module and the load pre-charging module can be implemented by circuits or devices independent of the existing pixel readout circuit, such as configuring a controllable power supply terminal to achieve real-time regulation. The offset pre-storage module and the load pre-charging module can also be integrated into the existing pixel readout circuit.

[0079] Taking the CTIA pixel readout circuit as an example, the present invention provides a specific embodiment of a novel CTIA pixel readout circuit structure, and its structure is as follows: Fig.10 As shown, it consists of an integrator, reset switches S1-S4, an integral control switch S5, and an offset storage capacitor C az , load capacitance C load And the output port V out The integrator includes an integrating operational amplifier Amp and an integrating capacitor C int .

[0080] like Fig.11As shown in FIG. 1 , it is the working timing of the readout circuit 1 with offset elimination function, where S1, S2, S3 represent the working timing of the reset switches S1, S2 and S3, and S4 and S5 represent the working timing of the reset switch S4 and the integral control switch S5 at the output end, respectively. The high level in the figure represents that the switch is closed, and the low level represents that the switch is open.

[0081] like Fig.10 and Fig.11 As shown, at time t0, the reset switches S1, S2, and S3 are closed, the pixel readout circuit working cycle begins, and the readout circuit is in reset phase 1, as shown in FIG. Fig.13 As shown. The charges at points A, B, and C are:

[0082] Q A1 =(V A1 -V ref )C int +(V A1 -V BIAS_PDN )C PD +(V A1 -V C1 )C az (11);

[0083] Q B1 =Q C1 =(V B1 -0)C load +(V B1 -V A1 )C az (12);

[0084] The voltages at points A, B, and C in equations (11) and (12) are: V A1 =V ref 、V B1 =V C1 =V ref +V os .

[0085] Then, the reset switch S1 is opened at time t1, and the reset switch S4 at the output end is closed to pre-charge the integrator output. Fig.14 As shown, at this time, the voltage V B By V ref +V os Reset to V ref , and then the reset phase ends. The charge at points A, B, and C in this phase is:

[0086] Q A2 =(V A2 -V ref )C int +(V A2 -V BIAS_PDN)C PD +(V A2 -V C2 )C az (13);

[0087] Q B2 =(V B2 -V ref )C int +(V B2 -0)C load (14);

[0088] Q C2 =(V C2 -V A2 )C az (15);

[0089] The voltages at points A, B, and C in equations (13), (14), and (15) are: V A2 =V B2 =V ref 、V C2 =V ref +V os .

[0090] It should be noted that the load capacitor may be a parasitic capacitor of the integrator or a newly added capacitor device.

[0091] Then, at time t2, the reset switches S2, S3, and S4 are opened, and the integration control switch S5 is closed, and the new CTIA pixel readout circuit with offset elimination function enters the integration state. Fig.15 As shown, the pixel readout circuit integrates and amplifies the integrated current until the integral control switch S5 is disconnected at time t4, and the entire readout circuit working cycle ends. The charge amount at points A, B, and C is:

[0092] Q A3 =(V A3 -V out )C int +(V A3 -V BIAS_PDN )C PD +(V A3 -V C3 )C az (16);

[0093] Q B3 =(V B3 -V A3 )C int +(V B3 -0)C load (17);

[0094] Q C3=(V C3 -V A3 )C az (18);

[0095] In formula (16), (17) and (18), V B3 =V out 、V C3 =V ref +V os .

[0096] For point C, the voltage V at point C can be known from the virtual short and virtual disconnect of the op amp. C2 =V ref +V os . Set the voltage values ​​V at points A, B, and C A2 、V B2 、V C2 Substituting into equation (15), we can know that Q C2 =V os C az After the reset is completed, point C is in a floating state. az The charge stored on the output remains constant during the precharge and reset phases at the output, so:

[0097] Q C3 =Q C2 =V os C az (19);

[0098] From formula (18), we can know that the voltage V at point A during the integration phase is A3 The expression is:

[0099]

[0100] Set the voltage V C3 =V ref +V os Substituting equation (19) into equation (20), we can get the voltage V at point A during the integration phase: A3 have:

[0101] V A3 =V ref (twenty one);

[0102] contrast Figure 8 The equivalent circuit of the integral state of the CTIA type pixel readout circuit in the case of an offset, the pixel circuit offset voltage pre-storage technology proposed in the present invention can make the voltage of each pixel A point in the pixel array always maintain V during the integral amplification process of the pixel readout circuit. A =V ref It is known from formulas (8) and (10) that at this time, the reverse bias voltage difference V of each pixel photodiode in the circuit pixel array is bFixed, so the integrated current change ΔI produced by each pixel photodiode in the pixel array compared to the case without offset int =ΔI d =0, the influence of inconsistent PD dark current caused by input mismatch between pixel circuits in the pixel array is eliminated.

[0103] For point B, at time t2, the reset switch S4 is disconnected, the integral control switch S5 is closed, and the readout circuit enters the integral stage. A3 、V B2 、V B3 Substituting into equations (14) and (17), we can obtain:

[0104] Q B2 =V ref C load (twenty two);

[0105] Q B3 =(V out -V ref )C int +V out C load (twenty three);

[0106] Considering that there is no integral current injection generated by PD at point A at the moment when the integral control switch S5 is closed, the charge Q at point B at the moment when the integral control switch S5 is closed can be known from the law of conservation of charge. B30 Q B2 =Q B30 , the combined equations (22) and (23) are:

[0107] (V out -V ref )(C load +C int )=0(24)

[0108] Because C load and C int are all actual capacitors, so (C load +C int )>0, so V out =V ref , that is, the initial voltage V at point B during the integration phase B30 have:

[0109] V B30 =V out0 =V ref (25);

[0110] Among them, V out0 Outputs the initial voltage at the beginning of integration.

[0111] Therefore, the initial output voltage V of the novel CTIA pixel readout circuit embodiment with offset elimination function proposed by the present invention is out =V B30 , that is, the initial value of point B in the integration phase remains unchanged. The offset pre-storage technology and load capacitance pre-charging technology mismatch error calibration combined readout method proposed in the present invention can simultaneously eliminate the mismatch between the outputs of the pixel circuits and reduce the pixel array FPN.

[0112] Substituting the above values ​​into formulas (13) and (16), we can obtain:

[0113] Q A2 =(V ref -V BIAS_PDN )C PD -V os C az (26);

[0114] Q A3 =(V A3 -V out )C int +(V A3 -V BIAS_PDN )C PD +(V A3 -V ref -V os )C az (27);

[0115] Combining equations (26) and (27), let the integration time t int =t3-t2, according to the charge conservation principle Q A2 =Q A3 +I int ×t int have:

[0116]

[0117] Substituting the values ​​in equations (21) and (25) into equation (28), it can be seen that under actual offset conditions, the output voltage V of the novel CTIA pixel readout circuit embodiment with offset elimination function proposed in the present invention is out for:

[0118]

[0119] It can be seen that the expression of formula (29) is the same as the output expression (4) of the CTIA pixel readout circuit under the ideal condition without offset mentioned above. Therefore, an embodiment of the combined readout method of the pixel circuit offset voltage pre-storage technology and the load capacitor pre-charging technology proposed in the present invention: the new CTIA pixel readout circuit with offset elimination function can eliminate the influence of the output offset of the pixel circuit, the mismatch of the PD reverse bias voltage, and the mismatch of the output between the pixels in the pixel array, thereby reducing the pixel array FPN and improving the non-uniformity of the pixel array.

[0120] like Fig.10 In the embodiment shown in the figure, the combined readout method of the pixel circuit offset voltage pre-storage technology and the load capacitor pre-charging technology proposed by the present invention ensures that the voltage V of the pixel bias node A during the integration period of the CTIA pixel readout circuit is A Always keep the reference voltage V ref , while making the output voltage V at the output node B out The initial value is the reference voltage V ref In the integration amplification process of the new CTIA pixel readout circuit with offset cancellation function, the reverse bias voltage difference V of each pixel photodiode in the pixel array of the readout circuit is b remains unchanged. From formulas (8) and (10), it can be seen that the integral current change ΔI generated by each pixel photodiode in the pixel array compared to the case without offset int =ΔI d =0, so the combined readout method of the offset voltage pre-storage technology and the load capacitor pre-charging technology proposed in the present invention can effectively reduce the influence of the inconsistent PD dark current caused by the offset of each pixel circuit in the pixel array. At the same time, the combined readout method of the pixel circuit offset voltage pre-storage technology and the load capacitor pre-charging technology proposed in the present invention effectively fixes the starting voltage of each pixel unit during the integration process, eliminating the influence of the offset of the pixel circuit on the integration output. Therefore, the combined readout method of the pixel circuit offset voltage pre-storage technology and the load capacitor pre-charging technology proposed in the present invention can effectively eliminate the pixel array FPN and reduce the non-uniformity of the image sensor readout circuit.

[0121] The present invention also describes an image sensor, comprising at least one novel CTIA pixel readout circuit as described above.

[0122] The present invention also describes an electronic device, comprising at least one image sensor as described above.

[0123] Working principle: The present invention ensures that the voltage of the pixel bias node A is always maintained at the reference voltage during the integration period of the CTIA pixel readout circuit through a combination of offset voltage pre-storage and load capacitor pre-charging, and at the same time makes the initial value of the output voltage at the output node the reference voltage, thereby eliminating the offset of the pixel circuit and the output mismatch between pixel circuits, suppressing and eliminating the FPN of the image sensor pixel array caused by circuit offset and mismatch, and improving the uniformity of pixels.

[0124] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A novel CTIA pixel readout circuit, comprising a pixel and an integrator composed of an integrating operational amplifier and an integrating capacitor, wherein the integrating operational amplifier is a differential input operational amplifier, and wherein: include: An offset pre-storage module is used to pre-store the offset voltage obtained for the integrating operational amplifier to the inverting input terminal of the integrating operational amplifier during the reset phase of the pixel readout circuit; The load pre-charging module is used to adjust the initial voltage of the output terminal of the integrating operational amplifier to the reference voltage during the reset phase of the pixel readout circuit.

2. A novel CTIA pixel readout circuit according to claim 1, characterized in that: The offset pre-storage module realizes offset voltage pre-storage by connecting an offset storage capacitor in series between the bias node of the pixel and the inverting input terminal of the integrating operational amplifier; And / or, the load pre-charging module realizes load pre-charging by connecting a load capacitor in series between the output terminal of the integrating operational amplifier and the ground terminal.

3. A novel CTIA pixel readout circuit according to claim 2, characterized in that: The pixel readout circuit also includes a reset switch S1, a reset switch S2 and a reset switch S3; The two ends of the reset switch S1 are respectively connected to the output end and the inverting input end of the integrating operational amplifier; The two ends of the reset switch S2 are respectively connected to the bias node of the pixel and the reference voltage end; The two ends of the reset switch S3 are connected to the integration capacitor and the reference voltage terminal respectively.

4. A novel CTIA pixel readout circuit according to claim 3, characterized in that At time t0 in the reset phase, the reset switch S1 , the reset switch S2 , and the reset switch S3 are all closed, so that the voltage at the inverting input terminal of the integrating operational amplifier is equal to the sum of the reference voltage and the offset voltage.

5. The novel CTIA pixel readout circuit according to claim 3, characterized in that: The pixel readout circuit further includes a reset switch S4, and two ends of the reset switch S4 are respectively connected to the reference voltage end and the output port.

6. A novel CTIA pixel readout circuit according to claim 5, characterized in that At time t1 in the reset phase, the reset switch S1 is opened and the reset switch S4 is closed to pre-charge the integrator output.

7. The novel CTIA pixel readout circuit according to claim 5, characterized in that: The pixel readout circuit further includes an integration control switch S5, and two ends of the integration control switch S5 are respectively connected to a connection point between the integration capacitor and the reset switch S3 and an output end of the integration amplifier.

8. A novel CTIA pixel readout circuit according to claim 7, characterized in that At time t2 of the reset phase, the reset switches S2, S3 and S4 are opened, and the integration control switch S5 is closed, and the pixel readout circuit enters an integration state.

9. An image sensor, characterized in that: The invention comprises at least one novel CTIA pixel readout circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising at least one image sensor as claimed in claim 9.

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