Memory device, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a memory device, a manufacturing method thereof and electronic equipment. The manufacturing method of the memory device comprises the following steps: providing a substrate, wherein the side wall of a groove on one side is vertical to the bottom wall; a first insulating layer and a sacrificial layer are sequentially and alternately formed, and the sacrificial layer is provided with a first sacrificial part parallel to the bottom wall and a second sacrificial part parallel to the side wall; removing all the sacrificial layers and all the first insulating layers in areas outside the storage area, the connection area and the step area; forming a second insulating layer to fill the part of the groove, which is located at one side, facing the storage region, of the step region; then, removing all the remaining sacrificial layers to form a plurality of empty slots; thirdly, forming a plurality of conductive layers corresponding to the plurality of empty grooves one by one, enabling each conductive layer to fill the corresponding empty groove, enabling each conductive layer to be provided with a step part parallel to the bottom wall, and enabling the plurality of step parts to form a step; according to the embodiment of the invention, the step structure can be manufactured through a simpler process, and the process difficulty and the manufacturing cost are low.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a storage device and a method for manufacturing the same, and an electronic device. Background Art

[0002] Memory is the main medium for storing data in computers. With the development and progress of storage technology, storage devices are constantly moving towards miniaturization, high device density, and high integration. At the same time, they are also facing problems and challenges from manufacturing and other aspects. Summary of the invention

[0003] The present application proposes a storage device and a manufacturing method thereof, and an electronic device. By adopting the manufacturing method of the storage device provided in the embodiment of the present application, a stepped structure can be manufactured through a simpler process, thereby reducing the process difficulty and manufacturing cost.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a memory device, comprising:

[0005] Providing a substrate, wherein a groove is formed on one side of the substrate, and a side wall of the groove is perpendicular to a bottom wall of the groove;

[0006] A first insulating layer and a sacrificial layer are alternately formed on the inner wall of the groove in sequence, wherein the sacrificial layer has a first sacrificial portion parallel to the bottom wall and a second sacrificial portion parallel to the side wall, and the last first insulating layer away from the substrate fills the groove completely;

[0007] Performing a graphic process to remove all sacrificial layers and all first insulating layers located outside the storage area, the connection area and the step area, wherein the storage area and the connection area are both located within the orthographic projection of the last first insulating layer on the bottom wall, and the step area extends along a first direction perpendicular to the second sacrificial portion and overlaps with the orthographic projections of all sacrificial layers and all first insulating layers on the bottom wall;

[0008] forming a second insulating layer so that the second insulating layer fills a portion of the groove located on a side of the step region facing the storage region;

[0009] removing all remaining sacrificial layers to form a plurality of empty grooves arranged in sequence and spaced apart in a direction perpendicular to the bottom wall;

[0010] A plurality of conductive layers corresponding to the plurality of empty slots are formed so that each conductive layer fills the corresponding empty slot, each conductive layer has a step portion parallel to the bottom wall and a contact portion parallel to the side wall, and the plurality of step portions form a step.

[0011] In some optional embodiments of the present application, a first insulating layer and a sacrificial layer are alternately formed on the inner wall of the groove, including:

[0012] On a side of the substrate where the groove is formed, first oxide layers and nitride layers are alternately deposited in sequence, wherein the first first oxide layer close to the substrate covers the inner wall of the groove, and among the first oxide layers and nitride layers formed in sequence, the nitride layer covers the side of the first oxide layer away from the substrate, and the last first oxide layer away from the substrate fills the groove completely;

[0013] The first oxide layer and the nitride layer are planarized to make the top surface of the first oxide layer, the top surface of the nitride layer flush with the top surface of the side wall.

[0014] In some optional implementations of the present application, the graphical processing includes:

[0015] A mask layer is formed on one side of the substrate, wherein the mask layer has a preset pattern, and the orthographic projection of the preset pattern on the bottom wall overlaps with the storage area, the connection area and the step area;

[0016] All sacrificial layers and all first insulating layers are etched using the mask layer as a mask to remove all sacrificial layers and all first insulating layers whose orthographic projections on the bottom wall are located outside the storage area, the connection area and the step area, and the orthographic projections of all remaining sacrificial layers and all first insulating layers on the bottom wall overlap with the storage area, the connection area and the step area.

[0017] In some optional embodiments of the present application, a substrate is provided, comprising:

[0018] providing an initial substrate;

[0019] The initial substrate is etched to form a rectangular groove on one side of the initial substrate, the rectangular groove serves as a groove, and the etched initial substrate serves as a substrate.

[0020] In some optional embodiments of the present application, forming a second insulating layer includes:

[0021] Depositing a second oxide layer on one side of the substrate so that the second oxide layer fills the groove;

[0022] The second oxide layer is etched to remove the second oxide layer located in the groove on the side of the step area away from the storage area to expose all the remaining sacrificial layers. The remaining second oxide layer forms a second insulating layer. The second insulating layer and the first insulating layer form at least a part of the insulating structure of the storage device.

[0023] In some optional embodiments of the present application, all remaining sacrificial layers are removed, including:

[0024] All remaining sacrificial layers are wet-etched to remove all remaining sacrificial layers and to form a plurality of empty grooves accordingly.

[0025] In some optional embodiments of the present application, a plurality of conductive layers corresponding to the plurality of empty slots are formed, including:

[0026] Depositing a metal material on one side of the substrate, wherein the metal material fills the plurality of empty grooves and covers the surface of the insulating structure and the substrate;

[0027] The metal material covering the insulating structure and the substrate surface is removed, and the remaining metal material forms a plurality of conductive layers corresponding to the plurality of empty slots.

[0028] In some optional implementations of the present application, after forming a plurality of conductive layers, the method for manufacturing a memory device further includes:

[0029] A third insulating layer is formed on one side of the substrate so that the third insulating layer fills the groove, and the third insulating layer, the first insulating layer and the second insulating layer form an insulating structure of the memory device.

[0030] In a second aspect, an embodiment of the present application provides a memory device, which is manufactured using the above-mentioned memory device manufacturing method;

[0031] Storage devices include:

[0032] A substrate, wherein a groove is formed on one side of the substrate, and a side wall of the groove is perpendicular to a bottom wall of the groove;

[0033] A storage structure is arranged on one side of the bottom wall, and its orthographic projection on the bottom wall is located in the storage area, the storage structure includes a plurality of storage array layers stacked in sequence along a direction perpendicular to the bottom wall, and each storage array layer includes a plurality of storage units arranged in an array;

[0034] A step structure is arranged on one side of the bottom wall, and its orthographic projection on the bottom wall is located in the step area, the step structure includes a plurality of step portions arranged in sequence and spaced apart in a direction perpendicular to the bottom wall and contact portions respectively connected to the step portions, and the plurality of step portions form a step;

[0035] The plurality of stepped portions correspond to the plurality of memory array layers one by one, and each stepped portion is connected to at least one column of memory cells of the corresponding memory array layer.

[0036] In some optional embodiments of the present application, the size of each step portion in the first direction gradually decreases in a direction away from the bottom wall;

[0037] Each contact portion is connected to an end portion of each corresponding step portion along the first direction.

[0038] In some optional embodiments of the present application, both ends of the plurality of stepped portions along the first direction form steps;

[0039] Two ends of each step portion along the first direction are correspondingly connected to a contact portion.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned storage device.

[0041] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0042] In an embodiment of the present application, a groove is formed on one side of the provided substrate, and the side wall of the groove is perpendicular to the bottom wall; a first insulating layer and a sacrificial layer are alternately formed on the inner wall of the groove in sequence, and the first first insulating layer close to the substrate covers the inner wall of the groove. Among the first insulating layers and sacrificial layers formed in sequence, the sacrificial layer covers the side of the first insulating layer away from the substrate, so that each sacrificial layer has a first sacrificial portion parallel to the bottom wall and a second sacrificial portion parallel to the side wall, and the second sacrificial portion is perpendicular to the first sacrificial portion, so that the subsequently formed step portion and the contact portion are perpendicular, which is convenient for routing and connection with external devices, and helps to achieve miniaturization and improve storage density; the dimensions of multiple first sacrificial portions along the first direction will decrease in the direction away from the bottom wall, so that the multiple first sacrificial portions form steps; the last first insulating layer away from the substrate fills the groove to avoid hollowing out, which is convenient for subsequent chemical mechanical polishing.

[0043] Then, a graphical processing is performed to remove all sacrificial layers and all first insulating layers located outside the storage area, the connection area and the step area, and only the sacrificial layers and the first insulating layers located in the storage area, the connection area and the step area are retained; wherein the storage area and the connection area are both located within the orthographic projection of the last first insulating layer on the bottom wall, and the step area extends along a first direction perpendicular to the second sacrificial portion, and overlaps with the orthographic projections of all sacrificial layers and all first insulating layers on the bottom wall.

[0044] Next, a second insulating layer is formed to fill the portion of the groove located on the side of the step area facing the storage area; then all remaining sacrificial layers are removed, and an empty groove is formed at the position corresponding to each removed sacrificial layer, and the empty groove has the same position and shape as the corresponding removed sacrificial layer, and the multiple empty grooves are arranged in sequence at intervals along a direction perpendicular to the bottom wall; then multiple conductive layers corresponding to the multiple empty grooves are formed one by one, and each conductive layer fills the corresponding empty groove, so that each conductive layer has the same shape as the sacrificial layer, that is, each conductive layer has a step portion parallel to the bottom wall and a contact portion parallel to the side wall, and the multiple step portions form a step.

[0045] In the embodiment of the present application, the substrate has a groove, and the side wall of the groove is perpendicular to the bottom wall. In this way, the first insulating layer and the sacrificial layer are alternately formed on the inner wall of the groove, and the first sacrificial part parallel to the bottom wall and the second sacrificial part parallel to the side wall can be naturally formed. Since the first insulating layer and the sacrificial layer are stacked in sequence, multiple first sacrificial parts can naturally form a step. After the steps are formed, all sacrificial layers are removed, and multiple conductive layers are formed accordingly. The sacrificial layers are replaced by conductive layers, so that each conductive layer has a step portion parallel to the bottom wall and a contact portion parallel to the side wall, and multiple step portions form a step. By using the method for manufacturing a storage device provided in the embodiment of the present application, a step structure can be naturally formed through a simpler process, which greatly simplifies the process steps and reduces the process difficulty and manufacturing cost.

[0046] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0048] Figure 1 A schematic diagram of a process for manufacturing a memory device provided in an embodiment of the present application;

[0049] Figures 2 to 13 A schematic diagram of the structure of a storage device in different processes in a method for manufacturing the storage device provided in an embodiment of the present application;

[0050] Fig.14 A schematic diagram of the structure of a storage device provided in an embodiment of the present application.

[0051] Reference numerals:

[0052] 100-storage device; 10-substrate; 11-groove; 12-side wall; 13-bottom wall; 14-initial substrate; 20-first insulating layer; 21-first oxide layer; 30-sacrificial layer; 31-first sacrificial portion; 32-second sacrificial portion; 33-empty groove; 34-nitride layer; 341-initial first sacrificial portion; 342-initial second sacrificial portion; 40-second insulating layer; 41-second oxide layer; 50-conductive layer; 51-step portion; 52-contact portion; 53-step; 54-metal structure; 60-mask layer; 61-preset pattern; 70-third insulating layer; 80-storage structure; 81-storage array layer; 82-storage cell; 83-channel; 84-bit line; 90-step structure; 110-insulating structure. DETAILED DESCRIPTION

[0053] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0054] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or may refer to the connection relationship between the element and the other element established through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0055] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0056] The following is an explanation of the relevant technologies:

[0057] With the development of advanced technologies such as the Internet of Things and smart driving, the market demand for memory devices is increasing day by day. Advanced technologies require advanced chips to be implemented, which leads to the need to continuously shrink the size of integrated circuits. Faced with this situation, the development of memory devices also faces challenges. At this time, 3D (3-Dimension) memory devices came into being. 3D memory devices can significantly increase storage density while reducing area, and are expected to solve the process challenges brought about by size shrinkage.

[0058] 3D DRAM (Dynamic Random Access Memory) devices need to use a staircase structure to achieve connections between each layer of storage cells and external devices.

[0059] At present, the process method for manufacturing the staircase structure is mainly to form each step of the staircase structure separately through multiple photolithography, which has complex process steps and high process difficulty.

[0060] The storage device and its manufacturing method, and the electronic device provided in this application are intended to solve the above technical problems in the prior art.

[0061] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0062] The present application embodiment provides a method for manufacturing a memory device. The flowchart of the method for manufacturing the memory device is as follows: Figure 1 As shown, including:

[0063] S101 , providing a substrate 10 , wherein a groove 11 is formed on one side of the substrate 10 , and a side wall 12 of the groove 11 is perpendicular to a bottom wall 13 of the groove 11 .

[0064] S102, first insulating layers 20 and sacrificial layers 30 are alternately formed on the inner wall of the groove 11, wherein the sacrificial layer 30 has a first sacrificial portion 31 parallel to the bottom wall 13 and a second sacrificial portion 32 parallel to the side wall 12, and the last first insulating layer 20 away from the substrate 10 fills the groove 11.

[0065] S103, perform graphical processing to remove all sacrificial layers 30 and all first insulating layers 20 located outside the storage area, the connection area and the step area. The storage area and the connection area are both located within the orthographic projection of the last first insulating layer 20 on the bottom wall 13. The step area extends along a first direction perpendicular to the second sacrificial portion 32 and overlaps with the orthographic projections of all sacrificial layers 30 and all first insulating layers 20 on the bottom wall 13.

[0066] S104 , forming a second insulating layer 40 , so that the second insulating layer 40 fills a portion of the groove 11 located on a side of the step region facing the storage region.

[0067] S105 , removing all remaining sacrificial layers 30 to form a plurality of empty grooves 33 arranged in sequence and spaced apart in a direction perpendicular to the bottom wall 13 .

[0068] S106. Form a plurality of conductive layers 50 corresponding to the plurality of empty slots 33 one by one, so that each conductive layer 50 fills the corresponding empty slot 33, and each conductive layer 50 has a step portion 51 parallel to the bottom wall 13 and a contact portion 52 parallel to the side wall 12, and the plurality of step portions 51 form a step 53.

[0069] In the embodiment of the present application, the memory device 100 can be manufactured by the memory device manufacturing method of the embodiment of the present application.

[0070] In the embodiment of the present application, the substrate 10 supports the first insulating layer 20 , the sacrificial layer 30 , the second insulating layer 40 , and the conductive layer 50 .

[0071] In the embodiment of the present application, a groove 11 is formed on one side of the provided substrate 10, and the side wall 12 of the groove 11 is perpendicular to the bottom wall 13; a first insulating layer 20 and a sacrificial layer 30 are alternately formed on the inner wall of the groove 11 in sequence, and the first first insulating layer 20 close to the substrate 10 covers the inner wall of the groove 11. Among the first insulating layers 20 and sacrificial layers 30 formed in sequence, the sacrificial layer 30 covers the side of the first insulating layer 20 away from the substrate 10, so that each sacrificial layer 30 has a first sacrificial portion 31 parallel to the bottom wall 13 and a second sacrificial portion 32 parallel to the side wall 12, and the second sacrificial portion 32 is perpendicular to the first sacrificial portion 31, so that the subsequently formed step portion 51 and the contact portion 52 are perpendicular, which is convenient for routing and connection with external devices, and helps to achieve miniaturization and improve storage density; the size of the multiple first sacrificial portions 31 along the first direction will decrease along the direction away from the bottom wall 13 (such as Figure 5 and Figure 6 As shown), the plurality of first sacrificial portions 31 form steps; the last first insulating layer 20 away from the substrate 10 fills the groove 11 to avoid hollowing out, which is convenient for subsequent chemical mechanical polishing.

[0072] Then, a graphical processing is performed to remove all sacrificial layers 30 and all first insulating layers 20 located outside the storage area, the connection area and the step area, and only the sacrificial layers 30 and the first insulating layers 20 located in the storage area, the connection area and the step area are retained; wherein the storage area and the connection area are both located within the orthographic projection of the last first insulating layer 20 on the bottom wall 13, and the step area extends along a first direction perpendicular to the second sacrificial portion 32, and overlaps with the orthographic projections of all sacrificial layers 30 and all first insulating layers 20 on the bottom wall 13.

[0073] Next, a second insulating layer 40 is formed to fill the portion of the groove 11 located on the side of the step area facing the storage area; then, all remaining sacrificial layers 30 are removed, and an empty groove 33 is formed at the position corresponding to each removed sacrificial layer 30, and the position and shape of the empty groove 33 are the same as those of the corresponding removed sacrificial layer 30, and the multiple empty grooves 33 are arranged in sequence and spaced apart in a direction perpendicular to the bottom wall 13; then, multiple conductive layers 50 corresponding to the multiple empty grooves 33 are formed one by one, and each conductive layer 50 fills the corresponding empty groove 33, so that each conductive layer 50 has the same shape as the sacrificial layer 30, that is, each conductive layer 50 has a step portion 51 parallel to the bottom wall 13 and a contact portion 52 parallel to the side wall 12, and the multiple step portions 51 form a step 53.

[0074] In the embodiment of the present application, the substrate 10 has a groove 11, and the side wall 12 of the groove 11 is perpendicular to the bottom wall 13. In this way, the first insulating layer 20 and the sacrificial layer 30 are alternately formed on the inner wall of the groove 11 in sequence, and a first sacrificial portion 31 parallel to the bottom wall 13 and a second sacrificial portion 32 parallel to the side wall 12 can naturally be formed. Moreover, since the first insulating layer 20 and the sacrificial layer 30 are stacked in sequence, it is natural that multiple first sacrificial portions 31 can form a step; after the steps are formed, all sacrificial layers 30 are removed, and multiple conductive layers 50 are formed accordingly, and the sacrificial layers 30 are replaced by the conductive layers 50, so that each conductive layer 50 has a step portion 51 parallel to the bottom wall 13 and a contact portion 52 parallel to the side wall 12, and multiple step portions 51 form a step 53.

[0075] In the embodiment of the present application, the portions of the multiple conductive layers 50 located in the step area form a staircase structure, that is, the step portions 51 and the contact portions 52 of the multiple conductive layers 50 arranged in sequence perpendicular to the bottom wall 13 form a staircase structure. One end of each contact portion 52 is connected to a corresponding step portion 51, and the other end passes through the insulating structure 110 and is connected to an external device, so that different step portions 51 are conveniently connected to external devices through corresponding contact portions 52, respectively, to achieve the purpose of connecting the storage structure to the external device through the staircase structure.

[0076] By adopting the manufacturing method of the memory device provided in the embodiment of the present application, a staircase structure can be naturally formed through a simpler process, which greatly simplifies the process steps and reduces the process difficulty and manufacturing cost.

[0077] like Figure 5 and Fig.12 As shown, in the embodiment of the present application, the second sacrificial portion 32 is formed at both ends of the first sacrificial portion 31 along the first direction, so that after the sacrificial layer 30 is replaced by the conductive layer 50, the contact portions 52 are formed at both ends of the step portion 51 along the first direction, and the step portion 51 is connected to the external device through the contact portions 52 connected at both ends. It should be noted that in some optional embodiments of the present application, the second sacrificial portion 32 can be formed at any end of the first sacrificial portion 31 along the first direction, so that after the sacrificial layer 30 is replaced by the conductive layer 50, a contact portion 52 is formed at one end of the step portion 51 along the first direction, so that the step portion 51 is connected to the external device through a connected contact portion 52.

[0078] It should be noted that in the embodiment of the present application, the side wall 12 is perpendicular to the bottom wall 13, the second sacrificial portion 32 is perpendicular to the first sacrificial portion 31, and the step portion 51 is perpendicular to the contact portion 52. This arrangement facilitates routing and connection with external devices, helps to achieve miniaturization, and improves storage density. Of course, in some optional embodiments of the present application, the side wall 12 and the bottom wall 13 can be made close to vertical, and / or the second sacrificial portion 32 and the first sacrificial portion 31 can be made close to vertical, and / or the step portion 51 and the contact portion 52 can be made close to vertical according to actual needs. Here, "close to vertical" is within a reasonable process error range, or fluctuates within a certain design error, such as an angle within the range of 90°±5°.

[0079] In the embodiment of the present application, the storage area, the connection area and the step area are sequentially continuous and extend along a second direction parallel to the bottom wall 13, and the second direction is arranged at an angle to the first direction. Optionally, the second direction is perpendicular to the first direction.

[0080] In some optional embodiments of the present application, such as Figure 2 and Figure 3 As shown, a substrate 10 is provided, comprising:

[0081] like Figure 2 As shown, an initial substrate 14 is provided; optionally, the initial substrate 14 is a silicon substrate. A thicker silicon substrate can be provided as the initial substrate 14 to facilitate the subsequent formation of the groove 11 on one side of the initial substrate 14.

[0082] Then, if Figure 3 As shown, the initial substrate 14 is etched to form a rectangular groove on one side of the initial substrate 14, and the rectangular groove serves as the groove 11, so that the side wall 12 of the groove 11 is perpendicular to the bottom wall 13, and the initial substrate 14 after etching serves as the substrate 10. Optionally, the initial substrate 14 is etched by a photolithography process to form a rectangular groove shape on one side of the initial substrate 14 to form the substrate 10.

[0083] In some optional embodiments of the present application, such as Figure 4 and Figure 5 As shown, a first insulating layer 20 and a sacrificial layer 30 are alternately formed in sequence on one side of a substrate 10 where a groove 11 is formed, including:

[0084] like Figure 4As shown, the first oxide layer 21 and the nitride layer 34 are alternately deposited on the side of the substrate 10 where the groove 11 is formed, the first first oxide layer 21 close to the substrate 10 covers the inner wall of the groove 11, and among the first oxide layers 21 and nitride layers 34 formed in sequence, the nitride layer 34 covers the side of the first oxide layer 21 away from the substrate 10, so that each nitride layer 34 has an initial first sacrificial portion 341 and an initial second sacrificial portion 342, the initial first sacrificial portion 341 is parallel to the bottom wall 13, and the dimensions of the multiple initial first sacrificial portions 341 along the first direction decrease along the direction away from the bottom wall 13, so that the multiple initial first sacrificial portions 341 form a step; the last first oxide layer 21 away from the substrate 10 fills the groove 11. The first oxide layer 21 plays a role of isolation and insulation.

[0085] Optionally, a first oxide layer 21 and a nitride layer 34 are deposited and grown in the groove 11 using a CVD (Chemical Vapor Deposition) process or an ALD (Atomic Layer Deposition) process with good conformality, so that the portion of the initial second sacrificial portion 342 located in the groove 11 is perpendicular or nearly perpendicular to the initial first sacrificial portion 341; and a thicker oxide is deposited at the top as the last first oxide layer 21, and the last first oxide layer 21 fills the groove 11 and the position of filling the groove 11 is higher than the top surface of the side wall 12.

[0086] Optionally, the orthographic projections of the first oxide layer 21 and the nitride layer 34 on the bottom wall 13 both cover the storage area, the connection area and the step area. Optionally, the material of the first oxide layer 21 can be an oxide that can play an insulating role (such as silicon oxide).

[0087] Then, if Figure 5 As shown, the first oxide layer 21 and the nitride layer 34 are planarized so that the top surface of the first oxide layer 21 and the top surface of the nitride layer 34 are flush with the top surface of the sidewall 12. The first oxide layer 21 after the planarization forms the first insulating layer 20, and the nitride layer 34 after the planarization forms the sacrificial layer 30. Optionally, the planarization process can be performed by a chemical mechanical polishing (CMP) process.

[0088] Compared with the current methods and technologies of manufacturing staircase structures step by step through photolithography, in the embodiment of the present application, the special shape of the groove 11 on one side of the substrate 10 (the side wall 12 is perpendicular to the bottom wall 13) and the deposition process with good conformality (such as CVD process) are used to naturally form a staircase structure, which greatly simplifies the process steps and reduces the process difficulty and manufacturing cost.

[0089] In some optional embodiments of the present application, such as Figure 6 and Figure 7 As shown, graphical processing is performed, including:

[0090] like Figure 6 As shown, a mask layer 60 is formed on one side of the substrate 10, and the mask layer 60 has a preset pattern 61 (the outer contour of the preset pattern 61 is as shown in FIG. Figure 6 As shown in the dashed box, it can be understood that the outer contour of the preset pattern 61 is the same as the outer contour of the positive projection of the mask layer 60 on the bottom wall 13), and the positive projection of the preset pattern 61 on the bottom wall 13 overlaps with the storage area, the connection area and the step area (along the Figure 6 The orthographic projections of the preset pattern 61 on the bottom wall 13 from back to front in the second direction correspond to the storage area, the connection area and the step area in sequence). Optionally, the material of the mask layer 60 includes but is not limited to photoresist (PR for short).

[0091] Then, if Figure 7 As shown, all sacrificial layers 30 and all first insulating layers 20 are etched using the mask layer 60 as a mask to remove all sacrificial layers 30 and all first insulating layers 20 whose orthographic projections on the bottom wall 13 are outside the storage area, the connection area, and the step area, and the orthographic projections of all remaining sacrificial layers 30 and all first insulating layers 20 on the bottom wall 13 overlap with the storage area, the connection area, and the step area. Optionally, all sacrificial layers 30 and all first insulating layers 20 are etched by a dry etching process.

[0092] In some optional embodiments of the present application, such as Figure 8 and Fig. 9 As shown, forming a second insulating layer 40 includes:

[0093] like Figure 8As shown, a second oxide layer 41 is deposited on one side of the substrate 10 so that the second oxide layer 41 fills the groove 11, and the second oxide layer 41 is planarized so that the surface of the second oxide layer 41 away from the bottom wall 13 is flush with the top surface of the side wall 12. Optionally, the material of the second oxide layer 41 can be an oxide that can play an insulating role (such as silicon oxide), and the material of the second oxide layer 41 and the first oxide layer 21 can be the same or different, and can be selected according to actual needs. Optionally, the planarization process can be performed by a chemical mechanical polishing (CMP) process.

[0094] Then, if Fig. 9 As shown, the second oxide layer 41 is etched to remove the second oxide layer 41 located on the side of the step area away from the storage area in the groove 11 to expose all the remaining sacrificial layers 30, which is convenient for the subsequent removal of all the sacrificial layers 30. The remaining second oxide layer 41 forms a second insulating layer 40, and the second insulating layer 40 and the first insulating layer 20 form at least a part of the insulating structure 110 of the memory device 100. The second insulating layer 40 can support the multiple first insulating layers 20 arranged at intervals after all the sacrificial layers 30 are removed.

[0095] In some optional embodiments of the present application, such as Fig.10 As shown, all remaining sacrificial layers 30 are removed, including:

[0096] All remaining sacrificial layers 30 are wet-etched to remove all remaining sacrificial layers 30 and to form a plurality of corresponding empty grooves 33. In this way, all nitride layers corresponding to the storage area, the connection area and the step area can be removed, so as to facilitate the subsequent formation of the conductive layer 50.

[0097] In some optional embodiments of the present application, such as Fig.11 and Fig.12 As shown, a plurality of conductive layers 50 corresponding to the plurality of empty slots 33 are formed, including:

[0098] like Fig.11 As shown, a metal material is deposited on one side of the substrate 10 to form a metal structure 54, which fills the plurality of empty grooves 33 and covers the insulating structure 110 and the surface of the substrate 10. Optionally, the metal material includes but is not limited to tungsten.

[0099] Then, if Fig.12As shown, the metal material covering the surface of the insulating structure 110 and the substrate 10 is removed, and the remaining metal material forms a plurality of conductive layers 50 corresponding to the plurality of empty grooves 33, completing the replacement of the etched sacrificial layer 30 with the conductive layer 50. Optionally, the metal material covering the insulating structure 110 and the substrate 10 is removed by etching (such as dry etching).

[0100] In some optional embodiments of the present application, such as Fig.13 As shown, after forming a plurality of conductive layers 50, the method for manufacturing a memory device further includes:

[0101] A third insulating layer 70 is formed on one side of the substrate 10, so that the third insulating layer 70 fills the groove 11, and the third insulating layer 70 is planarized so that the surface of the third insulating layer 70 away from the bottom wall 13 is flush with the top surface of the side wall 12. The third insulating layer 70, the first insulating layer 20 and the second insulating layer 40 after planarization form an insulating structure 110 of the storage device 100. The third insulating layer 70 can play a role of isolation and insulation, and can avoid the connection between the two storage arrays. Optionally, the material of the third insulating layer 70 can be an oxide (such as silicon oxide) that can play an insulating role. The material of the third insulating layer 70 and the first oxide layer 21 can be the same or different, and can be selected according to actual needs. Optionally, the planarization process can be performed by a chemical mechanical polishing (CMP) process.

[0102] Optionally, each stepped portion 51 may form a common bit line, and multiple stepped portions 51 form multiple common bit lines spaced in sequence along a direction perpendicular to the substrate 10 , that is, multiple common bit lines spaced in sequence along a direction perpendicular to the substrate 10 form a step 53 .

[0103] It should be noted that the manufacturing method of the storage device in the embodiment of the present application mainly involves the process improvement of the staircase structure of the storage device. The storage device also includes a storage structure corresponding to the storage area. The manufacturing process of the storage structure in the embodiment of the present application may be similar to or the same as the manufacturing process of the conventional storage structure, which will not be repeated here.

[0104] Optionally, the manufacturing process of the storage structure may be performed simultaneously with the manufacturing method of the storage device of the embodiment of the present application, or may be performed after the manufacturing method of the storage device of the embodiment of the present application is completed.

[0105] The method for manufacturing a memory device provided in the embodiment of the present application belongs to the field of semiconductor memory device preparation, can be used to manufacture a staircase structure of a memory device, and can be applied to 3D DRAM devices. Specifically, it can be applied to vertical oxide channel (VOC) 3D DRAM devices.

[0106] It should be noted that, in the embodiment of the present application, each film layer structure of the storage device can be patterned by a composition process to produce each corresponding film layer.

[0107] It should be noted that the "patterning process" mentioned in the embodiments of the present application includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping a photoresist, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in the embodiments of the present application includes processes such as coating a film layer, mask exposure, and development, which is a mature preparation process in the relevant technology. Among them, deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0108] Based on the same inventive concept, an embodiment of the present application provides a storage device 100 , which is manufactured using the above-mentioned storage device manufacturing method.

[0109] The structural diagram of the storage device 100 is shown in FIG. Fig.12 and Fig.14 As shown, it includes: a substrate 10 , a storage structure 80 and a step structure 90 .

[0110] A groove 11 is formed on one side of the substrate 10, and a side wall 12 of the groove 11 is perpendicular to the bottom wall 13 of the groove 11; a storage structure 80 is arranged on one side of the bottom wall 13, and its orthographic projection on the bottom wall 13 is located in the storage area, and the storage structure 80 includes a plurality of storage array layers 81 stacked in sequence along a direction perpendicular to the bottom wall 13, and each storage array layer 81 includes a plurality of storage units 82 arranged in an array; a step structure 90 is arranged on one side of the bottom wall 13, and its orthographic projection on the bottom wall 13 is located in the step area, and the step structure 90 includes a plurality of step portions 51 arranged in sequence at intervals along a direction perpendicular to the bottom wall 13 and contact portions 52 respectively connected to each step portion 51, and the plurality of step portions 51 form a step 53; the plurality of step portions 51 correspond one-to-one to the plurality of storage array layers 81, and each step portion 51 is connected to at least one storage unit 82 of the corresponding storage array layer 81.

[0111] Through this arrangement, a 3D stacking structure can be formed, which can improve the storage capacity of the storage device, reduce storage costs, increase integration and storage density, and help achieve miniaturization.

[0112] In some optional embodiments of the present application, such as Fig.12 As shown, the dimension of each step portion 51 in the first direction gradually decreases in the direction away from the bottom wall 13 ; each contact portion 52 is respectively connected to the end of each corresponding step portion 51 in the first direction.

[0113] In some optional embodiments of the present application, such as Fig.12 As shown, both ends of the plurality of step portions 51 along the first direction form steps; and both ends of each step portion 51 along the first direction are correspondingly connected to a contact portion 52 .

[0114] It should be noted that since the storage device of the embodiment of the present application is manufactured using the storage device manufacturing method of the embodiment of the present application, the storage device of the embodiment of the present application also has the above-mentioned beneficial effects of the storage device manufacturing method of the embodiment of the present application, which will not be repeated here.

[0115] In some optional implementations of the present application, the storage device may be a random access memory, specifically a static random access memory or a dynamic random access memory, and of course, may also be a flash memory storage, etc.

[0116] In a specific embodiment, Fig.12 and Fig.14 As shown, the memory device 100 is a vertical oxide channel 3D DRAM device, the channel 83 of the memory cell 82 is a vertical channel, the first electrode of the memory cell 82 is connected to the capacitor, the second electrode is connected to the bit line 84, the second electrodes of multiple memory cells 82 in the same memory array layer 81 share the same bit line 84, the bit line 84 is connected to the step portion 51, and the step portion 51 is a common bit line. That is, the multiple common bit lines in the vertical oxide channel 3D DRAM device are made into a staircase structure, so as to realize the connection between each layer of memory cells and external devices.

[0117] Optionally, the channel material includes but is not limited to a metal oxide semiconductor material. The metal oxide semiconductor material may be indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the metal oxide semiconductor material can also be ITO (Indium Tin Oxide, indium tin oxide), IZO (Indium Zinc Oxide, indium zinc oxide), IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnOx 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO, IAZO and other materials. As long as the leakage current of the transistor can meet the requirements, it can be adjusted according to the actual situation.

[0118] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the above-mentioned storage device 100.

[0119] It should be noted that, since the electronic device of the embodiment of the present application includes the storage device of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the storage device of the embodiment of the present application, which will not be repeated here.

[0120] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply, etc. Among them, the storage device may include a memory in a computer, etc., which is not limited here.

[0121] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0122] In an embodiment of the present application, a groove is formed on one side of the provided substrate, and the side wall of the groove is perpendicular to the bottom wall; a first insulating layer and a sacrificial layer are alternately formed on the inner wall of the groove in sequence, and the first first insulating layer close to the substrate covers the inner wall of the groove. Among the first insulating layers and sacrificial layers formed in sequence, the sacrificial layer covers the side of the first insulating layer away from the substrate, so that each sacrificial layer has a first sacrificial portion parallel to the bottom wall and a second sacrificial portion parallel to the side wall, and the second sacrificial portion is perpendicular to the first sacrificial portion, so that the subsequently formed step portion and the contact portion are perpendicular, which is convenient for routing and connection with external devices, and helps to achieve miniaturization and improve storage density; the dimensions of multiple first sacrificial portions along the first direction will decrease in the direction away from the bottom wall, so that the multiple first sacrificial portions form steps; the last first insulating layer away from the substrate fills the groove to avoid hollowing out, which is convenient for subsequent chemical mechanical polishing.

[0123] Then, a graphical processing is performed to remove all sacrificial layers and all first insulating layers located outside the storage area, the connection area and the step area, and only the sacrificial layers and the first insulating layers located in the storage area, the connection area and the step area are retained; wherein the storage area and the connection area are both located within the orthographic projection of the last first insulating layer on the bottom wall, and the step area extends along a first direction perpendicular to the second sacrificial portion, and overlaps with the orthographic projections of all sacrificial layers and all first insulating layers on the bottom wall.

[0124] Next, a second insulating layer is formed to fill the portion of the groove located on the side of the step area facing the storage area; then all remaining sacrificial layers are removed, and an empty groove is formed at the position corresponding to each removed sacrificial layer, and the empty groove has the same position and shape as the corresponding removed sacrificial layer, and the multiple empty grooves are arranged in sequence at intervals along a direction perpendicular to the bottom wall; then multiple conductive layers corresponding to the multiple empty grooves are formed one by one, and each conductive layer fills the corresponding empty groove, so that each conductive layer has the same shape as the sacrificial layer, that is, each conductive layer has a step portion parallel to the bottom wall and a contact portion parallel to the side wall, and the multiple step portions form a step.

[0125] In the embodiment of the present application, the substrate has a groove, and the side wall of the groove is perpendicular to the bottom wall. In this way, the first insulating layer and the sacrificial layer are alternately formed on the inner wall of the groove, and the first sacrificial part parallel to the bottom wall and the second sacrificial part parallel to the side wall can be naturally formed. Since the first insulating layer and the sacrificial layer are stacked in sequence, multiple first sacrificial parts can naturally form a step. After the steps are formed, all sacrificial layers are removed, and multiple conductive layers are formed accordingly. The sacrificial layers are replaced by conductive layers, so that each conductive layer has a step portion parallel to the bottom wall and a contact portion parallel to the side wall, and multiple step portions form a step. By using the method for manufacturing a storage device provided in the embodiment of the present application, a step structure can be naturally formed through a simpler process, which greatly simplifies the process steps and reduces the process difficulty and manufacturing cost.

[0126] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0127] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0128] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0129] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0130] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0131] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0132] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A method for manufacturing a memory device, characterized in that: include: Providing a substrate, wherein a groove is formed on one side of the substrate, and a side wall of the groove is perpendicular to a bottom wall of the groove; Alternatingly forming a first insulating layer and a sacrificial layer on the inner wall of the groove, the sacrificial layer having a first sacrificial portion parallel to the bottom wall and a second sacrificial portion parallel to the side wall, and the last first insulating layer away from the substrate fully fills the groove; Performing a graphic process to remove all the sacrificial layers and all the first insulating layers located in areas other than a storage area, a connection area, and a step area, wherein the storage area and the connection area are both located within the orthographic projection of the last first insulating layer on the bottom wall, and the step area extends along a first direction perpendicular to the second sacrificial portion and overlaps with the orthographic projections of all the sacrificial layers and all the first insulating layers on the bottom wall; forming a second insulating layer so that the second insulating layer fills a portion of the groove located on a side of the step area facing the storage area; removing all the remaining sacrificial layers to form a plurality of empty grooves arranged in sequence and spaced apart in a direction perpendicular to the bottom wall; A plurality of conductive layers corresponding to the plurality of empty slots are formed, so that each conductive layer fills the corresponding empty slot, each conductive layer has a stepped portion parallel to the bottom wall and a contact portion parallel to the side wall, and the plurality of stepped portions form a step.

2. The method for manufacturing a memory device according to claim 1, wherein: The first insulating layer and the sacrificial layer are alternately formed on the inner wall of the groove, comprising: On the side of the substrate where the groove is formed, first oxide layers and nitride layers are alternately deposited in sequence, wherein the first first oxide layer close to the substrate covers the inner wall of the groove, and among the first oxide layers and the nitride layers formed in sequence, the nitride layer covers the side of the first oxide layer away from the substrate, and the last first oxide layer away from the substrate fills the groove; The first oxide layer and the nitride layer are planarized so that a top surface of the first oxide layer, a top surface of the nitride layer and a top surface of the side wall are flush.

3. The method for manufacturing a memory device according to claim 2, wherein: Perform graphical processing, including: A mask layer is formed on one side of the substrate, wherein the mask layer has a preset pattern, and the orthographic projection of the preset pattern on the bottom wall overlaps with the storage area, the connection area, and the step area; All the sacrificial layers and all the first insulating layers are etched using the mask layer as a mask to remove all the sacrificial layers and all the first insulating layers whose orthographic projections on the bottom wall are located outside the storage area, the connection area and the step area, and the orthographic projections of all the remaining sacrificial layers and all the first insulating layers on the bottom wall overlap with the storage area, the connection area and the step area.

4. The method for manufacturing a memory device according to any one of claims 1 to 3, characterized in that: A substrate is provided, comprising: providing an initial substrate; The initial substrate is etched to form a rectangular groove on one side of the initial substrate, the rectangular groove serves as the groove, and the initial substrate after etching serves as the substrate.

5. The method for manufacturing a memory device according to any one of claims 1 to 3, characterized in that: Forming a second insulating layer, comprising: Depositing a second oxide layer on one side of the substrate so that the second oxide layer fills the groove; The second oxide layer is etched to remove the second oxide layer in the groove on the side of the step area away from the storage area to expose all the remaining sacrificial layers, and the remaining second oxide layer forms the second insulating layer, and the second insulating layer and the first insulating layer form at least a part of the insulating structure of the storage device.

6. The method for manufacturing a memory device according to claim 5, characterized in that: Removing all remaining sacrificial layers, including: All the remaining sacrificial layers are wet-etched to remove all the remaining sacrificial layers and to form a plurality of empty grooves accordingly.

7. The method for manufacturing a memory device according to claim 6, characterized in that: Forming a plurality of conductive layers corresponding to the plurality of empty slots one by one, comprising: Depositing a metal material on one side of the substrate, wherein the metal material fills the plurality of empty grooves and covers the insulating structure and the surface of the substrate; The metal material covering the insulating structure and the surface of the substrate is removed, and the remaining metal material forms a plurality of conductive layers corresponding to the plurality of empty grooves one by one.

8. The method for manufacturing a memory device according to claim 7, characterized in that: After forming a plurality of conductive layers, the method for manufacturing the memory device further includes: A third insulating layer is formed on one side of the substrate so that the third insulating layer fills the groove, and the third insulating layer, the first insulating layer and the second insulating layer form an insulating structure of a memory device.

9. A storage device, characterized in that: Made by the method for making a storage device according to any one of claims 1 to 8; The storage device comprises: A substrate, wherein a groove is formed on one side of the substrate, and a side wall of the groove is perpendicular to a bottom wall of the groove; A storage structure is arranged on one side of the bottom wall, and its orthographic projection on the bottom wall is located in the storage area, the storage structure comprises a plurality of storage array layers stacked in sequence along a direction perpendicular to the bottom wall, and each of the storage array layers comprises a plurality of storage units arranged in an array; a step structure, arranged on one side of the bottom wall, and having an orthographic projection on the bottom wall located in a step area, the step structure comprising a plurality of step portions arranged in sequence and spaced apart in a direction perpendicular to the bottom wall and contact portions respectively connected to the step portions, the plurality of step portions forming a step; The plurality of stepped portions correspond one-to-one to the plurality of storage array layers, and each of the stepped portions is connected to at least one column of storage cells of the corresponding storage array layer.

10. The memory device according to claim 9, wherein: The size of each of the step portions in the first direction gradually decreases in a direction away from the bottom wall; Each of the contact portions is connected to an end portion of each corresponding step portion along the first direction.

11. The memory device according to claim 10, wherein: Both ends of the plurality of step portions along the first direction form steps; Both ends of each step portion along the first direction are correspondingly connected to the contact portion.

12. An electronic device, characterized in that: A storage device comprising the storage device according to any one of claims 9 to 11.

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