Method of manufacturing three-dimensional memory

Abstract

The present disclosure provides a preparation method of a three-dimensional memory, and relates to the technical field of semiconductor chips, and is used for reducing the risk of leakage. The preparation method comprises the following steps: providing a substrate; the substrate comprises a first sub-substrate and a second sub-substrate connected to each other, and the thickness of the first sub-substrate is smaller than the thickness of the second sub-substrate. At least the first side of the first sub-substrate is processed, and a first sub-medium layer is generated on the first side of the first sub-substrate. A sacrificial layer is formed on the side of the first sub-medium layer away from the substrate; the sacrificial layer comprises a first sub-sacrificial part and a second sub-sacrificial part. A laminated structure is formed on the side of the sacrificial layer away from the substrate. A channel hole is formed through the laminated structure and extends into at least the second sub-sacrificial part. The second sub-sacrificial part is processed, so that the aperture of the part of the channel hole surrounded by the second sub-sacrificial part is reduced, and the thickness of the second sub-sacrificial part is increased. The preparation method of the three-dimensional memory is used for preparing the three-dimensional memory to realize the reading and writing operations of data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a method for fabricating a three-dimensional memory. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate. Summary of the Invention

[0003] The embodiments of this disclosure provide a method for fabricating a three-dimensional memory, which reduces the difficulty and cost of fabricating a three-dimensional memory and reduces the risk of leakage.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a method for fabricating a three-dimensional memory is provided. The method includes: providing a substrate; the substrate comprising a first sub-substrate and a second sub-substrate connected to each other, the thickness of the first sub-substrate being less than the thickness of the second sub-substrate; processing at least a first side surface of the first sub-substrate to form a first sub-dielectric layer on the first side surface of the first sub-substrate; forming a sacrificial layer on a side of the first sub-dielectric layer away from the substrate; the sacrificial layer comprising a first sub-sacrificial portion and a second sub-sacrificial portion, the first sub-sacrificial portion covering at least a portion of the first sub-substrate, and the second sub-sacrificial portion covering at least a portion of the second sub-substrate; forming a stacked structure on the side of the sacrificial layer away from the substrate; forming a channel hole penetrating the stacked structure and extending at least into the second sub-sacrificial portion; processing the second sub-sacrificial portion such that the aperture of the portion of the channel hole surrounded by the second sub-sacrificial portion is reduced, and the thickness of the second sub-sacrificial portion is increased.

[0006] Therefore, the three-dimensional memory fabrication method provided in some embodiments of this disclosure, by dividing the substrate, processing the first sub-substrate before forming the sacrificial layer, generating a first sub-dielectric layer on the first side of the first sub-substrate, increasing the distance between the surface of the first sub-sacrificial portion away from the first sub-substrate and the first side of the first sub-substrate, and after forming the stacked structure and the channel hole that penetrates the stacked structure and extends at least into the second sub-sacrificial portion, processing the second sub-sacrificial portion covering the second sub-substrate, causing the volume of the second sub-sacrificial portion to expand, not only reduces the aperture of the portion of the channel hole surrounded by the second sub-sacrificial portion, but also increases the thickness of the second sub-sacrificial portion. This allows the reduced aperture of the channel hole to limit the position of the channel layer in the subsequently formed channel structure, making the extension positions of the channel layers in different channel structures consistent or substantially consistent, reducing the influence of the channel hole depth on the extension position of the channel layer, thereby reducing the control over the channel hole slotting variation, reducing the fabrication process difficulty of the three-dimensional memory, and reducing the fabrication cost. Furthermore, the first sub-dielectric layer can be used to balance the volume expansion of the second sub-sacrificial portion. The first sub-dielectric layer can also reduce or even eliminate the impact of the increased thickness of the second sub-sacrificial portion. This results in a smaller or virtually no difference in the spacing between the side surface of the first sub-sacrificial portion away from the first sub-substrate and the first side surface of the first sub-substrate, and between the side surface of the second sub-sacrificial portion away from the second sub-substrate and the first side surface of the second sub-substrate. In other words, the spacing between the side surface of the sacrificial layer away from the substrate and the first side surface of the substrate is more uniform. Consequently, during the subsequent removal of the sacrificial layer and the storage functional layer of the channel structure from the bottom of the three-dimensional memory, the gate layer can be avoided from being exposed, reducing the risk of leakage due to short circuit between the gate layer and the gate line isolation structure through the source layer.

[0007] In some embodiments, processing at least a first side surface of the first sub-substrate to form a first sub-dielectric layer on the first side surface of the first sub-substrate includes: processing the first side surface of the first sub-substrate and the first side surface of the second sub-substrate, forming a first sub-dielectric layer on the first side surface of the first sub-substrate, and forming a second sub-dielectric layer on the first side surface of the second sub-substrate. The thickness of the first sub-dielectric layer is greater than the thickness of the second sub-dielectric layer.

[0008] In some embodiments, the difference between the thickness of the first sub-dielectric layer and the thickness of the second sub-dielectric layer is the same as the change in thickness of the second sub-sacrificial portion.

[0009] In some embodiments, processing the first side of the first sub-substrate and the first side surface of the second sub-substrate includes: simultaneously oxidizing the first side surface of the first sub-substrate and the first side surface of the second sub-substrate using a wet oxidation process. The oxidation rate of the first side surface of the first sub-substrate is greater than the oxidation rate of the first side surface of the second sub-substrate.

[0010] In some embodiments, the surface of the first sub-dielectric layer away from the substrate is flush with the surface of the second sub-dielectric layer away from the substrate.

[0011] In some embodiments, the processing of the second sub-sacrificial part includes: oxidizing the second sub-sacrificial part using a wet oxidation process.

[0012] In some embodiments, the difference between the thickness of the second sub-substrate and the thickness of the first sub-substrate is the same as the change in thickness of the second sub-sacrificial portion.

[0013] In some embodiments, providing a substrate includes: providing a substrate; thinning a portion of the substrate from a first side surface of the substrate; and doping the thinned portion of the substrate to obtain the substrate. The doped thinned portion of the substrate constitutes a first sub-substrate, and the unthinned portion of the substrate constitutes a second sub-substrate.

[0014] In some embodiments, after the step of processing the second sub-sacrificial portion, the fabrication method further includes: forming a storage functional layer within the channel hole; the storage functional layer filling the portion of the channel hole surrounded by the second sub-sacrificial portion. A channel layer is formed inside the storage functional layer; the channel layer is located on the side of the second sub-sacrificial portion away from the substrate.

[0015] In some embodiments, prior to the step of forming the stacked structure, the fabrication method further includes: forming a stop layer on the side of the sacrificial layer away from the substrate. After the step of forming the channel layer, the fabrication method further includes: removing the substrate, the first sub-dielectric layer, and the sacrificial layer up to the stop layer, and removing at least a portion of the storage functional layer extending into the second sub-sacrificial portion to expose the end of the channel layer; forming a source layer on the side of the stop layer away from the stacked structure, the source layer forming an electrical contact with the exposed end of the channel layer.

[0016] In some embodiments, prior to the steps of removing the substrate, the first sub-dielectric layer, and the sacrificial layer to the stop layer, and removing at least a portion of the storage functional layer extending into the second sub-sacrificial portion, the fabrication method further includes: forming a gate wire gap penetrating the stacked structure and extending at least into the sacrificial layer; and forming a gate wire isolation structure within the gate wire gap. During the process of removing the substrate, the first sub-dielectric layer, and the sacrificial layer to the stop layer, and removing at least a portion of the storage functional layer extending into the second sub-sacrificial portion, the portion of the gate wire isolation structure extending at least into the sacrificial layer is also removed. The source layer also forms an electrical contact with the exposed portion of the gate wire isolation structure.

[0017] In some embodiments, prior to the steps of removing the substrate, the first sub-dielectric layer, and the sacrificial layer to the stop layer, and removing at least a portion of the storage functional layer extending into the second sub-sacrificial portion, the fabrication method further includes: forming a virtual channel structure that penetrates the stacked structure and extends at least into the sacrificial layer. During the removal of the substrate, the first sub-dielectric layer, and the sacrificial layer to the stop layer, the portion of the virtual channel structure extending at least into the sacrificial layer is also removed. The source layer also covers the exposed portion of the virtual channel structure.

[0018] In some embodiments, prior to the steps of removing the substrate, the first sub-dielectric layer, and the sacrificial layer, the fabrication method further includes: providing peripheral devices; and electrically connecting the peripheral devices to a structure on the substrate.

[0019] In some embodiments, after the step of forming a source layer on the side of the stop layer away from the stacked structure, the fabrication method further includes: providing a peripheral device; and electrically connecting the peripheral device to a structure on the source layer. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0021] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to some embodiments;

[0022] Figure 2 for Figure 1 One flowchart of S100 in the flowchart shown;

[0023] Figure 3 This is a flowchart of another method for fabricating a three-dimensional memory according to some embodiments;

[0024] Figures 4a-4o This is a step diagram of a method for fabricating a three-dimensional memory according to some embodiments;

[0025] Figures 5a-5e This is a step diagram of another method for fabricating a three-dimensional memory according to some embodiments. Detailed Implementation

[0026] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0027] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0030] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0031] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0032] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0033] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0034] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0035] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0036] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0037] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0038] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0039] The term "three-dimensional memory" refers to a semiconductor device formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0040] In one implementation, in order to control the variation of the channel hole gouging and avoid damage to the channel structure in subsequent processes, the depth of different channel holes needs to be basically the same. This ensures that different channel holes can remain on the same film layer during the formation of the channel holes. This can easily increase the difficulty of the fabrication process of the three-dimensional memory and increase the fabrication cost.

[0041] Based on this, this disclosure provides a method for fabricating a three-dimensional memory. Among other things, Figures 1-3 A flowchart illustrating a method for fabricating a three-dimensional memory according to some embodiments of this disclosure; Figures 4a-4o and Figures 5a-5e These are cross-sectional structural diagrams corresponding to each step in the fabrication method of the three-dimensional memory according to some embodiments. It should be understood that... Figures 1-3 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps may be performed simultaneously, or they may be performed in a sequence different from the steps described. Figures 1-3 The execution is performed in the order shown.

[0042] The following description, in conjunction with the accompanying drawings, illustrates some embodiments of the three-dimensional memory fabrication method provided in this disclosure.

[0043] like Figure 1 As shown, the above-mentioned method for fabricating a three-dimensional memory includes steps S100 to S600.

[0044] S100, such as Figure 4c As shown, a substrate 1 is provided. The substrate 1 includes a first sub-substrate 11 and a second sub-substrate 12 connected to each other. The thickness of the first sub-substrate 11 is less than the thickness of the second sub-substrate 12.

[0045] For example, the substrate 1 described above is a wafer substrate, which can provide support for subsequent semiconductor fabrication process steps. For example, the material of the substrate 1 can be single-crystal silicon, polycrystalline silicon, single-crystal germanium, silicon-germanium, or silicon carbide, etc.; it can also be silicon-on-insulator or germanium-on-insulator, etc.; or it can be other materials, such as gallium arsenide or other group III-V compounds.

[0046] It is understood that the aforementioned wafer substrate may include multiple independent chip regions and grid-like dicing regions. On the aforementioned wafer substrate, after multiple semiconductor fabrication process steps, it can be diced through the dicing regions to obtain multiple three-dimensional memory chips located in the aforementioned multiple chip regions.

[0047] For example, a three-dimensional memory may have a storage region (or core region) and other regions besides the storage region (e.g., stepped regions). The storage region contains a channel structure 6, and the other regions contain structures such as drain select gate contacts, source select gate contacts, source contacts, and word line contacts. The channel structure 6 is described below and will not be repeated here.

[0048] Here, the division of the first sub-substrate 11 and the second sub-substrate 12 in substrate 1 can be determined, for example, based on the position of the channel structure 6 in the subsequently formed three-dimensional memory. For example, the second sub-substrate 12 can be located within the memory region of each chip area and positioned opposite to the channel structure 6; the first sub-substrate 11 can be located in other regions besides the memory region. Optionally, the first sub-substrate 11 can be located in the step region and the dicing region.

[0049] For example, the orthographic projection shape of the first sub-substrate 11 onto the plane of substrate 1 is complementary to the orthographic projection shape of the second sub-substrate 12 onto the plane of substrate 1.

[0050] For example, in the wafer substrate, since the second sub-substrate 12 is located within the storage region and the first sub-substrate 11 is located in a region other than the storage region, the orthographic projection shape of the second sub-substrate 12 onto the plane of substrate 1 can be block-shaped, and there can be multiple second sub-substrates 12, which are independently arranged. The orthographic projection shape of the first sub-substrate 11 onto the plane of substrate 1 can be grid-shaped, and there can be one of them. The first sub-substrate 11, for example, has multiple meshes. Each second sub-substrate 12 can be located within one mesh and connected to the first sub-substrate 11, forming an integral structure with the first sub-substrate 11.

[0051] For example, such as Figure 4c As shown, the direction perpendicular to the plane containing substrate 1 is direction Z. The thickness L1 of the first sub-substrate 11 refers to the dimension of the first sub-substrate 11 in direction Z. The thickness L2 of the second sub-substrate 12 refers to the dimension of the second sub-substrate 12 in direction Z. Where L1 < L2. The difference between L1 and L2 is ΔL. a The size can be determined according to actual needs.

[0052] It is understood that substrate 1 has a first side and a second side facing away from each other. The first side refers to the surface that contacts the film layer formed in subsequent semiconductor fabrication steps. The second side contacts the stage of the equipment used in the semiconductor process and is a flat surface. Because the first sub-substrate 11 and the second sub-substrate 12 have different thicknesses, with the second side of substrate 1 as a reference, the first side of the first sub-substrate 11 will be lower than the first side of the second sub-substrate 12, making the first side of substrate 1 an uneven surface, with an overall stepped shape.

[0053] For example, according to the position shown in the attached figure, the first side surface of substrate 1 can be the upper surface of substrate 1.

[0054] S200, such as Figure 4d-1 and Figure 4d-2 As shown, at least the first side surface of the first sub-substrate 11 is processed to generate a first sub-dielectric layer 21 on the first side surface of the first sub-substrate 11.

[0055] For example, during the processing of the first side surface of the first sub-substrate 11, some elements of the first sub-substrate 11 react and grow to form a new material on the first side surface of the first sub-substrate 11. This new material is generally in the form of a thin film. Some examples of this disclosure will generate a new material on the first side surface of the first sub-substrate 11, referred to as a first sub-dielectric layer 21.

[0056] For example, the first sub-dielectric layer 21 covers the first sub-substrate 11.

[0057] For example, the thickness of the first sub-dielectric layer 21 is L3.

[0058] For example, the term "at least" means that this disclosure may process only the first side surface of the first sub-substrate 11 in the substrate 1 (e.g., Figure 4d-2 As shown), the first side surface of the substrate 1, excluding the first sub-substrate 11, can also be processed simultaneously (e.g., Figure 4d-1 (As shown). For details on the processing of substrate 1, please refer to the description below, which will not be repeated here.

[0059] S300, such as Figure 4e As shown, a sacrificial layer 3 is formed on the side of the first sub-dielectric layer 21 away from the substrate 1. The sacrificial layer 3 includes a first sub-sacrificial portion 31 and a second sub-sacrificial portion 32, the first sub-sacrificial portion 31 covering at least a portion of the first sub-substrate 11 and the second sub-sacrificial portion 32 covering at least a portion of the second sub-substrate 12.

[0060] For example, a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, can be used to form a sacrificial layer 3 on the side of the first sub-dielectric layer 21 away from the substrate 1.

[0061] For example, the material of sacrificial layer 3 may include doped polycrystalline silicon. Dopant ions may include, but are not limited to, phosphorus ions, boron ions, etc.

[0062] For example, the thickness of the sacrificial layer 3 is relatively uniform at different locations. That is, the thickness of the first sub-sacrificial portion 31 and the thickness of the second sub-sacrificial portion 32 are, for example, the same.

[0063] For example, the first sub-sacrificial portion 31 may cover the first sub-substrate 11 and has the same or similar shape as the first sub-substrate 11. The second sub-sacrificial portion 32 may cover the second sub-substrate 12 and has the same or similar shape as the second sub-substrate 12. The first sub-sacrificial portion 31 and the second sub-sacrificial portion 32 may be connected to each other to form an integral structure.

[0064] For example, after forming the sacrificial layer 3, a positioning mark groove can be formed in the first sub-sacrificial portion 31. The projection of the positioning mark groove on the substrate 1 can be rectangular, cross-shaped, or circular, etc. For example, the positioning mark groove can be located in the dicing area.

[0065] S400, such as Figure 4e As shown, a stacked structure 4 is formed on the side of the sacrificial layer 3 away from the substrate 1.

[0066] For example, a stacked structure 4 can be formed on the side of the sacrificial layer 3 away from the substrate 1 using a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0067] For example, such as Figure 4e As shown, the aforementioned stacked structure 4 includes a plurality of film layers stacked sequentially along the Z direction. These plurality of film layers include, for example, a plurality of gate dielectric layers 41 and a plurality of gate sacrificial layers 42 stacked alternately.

[0068] In the aforementioned stacked structure 4, the thickness of each gate dielectric layer 41 can be the same or different, and the thickness of each gate sacrificial layer 42 can be the same or different, depending on actual needs. Furthermore, in the manufacturing process of the stacked structure 4, different numbers of stacked layers correspond to different stacking heights. For example, the stacked structure 4 can have 32, 64, or 128 layers. The more layers the stacked structure 4 has, the higher the integration density, and the more memory cells it forms. The number of stacked layers and the stacking height of the stacked structure 4 can be designed according to actual storage requirements; this application does not impose any restrictions on this.

[0069] For example, the gate dielectric layer 41 and the gate sacrificial layer 42 can have different etching selectivity ratios. This allows for the retention of the gate dielectric layer 41 and the removal of the gate sacrificial layer 42 in subsequent processes, forming a sacrificial gap between any two adjacent gate dielectric layers 41. This gap facilitates the subsequent filling of conductive material to form the gate layer 43 (i.e., the word line). Figure 4j As shown, after replacing the gate sacrificial layer 42 with the gate layer 43, the alternating stacked gate dielectric layers 41 and gate layers 43 can be referred to as the memory stack structure 4a.

[0070] Optionally, the material of the gate dielectric layer 41 may include silicon oxide, and the material of the gate sacrificial layer 42 may include silicon nitride.

[0071] For example, the edges of the stacked structure 4 described above are stepped. The edge structure of the stacked structure 4 can be formed, for example, by performing multiple trim-etch cycles on the multiple gate dielectric layers 41 and multiple gate sacrificial layers 42 of the stacked structure 4.

[0072] For example, an insulating capping layer can be provided at the edge of the stacked structure 4. This insulating capping layer can cover the stepped edge of the stacked structure 4. The material of the insulating capping layer can be a dielectric material. Further, the material of the insulating capping layer can be the same as the material of the gate dielectric layer 41, for example, the material of the insulating capping layer is silicon oxide.

[0073] S500, such as Figure 4f As shown, a channel hole 5 is formed that penetrates the above-mentioned stacked structure 4 and extends at least into the second sub-sacrificial part 32.

[0074] For example, the plurality of channel holes 5 can be formed using a dry etching process or a wet etching process. The channel holes 5 can extend in the direction Z toward the substrate 1.

[0075] For example, the orthographic projection of the aforementioned channel hole 5 onto the substrate 1 is located in the region where the second sub-substrate 12 is situated. Each second sub-substrate 12 may be disposed opposite to a plurality of channel holes 5.

[0076] The extension positions of the aforementioned multiple channel holes 5 may be the same or different, depending on the actual semiconductor fabrication process, and this disclosure does not limit this.

[0077] For example, the aforementioned plurality of channel holes 5 extend at the same position. Optionally, the aforementioned plurality of channel holes 5 may all extend into the second sub-sacrificial portion 32; or, the aforementioned plurality of channel holes 5 may all extend into the second sub-substrate 12; or, the aforementioned plurality of channel holes 5 may all extend into the film layer between the second sub-substrate 12 and the second sub-sacrificial portion 32.

[0078] For example, the extension positions of the above-mentioned multiple channel holes 5 are different. Optionally, among the above-mentioned multiple channel holes 5, some channel holes 5 can extend into the second sub-sacrificial portion 32, some channel holes 5 can extend into the second sub-substrate 12, and some channel holes 5 can extend into the film layer between the second sub-substrate 12 and the second sub-sacrificial portion 32.

[0079] S600, such as Figure 4g As shown, the second sub-sacrificial portion 32 is processed such that the aperture of the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32 is reduced, and the thickness of the second sub-sacrificial portion 32 is increased.

[0080] It should be noted that there are multiple ways to process the second sub-sacrifice unit 32 mentioned above, and the settings can be selected according to actual needs.

[0081] In some examples, in the above S600, the second sub-sacrificial part 32 is processed, including: oxidizing the second sub-sacrificial part 32 using a wet oxidation process.

[0082] For example, the present disclosure can process the second sub-sacrificial portion 32 through the channel hole 5. In this way, during the processing of the second sub-sacrificial portion 32, the material used in the wet oxidation process can come into contact with the second sub-sacrificial portion 32 through the channel hole 5 and undergo an oxidation reaction with the second sub-sacrificial portion 32 to generate an oxide. The volume and thickness of the oxide are greater than the volume and thickness of the second sub-sacrificial portion 32 before the oxidation reaction.

[0083] Understandably, since the channel hole 5 is positioned opposite to the second sub-sacrificial portion 32, the oxidation of the first sub-sacrificial portion 31 can be avoided during the oxidation process of the second sub-sacrificial portion 32 through the channel hole 5, thereby preventing changes in the volume and thickness of the first sub-sacrificial portion 31. That is, the volume and thickness of the processed second sub-sacrificial portion 32 are greater than the volume and thickness of the first sub-sacrificial portion 31.

[0084] For example, after processing the second sub-sacrificial portion 32, the second sub-sacrificial portion 32 as a whole will grow in different directions, causing the volume of the second sub-sacrificial portion 32 to expand. For example, the second sub-sacrificial portion 32 may expand in the direction pointing towards the plane where the second sub-substrate 12 is located, in the direction away from the plane where the second sub-substrate 12 is located, or in the direction parallel to the plane where the second sub-substrate 12 is located.

[0085] It is understandable that the presence of the support stage of the equipment used in semiconductor processes will affect the overall morphology of the sacrificial layer 3. For example, during the processing of the second sub-sacrificial portion 32, the second sub-sacrificial portion 32 will mainly grow and expand in a direction away from the plane of the second sub-substrate 12 and in a direction parallel to the plane of the second sub-substrate 12. When the second sub-sacrificial portion 32 grows and expands in a direction away from the plane of the second sub-substrate 12, the thickness of the second sub-sacrificial portion 32 will increase; when the second sub-sacrificial portion 32 grows and expands in a direction parallel to the plane of the second sub-substrate 12, the grown and expanded portion will extend into the channel hole 5, causing the aperture of the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32 to shrink.

[0086] In addition, after the second sub-sacrificial portion 32 grows and expands in a direction away from the plane where the second sub-substrate 12 is located, the second sub-sacrificial portion 32 will compress the stacked structure 4, so that the portion of the stacked structure 4 covering the second sub-sacrificial portion 32 will be slightly higher than the portion of the stacked structure 4 covering the first sub-sacrificial portion 31.

[0087] For example, such as Figure 4f As shown, before processing the second sub-sacrificial part 32, the diameter of the portion of the channel hole 5 surrounded by the second sub-sacrificial part 32 is D1. Figure 4g As shown, after processing the second sub-sacrificial part 32, the diameter of the portion of the channel hole 5 surrounded by the second sub-sacrificial part 32 is D2. The change in diameter of the portion of the channel hole 5 surrounded by the second sub-sacrificial part 32 is ΔD, where ΔD = D2 - D1, and ΔD is less than zero.

[0088] When the volume expansion of the second sub-sacrificial portion 32 is small, the aperture D2 is greater than zero. When the volume expansion of the second sub-sacrificial portion 32 is large, the aperture D2 is close to zero, or even equal to zero.

[0089] It is understandable that the aperture D2 ensures that the subsequently formed channel layer 62 is located on the side of the sacrificial layer 3 away from the substrate 1. In other words, regardless of whether the depth of the channel holes 5 formed in S500 is consistent, after processing the second sub-sacrificial portion 32 and reducing the aperture of the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32, the extension positions of the channel layers 62 of the subsequently formed different channel structures 6 are consistent or substantially consistent, all located on the side of the sacrificial layer 3 away from the substrate 1. Thus, during the subsequent complete removal of the sacrificial layer 3 from the bottom of the three-dimensional memory and the removal of the storage functional layer 61 of the channel structure 6 to expose the channel layer 62, the substrate 1, the first sub-dielectric layer 21, the sacrificial layer 3, and at least the portion of the storage functional layer 61 extending into the sacrificial layer 3 can be removed simultaneously, without needing to remove the substrate 1 first and then the portion of the storage functional layer 61 extending into the substrate 1.

[0090] This disclosure reduces the control over the groove variation of the channel hole 5, which not only helps to increase the etching process window of the channel structure 6, but also helps to reduce the difficulty of fabrication process of three-dimensional memory and reduce fabrication cost.

[0091] For example, such as Figure 4f As shown, before processing the second sub-sacrificial portion 32, the thickness of both the first sub-sacrificial portion 31 and the second sub-sacrificial portion 32 is L4; Figure 4g As shown, after processing the second sub-sacrificial part 32, the thickness of the second sub-sacrificial part 32 is L5. The thickness change of the second sub-sacrificial part 32 is ΔL. b , where △L b =L5-L4, and △L b Greater than zero.

[0092] It should be noted that the thickness change of the second sacrificial part 32 is ΔL. b The value is in the nanometer range, that is, △L b The value is very small. This disclosure is for clarity, in Figure 4g The thickness of each film layer and the thickness variation of the second sub-sacrificial portion 32 are magnified in the diagram. Furthermore, in actual products, not all film layers included in the stacked structure 4 deform with the thickness variation of the second sub-sacrificial portion 32; for example, film layers farther from the second sub-sacrificial portion 32 have a smoother morphology. This disclosure does not limit the structural changes of the three-dimensional memory caused by the thickness variation of the second sub-sacrificial portion 32.

[0093] After processing the second sub-sacrificial portion 32 and increasing its thickness, the distance between the side surface of the second sub-sacrificial portion 32 closest to the second sub-substrate 12 and the first side surface of the second sub-substrate 12 remains essentially unchanged, while the distance between the side surface of the second sub-sacrificial portion 32 furthest from the second sub-substrate 12 and the first side surface of the second sub-substrate 12 increases.

[0094] For example, before forming the first sub-dielectric layer 21, the distance between the surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11 is the thickness L4 of the first sub-sacrificial portion 31, where L4 < L5. After forming the first sub-dielectric layer 21 on the first sub-substrate 11, the distance between the surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11 is the sum of the thickness L4 of the first sub-sacrificial portion 31 and the thickness L3 of the first sub-dielectric layer 21, that is, L4 + L3, where L4 < L4 + L3.

[0095] In other words, after the first sub-dielectric layer 21 is formed on the first sub-substrate 11, the present disclosure can increase the distance between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and reduce the difference between the distance between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the distance between the side surface of the second sub-sacrificial portion 32 away from the second sub-substrate 12 and the first side surface of the second sub-substrate 12.

[0096] It is understandable that, in the subsequent process of completely removing the substrate 1, the first sub-dielectric layer 21, and the sacrificial layer 3 from the bottom of the three-dimensional memory (i.e., the side of the substrate 1 away from the stacked structure 4), and removing the storage functional layer 61 of the channel structure 6 to expose the channel layer 62 of the channel structure 6, the substrate 1 can be completely removed first, followed by the removal of the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61. The semiconductor fabrication process used to remove the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61 can be performed with equal amounts of removal in the Z direction.

[0097] Because the first sub-dielectric layer 21 is pre-formed on the first sub-substrate 11 in this disclosure, the distance between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the distance between the side surface of the second sub-sacrificial portion 32 away from the second sub-substrate 12 and the first side surface of the second sub-substrate 12, are small or essentially negligible. Thus, during the process of removing the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61 in equal quantities, the first sub-sacrificial portion 31 and the second sub-sacrificial portion 32 can be completely removed simultaneously or substantially simultaneously, ensuring that the bottom surface of the three-dimensional memory is not flush with the gate layer 43. There is a gap between the same positions, and the difference in gap between different positions of the gate layer 43 is small. This avoids the situation where the first sub-sacrifice portion 31 is completely removed, but the second sub-sacrifice portion 32 and the storage function layer 61 extending into the second sub-sacrifice portion 32 are not completely removed. This also avoids the situation where the gate layer 43 covering part of the first sub-substrate 11 is exposed due to the complete removal of the second sub-sacrifice portion 32 and the storage function layer 61 extending into the second sub-sacrifice portion 32. This also avoids the leakage phenomenon caused by the gate layer 43 and the gate line isolation structure 9 being shorted through the source layer 8 after the gate line isolation structure 9 and the source layer 8 are fabricated.

[0098] Therefore, the method for fabricating a three-dimensional memory provided by some embodiments of this disclosure divides the substrate 1, processes the first sub-substrate 11 before forming the sacrificial layer 3, generates a first sub-dielectric layer on the first side of the first sub-substrate 11, increases the spacing between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11 in advance, and processes the second sub-sacrificial portion 32 covering the second sub-substrate 12 after forming the stacked structure 4 and forming the channel hole 5 that penetrates the stacked structure 4 and extends at least into the second sub-sacrificial portion 32, thereby expanding the volume of the second sub-sacrificial portion 32. This not only reduces the aperture of the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32, but also increases the thickness of the second sub-sacrificial portion 32. This allows the reduced aperture of the channel hole 5 to restrict the position of the channel layer 62 of the subsequently formed channel structure 6, making the extension positions of the channel layer 62 of different channel structures 6 consistent or basically consistent. This reduces the influence of the depth of the channel hole 5 on the extension position of the channel layer 62, thereby reducing the control over the slotting variation of the channel hole 5, reducing the difficulty of the fabrication process of the three-dimensional memory, and reducing the fabrication cost. Furthermore, the first sub-dielectric layer 21 can be used to balance the volume expansion of the second sub-sacrificial portion 32. The first sub-dielectric layer 21 can also reduce or even eliminate the effect of the increased thickness of the second sub-sacrificial portion 32. This makes the gap between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the gap between the side surface of the second sub-sacrificial portion 32 away from the second sub-substrate 12 and the first side surface of the second sub-substrate 12, smaller or even negligible. In other words, the gap between the side surface of the sacrificial layer 3 away from the substrate 1 and the first side surface of the substrate 1 is more uniform. As a result, during the subsequent removal of the sacrificial layer 3 and the storage function layer 61 of the channel structure 6 from the bottom of the three-dimensional memory, the gate layer 33 can be avoided from being exposed, reducing the risk of leakage due to the short circuit between the gate layer 33 and the gate line isolation structure 9 through the source layer 8.

[0099] In the above S200, at least the first side surface of the first sub-substrate 11 is processed, including a variety of processing methods, which can be selected according to actual needs.

[0100] In some embodiments, such as Figure 4d-2 As shown, only the first side surface of the first sub-substrate 11 is processed. At this time, the first sub-dielectric layer 21 is generated only on the first side surface of the first sub-substrate 11.

[0101] For example, such as Figure 4d-2 As shown, after processing the first side surface of the first sub-substrate 11, the thickness of the first sub-dielectric layer 21 is the same as the thickness change of the second sub-sacrificial portion 32. That is, L3 = ΔL b =L5-L4, correspondingly, L3+L4=L5.

[0102] This means that the formation of the first sub-dielectric layer 21 can offset the effect of the increased thickness of the second sub-sacrificial portion 32, making the distance between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the distance between the side surface of the second sub-sacrificial portion 32 away from the second sub-substrate 12 and the first side surface of the second sub-substrate 12, the same. In this way, during the process of removing the first sub-dielectric layer 21, the sacrificial layer 3, and the storage function layer 61 in equal amounts, the first sub-sacrificial portion 31 and the second sub-sacrificial portion 32 can be completely removed simultaneously, avoiding exposure of the gate layer 43. This can prevent leakage caused by the gate layer 43 and the gate line isolation structure 9 being short-circuited through the source layer 8 after the subsequent fabrication of the gate line isolation structure 9 and the source layer 8.

[0103] For example, such as Figure 4d-2 As shown, the surface of the first sub-dielectric layer 21 away from the first sub-substrate 11 is flush with the first side surface of the second sub-substrate 12.

[0104] Understandably, the stacked structure 4 has a large number of layers. By aligning the surface of the first sub-dielectric layer 21 away from the first sub-substrate 11 with the first side surface of the second sub-substrate 12, this disclosure ensures that the morphology of the subsequently formed sacrificial layer 3 is relatively flat, and that the morphology of each film layer in the subsequently formed stacked structure 4 is relatively flat. This ensures that the three-dimensional memory can be fabricated normally and avoids affecting the electrical performance of the fabricated three-dimensional memory.

[0105] In this example, before S300, that is, before forming the sacrificial layer 3, the above-described fabrication method further includes, for example, forming a dielectric layer on the side of the first sub-dielectric layer 21 away from the substrate 1 and on the first side of the second sub-substrate 12. This dielectric layer is located between the first sub-dielectric layer 21 and the sacrificial layer 3, and between the second sub-substrate 12 and the sacrificial layer 3, so as to separate the second sub-substrate 12 and the sacrificial layer 3.

[0106] For example, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to form the dielectric layer.

[0107] For example, the material of the dielectric layer described above may include oxides, such as silicon oxide.

[0108] In other embodiments, such as Figure 4d-1As shown, at least the first side surface of the first sub-substrate 11 is processed to form a first sub-dielectric layer 21 on the first side surface of the first sub-substrate 11, including: processing the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12, forming the first sub-dielectric layer 21 on the first side surface of the first sub-substrate 11, and forming a second sub-dielectric layer 22 on the first side surface of the second sub-substrate 12. The thickness of the first sub-dielectric layer 21 is greater than the thickness of the second sub-dielectric layer 22.

[0109] In other words, in the above S200, the present disclosure can process the entire first side surface of the substrate 1.

[0110] It is understood that the first sub-substrate 11 is in a mesh-like shape. By simultaneously processing the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12, this disclosure avoids protecting the first side surfaces of multiple independent second sub-substrates 12, thereby reducing the difficulty of processing the substrate 1. This helps to reduce the fabrication process difficulty and manufacturing cost of the three-dimensional memory.

[0111] For example, the first sub-dielectric layer 21 and the second sub-dielectric layer 22 can be generated simultaneously, and the first sub-dielectric layer 21 and the second sub-dielectric layer 22 are connected to each other and form an integral structure. For example, the first sub-dielectric layer 21 and the second sub-dielectric layer 22 can constitute dielectric layer 2.

[0112] For example, the elements included in the first sub-substrate 11 and the elements included in the second sub-substrate 12 may be different.

[0113] For example, the substrate 1 is made of polycrystalline silicon, and the first sub-substrate 11 is doped. Accordingly, the elements included in the first sub-substrate 11 include silicon and the elements corresponding to the dopant ions; while the elements included in the second sub-substrate 12 include silicon.

[0114] In this way, during the overall processing of the first side surface of the substrate 1, it can be ensured that the thickness of the second sub-dielectric layer 22 generated on the first side surface of the second sub-substrate 12 is different from the thickness of the first sub-dielectric layer 21 generated on the first side surface of the first sub-substrate 11.

[0115] For example, such as Figure 4d-1 As shown, the thickness of the second sub-dielectric layer 22 is L6. Where L3 is greater than L6. The difference between the thickness L3 of the first sub-dielectric layer 21 and the thickness L6 of the second sub-dielectric layer 22 is ΔL. c , △L c =L3-L6, and △L c Greater than zero.

[0116] By making the thickness L3 of the first sub-dielectric layer 21 greater than the thickness L6 of the second sub-dielectric layer 22, it can be ensured that the difference ΔL between the thickness L3 of the first sub-dielectric layer 21 and the thickness L6 of the second sub-dielectric layer 22 is within a certain range. c It can reduce or even eliminate the thickness change ΔL of the second sub-sacrificial part 32. b The influence of this makes the distance between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the distance between the side surface of the second sub-sacrificial portion 32 away from the substrate 1 and the first side surface of the second sub-substrate 12, small or virtually no difference.

[0117] Furthermore, by processing the first side of the substrate 1 as a whole to form a dielectric layer 2 with an integral structure, the dielectric layer 2 can be used to separate the substrate 1 and the sacrificial layer 3, avoiding the formation of other film layers between the dielectric layer 2 and the sacrificial layer 3. This simplifies the fabrication process of the three-dimensional memory.

[0118] In some examples, the difference ΔL between the thickness L3 of the first sub-dielectric layer 21 and the thickness L6 of the second sub-dielectric layer 22 is... c The thickness change ΔL of the second sub-sacrificial part 32 b They are the same. That is, L3-L6=L5-L4.

[0119] This means that L3+L4=L5+L6. The distance between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the distance between the side surface of the second sub-sacrificial portion 32 away from the substrate 1 and the first side surface of the second sub-substrate 12 are the same.

[0120] This allows us to utilize the difference ΔL between the thickness L3 of the first sub-dielectric layer 21 and the thickness L6 of the second sub-dielectric layer 22. c This offsets the effect of the increased thickness of the second sub-sacrificial portion 32. During the process of removing the first sub-dielectric layer 21, the sacrificial layer 3, and the storage function layer 61 in equal amounts, the first sub-sacrificial portion 31 and the second sub-sacrificial portion 32 can be completely removed simultaneously, avoiding exposure of the gate layer 43. This also avoids leakage phenomena caused by the gate layer 43 and the gate line isolation structure 9 being short-circuited through the source layer 8 after the gate line isolation structure 9 and the source layer 8 are fabricated.

[0121] In some examples, such as Figure 4d-1 As shown, the surface of the first sub-dielectric layer 21 away from the substrate 1 is flush with the surface of the second sub-dielectric layer 22 away from the substrate 1.

[0122] It is understandable that the surface of the first sub-dielectric layer 21 away from the substrate 1 and the surface of the second sub-dielectric layer 22 away from the substrate 1 can be flush with the plane containing the substrate 1. That is, the distance between the surface of the first sub-dielectric layer 21 away from the substrate 1 and the plane containing the substrate 1 is the same as the distance between the surface of the second sub-dielectric layer 22 away from the substrate 1 and the plane containing the substrate 1. The surface of the dielectric layer 2 away from the substrate 1 is a flat plane.

[0123] This ensures that the morphology of each film layer in the subsequently formed stacked structure 4 is flat, and that one side surface of the same film layer is parallel or approximately parallel to the side surface of the dielectric layer 2 away from the substrate 1, ensuring that the three-dimensional memory can be fabricated normally and avoiding affecting the electrical performance of the fabricated three-dimensional memory.

[0124] It should be noted that there are multiple ways to process the first sub-substrate 11 and the second sub-substrate 12, and the appropriate method can be selected according to actual needs.

[0125] In some examples, the processing of the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12 includes: simultaneously oxidizing the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12 using a wet oxidation process. The oxidation rate of the first side surface of the first sub-substrate 11 is greater than the oxidation rate of the first side surface of the second sub-substrate 12.

[0126] For example, during the processing of the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12, the first side surface of the first sub-substrate 11 can undergo an oxidation reaction with the material used in the wet oxidation process to generate a first oxide (i.e., the first sub-dielectric layer 21); the first side surface of the second sub-substrate 12 can also undergo an oxidation reaction with the material used in the wet oxidation process to generate a second oxide (i.e., the second sub-dielectric layer 22). The thickness of the first oxide is greater than the thickness of the second oxide.

[0127] It is understood that since the elements included in the first sub-substrate 11 are different from those included in the second sub-substrate 12, the oxidation rate of the first side surface of the first sub-substrate 11 is different from that of the first side surface of the second sub-substrate 12. By making the oxidation rate of the first side surface of the first sub-substrate 11 greater than that of the first side surface of the second sub-substrate 12, it can be ensured that the thickness of the first sub-dielectric layer 21 formed on the first side surface of the first sub-substrate 11 is greater than the thickness of the second sub-dielectric layer 22 formed on the first side surface of the second sub-substrate 12.

[0128] For example, the oxidation rate of the first side of the first sub-substrate 11 is greater than the oxidation rate of the first side of the second sub-substrate 12, that is, the ratio of the oxidation rate of the first side of the first sub-substrate 11 to the oxidation rate of the first side of the second sub-substrate 12 is greater than 1.

[0129] For example, the ratio of the oxidation rate of the first side surface of the first sub-substrate 11 to the oxidation rate of the first side surface of the second sub-substrate 12 ranges from 1 to 16.

[0130] Optionally, the ratio of the oxidation rate of the first side surface of the first sub-substrate 11 to the oxidation rate of the first side surface of the second sub-substrate 12 can be 1.5:1, 3:1, 5:1, 8.9:1, 12:1 or 16:1, etc.

[0131] Here, the ratio of the oxidation rates of the first sub-substrate 11 and the first side surface of the second sub-substrate 12 can be determined according to actual needs and is not limited to the ratio exemplified above. Anything that can reduce or offset the increased thickness of the second sub-sacrificial portion 32 is acceptable, and this disclosure does not impose any limitations on this.

[0132] In some embodiments, the difference ΔL between the thickness L2 of the second sub-substrate 12 and the thickness L1 of the first sub-substrate 11 is... a The thickness change ΔL of the second sub-sacrificial part 32 b ,same.

[0133] For example, when only the first side surface of the first sub-substrate 11 is processed to form the first sub-dielectric layer 21 on the first side surface of the first sub-substrate 11, the distance between the surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11 can be controlled by simply controlling the thickness of the first sub-dielectric layer 21. This distance, and the difference between this distance and the distance between the surface of the second sub-sacrificial portion 32 away from the second sub-substrate 12 and the first side surface of the second sub-substrate 12, can be controlled. This helps reduce the difficulty of controlling the aforementioned difference, thereby reducing the manufacturing difficulty of the three-dimensional memory.

[0134] For example, the thickness L3 of the first sub-dielectric layer 21 can be equal to the difference ΔL between the thickness L2 of the second sub-substrate 12 and the thickness L1 of the first sub-substrate 11. a .

[0135] Optionally, the difference ΔL between the thickness L2 of the second sub-substrate 12 and the thickness L1 of the first sub-substrate 11 is... a The thickness is 100nm, where the thickness L3 of the first sub-dielectric layer 21 is 100nm.

[0136] At this time, after processing the first side surface of the first sub-substrate 11 to generate the first sub-dielectric layer 21 on the first side surface of the first sub-substrate 11, the surface of the first sub-dielectric layer 21 away from the first sub-substrate 11 is flush with the first side surface of the second sub-substrate 12.

[0137] This not only avoids exposing the gate layer 33 during the subsequent removal of the storage function layer 61 from the bottom of the three-dimensional memory, but also ensures the flatness of each film layer in the subsequently formed stacked structure 4.

[0138] For example, when the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12 are processed simultaneously, and the difference between the thickness of the first sub-dielectric layer 21 and the thickness of the second sub-dielectric layer 22 is the same as the change in thickness of the second sub-sacrificial portion 32, the difference between the thickness of the first sub-dielectric layer 21 and the thickness of the second sub-dielectric layer 22 can be controlled by controlling the ratio of the oxidation rate of the first side surface of the first sub-substrate 11 to the oxidation rate of the first side surface of the second sub-substrate 12. This helps to reduce the difficulty of controlling the difference between the spacing between the side surface of the first sub-sacrificial portion 31 away from the first sub-substrate 11 and the first side surface of the first sub-substrate 11, and the spacing between the side surface of the second sub-sacrificial portion 32 away from the second sub-substrate 12 and the first side surface of the second sub-substrate 12, thereby helping to reduce the process difficulty of three-dimensional memory.

[0139] For example, the difference ΔL between the thickness L2 of the second sub-substrate 12 and the thickness L1 of the first sub-substrate 11 is... a The thickness of the first sub-dielectric layer 21 is 100nm, the thickness of the first sub-dielectric layer 21 is 120nm, and the thickness of the second sub-dielectric layer 22 is 20nm.

[0140] At this time, the surface of the first sub-dielectric layer 21 away from the first sub-substrate 11 and the surface of the second sub-dielectric layer 22 away from the second sub-substrate 12 are flush.

[0141] This not only avoids exposing the gate layer 33 during the subsequent removal of the storage function layer 61 from the bottom of the three-dimensional memory, but also ensures the flatness of each film layer in the subsequently formed stacked structure 4.

[0142] In some embodiments, such as Figure 2 As shown, in the above S100, a substrate 1 is provided, including: S110~S130.

[0143] S110, such as Figure 4a As shown, a substrate 1a is provided.

[0144] For example, the material of substrate 1a is the same as the material of substrate 1 in S100 above.

[0145] For example, the material of substrate 1a can be polycrystalline silicon.

[0146] S120, such as Figure 4a and Figure 4b As shown, a portion of the substrate 1a is thinned from the first side of the substrate 1a.

[0147] For example, the substrate 1a can be divided before thinning a portion of it. The portion that does not require thinning can be located in the storage area mentioned in some of the examples above; the portion that requires thinning can be located in other areas besides the storage area mentioned in some of the examples above.

[0148] For example, this disclosure may employ a photolithography process to thin a portion of the substrate 1a.

[0149] For example, such as Figure 4a and Figure 4b As shown, the process of thinning a portion of substrate 1a can be as follows: a photoresist is coated on the first side of substrate 1a; then the photoresist is exposed and developed to obtain a patterned photoresist PR, which can cover the portion of substrate 1a that does not require thinning; then, using the patterned photoresist PR as a mask, substrate 1a is etched to reduce the thickness of the portion of substrate 1a not covered by the patterned photoresist PR.

[0150] S130, such as Figure 4c As shown, the thinned portion of substrate 1a is doped to obtain substrate 1. The doped thinned portion of substrate 1a constitutes the first sub-substrate 11, and the unthinned portion of substrate 1a constitutes the second sub-substrate 12.

[0151] For example, this disclosure may employ an ion implantation process to perform ion implantation on the thinned portion of the substrate 1a for doping treatment.

[0152] Here, the types of ions implanted in the thinned portion of substrate 1a include a variety, which can be selected and set according to actual needs.

[0153] For example, the ions implanted in the thinned portion of substrate 1a may include phosphorus ions or boron ions, etc.

[0154] It is understandable that during the ion implantation process of the thinned portion of substrate 1a, the ion implantation depth, dopant dosage, etc., can be selected and set according to actual needs, as long as the oxidation rate of the first side of the first sub-substrate 11 is greater than the oxidation rate of the first side of the second sub-substrate 12.

[0155] Optionally, the dopant dosage is positively correlated with the oxidation rate of the first side surface of the first sub-substrate 11. That is, the higher the dopant dosage, the higher the oxidation rate of the first side surface of the first sub-substrate 11; the lower the dopant dosage, the lower the oxidation rate of the first side surface of the first sub-substrate 11. In the same amount of time, the higher the oxidation rate, the greater the thickness of the oxide (e.g., the first sub-dielectric layer 21 or the second sub-dielectric layer 22) generated after oxidation treatment.

[0156] This disclosure allows control of the ratio of the oxidation rate of the first side surface of the first sub-substrate 11 to the oxidation rate of the first side surface of the second sub-substrate 12 by adjusting the dosage of the dopant, thereby controlling the relationship between the thicknesses of the first sub-dielectric layer 21 and the second sub-dielectric layer 22 formed after oxidation treatment. In this way, the difference between the thickness of the first sub-dielectric layer 21 and the second sub-dielectric layer 22 can be used to reduce or offset the effect of the increased thickness of the second sub-sacrificial portion 32.

[0157] It is understandable that in the above S120, the size of the part of the substrate 1a that is thinned can be selected and set according to actual needs, so that the difference between the thickness of the first sub-dielectric layer 21 and the thickness of the second sub-dielectric layer can reduce or even offset the influence of the thickness change of the second sub-sacrificial part 32.

[0158] In some embodiments, such as Figure 3 As shown, after S600, that is, after the step of processing the second sub-sacrificial part 32, the preparation method provided in this disclosure further includes: S700 to S800.

[0159] S700, such as Figure 4h As shown, a storage function layer 61 is formed within the channel hole 5. This storage function layer 61 fills the portion of the channel hole 5 surrounded by the first sub-sacrificial portion 31.

[0160] For example, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially deposit a charge blocking layer 611, a charge trapping layer 612, and a tunneling layer 613 within the channel hole 5. The charge blocking layer 611, charge trapping layer 612, and tunneling layer 613 can constitute a storage functional layer 61. The storage functional layer 61 has gaps to facilitate the subsequent formation of the channel layer 62.

[0161] For example, when the channel hole 5 extends into the second sub-sacrificial portion 32, during the formation of the storage functional layer 61, the material of the storage functional layer 61 can fill the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32 and completely fill the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32.

[0162] When the channel hole 5 extends into the second sub-dielectric layer 22 or the second sub-substrate 12, during the formation of the storage functional layer 61, the material of the storage functional layer 61 can adhere to the inner wall of the channel hole 5, pass through the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32, and fall into the bottom of the channel hole 5 until the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32 is filled. At this time, the portions of the channel hole 5 located on both sides of the second sub-sacrificial portion 32 are no longer connected.

[0163] S800, such as Figure 4h As shown, a channel layer 62 is formed inside the storage functional layer 61. This channel layer 62 is located on the side of the second sub-sacrificial portion 32 away from the substrate 1.

[0164] For example, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to deposit a channel layer 62 inside the storage functional layer 61. The storage functional layer 61 and the channel layer 62 can constitute the channel structure 6.

[0165] For example, during the formation of the trench layer 62, one or more voids can be formed inside the trench layer 62 by controlling the formation process of the trench layer 62 to reduce structural stress.

[0166] Optionally, the charge blocking layer 611 can be made of silicon oxide, the charge trapping layer 612 can be made of silicon nitride, the tunneling layer 613 can be made of silicon oxide, and the channel layer 62 can be made of polysilicon. The charge blocking layer 611, the charge trapping layer 612, the tunneling layer 613, and the channel layer 62 can form a "SONO" structure.

[0167] Understandably, after the storage functional layer 61 fills the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32, the bottoms of different channel layers 62 can all stop at the side of the second sub-sacrificial portion 32 away from the substrate 1. This can improve the uniformity of the position of the bottoms of different channel layers 62 and reduce the control over the slotting variation of the channel hole 5.

[0168] In some embodiments, such as Figure 4e As shown, prior to S400 above, that is, prior to the step of forming the stacked structure 4, the preparation method provided in this disclosure further includes forming a stop layer 7 on the side of the sacrificial layer 3 away from the substrate 1.

[0169] For example, a stop layer 7 can be deposited on the side of the sacrificial layer 3 away from the substrate 1 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0170] Optionally, the material of the stop layer 7 may include polycrystalline silicon.

[0171] For example, an isolation layer may be formed between the sacrificial layer 3 and the stop layer 7 before the stop layer 7 is formed. The material of this isolation layer may include, for example, silicon oxide.

[0172] By setting an isolation layer, the sacrificial layer 3 and the stop layer 7 can be separated to prevent them from coming into direct contact.

[0173] In some examples, after S800 above, that is, after the step of forming the channel layer 62, the preparation method provided in this disclosure further includes: S900 to S1000.

[0174] S900, such as Figures 4l to 4n and Figures 5a-5c As shown, the substrate 1, the first sub-dielectric layer 21, and the sacrificial layer 3 to the stop layer 7 are removed, and at least the portion of the storage function layer 61 extending into the second sub-sacrificial portion 32 is removed, exposing the end of the channel layer 62.

[0175] Optionally, if the first side surface of the first sub-substrate 11 and the first side surface of the second sub-substrate 12 are processed simultaneously, the second sub-dielectric layer 22 will also be removed in step S900 above.

[0176] For example, this disclosure may employ a grinding process (such as chemical mechanical polishing (CMP) or grinding) to grind the substrate 1 in order to remove the substrate 1.

[0177] It is understandable that the polishing process has a high selectivity. Thus, this disclosure allows for the removal of only the substrate 1 during the polishing process, avoiding the polishing removal of the first sub-dielectric layer 21.

[0178] Optionally, when the channel hole 5 extends into the substrate 1, the portion of the storage functional layer 61 extending into the substrate 1 can be polished simultaneously during the polishing process of the substrate 1.

[0179] For example, this disclosure may employ a dry etching process (e.g., a gas etching process) to etch the portions of the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61 extending into the second sub-sacrificial portion 32, in order to remove the portions of the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61 extending into the second sub-sacrificial portion 32.

[0180] Optionally, when an isolation layer is provided in the sacrificial layer 3 and the stop layer 7, during the etching of the portion of the first sub-dielectric layer 21, the sacrificial layer 3, and the portion of the storage function layer 61 extending into the second sub-sacrificial portion 32, the isolation layer and the portion of the storage function layer 61 extending into the isolation layer can be etched simultaneously.

[0181] For example, during the etching process of the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61 extending at least to the second sub-sacrificial portion 32, a suitable gas can be selected based on the materials of the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61. This allows the plasma in the gas to react with the portion of the first sub-dielectric layer 21, the sacrificial layer 3, and the storage functional layer 61 extending to the second sub-sacrificial portion 32, thereby etching away this portion. The plasma in the gas may not react with the channel layer 62, thus preserving and exposing the ends of the channel layer 62.

[0182] For example, the gas etching process described above can remove an equal amount of material in the Z direction.

[0183] This eliminates the need for additional grinding processes to smooth the storage functional layer of the channel structure from the bottom of the 3D memory, thus enhancing process controllability and adjustability.

[0184] Moreover, by using the above-mentioned preparation method, the portion of the channel hole 5 surrounded by the second sub-sacrificial portion 32 is pre-filled with the storage functional layer 61. This can prevent the polishing slurry from seeping into the storage functional layer 61 due to the presence of gaps on the side of the storage functional layer 61 close to the substrate during the removal of the substrate 1 using the polishing process, thus affecting the electrical performance of the three-dimensional memory and improving the yield of the prepared three-dimensional memory.

[0185] S1000, such as Figure 4o and Figure 5d As shown, a source layer 8 is formed on the side of the stop layer 7 away from the stacked structure 4, and the source layer 8 forms an electrical contact with the exposed end of the channel layer 62.

[0186] For example, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to deposit the source layer 8 on the side of the stop layer 7 away from the stacked structure 4.

[0187] There are various ways to form the source layer 8, which can be determined according to the material of the source layer 8.

[0188] For example, the source layer 8 can be made of polycrystalline silicon. In this case, after the source layer 8 is formed by polycrystalline silicon deposition, the source layer 8 can be doped by ion implantation, for example, by ion implantation. After that, the source layer 8 can be annealed by annealing (e.g., laser annealing) to repair the lattice damage to the material caused by the ion implantation process and to activate the implanted dopants.

[0189] For example, the source layer 8 can be made of doped polysilicon. In this case, doped polysilicon can be directly deposited to form the source layer 8.

[0190] For example, such as Figure 4o and Figure 5d As shown, the source layer 8 covers and surrounds the exposed end of the channel layer 62, and contacts the exposed end of the channel layer 62 to form an electrical connection. This allows the source layer 8 and the channel layer 62 to have a large contact area, which is beneficial to increasing the reliability of the contact connection and the performance of the 3D memory.

[0191] Optionally, a first conductive block can be formed at the exposed end of the channel layer 62 before forming the source layer 8. This allows the exposed end of the channel layer 62 to form an electrical contact with the source layer 8 through the first conductive block, which helps increase the reliability of the contact connection and the performance of the 3D memory.

[0192] Understandable Figure 4o and Figure 5d Only some of the film layers of the three-dimensional memory are shown; not all of the film layers are shown. Figure 4o and Figure 5d The illustrated structure does not impose limitations on the actual structure of the three-dimensional memory.

[0193] In some embodiments, prior to S900, that is, before the steps of removing the substrate 1, the first sub-dielectric layer 21, and the sacrificial layer 3 to the stop layer 7, and removing at least the portion of the storage functional layer 61 extending into the second sub-sacrificial portion 32, the above-described preparation method further includes: S810 to S820.

[0194] S810, such as Figure 4i As shown, a gate line gap (GLS) is formed that penetrates the stacked structure 4 and extends at least into the sacrificial layer 3.

[0195] It is understandable that, along the extension direction of the gate line slot (GLS), a portion of the GLS may be located in the storage region, while another portion of the GLS may be located in other regions besides the storage region (e.g., the step region).

[0196] For example, the above-mentioned gate line gap (GLS) can be formed using a dry etching process or a wet etching process.

[0197] Understandably, there can be multiple gate line slots (GLS).

[0198] For example, the gate line gap (GLS) can serve as an etching channel. In this case, the gate sacrificial layer 42 can be removed via the gate line gap (GLS). Here, for example, a wet etching process can be used to remove the gate sacrificial layer 42 in the stacked structure 4 via the gate line gap (GLS) to form multiple sacrificial gaps.

[0199] For example, after forming the sacrificial gap, a gate layer 43 can be formed within the sacrificial gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the gate layer 43 can be at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon, and silicides.

[0200] For example, since the edge of the stacked structure 4 is stepped, after the gate sacrificial layer 42 is replaced with the gate layer 43, the portion of the gate layer 43 located at the edge is stepped, and this portion can be called a stepped structure.

[0201] Optionally, before forming the gate layer 43 within the sacrificial gap, a gate barrier layer can be formed on the inner wall of the gate gap (GLS) and the sacrificial gap using a thin-film deposition process. The material of the gate barrier layer may include, for example, a material with a high dielectric constant, such as aluminum oxide.

[0202] Furthermore, an adhesive layer can be formed on the side surface of the gate barrier layer facing the sacrificial gap using a thin-film deposition process. The material of this adhesive layer may, for example, include tantalum nitride or titanium nitride.

[0203] Alternatively, after forming the gate barrier layer and the adhesive layer, a wet etching process can be used, for example, to remove the portion of the adhesive layer and gate layer 43 located within the gate line gap (GLS).

[0204] S820, such as Figure 4k As shown, a gate line isolation structure 9 is formed within the gate line gap (GLS).

[0205] For example, a first isolation layer 91, a second isolation layer 92, and a support pillar 93 can be sequentially deposited within the gate line gap (GLS) using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The first isolation layer 91, the second isolation layer 92, and the support pillar 93 can constitute the gate line isolation structure 9.

[0206] Optionally, the first isolation layer 91 can be made of silicon oxide, the second isolation layer 92 can be made of silicon oxide, and the support pillar 93 can be made of polycrystalline silicon.

[0207] For example, during the formation of the support column 93, one or more voids can be formed inside the support column 93 by controlling the formation process of the support column 93 to reduce structural stress.

[0208] Alternatively, the above-mentioned gate isolation structure 9 can also be called an array common source.

[0209] Based on this, in some examples, such as Figures 4l to 4n and Figures 5a-5c As shown, in the above S900, during the process of removing the substrate 1, the first sub-dielectric layer 21 and the sacrificial layer 3 to the stop layer 7, and removing at least the portion of the storage function layer 61 extending into the second sub-sacrificial portion 32, the portion of the gate line isolation structure 9 extending into the sacrificial layer 3 is also removed.

[0210] That is, in the above S900, at least the portion of the gate isolation structure 9 extending into the sacrificial layer 3 is also removed along with the removal of the substrate 1, the first sub-dielectric layer 21 and the sacrificial layer 3, exposing the support pillar 93.

[0211] In some examples, such as Figure 4o and Figure 5d As shown, in the above S1000, the source layer 8 also forms an electrical contact with the exposed portion of the gate line isolation structure 9.

[0212] That is, the aforementioned source layer 8 also covers the exposed portion of the gate isolation structure 9 and makes contact with the exposed portion of the gate isolation structure 9 to form an electrical connection. The fact that the source layer 8 surrounds the exposed portion of the gate isolation structure 9 allows for a larger contact area between the source layer 8 and the gate isolation structure 9, which is beneficial for increasing the reliability of the contact connection.

[0213] Here, the exposed portion of the grid isolation structure 9 refers, for example, to the exposed portion of the support column 93.

[0214] Optionally, before forming the source layer 8, a second conductive block can be formed at the end of the exposed portion of the support post 93. This allows the exposed portion of the support post 93 to form an electrical contact with the source layer 8 via the second conductive block, which helps increase the reliability of the contact connection and the performance of the 3D memory.

[0215] In some embodiments, such as Figure 4i As shown, prior to the above S900, that is, before the steps of removing the substrate 1, the first sub-dielectric layer 21 and the sacrificial layer 3 to the stop layer 7, and removing at least the portion of the storage function layer 61 extending into the second sub-sacrificial portion 32, the above preparation method further includes: forming a virtual channel structure DCH that penetrates the stacked structure 4 and extends at least into the sacrificial layer 3.

[0216] In some examples, a dry etching process or a wet etching process can be used to form the virtual channel via, and then a virtual channel structure (DCH) can be formed within the virtual channel via using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the material of the virtual channel structure (DCH) can be silicon oxide.

[0217] For example, the virtual channel structure DCH is used to provide mechanical support, but does not form the storage function layer 61 and the channel layer 62 with storage function.

[0218] In some examples, in the above S900, that is, in the process of removing the substrate 1, the first sub-dielectric layer 21 and the sacrificial layer 3 to the stop layer 7, and removing at least the portion of the storage function layer 61 extending into the second sub-sacrificial portion 32, the portion of the virtual channel structure DCH extending into the sacrificial layer 3 is also removed.

[0219] That is, in the above S900, at least the portion of the virtual channel structure DCH extending into the sacrificial layer 3 is also removed along with the removal of the substrate 1, the first sub-dielectric layer 21, and the sacrificial layer 3. The surface of the virtual channel structure DCH away from the stacked structure 4 can be flush with the surface of the stop layer 7 away from the stacked structure 4.

[0220] In some examples, such as Figure 4o and Figure 5d As shown, in the above S1000, the source layer 8 also covers the portion of the virtual channel structure DCH exposed.

[0221] For example, the source layer 8 can shield the exposed portion of the virtual channel structure DCH and form contact with the exposed portion of the virtual channel structure DCH.

[0222] In some embodiments, the method for fabricating a three-dimensional memory provided in this disclosure further includes: electrically connecting it to a peripheral device 10. The order of the steps for electrically connecting to the peripheral device 10 can be selected according to actual needs, and this disclosure does not limit this.

[0223] In some examples, before S900, that is, before the step of removing the substrate 1, the first sub-dielectric layer 21 and the sacrificial layer 3, the above preparation method further includes: S830~S840.

[0224] S830 provides peripheral devices 10.

[0225] S840, such as Figure 4l As shown, the peripheral device 10 and the structure on the substrate 1 are electrically connected.

[0226] For example, the structure on substrate 1 may refer to the channel structure 6 and the gate line isolation structure 9.

[0227] For example, the “electrical connection” mentioned above can be a bond, such as a connection.

[0228] It is understood that before electrically connecting the peripheral device 10 and the structure on the substrate 1, the structure on the substrate 1 can be flipped and inverted, and then the peripheral device 10 and the structure on the substrate 1 can be electrically connected. In this embodiment, the electrical connection between the peripheral device 10 and the structure on the substrate 1 can be a hybrid bonding method.

[0229] For example, the aforementioned peripheral device 10 may be electrically connected to the gate layer 43, the channel structure 6, and the gate line isolation structure 9.

[0230] The peripheral device 10 is configured to control the structure on the substrate 1. The peripheral device 10 may include any active (or passive) component (e.g., transistor, diode, resistor, capacitor, etc.) of a circuit, such as a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), or a circuit.

[0231] For example, peripheral device 10 may include a plurality of transistors, all or some of which are formed in the carrier substrate (e.g., below the top surface of the carrier substrate) and / or directly on the carrier substrate. Similarly, shallow trench isolation and doped regions (e.g., source and drain regions of transistors) may also be formed in the carrier substrate.

[0232] It should be noted that peripheral device 10 may also include any other circuitry compatible with advanced logic processes. For example, peripheral device 10 includes logic circuitry (e.g., processors and programmable logic devices (PLDs)) and / or memory circuitry (e.g., static random access memory (SRAM)).

[0233] It is understood that the structure of the peripheral device 10 is different from the structure on the substrate 1, and the fabrication methods of the two are independent of each other. This disclosure does not limit the fabrication order of the peripheral device 10 and the structure on the substrate 1.

[0234] In other examples, after S1000, that is, after the step of forming the source layer 8 on the side of the stop layer 7 away from the stacked structure 4, the above preparation method further includes: S1100~S1200.

[0235] S1100 provides peripheral devices 10.

[0236] For example, the peripheral device 10 in this example may have the same structure as the peripheral device 10 in some of the examples above.

[0237] S1200, such as Figure 5e As shown, the peripheral device 10 and the structure on the source layer 8 are electrically connected.

[0238] For example, the structure on the source layer 8 may refer to the channel structure 6 and the gate isolation structure 9.

[0239] For example, the “electrical connection” mentioned above can be a bond, such as a connection.

[0240] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a three-dimensional memory (e.g., a 3D memory) is determined relative to the substrate of the three-dimensional memory in the Z-direction when the substrate is located in the lowest plane of the three-dimensional memory in the Z-direction. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0241] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, The preparation method includes: A substrate is provided; the substrate includes a first sub-substrate and a second sub-substrate connected to each other, the thickness of the first sub-substrate being less than the thickness of the second sub-substrate; At least the first side surface of the first sub-substrate is processed to generate a first sub-dielectric layer on the first side surface of the first sub-substrate; A sacrificial layer is formed on the side of the first sub-dielectric layer away from the substrate; the sacrificial layer includes a first sub-sacrificial portion and a second sub-sacrificial portion, the first sub-sacrificial portion covering at least a portion of the first sub-subsubstrate, and the second sub-sacrificial portion covering at least a portion of the second sub-subsubstrate; A stacked structure is formed on the side of the sacrificial layer away from the substrate; A channel hole is formed that penetrates the stacked structure and extends at least into the second sub-sacrificial portion; The second sub-sacrificial portion is processed such that the diameter of the portion of the channel hole surrounded by the second sub-sacrificial portion is reduced, and the thickness of the second sub-sacrificial portion is increased.

2. The preparation method according to claim 1, characterized in that, The step of processing at least a first side surface of the first sub-substrate to form a first sub-dielectric layer on the first side surface of the first sub-substrate includes: The first side surface of the first sub-substrate and the first side surface of the second sub-substrate are processed to form a first sub-dielectric layer on the first side surface of the first sub-substrate and a second sub-dielectric layer on the first side surface of the second sub-substrate. The thickness of the first sub-dielectric layer is greater than the thickness of the second sub-dielectric layer.

3. The preparation method according to claim 2, characterized in that, The difference between the thickness of the first sub-dielectric layer and the thickness of the second sub-dielectric layer is the same as the change in thickness of the second sub-sacrificial portion.

4. The preparation method according to claim 2, characterized in that, The processing of the first side surface of the first sub-substrate and the first side surface of the second sub-substrate includes: A wet oxidation process is used to simultaneously oxidize the first side surface of the first sub-substrate and the first side surface of the second sub-substrate. The oxidation rate of the first side surface of the first sub-substrate is greater than the oxidation rate of the first side surface of the second sub-substrate.

5. The preparation method according to claim 2, characterized in that, The surface of the first sub-dielectric layer away from the substrate is flush with the surface of the second sub-dielectric layer away from the substrate.

6. The preparation method according to claim 1, characterized in that, The processing of the second sub-sacrificial part includes: The second sub-sacrificial part is oxidized using a wet oxidation process.

7. The preparation method according to claim 1, characterized in that, The difference between the thickness of the second sub-substrate and the thickness of the first sub-substrate is the same as the change in thickness of the second sub-sacrificial portion.

8. The preparation method according to any one of claims 1 to 7, characterized in that, The provision of the substrate includes: Provide a base; A portion of the substrate is thinned from a first side surface of the substrate; The thinned portion of the substrate is doped to obtain the substrate; The doped and thinned portion of the substrate constitutes the first sub-substrate, and the unthinned portion of the substrate constitutes the second sub-substrate.

9. The preparation method according to any one of claims 1 to 7, characterized in that, After the step of processing the second sub-sacrificial part, the preparation method further includes: A storage functional layer is formed within the channel hole; the storage functional layer fills the portion of the channel hole surrounded by the second sub-sacrificial portion; A channel layer is formed inside the storage functional layer; the channel layer is located on the side of the second sub-sacrificial portion away from the substrate.

10. The preparation method according to claim 9, characterized in that, Prior to the step of forming the laminated structure, the preparation method further includes: A stop layer is formed on the side of the sacrificial layer away from the substrate; After the step of forming the channel layer, the preparation method further includes: Remove the substrate, the first sub-dielectric layer, and the sacrificial layer down to the stop layer, and remove at least the portion of the storage functional layer extending into the second sub-sacrificial portion to expose the end of the channel layer; A source layer is formed on the side of the stop layer away from the stacked structure, and the source layer forms an electrical contact with the exposed end of the channel layer.

11. The preparation method according to claim 10, characterized in that, Prior to the steps of removing the substrate, the first sub-dielectric layer, and the sacrificial layer up to the stop layer, and removing at least the portion of the storage functional layer extending into the second sub-sacrificial portion, the fabrication method further includes: A gate line slot is formed that penetrates the stacked structure and extends at least into the sacrificial layer; A grid line isolation structure is formed within the grid line gaps; During the process of removing the substrate, the first sub-dielectric layer, and the sacrificial layer to the stop layer, and removing at least the portion of the storage function layer extending into the second sub-sacrificial portion, the portion of the gate isolation structure extending into the sacrificial layer is also removed. The source layer also forms an electrical contact with the exposed portion of the gate isolation structure.

12. The preparation method according to claim 10, characterized in that, Prior to the steps of removing the substrate, the first sub-dielectric layer, and the sacrificial layer up to the stop layer, and removing at least the portion of the storage functional layer extending into the second sub-sacrificial portion, the fabrication method further includes: A virtual channel structure is formed that penetrates the stacked structure and extends at least into the sacrificial layer; During the process of removing the substrate, the first sub-dielectric layer, and the sacrificial layer to the stop layer, at least a portion of the virtual channel structure extending into the sacrificial layer is also removed. The source layer also covers the exposed portion of the virtual channel structure.

13. The preparation method according to claim 10, characterized in that, Prior to the step of removing the substrate, the first sub-dielectric layer, and the sacrificial layer, the fabrication method further includes: Provide peripheral components; Electrically connect the peripheral device and the structure on the substrate.

14. The preparation method according to claim 10, characterized in that, After the step of forming the source layer on the side of the stop layer away from the stacked structure, the fabrication method further includes: Provide peripheral components; Electrically connect the peripheral devices and the structure on the source layer.

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