Semiconductor structure and method of manufacturing the same
By fabricating contact holes through a two-stage alignment process, the problem of controlling contact hole alignment and size in traditional dry etching processes is solved, thereby reducing contact resistance and improving semiconductor performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-05-30
- Publication Date
- 2026-07-21
AI Technical Summary
Traditional dry etching processes make it difficult to align and control the size of contact holes, resulting in high contact resistance or short circuits, which affects the performance of semiconductor devices.
The contact hole is prepared by a two-stage alignment process. The first through hole and the sacrificial part are formed by photomask patterning. The size and alignment accuracy of the contact hole are controlled by combining dry and wet etching processes.
It improves the alignment accuracy and dimensional control of contact holes, reduces contact resistance, and enhances the electrical performance of semiconductor structures.
Smart Images
Figure CN116631943B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology
[0002] With the continuous development of semiconductor technology, the size of semiconductor devices is constantly shrinking, and the size of conductive structures is also constantly decreasing. The aspect ratio of the contact structures that are electrically connected to the conductive structures is also constantly increasing.
[0003] In related technologies, contact holes that expose conductive structures are etched using a dry etching process (such as plasma etching), and then conductive materials are deposited into the contact holes to form a contact structure, so that the contact structure and the conductive structure can be connected to each other to achieve signal transmission.
[0004] However, traditional dry etching processes have difficulty in aligning and controlling the size of contact holes, resulting in high contact resistance or short circuits, which leads to poor performance or failure of semiconductor devices. Summary of the Invention
[0005] In view of the above problems, this application provides a semiconductor structure and its fabrication method, which can improve the accuracy of the alignment process when fabricating contact holes, facilitate the control of contact hole size, and thus improve the electrical performance of the semiconductor structure.
[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:
[0007] The first aspect of this application provides a method for fabricating a semiconductor structure, including:
[0008] A substrate is provided on which a conductive structure and a first dielectric layer are formed, wherein the first dielectric layer covers the conductive structure and the main surface of the substrate;
[0009] A portion of the first dielectric layer is removed using a photomask pattern to form a first via that exposes the conductive structure.
[0010] A sacrificial layer is formed on the first dielectric layer and in the first via, the sacrificial layer filling the first via and covering the main surface of the first dielectric layer; and a portion of the sacrificial layer is removed using the same photomask pattern, retaining the sacrificial layer in the first via and directly above the first via, the retained sacrificial layer forming a sacrificial portion;
[0011] A second dielectric layer is formed on the first dielectric layer, wherein the main surface of the second dielectric layer is flush with the main surface of the sacrificial portion;
[0012] The sacrificial portion is removed to form a contact hole that exposes the conductive structure, and a contact structure that contacts and connects with the conductive structure is formed in the contact hole.
[0013] As an optional implementation, after forming the contact hole exposing the conductive structure, the method further includes:
[0014] The contact hole is filled with a contact conductive material to form a contact structure, which is in contact with the conductive structure.
[0015] As an optional implementation, the step of removing a portion of the first dielectric layer using a photomask pattern to form a first via exposing the conductive structure includes:
[0016] A portion of the first dielectric layer is removed using a dry etching process to form the first via that exposes the conductive structure.
[0017] As an optional implementation, the step of removing the sacrificial portion to form a contact hole exposing the conductive structure includes:
[0018] The sacrificial portion is removed using a wet etching process to form the contact hole that exposes the conductive structure.
[0019] As an optional implementation, the step of forming a sacrificial layer on the first dielectric layer and in the first via includes:
[0020] The sacrificial layer is formed by filling the first dielectric layer and the first via with carbon material using a chemical vapor deposition process.
[0021] As an optional implementation, the etching selection ratio of the sacrificial layer to the first dielectric layer and the second dielectric layer is 100:1 to 250:1.
[0022] As an optional implementation, before filling the contact hole with a contact conductive material to form a contact structure, the following steps are further included:
[0023] A barrier layer is formed on the wall of the contact hole.
[0024] As an optional implementation, the depth of the first via is 100–500 nm in the direction perpendicular to the main surface of the substrate; and / or the depth of the contact hole is 200–800 nm.
[0025] A second aspect of this application provides a semiconductor structure, including:
[0026] A substrate having a conductive structure;
[0027] A first dielectric layer is located on the main surface of the substrate, and the first dielectric layer covers the conductive structure and the main surface of the substrate;
[0028] The second dielectric layer is located on the surface of the first dielectric layer on the side away from the main surface of the substrate;
[0029] The contact hole is formed by removing a portion of the second dielectric layer and a portion of the first dielectric layer using the same photomask pattern, wherein the contact hole penetrates the second dielectric layer and the first dielectric layer and exposes the conductive structure;
[0030] A contact structure is disposed in the contact hole and is in contact with the conductive structure.
[0031] As an optional implementation, the contact hole includes: a first through hole and a second through hole communicating with the first through hole, the first through hole penetrating the first dielectric layer, the second through hole penetrating the second dielectric layer, and the dimension of the bottom cross-section of the second through hole in the horizontal direction is larger than the dimension of the top cross-section of the first through hole in the horizontal direction.
[0032] In the semiconductor structure and its fabrication method provided in this application embodiment, the contact hole is fabricated using a two-stage alignment process. This reduces the depth of a single alignment process, thereby improving alignment accuracy. Furthermore, the two alignment processes use the same photomask pattern, which avoids the accumulation of errors between the two alignment processes, further improving alignment accuracy. This facilitates control over the contact hole size, thereby reducing the difficulty of the contact hole fabrication process while ensuring that the size of the conductive structure continues to shrink. It also guarantees the contact area between the contact structure and the conductive structure, reduces the contact resistance between the contact structure and the conductive structure, and ultimately improves the electrical performance of the semiconductor structure.
[0033] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;
[0036] Figure 2 A schematic cross-sectional view of a substrate in which a conductive structure and a first dielectric layer are formed in a method for fabricating a semiconductor structure provided in this application embodiment;
[0037] Figure 3 A cross-sectional schematic diagram of forming a photomask pattern on a first dielectric layer in the method for fabricating a semiconductor structure provided in this application embodiment;
[0038] Figure 4 A cross-sectional schematic diagram of the semiconductor structure fabrication method provided in this application, in which a first through-hole is formed using a photomask pattern;
[0039] Figure 5 This is a cross-sectional schematic diagram of the process for forming a sacrificial layer in the method for fabricating a semiconductor structure provided in this application embodiment;
[0040] Figure 6 A cross-sectional schematic diagram of the formation of a photomask pattern in the method for fabricating a semiconductor structure provided in this application embodiment;
[0041] Figure 7 This is a cross-sectional schematic diagram of the process for forming a sacrificial portion in the method for fabricating a semiconductor structure provided in this application embodiment;
[0042] Figure 8 This is a cross-sectional schematic diagram of the formation of the second dielectric layer in the method for fabricating the semiconductor structure provided in the embodiments of this application;
[0043] Figure 9 A cross-sectional schematic diagram of the formation of contact holes in the method for fabricating a semiconductor structure provided in the embodiments of this application;
[0044] Figure 10 This is a cross-sectional schematic diagram of the formation of a contact structure in a contact hole in a method for fabricating a semiconductor structure provided in an embodiment of this application.
[0045] Figure label:
[0046] 100 - Semiconductor structure; 110 - Substrate; 120 - Conductive structure;
[0047] 130 - First dielectric layer; 140 - Sacrificial layer; 141 - Sacrificial part;
[0048] 150 - Photomask pattern; 160 - Second dielectric layer; 170 - Contact hole;
[0049] 171 - First through hole; 172 - Second through hole; 180 - Contact structure. Detailed Implementation
[0050] The inventors of this application discovered in their practical work that, with the continuous development of semiconductor technology, the size of semiconductor devices is constantly shrinking, and the size of conductive structures is also constantly decreasing. Meanwhile, the aspect ratio of the contact structures electrically connected to the conductive structures is constantly increasing. In related technologies, contact holes exposing the conductive structures are typically formed by dry etching (e.g., plasma etching), and then conductive material is deposited into the contact holes to form a contact structure, allowing the contact structure to connect with the conductive structure and thus achieve signal transmission. However, as the microscopic dimensions of semiconductor structures shrink, the size of conductive structures continues to decrease, and the aspect ratio of contact holes exposing conductive structures is constantly increasing. Due to the characteristics of plasma etching processes, when etching to form high aspect ratio holes or trenches that expose conductive structures, the sidewalls of the formed holes or trenches often become tilted. This results in the bottom of the high aspect ratio hole or trench having a smaller horizontal cross-sectional dimension than the top. Moreover, the tilt becomes more pronounced as the aspect ratio of the hole or trench increases. Therefore, as the depth of the high aspect ratio contact hole increases, the bottom dimension of the contact hole becomes smaller and smaller, making it difficult to align and contact with the conductive structure to be connected at the bottom. This leads to increased contact resistance or short circuits, resulting in poor performance or failure of semiconductor devices.
[0051] To address the aforementioned issues, this application provides a semiconductor structure and its fabrication method. When fabricating the contact hole, a two-stage alignment process is employed. This reduces the aspect ratio of a single alignment process, thereby improving alignment accuracy. Furthermore, the two alignment processes utilize the same photomask pattern, preventing error accumulation and further enhancing alignment accuracy. Simultaneously, it facilitates control over the contact hole size. This reduces the fabrication difficulty of the contact hole while ensuring the contact area between the contact and conductive structures remains constant as the size of the conductive structure decreases. It also reduces the contact resistance between the contact and conductive structures, thereby improving the electrical performance of the semiconductor structure.
[0052] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0053] Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure provided in this application embodiment. Please refer to... Figure 1As shown in the embodiments of this application, a method for fabricating a semiconductor structure is provided, the method comprising:
[0054] Step S101: Provide a substrate on which a conductive structure and a first dielectric layer are formed, wherein the first dielectric layer covers the conductive structure and the main surface of the substrate.
[0055] Please combine Figure 2 As shown, substrate 110 serves as a support structure for semiconductor structure 100, providing a support or process foundation for devices or structural layers on substrate 110. The material constituting substrate 110 can be a semiconductor material, which can be any one or more of silicon, germanium, silicon germanium, silicon carbide, silicon-on-insulator, and germanium-on-insulator; alternatively, the material constituting substrate 110 can be other materials known to those skilled in the art. In this embodiment, at least a portion of substrate 110 is a silicon substrate, and the silicon material can be single-crystal silicon. Exemplarily, substrate 110 can be formed by chemical vapor deposition (CVD).
[0056] In some optional embodiments, the substrate 110 includes an array region and a peripheral circuit region adjacent to the array region. A conductive structure 120 is formed in the substrate 110. When the conductive structure 120 is disposed in the peripheral circuit region, it can be a lower-layer interconnect in the peripheral circuit region, such as a lower-layer interconnect in a multilayer interconnect. When the conductive structure 120 is disposed in the array region, it can also be a contact pad in the array region. Both the peripheral circuit region and the array region can have the conductive structure 120. The conductive structures 120 in the peripheral circuit region and the array region are located on the same horizontal layer. This allows the conductive structures 120 in the peripheral circuit region and the array region to be formed simultaneously using the same fabrication process, thereby reducing the number of fabrication steps and lowering the fabrication cost.
[0057] In addition, the substrate 110 may also include word lines (WL), bit lines (BL), and several shallow trench isolation structures (not shown in the figure).
[0058] In the embodiments of this application, please refer to Figure 2 As shown, a first dielectric layer 130 can be formed on the surface of the substrate 110 using deposition processes such as Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). The first dielectric layer 130 covers the conductive structure 120 and the main surface of the substrate 110, wherein the main surface of the substrate 110 is, for example, a... Figure 2 The upper surface of the middle substrate 110.
[0059] For example, the material of the first dielectric layer 130 may include at least one of silicon oxide, silicon oxynitride, and silicon carbonitride. Furthermore, the first dielectric layer 130 may be a single-layer film structure or a multi-layer film structure. The thickness of the deposited first dielectric layer 130 can be controlled according to the height of the first via 171 or the height of other film layers formed in subsequent processes. The thickness of the first dielectric layer 130 can be controlled at depths prone to insufficient etching based on the aspect ratio of the first via 171, thereby improving the problem of insufficient etching in subsequent processes. For example, the distance from the main surface of the first dielectric layer 130 to the conductive structure 120 is represented by H1, where the dimension of H1 is greater than or equal to 100 nm and less than or equal to 500 nm. For example, the distance H1 from the main surface of the first dielectric layer 130 to the conductive structure 120 may be, for example, 100 nm, 200 nm, 300 nm, 400 nm, or 500 nm.
[0060] In some alternative implementations, please refer to Figure 3 As shown, after forming a conductive structure 120 and a first dielectric layer 130 on a substrate 110, a photoresist layer is coated on the main surface (e.g., the upper surface) of the first dielectric layer 130, and a photomask (also called a mask) is disposed on the photoresist layer. The photomask has a photomask pattern 150, that is, the mask has a mask opening. In subsequent processes, ultraviolet light shines through the photomask pattern 150 onto the surface of the photoresist layer, causing a chemical reaction in the exposed area of the photoresist layer. Then, the photoresist in the exposed area (positive photoresist) or the photoresist in the unexposed area (negative photoresist) is dissolved and removed by a development technique.
[0061] Step S102: Use a photomask pattern to remove part of the first dielectric layer to form a first via that exposes the conductive structure.
[0062] Specifically, taking a positive photoresist layer as an example, the area on the photomask corresponding to the conductive structure 120 is a light-transmitting area, while other areas on the photomask are opaque. Ultraviolet light passes through the light-transmitting area to the photoresist layer and exposes it. The exposed area of the photoresist layer corresponds to the conductive structure 120. The photoresist in the exposed area is removed by a development technique, exposing the area on the first dielectric layer 130 corresponding to each conductive structure 120. Then, the exposed area of the first dielectric layer 130 is etched to form the first via 171 on the upper surface of the exposed conductive structure 120. Figure 4 As shown in the image.
[0063] In contrast to positive photoresist, if negative photoresist is used, the areas corresponding to each conductive structure 120 on the photomask can be set as opaque areas, while other areas on the photomask are transparent. The areas on the photoresist layer other than those corresponding to each conductive structure 120 become exposed areas. The photoresist layer in the unexposed areas is removed using a development technique, i.e., the photoresist layer corresponding to the conductive structure 120 is removed, exposing the areas on the first dielectric layer 130 corresponding to each conductive structure 120. Then, the exposed areas of the first dielectric layer 130 are etched to form first vias 171 on the first dielectric layer 130, exposing the upper surface of the conductive structure 120. Figure 3 As shown in the image.
[0064] In the embodiments of this application, such as Figure 3 and Figure 4 As shown, a positive photoresist is used, and the exposed area of the photoresist layer corresponds to the conductive structure 120. The photoresist in the exposed area is removed by a development technique, and then the exposed area of the first dielectric layer 130 is removed by, for example, a dry etching process, to form a first via 171 on the first dielectric layer 130 that exposes the conductive structure 120.
[0065] It is understandable that, due to the depth of the first through hole 171 (e.g. Figure 4 The depth H1 in the first through hole 171 is less than the total depth of the contact hole 170 formed in the subsequent process. That is, the aspect ratio of the first through hole 171 is less than the aspect ratio of the contact hole 170. Therefore, removing part of the first dielectric layer 130 using the photomask pattern 150 is beneficial to improving the alignment accuracy of the alignment process, making the opening size of the first through hole 171 easier to control, reducing the process difficulty of the first through hole 171, and the first through hole 171 is less likely to have insufficient etching or over-etching, thereby ensuring the dimensional accuracy of the first through hole 171.
[0066] Step S103: A sacrificial layer is formed on the first dielectric layer and in the first via, the sacrificial layer covering the main surface of the first dielectric layer; and part of the sacrificial layer is removed using the same photomask pattern, retaining the sacrificial layer in the first via and directly above the first via, the retained sacrificial layer forming the sacrificial part.
[0067] Specifically, after forming the first via 171 exposing the conductive structure 120 on the first dielectric layer 130, carbon material can be filled into the first dielectric layer 130 and the first via 171 using deposition processes such as atomic layer deposition (ALD), chemical vapor deposition, and physical vapor deposition. For example, the carbon material can be amorphous carbon, etc., to form a sacrificial layer 140. It can be understood that the sacrificial layer 140 fills the first via 171 and covers the main surface of the first dielectric layer 130, such as... Figure 5 As shown in the image.
[0068] For example, the distance from the main surface of the sacrificial layer 140 to the main surface of the conductive structure 120 is represented by, for example, H2. Figure 6 As shown, the size of H2 is greater than or equal to 200nm and less than or equal to 800nm. For example, the size of H2 is 200nm, 300nm, 400nm, 500nm, 600nm, 700nm or 800nm, etc.
[0069] Furthermore, after forming a sacrificial layer 140 in the first contact hole 170 and on the first dielectric layer 130, a photoresist layer is coated on the sacrificial layer 140. The photoresist layer is exposed using the same photomask as when forming the first via 171. Then, the photoresist in the exposed area (positive photoresist) or the photoresist in the unexposed area (negative photoresist) is dissolved and removed using a development technique. For example, in Figure 6 As shown, the photoresist layer uses negative photoresist. The area corresponding to the photoresist layer and the first via 171 is the exposed area, and the other areas are unexposed areas. The photoresist layer in the unexposed areas is removed by developing technology to expose the sacrificial layer 140. The exposed sacrificial layer 140 is then etched to expose the surface of the first dielectric layer 130. The sacrificial layer 140 in the first via 171 and directly above the first via 171 is retained. The retained sacrificial layer 140 is formed as a sacrificial portion 141, as shown. Figure 7 As shown in the image.
[0070] The sacrificial layer 140 and the first dielectric layer 130 have a high etching selectivity. This allows etching to stop when the sacrificial layer 140 is etched to the first dielectric layer 130, thus avoiding etching of the surface of the first dielectric layer 130. For example, the etching selectivity of the sacrificial layer 140 to the first dielectric layer 130 can be 100:1 to 250:1. For example, the etching selectivity of the sacrificial layer 140 to the first dielectric layer 130 can be 100:1, 150:1, 200:1, 250:1, etc. The specific design can be adapted according to actual needs, as long as the first dielectric layer 130 is not etched at the same time as the sacrificial layer 140 is etched. No specific limitation is made here.
[0071] It is understood that etch selectivity refers to the relative etching rate of one material to another under the same etching conditions; that is, the ratio of the etching rate of the material being etched to the etching rate of the other material. A high etch selectivity means that only the desired material layer is etched, and etching stops when the desired material layer is reached. For example, in the embodiments of this application, when etching the sacrificial layer 140, etching stops when the first dielectric layer 130 is reached, thereby protecting the first dielectric layer 130 from being etched.
[0072] It is understandable that since the photomask used in forming the sacrificial part 141 and the photomask used in forming the first through-hole 171 are the same photomask, that is, the first through-hole 171 is formed using the photomask pattern 150 and an alignment process, the alignment error, for example, is... It is indicated that; by using the same photomask pattern 150 and forming the sacrificial part 141 through an alignment process, the alignment error is... The relationship between the alignment errors caused by performing two alignment processes using the same photomask pattern 150 is expressed by the following formula:
[0073]
[0074] Since H2 > H1, therefore, according to the above formula, we know that:
[0075]
[0076] Therefore, in this embodiment of the application, by using the same photomask and forming the first through hole 171 and the sacrificial part 141 through two alignment processes, the cumulative error of the two alignment processes can be reduced, thereby improving the accuracy of the alignment process.
[0077] In addition, after removing part of the sacrificial layer 140 using the same photomask pattern 150, the photoresist layer on the sacrificial portion 141 can be removed using a cleaning solution or a cleaning gas, for example, by using a sulfuric acid-hydrogen peroxide mixture or oxygen plasma to remove the photoresist layer.
[0078] Step S104: A second dielectric layer is formed on the first dielectric layer, and the main surface of the second dielectric layer is flush with the main surface of the sacrificial part.
[0079] Please combine Figure 8 As shown, after the sacrificial portion 141 is formed, a second dielectric layer 160 can be deposited on the first dielectric layer 130 using deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The second dielectric layer 160 covers the exposed surface of the first dielectric layer 130, and the main surface of the second dielectric layer 160 is flush with the main surface of the sacrificial portion 141. For example, in... Figure 8 In this process, the main surface of the second dielectric layer 160 is the upper surface, and the main surface of the sacrificial part 141 is also its upper surface. The upper surface of the second dielectric layer 160 is flush with the upper surface of the sacrificial part 141.
[0080] The material of the second dielectric layer 160 may include at least one of silicon oxide, silicon oxynitride, and silicon carbonitride. Furthermore, the second dielectric layer 160 may be a single-layer film structure or a multi-layer film structure. The thickness of the deposited second dielectric layer 160 can be controlled according to the height of the contact hole 170 or the height of other film layers formed in subsequent processes, to ensure the formation of contact holes 170 with high aspect ratios in subsequent processes.
[0081] Step S105: Remove the sacrificial portion to form a contact hole that exposes the conductive structure, and form a contact structure in the contact hole that is in contact with the conductive structure.
[0082] Please combine Figure 9 As shown, after the second dielectric layer 160 is formed on the first dielectric layer 130, the sacrificial material in the second dielectric layer 160 and the sacrificial material in the first via 171 can be removed sequentially by an etching process, i.e., the sacrificial portion 141 can be removed, so that a second via 172 communicating with the first via 171 can be formed on the second dielectric layer 160. The second via 172 and the first via 171 together form a contact hole 170 exposing the conductive structure 120, as shown. Figure 9 As shown in the image.
[0083] In this process, the photoresists used in the two alignment steps have opposite polarities. Therefore, when etching to form the first via 171 and the sacrificial portion 141, due to the anisotropic plasma etching process, the cross-sectional dimension of the first via 171 near the substrate 110 is smaller than the cross-sectional dimension of the first via 171 away from the substrate 110. That is, the cross-sectional dimension of the bottom of the first via 171 in the horizontal direction is smaller than the cross-sectional dimension of the top of the first via 171 in the horizontal direction. For example, the ratio of the cross-sectional dimension of the bottom of the first via 171 in the horizontal direction to the cross-sectional dimension of the top of the first via 171 in the horizontal direction is greater than or equal to 0.7 and less than 1. Meanwhile, the cross-sectional dimension of the bottom of the sacrificial portion 141 in the second dielectric layer 160 in the horizontal direction is slightly larger than the cross-sectional dimension of the top of the sacrificial portion 141 in the horizontal direction. It is understood that since the depth-to-width ratio of the sacrificial layer 140 removed when the sacrificial layer 140 forms the sacrificial portion 141 is small, the cross-sectional dimension of the bottom of the formed sacrificial portion 141 in the horizontal direction is smaller. The cross-sectional dimension of the first through-hole 171 is slightly larger than the horizontal cross-sectional dimension of the top of the sacrificial portion 141, so that the horizontal cross-sectional dimension of the bottom of the second through-hole 172 formed in the second dielectric layer 160 is slightly larger than the horizontal cross-sectional dimension of the top of the second through-hole 172. For example, the ratio of the horizontal cross-sectional dimension of the bottom of the second through-hole 172 to the horizontal cross-sectional dimension of the top of the second through-hole 172 is greater than 1 and less than or equal to 1.1. Therefore, the inclination of the hole wall of the second through-hole 172 is small, which can increase the alignment accuracy between the subsequently formed contact hole and the conductive structure. In addition, since the same photomask is used to form the first through-hole 171 and the second through-hole 172, the horizontal cross-sectional dimensions of the top of the first through-hole 171 and the top of the second through-hole 172 are basically the same, and the horizontal cross-sectional dimension of the bottom of the second through-hole 172 is slightly larger than the horizontal cross-sectional dimension of the top of the first through-hole 171. Figure 9 As shown, this increases the contact area between the second through hole 172 and the first through hole 171, thereby ensuring excellent contact between the subsequently formed contact structure 180 and the conductive structure 120.
[0084] It is understood that in this embodiment of the application, the first through hole 171 and the second through hole 172 are formed by two alignment processes using the same photomask, and the photoresist used in the two alignment processes has opposite polarities. In this way, the cross-sectional dimensions of the bottom of the second through hole 172 in the horizontal direction can be adjusted to ensure alignment accuracy, thereby ensuring the contact area between the second through hole 172 and the first through hole 171, and thus achieving excellent contact between the subsequently formed contact structure 180 and the conductive structure 120.
[0085] In some alternative embodiments, the step of removing the sacrificial portion 141 to form a contact hole 170 exposing the conductive structure 120 includes:
[0086] The sacrificial portion 141 is removed using a wet etching process to form a contact hole 170 that exposes the conductive structure 120. For example, the sacrificial portion 141 is etched in an acid, alkali, or organic solution to remove the sacrificial material in the second dielectric layer 160 and the sacrificial material in the first via 171. Since the sacrificial layer 140 has a high etching selectivity with the first dielectric layer 130 and the second dielectric layer 160, the sidewalls of the first dielectric layer 130 and the second dielectric layer 160 can be protected when the sacrificial portion 141 is removed by the etching process. For example, the etching selectivity of the sacrificial layer 140 with the first dielectric layer 130 and the second dielectric layer 160 can be 100:1 to 250:1.
[0087] Therefore, in this embodiment, the contact hole 170 is prepared by two alignment processes. This reduces the aspect ratio of a single alignment process, thereby improving alignment accuracy. In addition, the two alignment processes use the same photomask pattern 150, which avoids the accumulation of errors between the two alignment processes, further improving alignment accuracy. At the same time, it is easy to control the size of the contact hole 170. This reduces the difficulty of the contact hole 170 preparation process while ensuring that the size of the conductive structure 120 is continuously reduced. It also ensures the contact area between the contact structure 180 and the conductive structure 120, reduces the contact resistance between the contact structure 180 and the conductive structure 120, and thus improves the electrical performance of the semiconductor structure 100.
[0088] In some alternative embodiments, after forming the contact hole 170 exposing the conductive structure 120, the method further includes:
[0089] Please combine Figure 10 As shown, a contact conductive material is deposited in the contact hole 170 through a deposition process such as atomic layer deposition, chemical vapor deposition or physical vapor deposition, so that the contact conductive material fills the contact hole 170 to form a contact structure 180, and the contact structure 180 is in contact with the conductive structure 120.
[0090] The material of the contact structure 180 can be conductive metal materials such as aluminum (Al) or tungsten (W).
[0091] In some alternative embodiments, prior to filling the contact hole 170 with a contact conductive material to form the contact structure 180, the method further includes:
[0092] A barrier layer is formed on the wall of the contact hole 170. The barrier layer is made of materials such as titanium or titanium nitride, so as to prevent the material of the contact structure 180 from diffusing into the first dielectric layer 130 and the second dielectric layer 160 by providing a barrier layer between the contact structure 180 and the wall of the contact hole 170.
[0093] In the embodiments of this application, the conductive structure 120 can be a contact pad of the array region or a lower interconnect of the peripheral circuit region. For example, when the conductive structure 120 is a contact pad of the array, the contact structure 180 is a capacitor, that is, the contact hole 170 is a capacitor hole. When the conductive structure 120 is a lower interconnect of the peripheral circuit region, the contact structure 180 is, for example, a contact plug, and the contact hole 170 is a conductive via, so as to connect one of the source, drain or gate of the transistor through the contact plug. Alternatively, the contact structure 180 can also be other structures with a large depth-to-width ratio, all of which can be prepared by the above preparation method, and no specific limitation is made here.
[0094] Example 2
[0095] Please continue to refer to Figure 10 As shown, this application embodiment provides a semiconductor structure 100, including: a substrate 110, a first dielectric layer 130, a second dielectric layer 160, a contact hole 170, and a contact structure 180. The substrate 110 has a conductive structure 120. The first dielectric layer 130 is located on the main surface of the substrate 110 and covers the conductive structure 120 and the main surface of the substrate 110. The second dielectric layer 160 is located on the surface of the first dielectric layer 130 away from the main surface of the substrate 110. The contact hole 170 is formed by removing a portion of the second dielectric layer 160 and a portion of the first dielectric layer 130 using the same photomask pattern 150. The contact hole 170 penetrates the second dielectric layer 160 and the first dielectric layer 130 and exposes the conductive structure 120. The contact structure 180 is disposed in the contact hole 170 and is electrically connected to the conductive structure 120.
[0096] The substrate 110 serves as the supporting foundation for the semiconductor structure 100 and can be made of semiconductor materials, such as silicon substrate.
[0097] In this embodiment, the contact hole 170 is prepared by two alignment processes. This reduces the aspect ratio of a single alignment process, thereby improving alignment accuracy. In addition, the two alignment processes use the same photomask pattern 150, which avoids the accumulation of errors between the two alignment processes, further improving alignment accuracy. At the same time, it is easy to control the size of the contact hole 170. This reduces the difficulty of the contact hole 170 preparation process while ensuring that the size of the conductive structure 120 is continuously reduced. It also ensures the contact area between the contact structure 180 and the conductive structure 120, reduces the contact resistance between the contact structure 180 and the conductive structure 120, and thus improves the electrical performance of the semiconductor structure 100.
[0098] In some alternative embodiments, the contact hole 170 includes a first through hole 171 and a second through hole 172 communicating with the first through hole 171. The first through hole 171 penetrates the first dielectric layer 130, and the second through hole 172 penetrates the second dielectric layer 160. The bottom of the second through hole 172 has a cross-sectional dimension in the horizontal direction that is slightly larger than the top of the first through hole 171 has a cross-sectional dimension in the horizontal direction.
[0099] It is understandable that when forming the first through-hole 171 and the second through-hole 172, the two alignment processes are performed using the same photomask, and the photoresist used in the two alignment processes has opposite polarities. Therefore, the cross-sectional dimensions of the top of the first through-hole 171 in the horizontal direction are basically the same as those of the top of the second through-hole 172 in the horizontal direction. The cross-sectional dimensions of the bottom of the second through-hole 172 in the horizontal direction are slightly larger than those of the top of the first through-hole 171 in the horizontal direction. In this way, the alignment accuracy can be ensured while adjusting the cross-sectional dimensions of the bottom of the second through-hole 172 in the horizontal direction, thereby ensuring the contact area between the second through-hole 172 and the first through-hole 171, and thus achieving excellent contact between the subsequently formed contact structure 180 and the conductive structure 120.
[0100] In some alternative embodiments, a barrier layer is provided between the hole wall of the contact hole 170 and the contact structure 180, wherein the barrier layer is, for example, titanium nitride, to prevent conductive ions of the contact structure 180 from diffusing into the dielectric layer.
[0101] The semiconductor structure and its fabrication method provided in this application embodiment include a substrate on which a conductive structure and a first dielectric layer are formed; a portion of the first dielectric layer is removed using a photomask pattern to form a first via exposing the conductive structure; a sacrificial layer is formed on the first dielectric layer and in the first via, the sacrificial layer covering the main surface of the first dielectric layer; a portion of the sacrificial layer is removed using the same photomask pattern, retaining the sacrificial layer in the first via and directly above the first via, the retained sacrificial layer forming a sacrificial portion; a second dielectric layer is formed on the first dielectric layer, the main surface of the second dielectric layer being flush with the main surface of the sacrificial portion; the sacrificial portion is removed to form a contact hole exposing the conductive structure, and a contact structure is formed in the contact hole. In the above scheme, a two-stage alignment process is used for fabrication. This reduces the depth of a single alignment process, thereby improving alignment accuracy. In addition, the same photomask pattern is used for both alignment processes, which avoids the accumulation of errors between the two alignment processes and further improves alignment accuracy. This allows for better control of the contact hole size, thereby reducing the difficulty of contact hole fabrication while ensuring that the size of the conductive structure continues to shrink. It also guarantees the contact area between the contact structure and the conductive structure, reduces the contact resistance between the contact structure and the conductive structure, and ultimately improves the electrical performance of the semiconductor structure.
[0102] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a conductive structure and a first dielectric layer are formed, wherein the first dielectric layer covers the conductive structure and the main surface of the substrate; A portion of the first dielectric layer is removed using a photomask pattern to form a first via that exposes the conductive structure. A sacrificial layer is formed on the first dielectric layer and in the first via, the sacrificial layer covering the main surface of the first dielectric layer; a portion of the sacrificial layer is removed using the same photomask pattern, retaining the sacrificial layer in the first via and directly above the first via, the retained sacrificial layer forming a sacrificial portion; A second dielectric layer is formed on the first dielectric layer, wherein the main surface of the second dielectric layer is flush with the main surface of the sacrificial portion; The sacrificial portion is removed to form a contact hole that exposes the conductive structure, and a contact structure that contacts and connects with the conductive structure is formed in the contact hole.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the contact hole that exposes the conductive structure, the method further includes: The contact hole is filled with a contact conductive material to form a contact structure, which is in contact with the conductive structure.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of removing a portion of the first dielectric layer using a photomask pattern to form a first via exposing the conductive structure includes: A portion of the first dielectric layer is removed using a dry etching process to form the first via that exposes the conductive structure.
4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The step of removing the sacrificial portion to form a contact hole exposing the conductive structure includes: The sacrificial portion is removed using a wet etching process to form the contact hole that exposes the conductive structure.
5. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The step of forming a sacrificial layer on the first dielectric layer and in the first via includes: The sacrificial layer is formed by filling the first dielectric layer and the first via with carbon material using a chemical vapor deposition process.
6. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The etching selectivity ratio of the sacrificial layer to the first dielectric layer and the second dielectric layer is 100:1 to 250:
1.
7. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before filling the contact hole with a contact conductive material to form a contact structure, the method further includes: A barrier layer is formed on the wall of the contact hole.
8. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, In the direction perpendicular to the main surface of the substrate, the depth of the first via is 100~500nm; and / or, the depth of the contact hole is 200~800nm.