Memory device and method of manufacturing the same
By dividing the formation of the barrier layer into two stages and using the atomic layer deposition process, the problem of residual barrier layer in the memory device is solved, and the high yield and stable electrical performance of the memory device are achieved.
Patent Information
- Application Number
- CN202311513778.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-17
- Filing Date
- 2023-11-14
- Publication Date
- 2025-04-18
AI Technical Summary
When manufacturing memory devices, the reduction in device size leads to a reduced process margin, which may cause metal or barrier layers to remain on the trench side walls of the buried word lines, affecting the reliability and electrical performance of the memory devices.
By dividing the formation of the barrier layer into two stages, the thickness of the barrier layer is controlled by using the atomic layer deposition process, avoiding its formation and residue on the side wall of the dielectric layer, and ensuring the ideal thickness of the barrier layer.
The residue of the barrier layer on the side wall of the dielectric layer is effectively avoided, the yield of the memory device is maintained, and the stability of electrical properties is ensured.
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Figure CN119855134A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to memory devices and methods for manufacturing the same. Background Art
[0002] In order to pursue lower costs and maintain product performance, in the current process of forming memory devices (e.g., dynamic random-access memory (DRAM) including buried word lines), the process margin is reduced as the device size continues to shrink. For example, when forming the buried word line, metal or barrier layer may remain on the dielectric layer of the trench sidewall of the buried word line, which may have an unnecessary impact on the memory device and cause electrical problems (such as reduced reliability or leakage current). Therefore, the industry still needs to improve the manufacturing method of the memory device to achieve the goal of maintaining the yield of the memory device. Summary of the invention
[0003] An embodiment of the present invention provides a method for manufacturing a memory device, comprising providing a substrate; forming a dielectric layer on the substrate; performing a patterning process to form a groove penetrating the dielectric layer to the substrate; forming a first conductor layer at the bottom of the groove and buried in the substrate; conformably forming a first barrier layer in the groove and covering the sidewalls of the dielectric layer and the top surface of the first conductor layer; performing a cleaning process to remove a portion of the first barrier layer located on the sidewalls of the dielectric layer, and the first barrier layer remains on the top surface of the first conductor layer; forming a second barrier layer above the first conductor layer and in contact with the first barrier layer; and forming a second conductor layer to fill the groove.
[0004] An embodiment of the present invention provides a memory device, comprising a substrate; a first conductor layer buried in the substrate; a first barrier layer disposed on the top surface of the first conductor layer; a second barrier layer disposed on the top surface of the first barrier layer; and a second conductor layer disposed on the second barrier layer, wherein the second barrier layer contains chlorine in element detection.
[0005] The embodiment of the invention divides the formation of the barrier layer into two stages and utilizes the characteristics of the atomic layer deposition process to effectively control the thickness of the barrier layer, while avoiding the formation and residue of the barrier layer on the sidewall of the dielectric layer, thereby further maintaining the yield of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] In order to make the features and advantages of the present invention more clearly understood, different embodiments are described in detail below with reference to the accompanying drawings:
[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 2 is a schematic cross-sectional view illustrating various intermediate stages of manufacturing a memory device according to an embodiment of the present invention.
[0008] Figure Number:
[0009] 10: Memory device
[0010] 100:Substrate
[0011] 105: Dielectric layer
[0012] 110: Patterning process
[0013] 115: Groove
[0014] 118: Lining
[0015] 120: first conductor layer
[0016] 125: first barrier layer
[0017] 125': First barrier layer
[0018] 130: Cleaning process
[0019] 135: Second barrier layer
[0020] 140: Plasma cleaning process
[0021] 145: Free Radicals
[0022] 150: Second conductor layer
[0023] 150': Second conductor layer
[0024] 155: Etching back process
[0025] X: Direction
[0026] Y: direction DETAILED DESCRIPTION
[0027] Generally speaking, in the process of forming a memory device, as the device size continues to shrink, the process margin also decreases. For example, when forming a buried word line, metal or a barrier layer may remain on the dielectric layer of the trench sidewall of the buried word line, which may have an unnecessary impact on the memory device and cause electrical problems (such as reduced reliability or leakage current). Although the residue can be avoided by adjusting the process seconds of the relevant film layer, the reduction in the thickness of the barrier layer may also cause different conductor layers to diffuse during subsequent high-temperature processes, further affecting the electrical problems of the memory device. The embodiment of the present invention utilizes the characteristics of the atomic layer deposition process to form barrier layers of different thicknesses on different components, effectively avoiding the residue of the barrier layer on the dielectric layer of the trench sidewall, while maintaining the required thickness of the barrier layer, thereby maintaining the yield of the memory device.
[0028] Figure 1 1 is a cross-sectional schematic diagram illustrating an intermediate stage of manufacturing a memory device 10 according to an embodiment of the present invention. A substrate 100 is provided. In some embodiments, the substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; a compound semiconductor substrate, such as a silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP) substrate; or an alloy semiconductor substrate, such as SiGe, SiGeC, GaAsP, or GaInP. In other embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate. The SOI substrate may include a base plate, a buried oxide layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer.
[0029] Continue to see Figure 1 , a dielectric layer 105 is formed on the substrate 100. In some embodiments, the dielectric layer 105 can be formed by a chemical vapor deposition (CVD) process. In some embodiments, the dielectric layer 105 can be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
[0030] Figure 21 is a schematic cross-sectional view of a memory device 10 performing a patterning process 110 according to an embodiment of the present invention. The patterning process 110 is performed to form a trench 115 penetrating the dielectric layer 105 to the substrate 100. For example, a mask layer (not shown) may be first formed on the dielectric layer 105, and a photoresist pattern may be formed on the mask layer by photolithography and etching processes, and then an etching process may be performed to transfer the photoresist pattern to the dielectric layer 105 and the substrate 100, thereby forming the trench 115. In some embodiments, the photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking (PEB), development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof.
[0031] Figure 31 is a cross-sectional view of forming a first conductor layer 120 in a memory device 10 according to an embodiment of the present invention. After forming the trench 115, the first conductor layer 120 is formed at the bottom of the trench 115 and buried in the substrate 100. More specifically, the formation of the first conductor layer 120 includes forming a liner 118 in the trench 115, forming a first conductor material layer (not shown) on the liner 118, and performing an etch-back process on the first conductor material layer to form the first conductor layer 120. In some embodiments, the top surface of the first conductor layer 120 is flush with the top surface of the substrate 100. In some embodiments, the liner 118 can be formed of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof. In some embodiments, the liner 118 can be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, the first conductor layer 120 can be formed of a metal material, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), other suitable metal materials, or a combination thereof. In some embodiments, the first conductor layer 120 can be formed using a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination thereof. In some embodiments, the back etching process may include an anisotropic etching process (or a directional etching process), such as a reactive ion etching (RIE) process, plasma etching, inductively coupled plasma (ICP) etching, or dry etching of a combination thereof.
[0032] Figure 4 1 is a cross-sectional schematic diagram of forming a first barrier layer 125 in the memory device 10 according to an embodiment of the present invention. The first barrier layer 125 is formed in the trench 115 and covers the sidewalls of the dielectric layer 105 and the top surface of the first conductor layer 120. In some embodiments, the first barrier layer 125 can be formed of titanium nitride (TiN). In some embodiments, the first barrier layer 125 is formed using a physical vapor deposition (PVD) process.
[0033] Figure 51 is a cross-sectional view of a memory device 10 performing a cleaning process 130 according to an embodiment of the present invention. The cleaning process 130 is performed to remove a portion of the first barrier layer 125 located on the sidewall of the dielectric layer 105, and the first barrier layer 125' remains on the top surface of the first conductive layer 120. The first barrier layer 125' can be used as a film layer to prevent diffusion between the first conductive layer 120 and the second conductive layer 150' due to subsequent high-temperature processes. In some embodiments, the cleaning process 130 includes a low-temperature sulfuric acid hydrogen peroxide mixture (SPM) cleaning process.
[0034] Figure 61 is a schematic cross-sectional view of forming a second barrier layer 135 in a memory device 10 according to an embodiment of the present invention. The second barrier layer 135 is formed above the first conductor layer 120 and in contact with the first barrier layer 125'. In order to avoid the barrier layer being too thin, in conventional processes, the barrier layer is usually formed to a larger thickness, which may cause the barrier layer to remain on the sidewall of the dielectric layer 105, thereby causing a risk of leakage in the conductor layer formed subsequently. In an embodiment of the present invention, the characteristics of the atomic layer deposition (ALD) process are utilized to divide the formation of the barrier layer into two stages, which not only reduces the possibility of the barrier layer remaining on the sidewall of the dielectric layer 105, but also ensures that the barrier layer can be formed to an ideal thickness. More specifically, for the atomic layer deposition process, its deposition rate depends on the number of cyclic depositions, that is, the deposition rate will be lower at the beginning of the process, and the deposition rate of the film layer can only be increased after the deposition surface is homogenized. In the embodiment of the present invention, the dielectric layer 105 and the first barrier layer 125' are different material surfaces. The deposition of the second barrier layer 135 on the surface of the dielectric material can be regarded as being in the early stage of the atomic layer deposition process, and the deposition of the second barrier layer 135 on the first barrier layer 125' can be regarded as being in the process stage after the deposition surface has been homogenized, thereby effectively controlling the formation of the second barrier layer 135. In other words, the second barrier layer 135 is deposited on the first barrier layer 125' in a manner similar to selective deposition. In other words, the formation rate of the second barrier layer 135 on the top surface of the first barrier layer 125' is greater than the formation rate of the second barrier layer 135 on the sidewall of the dielectric layer 105. In some embodiments, the thickness of the first barrier layer 125' is greater than the thickness of the second barrier layer 135. In some embodiments, the ratio of the thickness of the first barrier layer 125' to the thickness of the second barrier layer 135 is about 3:1 to about 4:1. In some embodiments, the second barrier layer 135 only covers the first barrier layer 125' but does not cover the sidewall of the dielectric layer 105. In some embodiments, the area of the vertical projection of the first barrier layer 125' on the substrate 100 is equal to the area of the vertical projection of the second barrier layer 135 on the substrate 100. In some embodiments, the thickness of the second barrier layer 135 ranges from about 1 nanometer to about 2 nanometers. In some embodiments, the sum of the thicknesses of the first barrier layer 125' and the second barrier layer 135 is less than about 6 nanometers. In some embodiments, the second barrier layer 135 can be formed of titanium nitride (TiN). In some embodiments, the second barrier layer 135 is formed using an atomic layer deposition (ALD) process.
[0035] It is worth noting that in the embodiment of the present invention, the first barrier layer 125' is formed by a physical vapor deposition (PVD) process. More specifically, the first barrier layer 125' formed by the physical vapor deposition process may only contain Ti and N, so the first barrier layer 125' does not contain chlorine (Cl) in element detection. In the embodiment of the present invention, the second barrier layer 135 is formed by an atomic layer deposition (ALD) process. More specifically, the second barrier layer 135 formed by the atomic layer deposition process may contain Ti, N, Cl, and H, so the second barrier layer 135 contains chlorine in element detection. In some embodiments, the first barrier layer 125' is disposed on the top surface of the first conductive layer 120, and the second barrier layer 135 is disposed on the top surface of the first barrier layer 125'.
[0036] Figure 7 FIG. 1 is a cross-sectional view showing a second conductive layer 150 formed in the memory device 10 according to an embodiment of the present invention. Figure 8 1 is a cross-sectional schematic diagram illustrating a memory device 10 performing an etch-back process 155 according to an embodiment of the present invention. A second conductor layer 150 is formed to fill the trench 115. In other words, the second conductor layer 150 is disposed on the second barrier layer 135. The second conductor layer 150 is separated from the first conductor layer 120 by the first barrier layer 125' and the second barrier layer 135. The second barrier layer 135 is in direct contact with the bottom surface of the second conductor layer 150 but not in contact with the sidewall of the second conductor layer 150. After the second conductor layer 150 is formed, an etch-back process 155 is performed on the second conductor layer 150 to form the second conductor layer 150'. After the second conductor layer 150' is formed, the first conductor layer 120, the first barrier layer 125', the second barrier layer 135, and the second conductor layer 150' can be regarded as a buried word line of the memory device 10. In some embodiments, the material of the second conductor layer 150 may include polysilicon. In some embodiments, the etch-back process 155 may include an anisotropic etching process (or a directional etching process), such as a dry etching process including a reactive ion etching (RIE) process, plasma etching, inductively coupled plasma (ICP) etching, or a combination thereof.
[0037] Fig. 9 According to another embodiment, a cross-sectional view of the memory device 10 performing a plasma cleaning process 140 is shown. Fig.10FIG. 1 is a schematic cross-sectional view of forming the second barrier layer 135 in the memory device 10 according to another embodiment. In addition to utilizing the characteristics of the atomic layer deposition process, in some embodiments, after performing the cleaning process 130 and before forming the second barrier layer 135, a plasma cleaning process 140 may be performed to leave free radicals 145 on the sidewalls of the dielectric layer 105. The free radicals 145 may be used to reduce the formation rate of the second barrier layer 135 on the sidewalls of the dielectric layer 105. After performing the plasma cleaning process 140, approximately Figure 6 , forming the second barrier layer 135 on the first conductive layer 120 and in contact with the first barrier layer 125 ′. Using the free radicals 145 can further reduce the surface homogenization of the dielectric layer 105 during the atomic layer deposition process and inhibit the formation of the second barrier layer 135 .
[0038] After forming the buried word line (including the first conductive layer 120, the first barrier layer 125', the second barrier layer 135, and the second conductive layer 150'), other semiconductor processes may be performed to form various components and devices of the memory device 10, which will not be described in detail here.
[0039] In summary, the embodiments of the present invention divide the formation of the barrier layer into two stages and utilize the characteristics of the atomic layer deposition process to effectively control the thickness of the barrier layer, while avoiding the formation and residue of the barrier layer on the sidewall of the dielectric layer, thereby further maintaining the yield of the memory device.
[0040] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for manufacturing a memory device, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate; Performing a patterning process to form a trench penetrating the dielectric layer to the substrate; forming a first conductor layer at the bottom of the trench and buried in the substrate; Conformably forming a first barrier layer in the trench and covering the sidewalls of the dielectric layer and the top surface of the first conductive layer; Performing a cleaning process to remove a portion of the first barrier layer located on the sidewall of the dielectric layer, and the first barrier layer remains on the top surface of the first conductive layer; forming a second barrier layer on the first barrier layer; and A second conductive layer is formed to fill the trench, wherein a formation rate of the second barrier layer on the top surface of the first barrier layer is greater than a formation rate of the second barrier layer on the sidewall of the dielectric layer.
2. The method for manufacturing a memory device according to claim 1, wherein: The second barrier layer only covers the first barrier layer but does not cover the sidewall of the dielectric layer.
3. The method for manufacturing a memory device according to claim 1, wherein: After performing the cleaning process and before forming the second barrier layer, the method further includes: A plasma cleaning process is performed to leave a radical on the sidewall of the dielectric layer, wherein the radical is used to reduce the formation rate of the second barrier layer.
4. The method for manufacturing a memory device according to claim 1, wherein: The first barrier layer is formed by using a physical vapor deposition process.
5. The method for manufacturing a memory device according to claim 1, wherein: The second barrier layer is formed by using an atomic layer deposition process.
6. The method for manufacturing a memory device according to claim 1, wherein: The cleaning process includes a low-temperature sulfuric acid and hydrogen peroxide mixed liquid cleaning process.
7. The method for manufacturing a memory device according to claim 1, wherein: The thickness of the first barrier layer is greater than the thickness of the second barrier layer.
8. A memory device, characterized in that: include: a substrate; a first conductor layer, buried in the substrate; a first barrier layer disposed on the top surface of the first conductive layer; a second barrier layer disposed on a top surface of the first barrier layer; and A second conductor layer is disposed on the second barrier layer, wherein the second barrier layer contains chlorine in element detection.
9. The memory device according to claim 8, wherein: The first barrier layer does not contain chlorine in elemental detection.
10. The memory device according to claim 8, wherein: The thickness of the first barrier layer is greater than the thickness of the second barrier layer.
11. The memory device according to claim 10, wherein: The ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is 3:1 to 4:
1.
12. The memory device according to claim 8, wherein: The second barrier layer directly contacts the bottom surface of the second conductor layer without contacting the sidewall of the second conductor layer.
13. The memory device according to claim 8, wherein: The area of a vertical projection of the first barrier layer on the substrate is equal to the area of a vertical projection of the second barrier layer on the substrate.