Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a first semiconductor structure including a cell region and a peripheral circuit region, and including a cell capacitor disposed in the cell region and a first insulating layer disposed in the cell region and the peripheral circuit region to cover the cell capacitor; a second semiconductor structure including a cell transistor disposed over the first insulating layer in the cell region and a peripheral circuit transistor disposed over the first insulating layer in the peripheral circuit region; and a first conductor passing through the first insulating layer to electrically connect the first cell source / drain region of the cell transistor with the electrode of the cell capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0138532, filed on October 17, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor technology, and more particularly, to a semiconductor device including a selector and a transistor and a method for manufacturing the same. Background Art

[0004] With the development of the electronics industry, the operating speed of electronic products is required to increase, while electronic products are becoming more and more miniaturized, high-performance and more integrated.

[0005] In order to meet these demands, it is necessary to develop a technology capable of maintaining and / or improving the characteristics of unit elements (such as transistors and capacitors) constituting electronic products while reducing the area they occupy. Summary of the invention

[0006] In an embodiment of the present disclosure, a semiconductor device may include: a first semiconductor structure, which includes a cell area and a peripheral circuit area, a cell capacitor arranged in the cell area, and a first insulating layer arranged in the cell area and the peripheral circuit area to cover the cell capacitor; a second semiconductor structure, which includes a cell transistor and a peripheral circuit transistor, the cell transistor is arranged on the first insulating layer in the cell area, and the peripheral circuit transistor is arranged on the first insulating layer in the peripheral circuit area; and a first conductor, which passes through the first insulating layer to electrically connect the first cell source / drain area of ​​the cell transistor with the electrode of the cell capacitor.

[0007] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: providing a first semiconductor structure, the first semiconductor structure including a cell region and a peripheral circuit region, a cell capacitor arranged in the cell region, and a first insulating layer arranged in the cell region and the peripheral circuit region to cover the cell capacitor; bonding a semiconductor substrate to an upper surface of the first insulating layer; using the semiconductor substrate, forming a cell transistor in the cell region and forming a peripheral circuit transistor in the peripheral circuit region; and forming a conductor that passes through the first insulating layer and connects a first source / drain region of the cell transistor to an electrode of the cell capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 3 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0009] Figures 4 to 6is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0010] Figure 7 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0011] Figures 8 to 11 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0012] Fig.12 yes Fig. 9 Enlarged stereogram of the P1 section.

[0013] Fig.13 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0015] The drawings are not necessarily drawn to scale. In some instances, the scale of at least some structures in the drawings may be enlarged to clearly illustrate certain features of the described embodiments. When presenting a specific example in a drawing or description of two or more layers in a multilayer structure, the relative positioning relationship of these layers shown or the order of arranging the layers reflects the specific implementation of the described or illustrated example, and different relative positioning relationships or the order of arranging the layers are possible. In addition, the example of the multilayer structure described or illustrated may not reflect all layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the multilayer structure described or illustrated is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or between the first layer and the substrate.

[0016] In the following description, a semiconductor structure may refer to a semiconductor wafer, a semiconductor chip, etc. including a circuit and / or a wiring structure that performs a predetermined function. In addition, a semiconductor device may include two or more semiconductor structures stacked in a vertical direction and electrically and / or physically connected to each other. Hereinafter, it will be described in more detail with reference to the accompanying drawings.

[0017] Figures 1 to 3 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0018] First, the manufacturing method will be described.

[0019] Reference Figure 1 , a first semiconductor structure 100 including a cell region A and a peripheral circuit region B may be provided. The cell region A and the peripheral circuit region B may be adjacent to each other. Alternatively, the cell region A and the peripheral circuit region B may be spaced apart from each other. The cell region A may correspond to a region where a cell capacitor 120 of the first semiconductor structure 100 is disposed and a cell transistor of a second semiconductor structure to be described later is disposed. The peripheral circuit region B may be arranged around the cell region A and may correspond to a region where a peripheral circuit transistor of a second semiconductor structure to be described later is disposed.

[0020] The first semiconductor structure 100 may include a first semiconductor substrate 110 , a cell capacitor 120 formed over the first semiconductor substrate 110 in the cell region A, and a first insulating layer 130 formed over the first semiconductor substrate 110 in the cell region A and the peripheral circuit region B to cover the cell capacitor 120 .

[0021] The unit capacitor 120 may include a first electrode 122, a second electrode 126, and a dielectric layer 124 between the first electrode 122 and the second electrode 126. Each of the first electrode 122 and the second electrode 126 may include a conductive material, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), or molybdenum (Mo), a compound of the metal, or an alloy of the metal. One of the first electrode 122 and the second electrode 126 may correspond to a storage electrode, and the other of the first electrode 122 and the second electrode 126 may correspond to a plate electrode. The dielectric layer 124 may include a dielectric material, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0022] In the unit capacitor 120 of the embodiment, the first electrode 122 may have a columnar shape. The second electrode 126 may have a columnar shape surrounding the upper surface and sidewalls of the first electrode 122. The term "upper surface" of the element when used in the present disclosure may refer to the "top surface" of the element. The dielectric layer 124 may be between the first electrode 122 and the second electrode 126. For example, the dielectric layer 124 may have a shape surrounding the upper surface and sidewalls of the first electrode 122 and extending below the lower surface of the second electrode 126. The term "lower surface" of the element when used in the present disclosure may refer to the "bottom surface" of the element. That is, the unit capacitor 120 may correspond to a columnar capacitor. The pillar-type unit capacitor 120 may be formed by depositing a conductive material on the first semiconductor substrate 110 and patterning the conductive material to form a pillar-shaped first electrode 122, conformally depositing a dielectric material on the entire surface of the first semiconductor substrate 110 in which the first electrode 122 is formed, depositing a conductive material having a thickness sufficient to cover the first electrode 122 on the deposited dielectric material, and selectively etching the conductive material and the dielectric material to form a second electrode 126 and a dielectric layer 124. However, the embodiments of the present disclosure are not limited thereto, and the structure or shape of the unit capacitor 120 may be modified in various ways as long as the unit capacitor 120 includes a dielectric layer between two electrodes. For example, in another embodiment, an insulating material may be deposited on the first semiconductor substrate 110, and a hole may be formed in the insulating material by etching the insulating material. The first electrode, the dielectric layer, and the second electrode may be sequentially buried in the hole to form a trench-type unit capacitor. In another embodiment, a conductive material, a dielectric material, and a conductive material may be sequentially deposited on the first semiconductor substrate 110, and these materials may be selectively etched to form a planar unit capacitor.

[0023] The first semiconductor substrate 110 may include a semiconductor material such as silicon or silicon germanium. In some embodiments, a lower structure (not shown) may be formed in the first semiconductor substrate 110. For example, a conductive structure (e.g., a plate electrode) electrically connected to the first electrode 122 of the cell capacitor 120 may be formed in the first semiconductor substrate 110 to apply a predetermined voltage to the first electrode 122.

[0024] The first insulating layer 130 may include a variety of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first insulating layer 130 may be formed, for example, by a deposition process of an insulating material. In some embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, may also be performed on the deposited insulating material. The first insulating layer 130 may have a planarized upper surface substantially parallel to the upper surface of the first semiconductor substrate 110.

[0025] In the first insulating layer 130, the first conductor 140 may be formed to pass through the first insulating layer 130 and be electrically connected to the second electrode 126 (e.g., storage electrode) of the cell capacitor 120. The first conductor 140 may include a conductive material, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru), or molybdenum (Mo), a compound of the metal, or an alloy of the metal. In an embodiment, the first conductor 140 may have a contact plug shape, that is, a column shape, and may be disposed above the second electrode 126 to contact the uppermost surface of the second electrode 126. The first conductor 140 may be formed by selectively etching the first insulating layer 130 to form a hole exposing the uppermost surface of the second electrode 126, depositing a conductive material on the first insulating layer 130 to fill the hole, and performing a planarization process to expose the upper surface of the first insulating layer 130. However, the embodiments of the present disclosure are not limited thereto, and the position, shape, and formation method of the first conductor 140 may be modified in various ways as long as the first conductor 140 is electrically connected to the second electrode 126. For example, the first conductor 140 may include one or more contact plugs, one or more pads, or a combination thereof.

[0026] Reference Figure 2 , a second semiconductor substrate 210 may be formed on the first semiconductor structure 100 .

[0027] The second semiconductor substrate 210 may include a semiconductor material such as silicon or silicon germanium. The second semiconductor substrate 210 may have a flat plate shape covering both the cell area A and the peripheral circuit area B. Therefore, it can be said that the second semiconductor substrate 210 also includes the cell area A and the peripheral circuit area B. The second semiconductor substrate 210 may be bonded to the upper surface of the first insulating layer 130 of the first semiconductor structure 100. Therefore, the second semiconductor substrate 210 may contact the upper surface of the first insulating layer 130. For example, the second semiconductor substrate 210 may correspond to a bare wafer.

[0028] Reference Figure 3 , the second semiconductor substrate 210 may undergo several processes to form a processed second semiconductor substrate 210'. The several processes may include at least one of a process of cutting the second semiconductor substrate 210 into a desired shape, a process of thinning the second semiconductor substrate 210 to a desired thickness, a cleaning process, etc. If necessary, the process may be performed, for example, when the second semiconductor substrate 210 is a bare wafer. In an embodiment, the second semiconductor substrate 210' may have a reduced thickness compared to the second semiconductor substrate 210 through the thinning process. However, the processing of the second semiconductor substrate 210 is optional and may be omitted, so in some embodiments, the second semiconductor substrate 210 and the second semiconductor substrate 210' may be the same or substantially the same.

[0029] Subsequently, a cell transistor and a peripheral circuit transistor may be formed. The cell transistor may include a cell gate pattern 220A formed on the second semiconductor substrate 210' in the cell region A, and a first cell source / drain region 232A and a second cell source / drain region 234A respectively formed in the second semiconductor substrate 210' on both sides of the cell gate pattern 220A. The peripheral circuit transistor may include a peripheral gate pattern 220B formed on the second semiconductor substrate 210' in the peripheral circuit region B, and a first peripheral source / drain region 232B and a second peripheral source / drain region 234B respectively formed in the second semiconductor substrate 210' on both sides of the peripheral gate pattern 220B.

[0030] The unit gate pattern 220A may include a stacked structure of a gate insulating layer 222A, a gate electrode layer 224A, and a gate hard mask layer 226A, and a gate spacer 228A covering the sidewall of the stacked structure. The peripheral gate pattern 220B may include a stacked structure of a gate insulating layer 222B, a gate electrode layer 224B, and a gate hard mask layer 226B, and a gate spacer 228B located on the sidewall of the stacked structure. The unit gate pattern 220A and the peripheral gate pattern 220B may be formed by the following steps: sequentially depositing a gate insulating material, a gate electrode material, and a gate hard mask material on the second semiconductor substrate 210', patterning the deposited materials, conformally depositing a gate spacer material on the patterned material and the second semiconductor substrate 210', and performing a blanket etching process on the gate spacer material to expose the upper surface of the second semiconductor substrate 210'. That is, the unit gate pattern 220A and the peripheral gate pattern 220B may be formed using the same process. However, the embodiments of the present disclosure are not limited thereto, and the unit gate pattern 220A and the peripheral gate pattern 220B may be formed using different processes. Figures 8 to 13 Give a description.

[0031] One of the first unit source / drain region 232A and the second unit source / drain region 234A may correspond to the source region, and the other of the first unit source / drain region 232A and the second unit source / drain region 234A may correspond to the drain region. One of the first peripheral source / drain region 232B and the second peripheral source / drain region 234B may correspond to the source region, and the other of the first peripheral source / drain region 232B and the second peripheral source / drain region 234B may correspond to the drain region. The first unit source / drain region 232A and the second unit source / drain region 234A and the first peripheral source / drain region 232B and the second peripheral source / drain region 234B may be formed by doping impurities into the second semiconductor substrate 210' exposed by the unit gate pattern 220A and the peripheral gate pattern 220B. That is, the first unit source / drain region 232A and the second unit source / drain region 234A and the first peripheral source / drain region 232B and the second peripheral source / drain region 234B can be formed using the same process. However, the embodiments of the present disclosure are not limited thereto, and the first unit source / drain region 232A and the second unit source / drain region 234A and the first peripheral source / drain region 232B and the second peripheral source / drain region 234B can be formed using different processes. This will be described later. Figures 8 to 13 Give a description.

[0032] One of the first unit source / drain region 232A and the second unit source / drain region 234A (e.g., the first unit source / drain region 232A) may be electrically connected to the second electrode 126 of the unit capacitor 120 through the first conductor 140. In an embodiment, the first unit source / drain region 232A may be formed at a position overlapping with the first conductor 140, and its depth is equal to the thickness of the second semiconductor substrate 210', so that the lower surface of the first unit source / drain region 232A may be in direct contact with the first conductor 140. However, the embodiments of the present disclosure are not limited thereto, and the depth or position of the first unit source / drain region 232A may be modified in various ways. When the lower surface of the first unit source / drain region 232A is not in direct contact with the first conductor 140, the first unit source / drain region 232A and the first conductor 140 may be electrically connected through another conductive member. The second unit source / drain region 234A and the first and second peripheral source / drain regions 232B and 234B may be formed to have substantially the same depth as the first unit source / drain region 232A, and therefore, they may have a lower surface that contacts the upper surface of the first insulating layer 130. However, the embodiments of the present disclosure are not limited thereto, and the depths of the first and second unit source / drain regions 232A and 234A and the first and second peripheral source / drain regions 232B and 234B may be modified in various ways. When the depths of the first and second unit source / drain regions 232A and 234A are the same as the thickness of the second semiconductor substrate 210', the channel of the unit transistor may be surrounded by the first and second unit source / drain regions 234A, 234A, and the first insulating layer 130. Therefore, the unit transistor can have the same / similar effects as the transistor formed on the SOI (silicon on insulator) substrate, such as the leakage current protection effect. Similarly, when the depth of the first peripheral source / drain region 232B and the second peripheral source / drain region 234B is the same as the thickness of the second semiconductor substrate 210', the channel of the peripheral circuit transistor can be surrounded by the first peripheral source / drain region 232B, the second peripheral source / drain region 234B and the first insulating layer 130, and thus, the leakage current protection effect can occur.

[0033] Subsequently, a second insulating layer 240 covering the cell gate pattern 220A and the peripheral gate pattern 220B may be formed over the second semiconductor substrate 210' in the cell region A and the peripheral circuit region B. Then, second to sixth conductors 252, 254, 262, 264, and 266 may be formed to pass through the second insulating layer 240 and be connected to the gate electrode layer 224A of the cell gate pattern 220A, the second cell source / drain region 234A, the first peripheral source / drain region 232B, the gate electrode layer 224B of the peripheral gate pattern 220B, and the second peripheral source / drain region 234B, respectively. For example, each of the second to sixth conductors 252, 254, 262, 264, and 266 may have a contact plug shape.

[0034] Subsequently, a wiring layer 270 may be formed over the second insulating layer 240. The wiring layer 270 may include conductive structures of various shapes and layers so that they are electrically connected to the second to sixth conductors 252, 254, 262, 264, and 266 and apply voltages thereto. For example, the wiring layer 270 may include contact plugs, conductive lines, or a combination thereof. For ease of description, the conductive structures in the wiring layer 270 are simply shown as boxes.

[0035] As a result, a semiconductor device in which the second semiconductor structure 200 is formed over the first semiconductor structure 100 may be manufactured.

[0036] Refer again Figure 3 The semiconductor device of the embodiment may include a first semiconductor structure 100 and a second semiconductor structure 200 . The second semiconductor structure 200 may be formed on the first semiconductor structure 100 .

[0037] The first semiconductor structure 100 may include a first semiconductor substrate 110 , a cell capacitor 120 formed over the first semiconductor substrate 110 in the cell region A, and a first insulating layer 130 formed over the first semiconductor substrate 110 in the cell region A and the peripheral circuit region B to cover the cell capacitor 120 .

[0038] The second semiconductor structure 200 may include: a second semiconductor substrate 210'; a cell transistor, including a cell gate pattern 220A formed on the second semiconductor substrate 210' in the cell area A and a first cell source / drain region 232A and a second cell source / drain region 234A formed in the second semiconductor substrate 210' on both sides of the cell gate pattern 220A; a peripheral circuit transistor, including a peripheral gate pattern 220B formed on the second semiconductor substrate 210' in the peripheral circuit area B and a first peripheral source / drain region 232B and a second peripheral source / drain region 234B formed in the second semiconductor substrate 210' on both sides of the peripheral gate pattern 220B; a second insulating layer 240, covering the cell gate pattern 220A and the peripheral gate pattern 220B on the semiconductor substrate 210' in the cell area A and the peripheral circuit area B; and a wiring layer 270 arranged on the second insulating layer 240.

[0039] The second semiconductor substrate 210 ′ may be bonded to an upper surface of the first insulating layer 130 , and thus the second semiconductor structure 200 may be physically connected to the first semiconductor structure 100 .

[0040] The first cell source / drain region 232A of the cell transistor may be electrically connected to the second electrode 126 of the cell capacitor 120 through the first conductor 140 located below the cell transistor. Here, the depth of the first cell source / drain region 232A may be the same as the thickness of the second semiconductor substrate 210', and thus, the first cell source / drain region 232A may have a lower surface directly in contact with the first conductor 140. The gate electrode layer 224A of the cell gate pattern 220A and the second cell source / drain region 234A may be electrically connected to the wiring layer 270 through the second conductor 252 and the third conductor 254 located thereon. The first peripheral source / drain region 232B, the gate electrode layer 224B of the peripheral gate pattern 220B, and the second peripheral source / drain region 234B may be electrically connected to the wiring layer 270 through the fourth to sixth conductors 262, 264, and 266 located thereon.

[0041] According to the above-described semiconductor device and the method for manufacturing the same, the following effects can be obtained.

[0042] First, since the cell transistor and the peripheral circuit transistor are formed after the cell capacitor 120 is formed, it is possible to prevent the high temperature heat treatment process used when forming the cell capacitor 120 from adversely affecting the characteristics of the cell transistor and the peripheral circuit transistor.

[0043] In addition, by adjusting the depth of the source / drain 232A and 234A of the unit transistor and / or the depth of the source / drain 232B and 234B of the peripheral circuit transistor, the same / similar effect as when the unit transistor and / or the peripheral circuit transistor are formed using an SOI substrate can be obtained.

[0044] In addition, in the peripheral circuit region B, the peripheral circuit transistor of the second semiconductor structure 200 may be electrically connected to the wiring layer 270 above it, and may not be electrically connected to the first semiconductor structure 100. That is, the space between the first semiconductor substrate 110 and the second semiconductor substrate 210' in the peripheral circuit region B may be filled with the first insulating layer 130. Therefore, by arranging various electronic components on the first semiconductor substrate 110 in the peripheral circuit region B, the area efficiency of the semiconductor device may be improved. For example, a decoupling capacitor may be arranged on the first semiconductor substrate 110 in the peripheral circuit region B, which will be referred to as Figures 4 to 6 Give a description.

[0045] Figures 4 to 6 1 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. The description will focus on the differences from the above-described embodiment.

[0046] First, the manufacturing method will be described.

[0047] Reference Figure 4 , a first semiconductor structure 300 including a cell region A and a peripheral circuit region B may be provided. The first semiconductor structure 300 may include a first semiconductor substrate 310, a cell capacitor 320A formed on the first semiconductor substrate 310 in the cell region A, a decoupling capacitor 320B formed on the first semiconductor substrate 310 in the peripheral circuit region B, and a first insulating layer 330 covering the cell capacitor 320A and the decoupling capacitor 320B on the first semiconductor substrate 310 in the cell region A and the peripheral circuit region B.

[0048] The unit capacitor 320A may include a first electrode 322A, a second electrode 326A, and a dielectric layer 324A interposed between the first electrode 322A and the second electrode 326A.

[0049] The decoupling capacitor 320B may include a first electrode 322B, a second electrode 326B, and a dielectric layer 324B between the first electrode 322B and the second electrode 326B. The decoupling capacitor 320B may be used to reduce noise between operating power supplies (eg, power supply voltage VDD, ground voltage VSS, etc.).

[0050] The decoupling capacitor 320B of the embodiment may include a plurality of first electrodes 322B having a columnar shape, a second electrode 326B overlapping the plurality of first electrodes 322B and surrounding the upper surface and sidewall of the first electrode 322B, and a dielectric layer 324B between the first electrode 322B and the second electrode 326B. For example, the dielectric layer 324B may have a shape surrounding the upper surface and sidewall of the plurality of first electrodes 322B and extending below the lower surface of the second electrode 326B. Each of the plurality of first electrodes 322B may correspond to a plate electrode, and the second electrode 326B may correspond to a storage electrode. Some of the plurality of first electrodes 322B may be electrically connected to a first power supply voltage V1, and others of the plurality of first electrodes 322B may be electrically connected to a second power supply voltage V2.

[0051] The unit capacitor 320A and the decoupling capacitor 320B may be formed using the same process. For example, the unit capacitor 320A and the decoupling capacitor 320B may be formed by the following steps: forming columnar first electrodes 322A and 322B by depositing a conductive material on the first semiconductor substrate 310 and patterning the conductive material, conformally depositing a dielectric material on the entire surface of the first semiconductor substrate 310 on which the first electrodes 322A and 322B are formed, depositing a conductive material having a thickness sufficient to cover the first electrodes 322A and 322B on the deposited dielectric material, and selectively etching the conductive material and the dielectric material to form second electrodes 326A and 326B and dielectric layers 324A and 324B. However, the embodiments of the present disclosure are not limited thereto, and as long as each of the unit capacitor 320A and the decoupling capacitor 320B includes a dielectric layer between the two electrodes, the structure or shape of the unit capacitor 320A and the decoupling capacitor 320B may be modified in a variety of ways. Even if the types of the unit capacitor 320A and the decoupling capacitor 320B are modified, the unit capacitor 320A and the decoupling capacitor 320B may be formed using the same process, and thus, process simplification is possible.

[0052] A conductive structure may be formed in the first semiconductor substrate 310 to be electrically connected to the first electrode 322A of the unit capacitor 320A to apply a predetermined voltage to the first electrode 322A. In addition, a conductive structure may be formed in the first semiconductor substrate 310 to be electrically connected to some of the plurality of first electrodes 322B of the decoupling capacitor 320B to apply a first power supply voltage V1 thereto, and to be electrically connected to other of the plurality of first electrodes 322B of the decoupling capacitor 320B to apply a second power supply voltage V2 thereto.

[0053] The first conductor 340 may be formed in the first insulating layer 330 to pass through the first insulating layer 330 and be electrically connected to the second electrode 326A of the cell capacitor 320A.

[0054] Reference Figure 5 , the second semiconductor substrate 410 may be formed on the first semiconductor structure 300 .

[0055] Reference Figure 6 , the second semiconductor substrate 410 may be processed to form a processed second semiconductor substrate 410 ′.

[0056] Subsequently, a cell transistor and a peripheral circuit transistor may be formed, the cell transistor including a cell gate pattern 420A formed on the second semiconductor substrate 410' in the cell region A and a first cell source / drain region 432A and a second cell source / drain region 434A formed in the second semiconductor substrate 410' on both sides of the cell gate pattern 420A, and a peripheral circuit transistor including a peripheral gate pattern 420B formed on the second semiconductor substrate 410' in the peripheral circuit region B and a first peripheral source / drain region 432B and a second peripheral source / drain region 434B formed in the second semiconductor substrate 410' on both sides of the peripheral gate pattern 420B. The cell gate pattern 420A may include a stacked structure of a gate insulating layer 422A, a gate electrode layer 424A, and a gate hard mask layer 426A, and a gate spacer 428A formed on a sidewall of the stacked structure. The peripheral gate pattern 420B may include a stack structure of a gate insulating layer 422B, a gate electrode layer 424B and a gate hard mask layer 426B and a gate spacer 428B formed on a sidewall of the stack structure. The first cell source / drain region 432A may be electrically connected to the second electrode 326A of the cell capacitor 320A through the first conductor 340 .

[0057] Subsequently, a second insulating layer 440 covering the cell gate pattern 420A and the peripheral gate pattern 420B may be formed over the second semiconductor substrate 410' in the cell region A and the peripheral circuit region B. Then, second to sixth conductors 452, 454, 462, 464, and 466 may be formed, the second to sixth conductors 452, 454, 462, 464, and 466 passing through the second insulating layer 440 and electrically connected to the gate electrode layer 424A of the cell gate pattern 420A, the second cell source / drain region 434A, the first peripheral source / drain region 432B, the gate electrode layer 424B of the peripheral gate pattern 420B, and the second peripheral source / drain region 434B, respectively. In addition, a seventh conductor 468 may be formed, the seventh conductor 468 passing through the second insulating layer 440, the second semiconductor substrate 410', and the first insulating layer 330 and electrically connected to the second electrode 326B of the decoupling capacitor 320B. The seventh conductor 468 may have a pillar shape in contact with the uppermost surface of the second electrode 326B, and may be formed using the same process as that of the second to sixth conductors 452 , 454 , 462 , 464 , and 466 .

[0058] Subsequently, a wiring layer 470 may be formed over the second insulating layer 440. The wiring layer 470 may be electrically connected to the second to seventh conductors 452, 454, 462, 464, 466, and 468, and apply a voltage thereto. Specifically, the wiring layer 470 may apply, for example, a ground voltage as a desired voltage to the second electrode 326B of the decoupling capacitor 320B through the seventh conductor 468.

[0059] As a result, a semiconductor device in which the second semiconductor structure 400 is formed over the first semiconductor structure 300 may be manufactured.

[0060] According to the semiconductor device and the manufacturing method thereof described above, during the process of forming the unit capacitor 320A, the decoupling capacitor 320B can be formed over the first semiconductor substrate 310 in the peripheral circuit region B. Therefore, the decoupling capacitor 320B can be obtained without increasing the process operation or increasing the area. As a result, the integration and characteristics of the semiconductor device can be significantly improved.

[0061] In the above embodiment, the first conductor is formed together in the process of forming the first semiconductor structure, but the embodiment of the present invention is not limited thereto. As long as the first conductor electrically connects the source / drain region of the cell transistor to the electrode of the cell capacitor, the order of the formation process of the first conductor or the shape of the first conductor may be modified in various ways. This will refer to Figure 7 Describe by example.

[0062] Figure 7 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. The description will focus on Figures 1 to 3 The difference between the embodiments of Figures 1 to 3 Components that are substantially the same as those of the embodiments will be denoted by the same reference numerals.

[0063] Reference Figure 7 , a first semiconductor structure 100 including a cell region A and a peripheral circuit region B may be provided. The first semiconductor structure 100 may include a first semiconductor substrate 110, a cell capacitor 120, and a first insulating layer 130, the cell capacitor 120 being formed on the first semiconductor substrate 110 in the cell region A and including a first electrode 122, a dielectric layer 124, and a second electrode 126, the first insulating layer 130 covering the cell capacitor 120 and the first semiconductor substrate 110 in the cell region A and the peripheral circuit region B.

[0064] Subsequently, a second semiconductor substrate 210 ′ may be formed on the first semiconductor structure 100 , and the second semiconductor substrate 210 ′ covers the first semiconductor structure 100 .

[0065] Subsequently, a cell transistor and a peripheral circuit transistor may be formed, the cell transistor including a cell gate pattern 220A formed on the second semiconductor substrate 210' in the cell region A and a first cell source / drain region 232A' and a second cell source / drain region 234A' formed in the second semiconductor substrate 210' on both sides of the cell gate pattern 220A, and a peripheral circuit transistor including a peripheral gate pattern 220B formed on the second semiconductor substrate 210' in the peripheral circuit region B and a first peripheral source / drain region 232B' and a second peripheral source / drain region 234B' formed in the second semiconductor substrate 210' on both sides of the peripheral gate pattern 220B. In an embodiment, the depth of the first source / drain region 232A' may be less than the thickness of the second semiconductor substrate 210'. In addition, the depths of the second cell source / drain region 234A' and the first peripheral source / drain region 232B' and the second peripheral source / drain region 234B' may be less than the thickness of the second semiconductor substrate 210'.

[0066] Subsequently, a first conductor 280 may be formed to overlap the first unit source / drain region 232A' and pass through the second semiconductor substrate 210' and the first insulating layer 130 to be electrically connected to the second electrode 126 of the unit capacitor 120. The first conductor 280 may be formed by selectively etching the second semiconductor substrate 210' and the first insulating layer 130 to form a hole exposing the upper surface of the second electrode 126 of the unit capacitor 120, depositing a conductive material with a thickness sufficient to fill the hole, and performing a planarization process to expose the upper surface of the second semiconductor substrate 210'. Thus, the upper surface of the first conductor 280 may be located at substantially the same height as the upper surface of the second semiconductor substrate 210', and a portion of the sidewall of the first conductor 280 may contact the first unit source / drain region 232A'. For example, a portion of the sidewall of the first conductor 280 may be surrounded by the first unit source / drain region 232A'.

[0067] The subsequent processes may be substantially the same as those described in the above embodiments.

[0068] According to the above-mentioned semiconductor device and the manufacturing method thereof, even if the depth of the first unit source / drain region 232A' is less than the thickness of the second semiconductor substrate 210', the first unit source / drain region 232A' and the second electrode 126 of the unit capacitor 120 can be electrically connected to each other using the first conductor 280 that passes through the second semiconductor substrate 210' and the first insulating layer 130.

[0069] In the above-described embodiments, the cell transistors and the peripheral circuit transistors are formed using the same process, so that the cell transistors and the peripheral circuit transistors of the same type (e.g., planar type) are formed. However, the embodiments of the present disclosure are not limited thereto, and the cell transistors and the peripheral circuit transistors may be formed separately using separate processes. In this case, not only the same type of cell transistors and the peripheral circuit transistors but also different types of cell transistors and the peripheral circuit transistors may be formed, and therefore, a semiconductor device including cell transistors and the peripheral circuit transistors having independently required characteristics may be realized. This will refer to Figures 8 to 13 Give a description.

[0070] Figures 8 to 11 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0071] Reference Figure 8 , a first semiconductor structure 100 including a cell region A and a peripheral circuit region B may be provided. The first semiconductor structure 100 may include a first semiconductor substrate 110, a cell capacitor 120, and a first insulating layer 130, the cell capacitor 120 being formed on the first semiconductor substrate 110 in the cell region A and including a first electrode 122, a dielectric layer 124, and a second electrode 126, the first insulating layer 130 covering the cell capacitor 120 on the first semiconductor substrate 110 in the cell region A and the peripheral circuit region B.

[0072] Subsequently, a second semiconductor substrate 510 may be formed over the first semiconductor structure 100 .

[0073] Subsequently, the first mask pattern M1 may cover the second semiconductor substrate 510 of the peripheral circuit region B. Thus, the second semiconductor substrate 510 of the cell region A may be exposed.

[0074] Reference Fig. 9 The second semiconductor substrate 510 exposed by the first mask pattern M1 may be selectively etched to form semiconductor fins 510A.

[0075] Subsequently, a gate insulating material and a gate electrode material may be deposited along the sidewalls and upper surface of the semiconductor fin 510A, and may be patterned to form a cell gate pattern 520A including a gate insulating layer 522A and a gate electrode layer 524A.

[0076] Subsequently, by doping impurities into the semiconductor fins 510A exposed by the cell gate pattern 520A to form source / drain regions, a FinFET structure may be formed. In this cross-sectional view, the source / drain regions are not shown for convenience of description.

[0077] Will refer to Fig.12The P1 portion including the semiconductor fin 510A, the cell gate pattern 520A, and the source / drain regions is described in more detail.

[0078] Fig.12 yes Fig. 9 An enlarged stereogram of portion P1. Fig. 9 The part P1 is Fig.12 A front view of the semiconductor fin 510A and the cell gate pattern 520A and may correspond to the Fig.12 A cross-sectional view along a first direction.

[0079] Reference Fig.12 , the semiconductor fin 510A may have a columnar shape in which the width in the first direction is less than the width in the second direction. The unit gate pattern 520A may surround the sidewall and the upper surface of the semiconductor fin 510A while crossing the semiconductor fin 510A in the first direction. Therefore, the semiconductor fin 510A may have a portion exposed by the unit gate pattern 520A and located on both sides of the unit gate pattern 520A in the second direction. Doping impurities into the exposed portion of the semiconductor fin 510A may be performed to form a first unit source / drain region 532A and a second unit source / drain region 534A in the semiconductor fin 510A on both sides of the unit gate pattern 520A. For example, the depth of the first unit source / drain region 532A and the second unit source / drain region 534A may be substantially the same as the thickness of the semiconductor fin 510A.

[0080] The first unit source / drain region 532A may be electrically connected to the first conductor 140 located therebelow. For example, a lower surface of the first source / drain region 532A may directly contact the first conductor 140. Except for a portion of the lower surface of the first source / drain region 532A that contacts the first conductor 140, a remaining portion of the lower surface of the first source / drain region 532A may contact an upper surface of the first insulating layer 130. As will be described later, as an example, the second unit source / drain region 534A of the semiconductor fin 510A may be electrically connected to a third conductor 554 located above the second unit source / drain region 534A.

[0081] Refer again Fig. 9 , a portion of the second semiconductor substrate 510 covered by the first mask pattern M1 may remain, as indicated by reference numeral 510B.

[0082] Reference Fig.10 After removing the first mask pattern M1, a second mask pattern M2 covering only the cell gate pattern 520A and the first insulating layer 130 in the cell region A may be formed. Thus, the second semiconductor substrate 510B in the peripheral circuit region B may be exposed.

[0083] Subsequently, a peripheral circuit transistor including a peripheral gate pattern 520B formed over the second semiconductor substrate 510B in the peripheral circuit region B may be formed. In addition, a first peripheral source / drain region 532B and a second peripheral source / drain region 534B may be formed at either side of the peripheral gate pattern 520B in the second semiconductor substrate 510B.

[0084] Reference Fig.11 After removing the second mask pattern M2 , the second insulating layer 540 may cover the cell gate pattern 520A and the peripheral gate pattern 520B over the first insulating layer 130 of the cell region A and the second semiconductor substrate 510B of the peripheral circuit region B.

[0085] Subsequently, second to sixth conductors 552, 554, 562, 564 and 566 may be formed, and the second to sixth conductors 552, 554, 562, 564 and 566 pass through the second insulating layer 540 and are respectively connected to the gate electrode layer 524A of the cell gate pattern 520A, the second cell source / drain region (see Fig.12 534A in the figure), a first peripheral source / drain region 532B, a gate electrode layer 524B of the peripheral gate pattern 520B, and a second peripheral source / drain region 534B.

[0086] Subsequently, a wiring layer 570 may be formed over the second insulating layer 540 .

[0087] As a result, a semiconductor device in which the second semiconductor structure 500 is formed over the first semiconductor structure 100 may be manufactured.

[0088] According to the above-mentioned semiconductor device and its manufacturing method, a cell transistor can be formed when a first mask pattern M1 covering the peripheral circuit area B is formed, and a peripheral circuit transistor can be formed when a second mask pattern M2 covering the cell area A is formed. Therefore, the cell transistor and the peripheral circuit transistor can be formed using different processes. As a result, different types of cell transistors and peripheral circuit transistors can be formed independently. For example, as in an embodiment, a semiconductor device including a fin-type cell transistor and a planar peripheral circuit transistor can be realized. The semiconductor device can be suitable for low-power devices. In addition, in an embodiment, the peripheral circuit transistor is formed after the cell transistor is formed, but the embodiments of the present disclosure are not limited thereto. In another embodiment, the peripheral circuit transistor can be first formed by covering the cell area A, and then the cell transistor can be formed by covering the peripheral circuit area B.

[0089] In the embodiment, the case where the FinFET structure is formed in the cell region A has been described, but the embodiments of the present disclosure are not limited thereto. Transistors of various structures using the semiconductor fin 510A as a channel may be formed in the cell region A. For example, a transistor may be formed in which a gate electrode surrounds the sidewall of the semiconductor fin 510A and a gate insulating layer is interposed between the gate electrode and the semiconductor fin 510A.

[0090] Fig.13 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0091] Reference Fig.13 , a first semiconductor structure 100 including a cell region A and a peripheral circuit region B may be provided. The first semiconductor structure 100 may include a first semiconductor substrate 110, a cell capacitor 120, and a first insulating layer 130, the cell capacitor 120 being formed on the first semiconductor substrate 110 in the cell region A and including a first electrode 122, a dielectric layer 124, and a second electrode 126, the first insulating layer 130 covering the cell capacitor 120 on the first semiconductor substrate 110 in the cell region A and the peripheral circuit region B.

[0092] Subsequently, a fin-type cell transistor may be formed on the first semiconductor structure 100 in the cell region A, and a fin-type peripheral circuit transistor may be formed on the first semiconductor structure 100 in the peripheral circuit region B. The cell transistor may include a cell semiconductor fin 610A and a cell gate pattern 620A. The cell gate pattern 620A may include a gate insulating layer 622A and a gate electrode 624A. The peripheral circuit transistor may include a peripheral semiconductor fin 610B and a peripheral gate pattern 620B. The peripheral gate pattern 620B may include a gate insulating layer 622B and a gate electrode 624B.

[0093] Here, even if the cell transistor and the peripheral circuit transistor have the same fin type, their formation materials or shapes may be different. As described below, this may be because the cell transistor and the peripheral circuit transistor are formed independently. For example, at least one of the thickness T1 and the width W1 of the cell semiconductor fin 610A of the cell transistor may be different from at least one of the thickness T2 and the width W2 of the peripheral semiconductor fin 610B of the peripheral circuit transistor. Thicknesses T1 and T2 may also be referred to as heights. When the thickness T2 of the peripheral semiconductor fin 610B of the peripheral circuit transistor is greater than the thickness T1 of the cell semiconductor fin 610A of the cell transistor, a high-performance semiconductor device can be achieved.

[0094] Since the process of forming unit transistors and peripheral circuit transistors is different Figures 8 to 13 The process is similar to that described in , so it will be briefly described below.

[0095] First, a second semiconductor substrate (not shown) may be formed on the first semiconductor structure 100, and then the second semiconductor substrate in the cell region A may be selectively etched to form a cell semiconductor fin 610A while covering the peripheral circuit region B. Then, a cell gate pattern 620A may be formed on the cell semiconductor fin 610A, and a source / drain region may be formed by doping impurities, thereby forming a cell transistor. Although not shown, the depth of the source / drain region may be the same as the thickness of the cell semiconductor fin 610A, similar to Fig.12 Described in .

[0096] Subsequently, the second semiconductor substrate in the peripheral circuit region B may be selectively etched to form a peripheral semiconductor fin 610B while covering the cell region A. Then, a peripheral gate pattern 620B may be formed on the peripheral semiconductor fin 610B, and a source / drain region may be formed by doping impurities to form a peripheral circuit transistor. Although not shown, the depth of the source / drain region may be the same as the thickness of the peripheral semiconductor fin 610B, similar to Fig.12 At this time, in order to increase the thickness T2 of the peripheral semiconductor fin 610B compared to the thickness T1 of the cell semiconductor fin 610A, the thickness of the second semiconductor substrate in the peripheral circuit region B exposed by the mask pattern covering the cell region A may be increased. The peripheral semiconductor fin 610B may be formed by selectively etching the second semiconductor substrate having the increased thickness. The thickness of the second semiconductor substrate in the peripheral circuit region B may be increased by additionally forming a semiconductor material on the second semiconductor substrate through deposition, epitaxial growth, etc.

[0097] Subsequent processes can be Fig.11 The process described in is essentially the same.

[0098] According to the above-described embodiments of the present disclosure, the integration degree and characteristics of a semiconductor device can be improved.

[0099] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present teachings as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A first semiconductor structure, comprising a cell region and a peripheral circuit region, a cell capacitor and a first insulating layer, wherein the cell capacitor is disposed in the cell region, and the first insulating layer is disposed in the cell region and the peripheral circuit region to cover the cell capacitor; A second semiconductor structure includes a cell transistor and a peripheral circuit transistor, wherein the cell transistor is disposed on the first insulating layer in the cell region, and the peripheral circuit transistor is disposed on the first insulating layer in the peripheral circuit region; as well as A first conductor passes through the first insulating layer to electrically connect a first cell source / drain region of the cell transistor with an electrode of the cell capacitor.

2. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a semiconductor substrate, the semiconductor substrate contacts an upper surface of the first insulating layer, The unit transistor includes a unit gate pattern and the first unit source / drain region and the second unit source / drain region, the unit gate pattern is arranged on the semiconductor substrate, and the first unit source / drain region and the second unit source / drain region are respectively formed in the semiconductor substrate on both sides of the unit gate pattern, and Wherein, a depth of each of the first unit source / drain region and the second unit source / drain region is equal to a thickness of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a semiconductor substrate, the semiconductor substrate contacts an upper surface of the first insulating layer, The peripheral circuit transistor includes a peripheral gate pattern and a first peripheral source / drain region and a second peripheral source / drain region, the peripheral gate pattern is arranged on the semiconductor substrate, and the first peripheral source / drain region and the second peripheral source / drain region are respectively formed in the semiconductor substrate on both sides of the peripheral gate pattern, and Wherein, a depth of each of the first peripheral source / drain region and the second peripheral source / drain region is equal to a thickness of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein: The second semiconductor structure includes a cell semiconductor fin, the cell semiconductor fin contacts an upper surface of the first insulating layer in the cell region, The cell transistor includes a cell gate pattern and the first cell source / drain region and the second cell source / drain region, the cell gate pattern surrounds the upper surface and sidewall of the cell semiconductor fin, and the first cell source / drain region and the second cell source / drain region are respectively formed in the cell semiconductor fin on both sides of the cell gate pattern, and Wherein, a depth of each of the first unit source / drain region and the second unit source / drain region is equal to a thickness of the unit semiconductor fin.

5. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a peripheral semiconductor fin, the peripheral semiconductor fin contacts the upper surface of the first insulating layer in the peripheral circuit region, wherein the peripheral circuit transistor comprises a peripheral gate pattern and a first peripheral source / drain region and a second peripheral source / drain region, the peripheral gate pattern surrounds the upper surface and sidewalls of the peripheral semiconductor fin, and the first peripheral source / drain region and the second peripheral source / drain region are respectively formed in the peripheral semiconductor fin on both sides of the peripheral gate pattern, and Wherein, a depth of each of the first peripheral source / drain region and the second peripheral source / drain region is equal to a thickness of the peripheral semiconductor fin.

6. The semiconductor device according to claim 1, wherein A lower surface of the first unit source / drain region contacts the first conductor.

7. The semiconductor device according to claim 1, wherein The first conductor also passes through the first cell source / drain region and has a sidewall contacting the first cell source / drain region.

8. The semiconductor device according to claim 1, wherein The second semiconductor structure further includes: a second insulating layer covering the cell transistor and the peripheral circuit transistor; and The second conductor to the sixth conductor pass through the second insulating layer and are respectively connected to the gate electrode of the unit transistor, the second unit source / drain region of the unit transistor, the first peripheral source / drain region of the peripheral circuit transistor, the gate electrode of the peripheral circuit transistor, and the second peripheral source / drain region of the peripheral circuit transistor.

9. The semiconductor device according to claim 1, wherein: The first semiconductor structure further includes a decoupling capacitor disposed in the first insulating layer in the peripheral circuit region.

10. The semiconductor device according to claim 9, wherein The second semiconductor structure further includes: a second insulating layer covering the cell transistor and the peripheral circuit transistor; second to sixth conductors passing through the second insulating layer and connected to the gate electrode of the cell transistor, the second cell source / drain region of the cell transistor, the first peripheral source / drain region of the peripheral circuit transistor, the gate electrode of the peripheral circuit transistor, and the second peripheral source / drain region of the peripheral circuit transistor, respectively; and A seventh conductor passes through the second insulating layer and the first insulating layer and is connected to an electrode of the decoupling capacitor.

11. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a semiconductor substrate, the semiconductor substrate contacts an upper surface of the first insulating layer, The unit transistor includes a unit gate pattern and the first unit source / drain region and the second unit source / drain region, the unit gate pattern is arranged on the semiconductor substrate, and the first unit source / drain region and the second unit source / drain region are respectively formed in the semiconductor substrate on both sides of the unit gate pattern, and In which, the peripheral circuit transistor includes a peripheral gate pattern and a first peripheral source / drain region and a second peripheral source / drain region, the peripheral gate pattern is arranged on the semiconductor substrate, and the first peripheral source / drain region and the second peripheral source / drain region are respectively formed in the semiconductor substrate on both sides of the peripheral gate pattern.

12. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a unit semiconductor fin and a semiconductor substrate, the unit semiconductor fin contacts an upper surface of the first insulating layer in the unit region, and the semiconductor substrate contacts the upper surface of the first insulating layer in the peripheral circuit region, The cell transistor includes a cell gate pattern and the first cell source / drain region and the second cell source / drain region, the cell gate pattern surrounds the upper surface and sidewall of the cell semiconductor fin, and the first cell source / drain region and the second cell source / drain region are respectively formed in the cell semiconductor fin on both sides of the cell gate pattern, and In which, the peripheral circuit transistor includes a peripheral gate pattern and a first peripheral source / drain region and a second peripheral source / drain region, the peripheral gate pattern is arranged on the semiconductor substrate, and the first peripheral source / drain region and the second peripheral source / drain region are respectively formed in the semiconductor substrate on both sides of the peripheral gate pattern.

13. The semiconductor device according to claim 1, wherein The second semiconductor structure includes a cell semiconductor fin and a peripheral semiconductor fin, the cell semiconductor fin contacts an upper surface of the first insulating layer in the cell region, and the peripheral semiconductor fin contacts the upper surface of the first insulating layer in the peripheral circuit region, The cell transistor includes a cell gate pattern and the first cell source / drain region and the second cell source / drain region, the cell gate pattern surrounds the upper surface and sidewall of the cell semiconductor fin, and the first cell source / drain region and the second cell source / drain region are respectively formed in the cell semiconductor fin on both sides of the cell gate pattern, and In which, the peripheral circuit transistor includes a peripheral gate pattern and a first peripheral source / drain region and a second peripheral source / drain region, the peripheral gate pattern surrounds the upper surface and side wall of the peripheral semiconductor fin, and the first peripheral source / drain region and the second peripheral source / drain region are respectively formed in the peripheral semiconductor fin on both sides of the peripheral gate pattern.

14. The semiconductor device according to claim 13, wherein: At least one of a thickness and a width of the unit semiconductor fin and at least one of a thickness and a width of the peripheral semiconductor fin are different from each other.

15. A method for manufacturing a semiconductor device, the method comprising: Providing a first semiconductor structure, the first semiconductor structure comprising a cell region and a peripheral circuit region, a cell capacitor and a first insulating layer, the cell capacitor being disposed in the cell region, and the first insulating layer being disposed in the cell region and the peripheral circuit region to cover the cell capacitor; bonding a semiconductor substrate to an upper surface of the first insulating layer; Using the semiconductor substrate, forming a cell transistor in the cell region and forming a peripheral circuit transistor in the peripheral circuit region; as well as A conductor is formed that passes through the first insulating layer and connects the first source / drain region of the cell transistor with an electrode of the cell capacitor.

16. The method according to claim 15, wherein: forming the conductor is performed before bonding the semiconductor substrate, and The semiconductor substrate contacts an upper surface of the conductor.

17. The method according to claim 15, wherein: After forming the unit transistor, forming the conductor is performed such that the conductor further passes through the first source / drain region of the unit transistor.

18. The method according to claim 15, wherein: Forming the cell transistor includes: forming a source / drain region by doping impurities into a semiconductor substrate or a semiconductor fin of the cell region, wherein the semiconductor fin is formed by selectively etching the semiconductor substrate of the cell region, and The depth of the source / drain region is equal to the thickness of the semiconductor substrate or the semiconductor fin.

19. The method according to claim 15, wherein: Forming the peripheral circuit transistor includes: forming source / drain regions by doping impurities into the semiconductor substrate or semiconductor fins of the peripheral circuit region, the semiconductor fins being formed by selectively etching the semiconductor substrate of the peripheral circuit region, and The depth of the source / drain region is equal to the thickness of the semiconductor substrate or the semiconductor fin.

20. The method according to claim 15, wherein: The cell transistor is formed in a state where a first mask pattern covering the semiconductor substrate in the peripheral circuit region is formed, and The peripheral circuit transistor is formed in a state where a second mask pattern covering the semiconductor substrate in the cell region is formed.

21. The method according to claim 15, wherein: Forming the unit transistor includes: forming a unit gate pattern on the semiconductor substrate; and forming a first unit source / drain region and a second unit source / drain region in the semiconductor substrate on both sides of the unit gate pattern, respectively, and The forming of the peripheral circuit transistor includes: forming a peripheral gate pattern on the semiconductor substrate; and forming a first peripheral source / drain region and a second peripheral source / drain region in the semiconductor substrate on both sides of the peripheral gate pattern.

22. The method according to claim 15, wherein: The forming of the unit transistor comprises: forming a unit semiconductor fin by etching the semiconductor substrate of the unit area while the peripheral circuit area is covered; forming a unit gate pattern along the upper surface and sidewall of the unit semiconductor fin; and forming a first unit source / drain region and a second unit source / drain region in the unit semiconductor fin on both sides of the unit gate pattern, respectively, and Among them, forming the peripheral circuit transistor includes: forming a peripheral gate pattern on the semiconductor substrate in the peripheral circuit area while the unit area is covered; and forming a first peripheral source / drain area and a second peripheral source / drain area in the semiconductor substrate on both sides of the peripheral gate pattern, respectively.

23. The method according to claim 15, wherein: The forming of the unit transistor comprises: forming a unit semiconductor fin by etching the semiconductor substrate of the unit area while the peripheral circuit area is covered; forming a unit gate pattern along the upper surface and sidewall of the unit semiconductor fin; and forming a first unit source / drain region and a second unit source / drain region in the unit semiconductor fin on both sides of the unit gate pattern, respectively, and Among them, forming the peripheral circuit transistor includes: forming a peripheral semiconductor fin by etching the semiconductor substrate of the peripheral circuit area while the unit area is covered; forming a peripheral gate pattern along the upper surface and side wall of the peripheral semiconductor fin; and respectively forming a first peripheral source / drain region and a second peripheral source / drain region in the peripheral semiconductor fin on both sides of the peripheral gate pattern.

24. The method according to claim 15, wherein: The first semiconductor structure further includes a decoupling capacitor disposed in the first insulating layer in the peripheral circuit region.

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