Three-dimensional Ga2O3 heterojunction diode and its preparation method

Abstract

The present invention discloses a three-dimensional Ga2O3 heterojunction diode and a method for preparing the same, comprising: providing a substrate, sequentially growing a p+-type NiO epitaxial layer and an alkaline-earth-doped silicon oxide layer on its surface; windowing the alkaline-earth-doped silicon oxide layer to form multiple spaced windows, and then reflowing the remaining alkaline-earth-doped silicon oxide layer using a rapid thermal annealing process to form a hemispherical mask; etching the p+-type NiO epitaxial layer using the hemispherical mask to form multiple hemispherical structures; growing an n+-type Ga2O3 epitaxial layer on the device's upper surface, and performing ion implantation into multiple sub-regions therein to form an n+-type electron transport layer; windowing the source electrode region of the n+-type Ga2O3 epitaxial layer on the surface of the hemispherical structure in the source region, and growing a field oxygen passivation layer on the device's upper surface; removing the field oxygen passivation layer in the source region to window the source electrode region, forming a front electrode on the upper surface of the source region and a back electrode on the lower surface of the substrate. The diode has excellent voltage-resistance balance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a three-dimensional Ga2O3 heterojunction diode and a preparation method thereof. Background Art

[0002] Super junction (SJ) devices are a new type of power semiconductor device that combines the excellent properties of silicon carbide materials and the advantages of super junction structures. They have good application prospects in electric vehicles, renewable energy, industrial power supplies and consumer electronics.

[0003] Gallium oxide is a third-generation wide-bandgap semiconductor material with an ultra-wide bandgap (4.8-5.3eV) and an ultra-high breakdown electric field (8MV / cm). Its power factor (BFOM) far exceeds that of silicon and silicon carbide, making it suitable for high-voltage, high-efficiency power electronics. Gallium oxide single crystals can be grown using a low-cost melt growth method and exhibit low reverse leakage current, high-temperature stability, and excellent breakdown performance, making them suitable for use in superjunction devices.

[0004] However, there is no reliable P-type material for gallium oxide, and it can only form a superjunction structure through heterojunction. The conventional lateral heterojunction structure used in the existing technology is not conducive to improving the blocking pressure bearing capacity of the device; in addition, the thermal conductivity of gallium oxide is low and cannot meet the requirements of high power density applications. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, the present invention provides a three-dimensional Ga2O3 heterojunction superjunction diode and a method for fabricating the same. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode, comprising:

[0007] Providing an n+ type SiC substrate, and sequentially growing a p+ type NiO epitaxial layer and an alkaline earth doped silicon oxide layer on the surface of the n+ type SiC substrate;

[0008] Opening windows in the alkaline earth doped silicon oxide layer to form a plurality of spaced windows, and then reflowing the remaining alkaline earth doped silicon oxide layer using a rapid thermal annealing process to form a hemispherical mask;

[0009] The p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask to form a plurality of hemispherical structures arranged at intervals; wherein the hemispherical structure with the largest diameter is located in the transition region of the device, and the two sides of the transition region are the source region and the terminal region of the device respectively;

[0010] An n+-type Ga2O3 epitaxial layer is epitaxially grown on the upper surface of the device, and ion implantation is performed on multiple sub-regions of the n+-type Ga2O3 epitaxial layer to form an n+-type electron transport layer; in a direction perpendicular to the plane of the n+-type SiC substrate, the orthographic projection of the sub-region is located between the orthographic projections of two adjacent hemispherical structures in the source region, or between the orthographic projection of the hemispherical structure in the source region and the orthographic projection of the hemispherical structure in the transition region;

[0011] Opening a source electrode region window on the n+ type Ga2O3 epitaxial layer located on the surface of the hemispherical structure in the source region of the device, growing a field oxygen passivation layer on the upper surface of the device, and forming an ohmic contact on the lower surface of the n+ type SiC substrate;

[0012] The field oxide passivation layer in the source region is removed to open a window in the source region electrode region, a Schottky contact and a front electrode are formed on the upper surface of the device source region, and a back electrode is formed on the lower surface of the n+ type SiC substrate.

[0013] In one embodiment of the present invention, after opening windows in the alkaline earth doped silicon oxide layer to form a plurality of spaced windows, the step of reflowing the remaining alkaline earth doped silicon oxide layer using a rapid thermal annealing process to form a hemispherical mask includes:

[0014] The alkaline earth doped silicon oxide layer is opened by photolithography and etching processes to form a plurality of windows arranged at intervals; wherein, in a direction perpendicular to the plane of the n+ type SiC substrate, the orthographic projection of the windows is a square, and the side length of the square is 6 to 20 μm;

[0015] Under the conditions of an annealing temperature of 900-1000° C. and a time of 120-180 seconds, the remaining alkaline earth doped silicon oxide layer is reflowed by a rapid thermal annealing process to form a hemispherical mask.

[0016] In one embodiment of the present invention, the n+ type Ga2O3 epitaxial layer and the p+ type NiO epitaxial layer maintain a charge balance state.

[0017] In one embodiment of the present invention, the thickness of the n+ type SiC substrate is 350 μm and the doping concentration is 5×10 18 cm -3 The thickness of the p+ type NiO epitaxial layer is 6 to 20 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 The thickness of the alkaline earth doped silicon oxide layer is 6 to 20 μm, the thickness of the n+ type Ga2O3 epitaxial layer is 4 to 28 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 .

[0018] In one embodiment of the present invention, when the p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask, the etching selectivity is 1.

[0019] In one embodiment of the present invention, the step of forming an ohmic contact on the lower surface of the n+ type SiC substrate includes:

[0020] Depositing Ni metal with a thickness of 75 to 100 nm on the lower surface of the n+ type SiC substrate using an electron beam evaporation process;

[0021] Under the conditions of an annealing temperature of 950 to 1050° C. and an annealing time of 120 to 300 seconds, an ohmic contact is formed on the lower surface of the n+ type SiC substrate by using a rapid thermal annealing process.

[0022] In one embodiment of the present invention, the steps of removing the field oxide passivation layer in the source region, opening a window in the source electrode region, forming a Schottky contact on the upper surface of the device source region, and forming a front electrode include:

[0023] Using photolithography and wet etching processes, the field oxide passivation layer in the source region is removed to open a window in the source electrode region;

[0024] Deposit Schottky metal Ti or Ni on the upper surface of the device using electron beam evaporation or magnetron sputtering technology;

[0025] A Schottky pattern is formed by a photolithography process, and a Schottky contact is formed by a rapid thermal annealing process at an annealing temperature of 400 to 600° C. and an annealing time of 5 to 10 minutes.

[0026] Al is deposited on the upper surface of the device using electron beam evaporation or magnetron sputtering technology, and a front electrode is formed on the upper surface of the source region of the device using photolithography and wet etching technology.

[0027] In one embodiment of the present invention, before the step of forming a back electrode on the lower surface of the n+ type SiC substrate, the method further includes:

[0028] A polyimide PI passivation layer with a thickness of 6 mm is formed on the upper surface of the field oxide passivation layer in the transition zone and the terminal zone.

[0029] In one embodiment of the present invention, the step of forming a back electrode on the lower surface of the n+ type SiC substrate includes:

[0030] Ti / Ni / Ag with a thickness of 200 nm / 200 nm / 1000 nm was deposited on the lower surface of the n+ type SiC substrate using an electron beam evaporation process to form a back electrode.

[0031] In a second aspect, the present invention further provides a three-dimensional Ga2O3 heterojunction superjunction diode, which is manufactured using the method described in the first aspect.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] This invention provides a three-dimensional Ga2O3 heterojunction superjunction diode and its fabrication method. The resulting superjunction diode has a three-dimensional structure and exhibits a slower electric field extension than existing two-dimensional structures. This results in a better voltage-resistance balance and lower resistance at the same voltage level. Furthermore, the invention utilizes an n+-type SiC substrate during the fabrication process. SiC, with its high thermal conductivity, facilitates heat dissipation, further enhancing the performance of the three-dimensional Ga2O3 heterojunction diode.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a flow chart of a method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode provided by an embodiment of the present invention;

[0036] Figures 2 to 12 This is a schematic diagram of the preparation process of the three-dimensional Ga2O3 heterojunction superjunction diode provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0038] Figure 1 This is a flow chart of a method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode provided by an embodiment of the present invention. Figures 2 to 12 Schematic diagram of the preparation process of the three-dimensional Ga2O3 heterojunction superjunction diode provided by the embodiment of the present invention. Figures 1 to 12 As shown, an embodiment of the present invention provides a method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode, comprising:

[0039] S1. Provide an n+ type SiC substrate 1, and sequentially grow a p+ type NiO epitaxial layer 2 and an alkaline earth doped silicon oxide layer 3 on the surface of the n+ type SiC substrate 1;

[0040] S2, after opening windows in the alkaline earth doped silicon oxide layer 3 to form a plurality of spaced windows 4, the remaining alkaline earth doped silicon oxide layer 3 is reflowed by a rapid thermal annealing process to form a hemispherical mask 5;

[0041] S3. Etching the p+-type NiO epitaxial layer 2 using a dry etching process and a hemispherical mask 5 to form a plurality of hemispherical structures 6 arranged at intervals; wherein the hemispherical structure 6 with the largest diameter is located in the transition region of the device, and the two sides of the transition region are the source region and the terminal region of the device respectively;

[0042] S4. Epitaxially grow an n+ type Ga2O3 epitaxial layer 7 on the upper surface of the device, and perform ion implantation on multiple sub-regions of the n+ type Ga2O3 epitaxial layer 7 to form an n+ type electron transport layer 8; in a direction perpendicular to the plane of the n+ type SiC substrate 1, the orthographic projection of the sub-region is located between the orthographic projections of two adjacent hemispherical structures 6 in the source region, or between the orthographic projection of the hemispherical structure 6 in the source region and the orthographic projection of the hemispherical structure 6 in the transition region;

[0043] S5, opening a source electrode region window in the n+ type Ga2O3 epitaxial layer 7 located on the surface of the hemispherical structure 6 in the source region of the device, growing a field oxide passivation layer 9 on the upper surface of the device, and forming an ohmic contact on the lower surface of the n+ type SiC substrate 1;

[0044] S6. Remove the field oxide passivation layer 9 in the source region to open a window in the source electrode region, form a Schottky contact and a front electrode 10 on the upper surface of the device source region, and form a back electrode 11 on the lower surface of the n+ type SiC substrate 1.

[0045] It should be understood that existing two-dimensional superjunction structures can be decomposed into a superposition of electric field vectors in both the lateral and longitudinal directions. Excessive extension of the electric field in either direction will cause device avalanche breakdown. The superjunction diode prepared by the above-described method in the present invention is a three-dimensional structure, which can achieve better PN junction depletion and high vertical electric field controllability. Compared with two-dimensional structures, it has a slower electric field extension capability, thus achieving better voltage-resistance balance and lower resistance under the same voltage level conditions. Furthermore, because the heat dissipation performance of power devices can also affect device reliability, the present invention uses an n+-type SiC substrate during the preparation process. SiC, a material with high thermal conductivity, facilitates heat dissipation, further improving the performance of the three-dimensional Ga2O3 heterojunction superjunction diode.

[0046] Optionally, in this embodiment, the thickness of the n+ type SiC substrate 1 is 350 μm, and the doping concentration is 5×10 18 cm -3 The thickness of the p+ type NiO epitaxial layer 2 is 6 to 20 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 The thickness of the alkaline earth doped silicon oxide layer 3 is 6 to 20 μm.

[0047] like Figures 3-5As shown, in step S2, after opening windows in the alkaline earth doped silicon oxide layer 3 to form a plurality of spaced windows 4, the remaining alkaline earth doped silicon oxide layer 3 is reflowed by a rapid thermal annealing process to form a hemispherical mask 5, including:

[0048] S201, using photolithography and etching processes to open windows in the alkaline earth-doped silicon oxide layer 3 to form a plurality of windows 4 arranged at intervals; wherein, in a direction perpendicular to the plane of the n+ type SiC substrate 1, the orthographic projection of the window 4 is a square, and the side length of the square is 6 to 20 μm;

[0049] S202 , under the conditions of an annealing temperature of 900-1000° C. and a time of 120-180 seconds, use a rapid thermal annealing process to reflow the remaining alkaline earth doped silicon oxide layer 3 to form a hemispherical mask 5 .

[0050] Specifically, first, the alkaline earth doped silicon oxide layer 3 is opened by photolithography and etching process, and the formed multiple windows 4 are arranged at intervals. Figure 4 Under the viewing angle shown, the vertical projection of each window 4 is a square. Figure 4 Here, only six windows 4 are used as an example. In practice, this application does not limit the number or shape of windows 4. Next, a rapid thermal annealing process is performed at a temperature of 900-1000°C for 120-180 seconds. During this process, the alkaline earth-doped silicon oxide layer 3 remaining after etching in step S201, i.e., the alkaline earth-doped silicon oxide layer 3 between two adjacent windows 4, reflows to form a hemispherical mask 5.

[0051] Furthermore, in step S3 , when the p + -type NiO epitaxial layer 2 is etched using the dry etching process and the hemispherical mask 5 , the etching selectivity is 1.

[0052] Still Figure 4 For example, it is worth noting that Figure 4 The six windows 4 divide the remaining alkaline earth doped silicon oxide layer 3 into five parts. The alkaline earth doped silicon oxide layer 3 in each part is reflowed to form a hemispherical mask 5. Among them, the hemispherical mask 5 formed by the reflow of the alkaline earth doped silicon oxide layer 3 in the middle part has the largest width in the horizontal direction. Therefore, when the etching selectivity is 1, five hemispherical structures 6 (such as Figure 6 As shown), similarly, the hemispherical structure 6 in the middle is the largest and is located in the transition region of the device, with the source region and the terminal region being on its left and right sides.

[0053] In addition, it should be noted that if more windows 4 are etched in step S2, more hemispherical structures 6 will be formed accordingly. At this time, the hemispherical structure 6 located in the middle position is still the largest in size. It is located in the transition zone, and the left and right sides are the source region and terminal region of the device respectively.

[0054] See Figure 7 In step S4, an n+ type Ga2O3 epitaxial layer 7 is epitaxially grown on the upper surface of the device. The n+ type Ga2O3 epitaxial layer 7 covers the surface of the above-mentioned multiple hemispherical structures 6 and is wavy. The thickness of the layer is 4 to 28 μm and the doping concentration is 2×10 16 ~6×10 16 cm -3 By designing the thickness and doping concentration of the p+ type NiO epitaxial layer 2 and the n+ type Ga2O3 epitaxial layer 7, the two can be kept in a charge balance state to avoid premature breakdown of the device.

[0055] The n+ type Ga2O3 epitaxial layer 7 includes multiple sub-regions. Specifically, the sub-regions are located in the n+ type Ga2O3 epitaxial layer 7 between two adjacent hemispherical structures 6 in the source region, and in the n+ type Ga2O3 epitaxial layer 7 between two hemispherical structures 6 at the junction of the source region and the transition region. By using the ion implantation process to implant into each sub-region, an n+ type electron transport layer 8 can be formed with a concentration of 1×10 18 ~5×10 18 cm -3 , and finally high temperature ion implantation activation is performed.

[0056] Furthermore, in step S5, a dry etching process is used to open a window in the source electrode region of the n+ type Ga2O3 epitaxial layer 7 on the surface of the hemispherical structure 6 in the source region of the device, followed by sacrificial oxidation, and a field oxygen passivation layer 9 is grown on the upper surface of the device using a PECVD process.

[0057] The step of forming an ohmic contact on the lower surface of the n+ type SiC substrate 1 includes:

[0058] S501, using electron beam evaporation process to deposit Ni metal with a thickness of 75 to 100 nm on the lower surface of the n+ type SiC substrate 1;

[0059] S502 , forming an ohmic contact on the lower surface of the n + -type SiC substrate 1 by using a rapid thermal annealing process under the conditions of an annealing temperature of 950-1050° C. and an annealing time of 120-300 s.

[0060] like Figures 10-11 As shown, in step S6, the field oxide passivation layer 9 in the source region is removed to open a window in the source region electrode region, and a Schottky contact is formed on the upper surface of the device source region and a front electrode 10 is formed, including:

[0061] S601, using photolithography and wet etching processes to remove the field oxide passivation layer 9 in the source region to open a window in the source electrode region;

[0062] S602, depositing Schottky metal Ti or Ni on the upper surface of the device by electron beam evaporation or magnetron sputtering process;

[0063] S603, forming a Schottky pattern by using a photolithography process, and forming a Schottky contact by performing a rapid thermal annealing process at an annealing temperature of 400-600° C. and an annealing time of 5-10 minutes;

[0064] S604 , using electron beam evaporation or magnetron sputtering technology to deposit Al on the upper surface of the device, and using photolithography and wet etching technology to form a front electrode 10 on the upper surface of the source region of the device.

[0065] Alternatively, as Figure 12 As shown, before the step of forming the back electrode 11 on the lower surface of the n+ type SiC substrate 1, the following steps are further included:

[0066] A polyimide PI passivation layer 12 is formed on the upper surface of the field oxide passivation layer 9 in the transition region and the terminal region, with a thickness of 6 mm.

[0067] The step of forming a back electrode 11 on the lower surface of the n+ type SiC substrate 1 includes:

[0068] Using an electron beam evaporation process, Ti / Ni / Ag with a thickness of 200 nm / 200 nm / 1000 nm is deposited on the lower surface of the n + -type SiC substrate 1 to form a back electrode 11 .

[0069] On the other hand, Figure 12 As shown, the present invention also provides a three-dimensional Ga2O3 heterojunction super junction diode, which is prepared using the above-mentioned preparation method of the three-dimensional Ga2O3 heterojunction super junction diode.

[0070] It can be seen from the above embodiments that the beneficial effects of the present invention are:

[0071] This invention provides a three-dimensional Ga2O3 heterojunction superjunction diode and its fabrication method. The resulting superjunction diode has a three-dimensional structure and exhibits a slower electric field extension than existing two-dimensional structures. This results in a better voltage-resistance balance and lower resistance at the same voltage level. Furthermore, the invention utilizes an n+-type SiC substrate during the fabrication process. SiC, with its high thermal conductivity, facilitates heat dissipation, further enhancing the performance of the three-dimensional Ga2O3 heterojunction diode.

[0072] In the description of the present invention, reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0073] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode, characterized in that: include: Providing an n+ type SiC substrate, and sequentially growing a p+ type NiO epitaxial layer and an alkaline earth doped silicon oxide layer on the surface of the n+ type SiC substrate; Opening windows in the alkaline earth doped silicon oxide layer to form a plurality of spaced windows, and then reflowing the remaining alkaline earth doped silicon oxide layer using a rapid thermal annealing process to form a hemispherical mask; The p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask to form a plurality of hemispherical structures arranged at intervals; wherein the hemispherical structure with the largest diameter is located in the transition region of the device, and the two sides of the transition region are the source region and the terminal region of the device respectively; An n+-type Ga2O3 epitaxial layer is epitaxially grown on the upper surface of the device, and ion implantation is performed on multiple sub-regions of the n+-type Ga2O3 epitaxial layer to form an n+-type electron transport layer; in a direction perpendicular to the plane of the n+-type SiC substrate, the orthographic projection of the sub-region is located between the orthographic projections of two adjacent hemispherical structures in the source region, or between the orthographic projection of the hemispherical structure in the source region and the orthographic projection of the hemispherical structure in the transition region; Opening a source electrode region window on the n+ type Ga2O3 epitaxial layer located on the surface of the hemispherical structure in the source region of the device, growing a field oxygen passivation layer on the upper surface of the device, and forming an ohmic contact on the lower surface of the n+ type SiC substrate; The field oxide passivation layer in the source region is removed to open a window in the source region electrode region, a Schottky contact and a front electrode are formed on the upper surface of the device source region, and a back electrode is formed on the lower surface of the n+ type SiC substrate.

2. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 1, characterized in that: After opening windows in the alkaline earth doped silicon oxide layer to form a plurality of spaced windows, the remaining alkaline earth doped silicon oxide layer is reflowed by a rapid thermal annealing process to form a hemispherical mask, comprising: The alkaline earth doped silicon oxide layer is opened by photolithography and etching processes to form a plurality of windows arranged at intervals; wherein, in a direction perpendicular to the plane of the n+ type SiC substrate, the orthographic projection of the windows is a square, and the side length of the square is 6 to 20 μm; Under the conditions of an annealing temperature of 900-1000° C. and a time of 120-180 seconds, the remaining alkaline earth doped silicon oxide layer is reflowed by a rapid thermal annealing process to form a hemispherical mask.

3. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 1, characterized in that: The n+ type Ga2O3 epitaxial layer and the p+ type NiO epitaxial layer maintain a charge balance state.

4. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 3, characterized in that: The thickness of the n+ type SiC substrate is 350 μm and the doping concentration is 5×10 18 cm -3 The thickness of the p+ type NiO epitaxial layer is 6 to 20 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 The thickness of the alkaline earth doped silicon oxide layer is 6 to 20 μm, the thickness of the n+ type Ga2O3 epitaxial layer is 4 to 28 μm, and the doping concentration is 2×10 16 ~6×10 16 cm -3 .

5. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 1, characterized in that: When the p+ type NiO epitaxial layer is etched using a dry etching process and the hemispherical mask, the etching selectivity is 1.

6. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 1, characterized in that: The step of forming an ohmic contact on the lower surface of the n+ type SiC substrate comprises: Depositing Ni metal with a thickness of 75 to 100 nm on the lower surface of the n+ type SiC substrate using an electron beam evaporation process; Under the conditions of an annealing temperature of 950 to 1050° C. and an annealing time of 120 to 300 seconds, an ohmic contact is formed on the lower surface of the n+ type SiC substrate by using a rapid thermal annealing process.

7. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 1, characterized in that: The steps of removing the field oxide passivation layer in the source region to open a window in the source electrode region, forming a Schottky contact on the upper surface of the device source region and forming a front electrode include: Using photolithography and wet etching processes, the field oxide passivation layer in the source region is removed to open a window in the source electrode region; Deposit Schottky metal Ti or Ni on the upper surface of the device using electron beam evaporation or magnetron sputtering technology; A Schottky pattern is formed by a photolithography process, and a Schottky contact is formed by a rapid thermal annealing process at an annealing temperature of 400 to 600° C. and an annealing time of 5 to 10 minutes. Al is deposited on the upper surface of the device using electron beam evaporation or magnetron sputtering technology, and a front electrode is formed on the upper surface of the source region of the device using photolithography and wet etching technology.

8. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 7, characterized in that: Before the step of forming a back electrode on the lower surface of the n+ type SiC substrate, the method further includes: A polyimide PI passivation layer with a thickness of 6 mm is formed on the upper surface of the field oxide passivation layer in the transition zone and the terminal zone.

9. The method for preparing a three-dimensional Ga2O3 heterojunction superjunction diode according to claim 8, characterized in that: The step of forming a back electrode on the lower surface of the n+ type SiC substrate comprises: Ti / Ni / Ag with a thickness of 200 nm / 200 nm / 1000 nm was deposited on the lower surface of the n+ type SiC substrate using an electron beam evaporation process to form a back electrode.

10. A three-dimensional Ga2O3 heterojunction superjunction diode, characterized in that: The method according to any one of claims 1 to 9 is used to prepare the product.

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