Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the device comprises a substrate which comprises a source region and a drain region which are arranged at intervals; the top surface of the substrate comprises a gate structure located between the source region and the drain region, and the gate structure comprises a gate dielectric layer, a composite work function layer and a gate material layer which are sequentially stacked in the first direction away from the substrate. The composite work function layer at least comprises a first work function adjusting structure and a second work function adjusting structure which are arranged along a second direction parallel to the substrate and have different work function values; wherein the first work function adjusting structure and the second work function adjusting structure respectively comprise work function material lamination structures with different lamination numbers along the first direction. Through enabling the composite work function layer to have different work function values in different regions in the transverse direction, the semiconductor device can resist different intensities of an electric field in the transverse direction, and the breakdown voltage of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] With the technological iteration of CMOS, SiO2 gate dielectrics and polysilicon gate transistors have reached their physical limits. For example, the excessive leakage current and polysilicon depletion caused by the quantum tunneling effect seriously affect the performance of the device. Therefore, the HKMG (High-k Metal Gate) process is gradually introduced, which includes a metal gate, a high dielectric constant layer, and a metal work function layer. Since the HKMG process has a Fermi level pinning effect, that is, the work function is pulled to the center of the bandgap, reducing the adjustment ability and gate control ability of the threshold voltage Vt, it is necessary to add a metal work function layer between the high dielectric constant layer and the metal gate to solve the Fermi level pinning effect.

[0003] The work function of the metal work function layer is different, and the flat band voltage of the device is different, and the threshold voltage of the device is also different. The metal work function layer of NMOS (N-Metal-Oxide-Semiconductor) is an N-type metal work function layer, and the work function of the N-type metal work function layer usually depletes the bottom of the conduction band of the substrate (for example, silicon substrate), thereby reducing the threshold voltage of NMOS, which is beneficial to improving the speed of the device and reducing power consumption. The metal work function layer of PMOS (P-Metal-Oxide-Semiconductor) is a P-type metal work function layer, and the work function of the P-type metal work function layer usually depletes the top of the valence band of the substrate such as silicon substrate, thereby reducing the absolute value of the threshold voltage of PMOS, which is beneficial to improving the speed of the device and reducing power consumption. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device in order to address the problems in the above-mentioned background technology, wherein the gate structure thereof includes a work function adjustment structure with different work function values, so as to improve the breakdown voltage of the semiconductor device.

[0005] To achieve the above objectives and other related objectives, one aspect of the present application provides a semiconductor device, including:

[0006] A substrate, wherein the substrate includes a source region and a drain region separated from each other;

[0007] The top surface of the substrate includes a gate structure located between the source region and the drain region, the gate structure includes a gate dielectric layer, a composite work function layer and a gate material layer stacked in sequence along a first direction away from the substrate, and the composite work function layer includes at least a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values;

[0008] The first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction.

[0009] In one embodiment, the work function material stack structure is formed by alternately stacking at least two work function materials, or each layer in the work function material stack structure uses a different work function material.

[0010] In one embodiment, at the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different; in the second direction, the end surface of the first work function material of the first work function adjustment structure is joined to the end surface of the second work function material of the second work function adjustment structure.

[0011] In one embodiment, the first work function adjustment structure includes a first TiN material layer, a first TiAl material layer, and a second TiN material layer alternately stacked along the first direction, and the second work function adjustment structure includes a second TiAl material layer and a third TiN material layer stacked in sequence along the first direction, wherein the first TiN material layer is bonded to the second TiAl material layer, and the first TiAl material layer is bonded to the third TiN material layer.

[0012] In one embodiment, the number of stacked layers of the first work function adjustment structure is greater than the number of stacked layers of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than the work function value of the second work function adjustment structure.

[0013] In one embodiment, the composite work function layer includes a P-type work function portion and an N-type work function portion, the P-type work function portion includes the first work function adjustment structure, and the N-type work function portion includes the second work function adjustment structure.

[0014] In one embodiment, a bottom work function layer is further arranged between the gate dielectric layer and the first work function adjustment structure and the second work function adjustment structure. The bottom work function layer includes a single-layer structure or a multi-layer structure. The bottom work function layer includes a TiN material layer and a TaN material layer stacked in sequence along the first direction.

[0015] In one embodiment, the gate dielectric layer comprises a high-K dielectric layer, and the gate material layer comprises a metal gate.

[0016] Another aspect of the present application provides a method for preparing a semiconductor device, comprising the following steps:

[0017] Providing a substrate, wherein the substrate includes a source region and a drain region separated from each other;

[0018] A gate dielectric layer, a composite work function layer and a gate material layer are sequentially formed on the top surface of the substrate along a first direction away from the substrate, wherein the composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values, and the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction.

[0019] In one embodiment, the substrate comprises a first region for forming the first work function regulating structure thereon and a second region for forming the second work function regulating structure thereon,

[0020] Forming the first work function adjustment structure and the second work function adjustment structure includes:

[0021] forming a first work function material layer covering the first region and the second region of the substrate;

[0022] Etching and removing the first work function material layer covering the second region;

[0023] A second work function material layer is formed on the first work function material layer and covers the first region and the second region.

[0024] According to the semiconductor device and the preparation method thereof provided by the present invention, the unexpected technical effect of the present application is: by forming a composite work function layer including a first work function adjustment structure and a second work function adjustment structure between the gate dielectric layer and the gate material layer, the composite work function layer has different work function values ​​in different regions in the lateral direction, so that the semiconductor device can resist different strengths of the electric field in the lateral direction, thereby improving the breakdown voltage of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to better describe and illustrate the embodiments and / or examples of those applications disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, and the best modes of these applications currently understood.

[0026] Figure 1A schematic diagram of a process for preparing a semiconductor device provided in an embodiment;

[0027] Figure 2 It is a schematic diagram of a process of forming a gate structure in a method for preparing a semiconductor device provided in an embodiment;

[0028] Figure 3 A schematic diagram of a cross-sectional structure of a substrate in a method for preparing a semiconductor device provided in an embodiment;

[0029] Figure 4 It is a schematic cross-sectional structure diagram of the structure after a dummy gate is formed in a method for preparing a semiconductor device provided in an embodiment;

[0030] Figure 5 It is a schematic cross-sectional structural diagram of a structure obtained after a bottom work function layer is formed in step S121 of a method for preparing a semiconductor device provided in an embodiment;

[0031] Figure 6 It is a schematic cross-sectional structural diagram of the structure after the first work function material layer is formed in step S122 of the method for preparing a semiconductor device provided in an embodiment;

[0032] Figure 7 It is a schematic cross-sectional structural diagram of the structure after the first work function material layer covering the second region is removed in step S123 of the method for preparing a semiconductor device provided in an embodiment;

[0033] Figure 8 It is a schematic cross-sectional structural diagram of the structure after the second work function material layer and the third work function material layer are formed in step S124 of the method for preparing a semiconductor device provided in an embodiment;

[0034] Fig. 9 It is a schematic cross-sectional structure diagram of the structure after a metal gate is formed in step S125 of the method for preparing a semiconductor device provided in an embodiment;

[0035] Fig.10 It is a schematic cross-sectional structural diagram of the structure after a metal plug is formed in a method for preparing a semiconductor device provided in an embodiment.

[0036] Description of reference numerals:

[0037] 200, substrate; 210, source region; 211, first high-voltage N drift region; 212, first high-voltage P drift region; 220, drain region; 221, second high-voltage N drift region; 222, second high-voltage P drift region; 230, gate dielectric layer; 240, bottom work function layer; 241, first bottom work function layer; 242, second bottom work function layer; 250, dummy gate material layer; 261, first work function material layer; 262, second work function material layer; 263, third work function material layer. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing, and the zones shown in the figures are schematic in nature, and their shapes are not intended to display the actual shapes of the zones of the device and are not intended to limit the scope of the application.

[0044] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0045] The present invention provides a method for preparing a semiconductor device, such as Figure 1 As shown, the following steps are included:

[0046] Step S110: providing a substrate, wherein an active region and a drain region are formed in the substrate;

[0047] Step S120: forming a gate dielectric layer, a composite work function layer and a gate material layer in sequence on the top surface of the substrate along a first direction away from the substrate, wherein the composite work function layer includes at least a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values, and the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction.

[0048] Further, the substrate includes a first region for forming a first work function adjustment structure thereon, and a second region for forming a second work function adjustment structure thereon, and sequentially forming a gate dielectric layer, a composite work function layer, and a gate material layer along a first direction on the substrate includes the following steps:

[0049] Step S121: forming a gate dielectric layer and a bottom work function layer covering the first region and the second region of the substrate;

[0050] Step S122: forming a first work function material layer covering the first region and the second region on the bottom work function layer;

[0051] Step S123: etching and removing the first work function material layer covering the second region;

[0052] Step S124: forming a second work function material layer and a third work function material layer covering the first region and the second region on the first work function material layer, wherein the first work function material layer, the second work function material layer and the third work function material layer in the first region constitute the first work function adjustment structure, and the second work function material layer and the third work function material layer in the second region constitute the second work function adjustment structure;

[0053] Step S125: forming a gate material layer to fill the gate groove.

[0054] First, refer to Figure 3 As shown, step S110 is performed to provide a substrate 200, wherein the substrate 200 includes a spaced source region 210 and a drain region 220. In one embodiment, a first direction away from the substrate 200 is a longitudinal direction, a second direction parallel to the substrate 200 is a lateral direction, and the second direction is parallel to the arrangement direction of the source region 210 and the drain region 220.

[0055] In one embodiment, the substrate 200 may be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. Preferably, the substrate 200 is a P-type substrate.

[0056] In one embodiment, the substrate includes a source region 210 and a drain region 220 spaced apart, and a gate region located between the source region 210 and the drain region 220. The gate region is used to form a gate thereon, and the gate region further includes a first region for forming a first work function adjustment structure thereon, and a second region for forming a second work function adjustment structure thereon. Further, the areas of the first region and the second region can be set as needed, and preferably, the areas of the first region and the second region are equal. It should be noted that dividing the gate region into two regions is only exemplary, and the gate region can also be divided into more regions as needed, each region being used to form a work function adjustment structure with a different work function value thereon.

[0057] In one embodiment, the semiconductor device includes but is not limited to an NMOS device, a PMOS device, a symmetrical device, an asymmetrical device, a high voltage device or a low voltage device. Taking a high voltage asymmetrical NMOS device as an example, refer to Figure 3 As shown, the first high-voltage N drift region 211 and the first high-voltage P drift region 212 are arranged between the gate region of the substrate and the first shallow trench isolation (STI): the gate region is directly adjacent to the first high-voltage N drift region 211, and no STI is arranged therebetween; the first high-voltage P drift region 212 and the first high-voltage N drift region 211 are directly adjacent to each other, and no STI is arranged therebetween. The second high-voltage N drift region 221 and the second high-voltage P drift region 222 are arranged between the gate region and the second STI: the third STI is arranged between the gate region and the second high-voltage N drift region 221; the fourth STI is arranged between the second high-voltage P drift region 222 and the second high-voltage N drift region 221. The first high-voltage P drift region 212 and the second high-voltage P drift region 222 together form a ring-shaped high-voltage P drift region.

[0058] In one embodiment, the substrate 200 is etched to form four STI grooves, and isolation materials are filled in the STI grooves to form four STIs; a mask layer is formed on the substrate, and an N-type ion implantation process is performed using the mask layer as a mask to simultaneously form a first high-voltage N drift region 211 and a second high-voltage N drift region 221; the mask layer is removed to form a new mask layer, and a P-type ion implantation process is performed using the mask layer as a mask to simultaneously form a first high-voltage P drift region 212 and a second high-voltage P drift region 222.

[0059] In one embodiment, after forming the STI and the drift region, a step of etching back the gate region to form a groove is further included, so that the top surface of the gate region of the substrate is lower than the top surface of the substrate 200. Next, a high voltage gate oxide layer (HV GOX) is formed in the groove.

[0060] Next, refer to Figure 4~Figure 5As shown, step S121 is performed to form a gate dielectric layer 230 and a bottom work function layer 240 covering the first region and the second region of the substrate 200 .

[0061] In one embodiment, after forming a high voltage gate oxide layer (HV GOX), a gate dielectric layer 230, a first bottom work function layer 241 and a dummy gate material layer 250 are sequentially formed on the substrate 200. Specifically, the gate dielectric layer 230 is made of a high-K dielectric material, and the high-K dielectric material includes but is not limited to one or more of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide or aluminum oxide. The first bottom work function layer 241 is but is not limited to one or more of TiN, TaN, TiC, TiAl, TiAlC or TaAlC, preferably TiN. The dummy gate material layer 250 is made of polysilicon material. The gate dielectric layer 230, the first bottom work function layer 241 and the dummy gate material layer 250 may be formed by chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).

[0062] In one embodiment, the gate dielectric layer 230, the first bottom work function layer 241 and the dummy gate material layer 250 are etched to form a dummy gate structure. Specifically, a mask layer is formed on the dummy gate material layer 250, and the mask layer may include a nitride layer, an oxide layer, or a stacked structure of nitride and oxide. Using the mask layer as a mask, the method of etching the gate dielectric layer 230, the first bottom work function layer 241 and the dummy gate material layer 250 can be completed by a dry etching process or other process techniques familiar to those skilled in the art, which will not be described in detail here. Furthermore, after forming the dummy gate, a step of forming a gate sidewall is also included, and the gate sidewall may include a nitride layer, an oxide layer, or a stacked structure of nitride and oxide.

[0063] In one embodiment, after forming the gate sidewall, the process further includes the step of performing ion implantation on the drift region to form the source region 210 and the drain region 220. Specifically, after forming a patterned mask, a P-type ion implantation process is performed to simultaneously increase the P-type ion doping concentration of the top regions of the first high-voltage P drift region 212 and the second high-voltage P drift region 222 to form a P-type ion doping region; the mask is removed and a patterned mask is re-formed, and an N-type ion implantation process is performed to simultaneously increase the N-type ion doping concentration of the top regions of the first high-voltage N drift region 211 and the second high-voltage N drift region 221 to form the source region 210 and the drain region 220, respectively. Part of the first high-voltage N drift region 211 is blocked by the gate sidewall, so the source region 210 is formed in the upper region of the first high-voltage N drift region 211 that is not blocked. Next, the mask is removed, and nickel silicide (NiSi) is formed as a metal silicide layer on the exposed upper surface of the first high voltage N drift region 211 , the upper surface of the second high voltage N drift region 221 , and the upper surface of the second high voltage P drift region 222 .

[0064] Next, an etch stop layer (CESL) and an interlayer dielectric layer (ILD) are formed, the etch stop layer covers the upper surfaces of the source region 210 and the drain region 220, as well as the sidewalls of the gate spacer, and the upper surface of the interlayer dielectric layer is flush with the upper surface of the dummy gate material layer 250. The method for forming the etch stop layer and the interlayer dielectric layer can be chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0065] Next, the dummy gate material layer 250 is etched away to expose the first bottom work function layer 241 and form a gate groove. The dummy gate material layer 250 can be removed by combining dry etching with wet etching to completely remove the polysilicon and expose the upper surface of the first bottom work function layer 241. Then, a second bottom work function layer 242 is formed. Specifically, the material of the second bottom work function layer 242 includes but is not limited to a tantalum nitride (TAN) layer. The second bottom work function layer 242 covers the interlayer dielectric layer, the bottom and sidewalls of the gate groove. The first bottom work function layer 241 and the second bottom work function layer 242 together constitute a bottom work function layer.

[0066] Next, refer to Figure 6 As shown, step S122 is performed to form a first work function material layer 261 covering the first region and the second region on the bottom work function layer.

[0067] In one embodiment, the material of the first work function material layer 261 includes but is not limited to titanium nitride (TiN). The first work function material layer 261 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic vapor deposition (ALD).

[0068] Next, refer to Figure 7 As shown, step S123 is performed to etch and remove the first work function material layer 261 covering the second region.

[0069] In one embodiment, a photolithography process is performed to remove the first work function material layer 261 covering the second region. Specifically, a patterned mask layer is first formed, the mask layer includes a photoresist layer (PR) and a bottom anti-reflective coating (BARC), the patterned mask layer exposes the second region, and dry etching is performed to remove the exposed first work function material layer 261 until the second bottom work function layer 242 is exposed, and the second bottom work function layer 242 is used as an etching stop layer. The dry etching process includes, but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser ablation, and a single etching method can be used, or more than one etching method can be used.

[0070] Next, refer to Figure 8 As shown, step S124 is performed to form a second work function material layer 262 and a third work function material layer 263 covering the first region and the second region on the first work function material layer 261, wherein the first work function material layer, the second work function material layer and the third work function material layer in the first region constitute the first work function adjustment structure, and the second work function material layer and the third work function material layer in the second region constitute the second work function adjustment structure.

[0071] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction, wherein the work function material stacking structure is formed by alternating stacking of at least two work function materials. In one embodiment, the first work function material layer 261 and the third work function material layer 263 use the same work function material, such as titanium nitride (TiN). The second work function material layer 262 uses a work function material different from the first work function material layer 261, for example, the second work function material layer 262 uses titanium aluminide (TiAl). It should be noted that in this embodiment, the first work function adjustment structure uses a three-layer stacking structure of TiN+TiAl+TiN, and the second work function adjustment structure uses a two-layer stacking structure of TiAl+TiN, which is only exemplary. The number of stacking layers of the first work function adjustment structure and the second work function adjustment structure can be set as needed, and this application does not limit this.

[0072] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different stacking numbers along the first direction, wherein each layer in the work function material stacking structure adopts a different work function material. In one embodiment, the first work function material layer 261 adopts titanium nitride (TiN), the second work function material layer 262 adopts a work function material different from the first work function material layer 261, such as titanium aluminide (TiAl), and the third work function material layer 263 can adopt a work function material different from the first work function material layer 261 and the second work function material layer 262.

[0073] Exemplarily, at the same height in the first direction, the work function materials of the first work function regulating structure and the second work function regulating structure are different; in the second direction, the first work function material end face of the first work function regulating structure is bonded to the second work function material end face of the second work function regulating structure. In one embodiment, the thickness of each layer in the work function material stack structure is the same, so that after removing the first work function material layer 261 of the second region, the first work function material layer (e.g., TiN material layer) of the first region is bonded and flush with the second work function material layer (e.g., TiAl material layer) of the second region, and the second work function material layer (e.g., TiAl material layer) of the first region is bonded and flush with the third work function material layer (e.g., TiN material layer) of the second region.

[0074] Exemplarily, the number of stacked layers of the first work function adjustment structure is greater than the number of stacked layers of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than the work function value of the second work function adjustment structure. In one embodiment, the first work function adjustment structure is a three-layer stacked structure of TiN+TiAl+TiN, and the work function value is about 5.2eV; the second work function adjustment structure is a two-layer stacked structure of TiAl+TiN, and the work function value is about 4.2eV.

[0075] Exemplarily, the composite work function layer includes a P-type work function portion and an N-type work function portion, the P-type work function portion includes the first work function adjustment structure, and the N-type work function portion includes the second work function adjustment structure. Among them, the work function of the N-type metal work function portion usually depletes the bottom of the conduction band of the substrate, thereby reducing the threshold voltage of the NMOS, which is beneficial to improving the speed of the device and reducing power consumption; the work function of the P-type metal work function layer usually depletes the top of the valence band of the substrate, thereby reducing the absolute value of the threshold voltage of the PMOS, which is beneficial to improving the speed of the device and reducing power consumption. In this embodiment, by making the composite work function layer include both the P-type work function portion and the N-type work function portion, the composite work function layer of the metal gate is different from that of the NMOS and the PMOS. Such a structure can adjust the threshold voltage Vt. Since the N-type work function portion and the P-type work function portion have different stacking numbers and different total thicknesses, their profiles are different, so the strength of resisting the electric field in the lateral direction is different, which can improve the breakdown voltage (BVD) of the semiconductor device.

[0076] Through the method provided by the present invention, it is only necessary to add step S123 in the process of forming the work function stack structure, and etch away the first work function material layer in the second region, so that the number of stacking layers and the total thickness of the work function stack structure formed in the first region and the second region can be different, and they have different work function values. The composite work function layer has different strengths in resisting the electric field in the lateral direction, thereby improving the breakdown voltage of the semiconductor device.

[0077] Next, refer to Fig. 9 As shown, step S125 is performed to form a gate material layer to fill the gate groove.

[0078] In one embodiment, after forming the first work function adjustment structure and the second work function adjustment structure, a step of forming a metal gate in the gate groove is also included. In one embodiment, the material of the metal gate includes but is not limited to metal materials such as aluminum and copper. The method of forming the metal gate can be completed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic vapor deposition (ALD) and other process technologies familiar to those skilled in the art, which will not be described in detail here.

[0079] Next, refer to Fig.10 As shown, after forming the metal gate, the step of forming a contact plug (CT) and a metal wiring layer is also included.

[0080] So far, the introduction of the relevant steps of the method for preparing a semiconductor device according to an embodiment of the present invention has been completed. It can be understood that the method for preparing a semiconductor device according to this embodiment not only includes the above steps, but also may include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method according to this embodiment.

[0081] The present invention also provides a semiconductor device, referring to Fig.10 As shown, including:

[0082] A substrate, wherein the substrate includes a source region and a drain region separated from each other;

[0083] The top surface of the substrate includes a gate structure located between the source region and the drain region, the gate structure includes a gate dielectric layer, a composite work function layer and a gate material layer stacked in sequence along a first direction away from the substrate, the composite work function layer includes at least a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values; wherein the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacked structures with different numbers of layers stacked along the first direction.

[0084] In one embodiment, the substrate includes a source region 210 and a drain region 220 spaced apart, and a gate region located between the source region 210 and the drain region 220. In one embodiment, the first direction away from the substrate 200 is the longitudinal direction, the second direction parallel to the substrate 200 is the transverse direction, and the second direction is parallel to the arrangement direction of the source region 210 and the drain region 220. Wherein, the gate region is used to form a gate thereon, and the gate region further includes a first region for forming a first work function adjustment structure thereon, and a second region for forming a second work function adjustment structure thereon. Further, the areas of the first region and the second region can be set as needed, and preferably, the areas of the first region and the second region are equal. It should be noted that dividing the gate region into two regions is only exemplary, and the gate region can also be divided into more regions as needed, each region is used to form a work function adjustment structure with a different work function value thereon.

[0085] In one embodiment, the semiconductor device includes but is not limited to an NMOS device, a PMOS device, a symmetrical device, an asymmetrical device, a high voltage device or a low voltage device. Taking a high voltage asymmetrical NMOS device as an example, a first high voltage N drift region 211 and a first high voltage P drift region 212 are provided between the gate region (used to form a gate thereon) of the substrate and the first shallow trench isolation (STI): the gate region is directly adjacent to the first high voltage N drift region 211, and no STI is provided therebetween; the first high voltage P drift region 212 and the first high voltage N drift region 211 are directly adjacent to each other, and no STI is provided therebetween. A second high voltage N drift region 221 and a second high voltage P drift region 222 are provided between the gate region and the second STI: a third STI is provided between the gate region and the second high voltage N drift region 221; a fourth STI is provided between the second high voltage P drift region 222 and the second high voltage N drift region 221. Among them, the first high voltage P drift region 212 and the second high voltage P drift region 222 together constitute a ring-shaped high voltage P drift region. Furthermore, the top regions of the first high-voltage P drift region 212 and the second high-voltage P drift region 222 are P-type ion doping regions, and their P-type ion doping concentration is higher than that of the drift region; the portion of the first high-voltage N drift region 211 that does not overlap with the gate sidewall and the top region of the second high-voltage N drift region 221 are the source region 210 and the drain region 220, and the N-type ion doping concentration of the source region 210 and the drain region 220 is higher than that of the drift region. Metal silicide, such as nickel silicide (NiSi), is formed on the upper surface of the first high-voltage N drift region 211, the upper surface of the second high-voltage N drift region 221, and the upper surface of the second high-voltage P drift region 222.

[0086] In one embodiment, a high voltage gate oxide layer (HV GOX) is formed on the top surface of the gate region of the substrate, and the top surface of the high voltage gate oxide layer is flush with the top surface of the metal silicide of the source region 210 and the drain region 220. A gate dielectric layer 230 is formed on the high voltage gate oxide layer, and the gate dielectric layer 230 adopts a high K dielectric material, and the high K dielectric material includes but is not limited to one or more of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide or aluminum oxide. A composite work function layer is formed on the gate dielectric layer 230, and the composite work function includes a bottom work function layer located at the bottom, and the bottom work function layer includes a single-layer structure or a multi-layer structure. Specifically, the bottom work function layer includes a first bottom work function layer 241 (for example, a TiN material layer) and a second bottom work function layer 242 (for example, a TaN material layer). Among them, the first bottom work function layer 241 only covers the bottom of the gate groove, and the second bottom work function layer 242 covers the bottom and sidewalls of the gate groove.

[0087] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction, wherein the work function material stacking structure is formed by alternating stacking of at least two work function materials. In one embodiment, the first work function material layer 261 and the third work function material layer 263 use the same work function material, such as titanium nitride (TiN). The second work function material layer 262 uses a work function material different from the first work function material layer 261, for example, the second work function material layer 262 uses titanium aluminide (TiAl). It should be noted that in this embodiment, the first work function adjustment structure uses a three-layer stacking structure of TiN+TiAl+TiN, and the second work function adjustment structure uses a two-layer stacking structure of TiAl+TiN, which is only exemplary. The number of stacking layers of the first work function adjustment structure and the second work function adjustment structure can be set as needed, and this application does not limit this.

[0088] Exemplarily, the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction, wherein each layer in the work function material stacking structure uses a different work function material. In one embodiment, the first work function material layer 261 uses titanium nitride (TiN), the second work function material layer 262 uses a work function material different from the first work function material layer 261, such as titanium aluminide (TiAl), and the third work function material layer 263 uses a work function material different from the first work function material layer 261 and the second work function material layer 262.

[0089] Exemplarily, at the same height in the first direction, the work function materials of the first work function regulating structure and the second work function regulating structure are different; in the second direction, the first work function material end face of the first work function regulating structure is bonded to the second work function material end face of the second work function regulating structure. In one embodiment, the thickness of each layer in the work function material stack structure is the same, so that after removing the first work function material layer 261 of the second region, the first work function material layer (e.g., TiN material layer) of the first region is bonded and flush with the second work function material layer (e.g., TiAl material layer) of the second region, and the second work function material layer (e.g., TiAl material layer) of the first region is bonded and flush with the third work function material layer (e.g., TiN material layer) of the second region.

[0090] Exemplarily, the number of stacked layers of the first work function adjustment structure is greater than the number of stacked layers of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than the work function value of the second work function adjustment structure. In one embodiment, the first work function adjustment structure is a three-layer stacked structure of TiN+TiAl+TiN, and the work function value is about 5.2eV; the second work function adjustment structure is a two-layer stacked structure of TiAl+TiN, and the work function value is about 4.2eV.

[0091] Exemplarily, the composite work function layer includes a P-type work function portion and an N-type work function portion, the P-type work function portion includes the first work function adjustment structure, and the N-type work function portion includes the second work function adjustment structure. Among them, the work function of the N-type metal work function portion usually depletes the bottom of the conduction band of the substrate, thereby reducing the threshold voltage of the NMOS, which is beneficial to improving the speed of the device and reducing power consumption; the work function of the P-type metal work function layer usually depletes the top of the valence band of the substrate, thereby reducing the absolute value of the threshold voltage of the PMOS, which is beneficial to improving the speed of the device and reducing power consumption. In this embodiment, by making the composite work function layer include both the P-type work function portion and the N-type work function portion, the composite work function layer of the metal gate is different from that of the NMOS and the PMOS. Such a structure can adjust the threshold voltage Vt. Since the N-type work function portion and the P-type work function portion have different stacking numbers and total thicknesses, their profiles are different, so the strength of resisting the electric field in the lateral direction is different, which can improve the breakdown voltage of the semiconductor device.

[0092] In one embodiment, the material of the metal gate includes but is not limited to metal materials such as aluminum and copper. The semiconductor device also includes a contact plug (CT) and a metal wiring layer, which will not be described in detail here.

[0093] According to the semiconductor device and preparation method thereof provided by the present invention, a composite work function layer including a first work function adjustment structure and a second work function adjustment structure is formed between the gate dielectric layer and the gate material layer, and the composite work function layer has different work function values ​​in different regions in the lateral direction, so that the semiconductor device can resist different strengths of the electric field in the lateral direction, thereby improving the breakdown voltage of the semiconductor device.

[0094] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0095] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0096] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, wherein the substrate includes a source region and a drain region separated from each other; The top surface of the substrate includes a gate structure located between the source region and the drain region, the gate structure includes a gate dielectric layer, a composite work function layer and a gate material layer stacked in sequence along a first direction away from the substrate, and the composite work function layer includes at least a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values; The first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction.

2. The semiconductor device according to claim 1, wherein: The work function material stack structure is formed by alternately stacking at least two work function materials, or each layer in the work function material stack structure uses a different work function material.

3. The semiconductor device according to claim 2, characterized in that At the same height in the first direction, the work function materials of the first work function adjustment structure and the second work function adjustment structure are different; in the second direction, the end surface of the first work function material of the first work function adjustment structure is bonded to the end surface of the second work function material of the second work function adjustment structure.

4. The semiconductor device according to claim 3, characterized in that The first work function adjustment structure includes a first TiN material layer, a first TiAl material layer, and a second TiN material layer stacked in sequence along the first direction, and the second work function adjustment structure includes a second TiAl material layer and a third TiN material layer stacked in sequence along the first direction, wherein the first TiN material layer is bonded to the second TiAl material layer, and the first TiAl material layer is bonded to the third TiN material layer.

5. The semiconductor device according to claim 1, wherein: The number of stacked layers of the first work function adjustment structure is greater than the number of stacked layers of the second work function adjustment structure, and the work function value of the first work function adjustment structure is greater than the work function value of the second work function adjustment structure.

6. The semiconductor device according to claim 5, characterized in that The composite work function layer includes a P-type work function portion and an N-type work function portion, the P-type work function portion includes the first work function adjustment structure, and the N-type work function portion includes the second work function adjustment structure.

7. The semiconductor device according to claim 1 or 6, characterized in that: A bottom work function layer is also arranged between the gate dielectric layer and the first work function adjustment structure and the second work function adjustment structure. The bottom work function layer includes a single-layer structure or a multi-layer structure. The bottom work function layer includes a TiN material layer and a TaN material layer stacked in sequence along the first direction.

8. The semiconductor device according to claim 1, wherein: The gate dielectric layer includes a high-K dielectric layer, and the gate material layer includes a metal gate.

9. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, wherein the substrate includes a source region and a drain region separated from each other; A gate dielectric layer, a composite work function layer and a gate material layer are sequentially formed on the top surface of the substrate along a first direction away from the substrate, wherein the composite work function layer at least includes a first work function adjustment structure and a second work function adjustment structure arranged along a second direction parallel to the substrate and having different work function values, and the first work function adjustment structure and the second work function adjustment structure respectively include work function material stacking structures with different numbers of stacking layers along the first direction.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The substrate includes a first region for forming the first work function regulating structure thereon and a second region for forming the second work function regulating structure thereon, Forming the first work function adjustment structure and the second work function adjustment structure includes: forming a first work function material layer covering the first region and the second region of the substrate; Etching and removing the first work function material layer covering the second region; A second work function material layer is formed on the first work function material layer and covers the first region and the second region.

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