Semiconductor component and method of manufacturing the same
By designing an asymmetric doping distribution in the semiconductor component, the light doped drain region and pocket region are only located on the source side, solving the problem of degradation of driving capability and electrical performance of the semiconductor component in the case of reduced size, and achieving higher current and lower leakage current.
Patent Information
- Application Number
- CN202410054718.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-12
- Filing Date
- 2024-01-15
- Publication Date
- 2025-04-18
AI Technical Summary
How to maintain or improve the driving capability and electrical performance of semiconductor components when the size of semiconductor components is reduced.
A semiconductor component with an asymmetric structure is designed, with a light doped drain region and pocket region (or halo region) located only on the source side, forming an asymmetric doping distribution.
High source and drain currents (Ids), lower leakage currents and avoid drain-induced barrier reduction (DIBL), thereby improving the performance of semiconductor components.
Smart Images
Figure CN119855203A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor component and a manufacturing method thereof, and in particular to a semiconductor component with an asymmetric structure and a manufacturing method thereof. Background Art
[0002] With the development of semiconductor technology, the size of semiconductor components is continuously reduced. However, semiconductor components with smaller size may not meet the electrical requirements.
[0003] A driving circuit with a larger size usually has a larger driving capability. In general, in order to improve the driving capability of the driving circuit, the transistor in the driving circuit may include a gate structure disposed on a substrate (including a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on the sidewalls of the gate and the gate dielectric layer) and a source region and a drain region disposed in the substrate on both sides of the gate structure, respectively, and a lightly doped drain (LDD) region and a pocket region (or halo region) disposed in the substrate and adjacent to the source region and the drain region. The reduction in the size of the transistor leads to a reduction in the driving capability of the driving circuit. Therefore, how to maintain or even improve the performance of semiconductor components when the size of the components is reduced is an important issue. Summary of the invention
[0004] The present invention is directed to a semiconductor component with an asymmetric structure and a method for manufacturing the same, wherein a lightly doped drain region and a pocket region (or halo region) are formed in a substrate and are only adjacent to a source region.
[0005] The semiconductor component of the present invention comprises a gate structure, a first doping region and a second doping region. The gate structure is arranged on a substrate and comprises a gate, a gate dielectric layer and a spacer. The gate is arranged on the substrate. The gate dielectric layer is arranged between the gate and the substrate. The spacer is arranged on the sidewalls of the gate and the gate dielectric layer. The source region and the drain region are arranged in the substrate and are respectively located on both sides of the gate structure. The first doping region is arranged in the substrate and is adjacent to the source region. The second doping region is arranged in the substrate and is located below the first doping region. The source region, the drain region and the first doping region have a first conductivity type, and the second doping region has a second conductivity type opposite to the first conductivity type. The doping concentration of the first doping region is less than the doping concentration of the source region and the drain region.
[0006] In an embodiment of the semiconductor device of the present invention, the depth of the drain region is not greater than the depth of the source region.
[0007] In one embodiment of the semiconductor device of the present invention, the doping concentration of the source region and the drain region is between 10 16 cm -3 and 10 23 cm -3 between.
[0008] In one embodiment of the semiconductor device of the present invention, the doping concentration of the first doping region is between 10 16 cm -3 and 10 23 cm -3 between.
[0009] In one embodiment of the semiconductor device of the present invention, the doping concentration of the second doping region is between 10 16 cm -3 and 10 23 cm -3 between.
[0010] The manufacturing method of the semiconductor component of the present invention comprises the following steps. A gate structure is formed on a substrate, wherein the gate structure comprises a gate formed on the substrate, a gate dielectric layer formed between the gate and the substrate, and a spacer formed on the sidewalls of the gate and the gate dielectric layer. A source region and a drain region are respectively formed in the substrate on both sides of the gate structure. A first doping region is formed in the substrate adjacent to the source region. A second doping region is formed in the substrate below the first doping region. The source region, the drain region, and the first doping region have a first conductivity type, and the second doping region has a second conductivity type opposite to the first conductivity type. The doping concentration of the first doping region is less than the doping concentration of the source region and the drain region.
[0011] In an embodiment of the method for manufacturing a semiconductor device of the present invention, a depth of the drain region is not greater than a depth of the source region.
[0012] In one embodiment of the method for manufacturing a semiconductor device of the present invention, the doping concentration of the source region and the drain region is between 10 16 cm -3 and 10 23 cm -3 between.
[0013] In one embodiment of the method for manufacturing a semiconductor device of the present invention, the doping concentration of the first doping region is between 10 16 cm -3 and 10 23 cm -3 between.
[0014] In one embodiment of the method for manufacturing a semiconductor device of the present invention, the doping concentration of the second doping region is between 10 16 cm -3 and 10 23 cm -3 between.
[0015] Based on the above, in the present invention, the semiconductor device has an asymmetric structure, wherein the first doped region as the lightly doped drain region and the second doped region as the pocket region (or halo region) are only located at the source side. Therefore, the semiconductor device of the present invention can have improved performance, such as higher source-drain current (Ids), lower leakage current, and avoidance of drain induced barrier lowering (DIBL). BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figures 1A to 1D FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention;
[0017] Figure 2 is a graph showing the relationship between Ids and leakage current of semiconductor devices according to an embodiment of the present invention and a comparative example;
[0018] Figure 3 is another relationship diagram between Ids and leakage current of the semiconductor devices of the embodiment of the present invention and the comparative example;
[0019] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention. DETAILED DESCRIPTION
[0020] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components are indicated by the same symbols in the following description.
[0021] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".
[0022] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component can also be called the second component, and the second component can also be called the first component, and this does not deviate from the scope of the present invention.
[0023] In addition, directional terms such as "upper", "lower", etc. mentioned herein are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when a component such as a layer or film is placed "on" another component, the component can be placed directly on the other component, or there can be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between the two.
[0024] In addition, in this article, the range expressed by "a value to another value" is a summary expression method to avoid listing all the values in the range one by one in the specification. Therefore, the description of a specific numerical range covers any value in the numerical range, and covers a smaller numerical range defined by any value in the numerical range.
[0025] Figures 1A to 1D FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
[0026] Please refer to Figure 1A , provide a substrate 100. In the present embodiment, the substrate 100 is a silicon substrate, but the present invention is not limited thereto. In other embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate. Next, a gate dielectric layer 102 and a gate 104 are formed on the substrate 100. In the present embodiment, the material of the gate dielectric layer 102 is oxide, and the material of the gate 104 is polysilicon, but the present invention is not limited thereto. In the present embodiment, the method for forming the gate dielectric layer 102 and the gate 104 may include the following steps. A gate dielectric material layer and a gate material layer are sequentially formed on the substrate 100. Then, a patterning process is performed on the gate dielectric material layer and the gate material layer to form the gate dielectric layer 102 and the gate 104.
[0027] Please refer to Figure 1B , a first doping region 106 is formed in the substrate 100 on one side of the gate 104. In the present embodiment, the first doping region 106 is formed by, for example, an ion implantation process. In the present embodiment, the first doping region 106 has a first conductivity type, for example, one of an n-type and a p-type. In the present embodiment, the doping concentration of the first doping region 106 is between 10 16 cm -3 Up to 10 23 cm -3 The first doped region 106 can be used as a lightly doped drain region of the semiconductor device of this embodiment.
[0028] In addition, in the present embodiment, after forming the first doping region 106, a thermal process may be performed so that the dopant in the first doping region 106 may diffuse into the region under the gate 104, but the present invention is not limited thereto. In other words, in the present embodiment, the first doping region 106 may extend under the gate 104. In other embodiments, the boundary of the first doping region 106 may be aligned with the sidewall of the gate 104.
[0029] Please refer to Figure 1C , forming a spacer 108 on the sidewalls of the gate 104 and the gate dielectric layer 102. In the present embodiment, the material of the spacer 108 is nitride, but the present invention is not limited thereto. In the present embodiment, the method for forming the spacer 108 may include the following steps. A spacer material layer is conformally formed on the substrate 100. Then, an anisotropic etching process is performed to remove a portion of the spacer material layer. In the present embodiment, the gate dielectric layer 102, the gate 104 and the spacer 108 form a gate structure 109.
[0030] Next, a source region 110S and a drain region 110D are formed in the substrate 100 on both sides of the gate structure 109. In the present embodiment, the source region 110S and the drain region 110D are formed by, for example, using the gate structure 109 as a mask to perform an ion implantation process. In the present embodiment, the source region 110S and the drain region 110D have a first conductivity type. In the present embodiment, the source region 110S and the drain region 110D have the same depth, and the depth of the source region 110S and the drain region 110D is greater than the depth of the first doping region 106. In the present embodiment, the doping concentration of the source region 110S and the drain region 110D is between 10 16 cm -3 Up to 10 23 cm -3 The doping concentration of the first doping region 106 is lower than the doping concentration of the source region 110S and the drain region 110D.
[0031] Please refer to Figure 1D , a second doping region 112 is formed in the substrate 100, and the second doping region 112 is located below the first doping region 106. The bottom of the second doping region 112 is not lower than the bottom of the source region 110S. In this embodiment, the second doping region 112 is formed by, for example, performing an inclined ion implantation process. In this embodiment, the second doping region 112 has a second conductivity type opposite to the first conductivity type, for example, the other of the n-type and the p-type. In this embodiment, the doping concentration of the second doping region 112 is between 10 16 cm -3 Up to 10 23 cm -3The second doped region 112 can be used as a pocket region (or halo region) of the semiconductor device of this embodiment. In this way, the semiconductor device 10 of this embodiment is formed.
[0032] In the present embodiment, the semiconductor device 10 has an asymmetric structure. Specifically, in the semiconductor device 10, the first doped region 106 as a lightly doped drain region and the second doped region 112 as a pocket region (or halo region) are only located on the source side. There is no lightly doped drain region and pocket region (or halo region) on the drain side. In this way, the semiconductor device 10 can have better performance, such as higher Ids, lower leakage current and prevention of DIBL. The semiconductor device 10 can be applied to core circuits.
[0033] The effect of the present invention will be described below using the semiconductor component 10 of this embodiment and a comparative example. In the comparative example, a lightly doped drain region and a pocket region (or halo region) are provided on both the source side and the drain side.
[0034] Figure 2 is a graph showing the relationship between Ids and leakage current of semiconductor devices of the embodiment of the present invention and the comparative example. Figure 2 Compared with the comparative example, the semiconductor device 10 of the present embodiment can have a higher Id without causing an increase in leakage current.
[0035] Figure 3 Another relationship diagram between Ids and leakage current of semiconductor devices of the embodiment of the present invention and the comparative example is shown in FIG. Figure 3 , under the same Ids, compared with the comparative example, the semiconductor device 10 of the present embodiment can have a lower leakage current.
[0036] In the semiconductor device 10 of the present embodiment, the source region 110S and the drain region 110D have the same depth, but the present invention is not limited thereto. In other embodiments, the source region 110S and the drain region 110D have different depths.
[0037] Figure 4 FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by the same reference symbols and will not be described again.
[0038] Please refer to Figure 4In the semiconductor device 20, the depth of the drain region 110D is less than the depth of the source region 110S. Like the semiconductor device 10 of the first embodiment, the semiconductor device 20 has an asymmetric structure, wherein the first doped region 106 as a lightly doped drain region and the second doped region 112 as a pocket region (or halo region) are only located on the source side. Therefore, the semiconductor device 20 can have a higher Ids, a lower leakage current, and prevent DIBL. The semiconductor device 20 can be applied to core circuits.
[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor component, characterized in that: include: The gate structure is disposed on the substrate and includes: A gate is disposed on the substrate; a gate dielectric layer disposed between the gate and the substrate; and A spacer, disposed on the sidewalls of the gate and the gate dielectric layer; A source region and a drain region are disposed in the substrate and are respectively located on two sides of the gate structure; A first doped region disposed in the substrate and adjacent to the source region; and a second doping region, disposed in the substrate and located below the first doping region, wherein the source region, the drain region and the first doped region have a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type, and The doping concentration of the first doping region is less than the doping concentration of the source region and the drain region.
2. The semiconductor component according to claim 1, characterized in that The depth of the drain region is not greater than the depth of the source region.
3. The semiconductor component according to claim 1, characterized in that The doping concentration of the source region and the drain region is between 10 16 cm -3 and 10 23 cm -3 between.
4. The semiconductor component according to claim 1, characterized in that The doping concentration of the first doping region is between 10 16 cm -3 and 10 23 cm -3 between.
5. The semiconductor component according to claim 1, characterized in that The doping concentration of the second doping region is between 10 16 cm -3 and 10 23 cm -3 between.
6. A method for manufacturing a semiconductor component, characterized in that: include: forming a gate structure on a substrate, wherein the gate structure comprises a gate formed on the substrate, a gate dielectric layer formed between the gate and the substrate, and a spacer formed on sidewalls of the gate and the gate dielectric layer; forming a source region and a drain region in the substrate at both sides of the gate structure respectively; forming a first doped region in the substrate adjacent to the source region; as well as forming a second doped region in the substrate below the first doped region, wherein the source region, the drain region and the first doped region have a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type, and The doping concentration of the first doping region is less than the doping concentration of the source region and the drain region.
7. The method for manufacturing a semiconductor component according to claim 6, characterized in that: The depth of the drain region is not greater than the depth of the source region.
8. The method for manufacturing a semiconductor component according to claim 6, wherein: The doping concentration of the source region and the drain region is between 10 16 cm -3 and 10 23 cm -3 between.
9. The method for manufacturing a semiconductor component according to claim 6, wherein: The doping concentration of the first doping region is between 10 16 cm -3 and 10 23 cm -3 between.
10. The method for manufacturing a semiconductor component according to claim 6, wherein: The doping concentration of the second doping region is between 10 16 cm -3 and 10 23 cm -3 between.