Radio frequency device of gold-free electrode process, preparation method of radio frequency device, chip and equipment

Abstract

The invention relates to a radio frequency device of a gold-free electrode process and a preparation method thereof, a chip and equipment, the radio frequency device comprises a substrate layer, a first semiconductor layer, a second semiconductor layer, a source electrode, a drain electrode, a passivation layer and a gate electrode, and the substrate layer, the first semiconductor layer and the second semiconductor layer are sequentially arranged from bottom to top; the first semiconductor layer and the second semiconductor layer form a heterostructure; the source electrode and the drain electrode are located at the two ends of the second semiconductor layer respectively and extend into the first semiconductor layer; the source electrode and the drain electrode are both made of non-gold ohmic electrode metal, and the source electrode and the drain electrode are both of a cap-shaped structure; the passivation layer covers the surfaces of the second semiconductor layer, the source electrode and the drain electrode; the gate electrode is located between the source electrode and the drain electrode and extends to the upper surface of the second semiconductor layer from the passivation layer; and the gate electrode is made of gold-free gate metal. The device provided by the invention is realized through an over-etching scheme, and the ohmic contact is good.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a radio frequency device without gold electrode technology and a preparation method, chip and equipment thereof. Background Art

[0002] Gallium nitride (GaN) is a third-generation semiconductor with the advantages of large bandgap, high breakdown field strength, and high electron saturation velocity. The high electron mobility transistor (HEMT) prepared by it uses the polarization characteristics of the material itself to form a two-dimensional electron gas (2DEG) with high electron concentration and high electron mobility, which can provide higher output power at the same operating voltage. Although GaN devices have many advantages, they are limited by their epitaxial technology, the epitaxy of the material is difficult and the cost of epitaxy is high, making it difficult to mass produce. At the same time, the Si-based device industry is mature and has low production costs, making it suitable for mass production. Therefore, researchers considered making the production of Si-based devices compatible with GaN devices. However, the current GaN-based HEMT generally uses a gold-containing process, and the diffusion of Au into Si will form a minority carrier recombination center, so the conventional GaN process is not compatible with the complementary metal oxide semiconductor (CMOS) process.

[0003] The prior art proposes a gold-free ohmic electrode by optimizing the device structure in the ohmic region. However, in order to obtain a better current level, the gold-free ohm needs to first perform deep etching or over-etching on the ohmic region and then deposit the ohmic metal. Deep etching means that the barrier layer in the ohmic region is left with a barrier layer of about 2nm. Deep etching requires precise control of the etching depth and extremely high precision requirements for the etching equipment. Over-etching means completely etching the barrier layer and etching all the way to the channel layer.

[0004] The over-etching scheme can reduce the precision control of etching depth to a certain extent, but in the over-etching scheme, the bottom metal of the ohmic metal directly contacts the 2DEG, which has high requirements for ohmic contact. In the over-etching scheme, the ohmic contact is basically achieved by side contact, but when the ohmic metal is filled, the contact between the side wall of the electrode groove and the ohmic metal is very poor, resulting in the ohmic contact of the device failing to meet the standards. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a radio frequency device without gold electrode process and its preparation method, chip and equipment. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] The first aspect of the present invention provides a radio frequency device with a gold-free electrode process, comprising: a substrate layer, a first semiconductor layer, a second semiconductor layer, a source electrode, a drain electrode, a passivation layer and a gate electrode, wherein:

[0007] The substrate layer, the first semiconductor layer and the second semiconductor layer are arranged in sequence from bottom to top; the first semiconductor layer and the second semiconductor layer form a heterostructure;

[0008] The source electrode and the drain electrode are respectively located at two ends of the second semiconductor layer and extend into the first semiconductor layer; the materials of the source electrode and the drain electrode are both gold-free ohmic electrode metals, and the source electrode and the drain electrode are both cap-shaped structures;

[0009] The passivation layer covers the surfaces of the second semiconductor layer, the source electrode and the drain electrode;

[0010] The gate electrode is located between the source electrode and the drain electrode, and extends from the passivation layer to the upper surface of the second semiconductor layer; the material of the gate electrode is a gold-free gate metal.

[0011] The second aspect of the present invention provides a method for preparing a radio frequency device using a gold-free electrode process, which is used to prepare the radio frequency device using a gold-free electrode process provided by the first aspect of the present invention, comprising the following steps:

[0012] A first semiconductor layer and a second semiconductor layer are sequentially prepared from bottom to top on the surface of the substrate layer; the first semiconductor layer and the second semiconductor layer form a heterostructure;

[0013] Over-etching is performed at both ends of the second semiconductor layer to form a source groove and a drain groove extending from the upper surface of the second semiconductor layer to the inside of the first semiconductor layer;

[0014] Depositing a gold-free ohmic electrode metal at the source groove and the drain groove to form a source electrode of a cap-shaped structure and a drain electrode of a cap-shaped structure; the deposition area of ​​the gold-free ohmic electrode metal deposition is larger than the etching area of ​​the overetching;

[0015] preparing a passivation layer on the upper surface of the second semiconductor layer, the surface of the source electrode and the surface of the drain electrode;

[0016] Etching the upper surface of the passivation layer between the source electrode and the drain electrode to form a gate groove extending from the upper surface of the passivation layer to the upper surface of the second semiconductor layer;

[0017] A gold-free gate metal is deposited in the gate groove to form a gate electrode.

[0018] The third aspect of the present invention provides a chip, comprising the radio frequency device with gold-free electrode process provided by the first aspect of the present invention.

[0019] A fourth aspect of the present invention provides a device, comprising the chip provided by the third aspect of the present invention.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The present invention provides a radio frequency device with a gold-free electrode process, which realizes the gold-free electrode process through an over-etching scheme, and proposes a source electrode and a drain electrode with a cap-type structure by improving the structure of the source electrode and the drain electrode. The side walls of the source electrode and the drain electrode of the cap-type structure have good contact with the heterostructure material and can form a good ohmic contact. Therefore, the etching accuracy requirements of the device provided by the present invention are low, and the ohmic contact is good. The radio frequency device with a gold-free electrode process provided by the present invention can achieve compatibility between Si-CMOS and GaN device production, and replace the traditional SiC substrate with a Si substrate, which is conducive to the integration, miniaturization and portability of the device, significantly reducing the manufacturing cost, simplifying the production process, reducing the overall manufacturing cost, and improving the feasibility of mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0023] Figure 2 It is a top view of a source electrode and a drain electrode of a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0024] Figure 3 It is a flowchart of the steps of a method for preparing a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0025] Figure 4a to Figure 4f It is a step structure diagram of a method for preparing a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0026] Figure 5 It is a schematic structural diagram of another radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0027] Figure 6a to Figure 6g It is a step structure diagram of another method for preparing a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0028] Figure 7 It is a structural schematic diagram of another radio frequency device without gold electrode process provided by an embodiment of the present invention;

[0029] Figure 8 It is a structural schematic diagram of another radio frequency device with a gold-free electrode process provided by an embodiment of the present invention.

[0030] Reference numerals:

[0031] 1: substrate layer; 2: first semiconductor layer; 21: GaN buffer layer; 22: GaN channel layer; 3: second semiconductor layer; 4: source electrode; 41: source groove; 5: drain electrode; 51: drain groove; 6: passivation layer; 7: gate electrode; 71: gate groove; 8: metal interconnect layer. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0033] Embodiment 1

[0034] The first aspect of this embodiment provides a radio frequency device without gold electrode process. Figure 1 , Figure 1 It is a structural schematic diagram of a radio frequency device with a gold-free electrode process provided by an embodiment of the present invention.

[0035] The present embodiment provides a radio frequency device with a gold-free electrode process, comprising: a substrate layer 1, a first semiconductor layer 2, a second semiconductor layer 3, a source electrode 4, a drain electrode 5, a passivation layer 6 and a gate electrode 7. The substrate layer 1, the first semiconductor layer 2 and the second semiconductor layer 3 are arranged in sequence from bottom to top. The first semiconductor layer 2 and the second semiconductor layer 3 form a heterostructure. The source electrode 4 and the drain electrode 5 are respectively located at both ends of the second semiconductor layer 3 and extend to the inside of the first semiconductor layer 2. The materials of the source electrode 4 and the drain electrode 5 are both gold-free ohmic electrode metals, and the source electrode 4 and the drain electrode 5 are both cap-shaped structures. The passivation layer 6 covers the surface of the second semiconductor layer 3, the source electrode 4 and the drain electrode 5. The gate electrode 7 is located between the source electrode 4 and the drain electrode 5, and extends from the passivation layer 6 to the upper surface of the second semiconductor layer 3. The material of the gate electrode 7 is a gold-free gate metal.

[0036] Specifically, the first semiconductor layer 2 and the second semiconductor layer 3 are single-layer structures or multi-layer structures, and the first semiconductor layer 2 and the second semiconductor layer 3 are both III-V semiconductor materials. The first semiconductor layer 2 and the second semiconductor layer 3 form a heterostructure, and a two-dimensional electron gas 2DEG is formed at the interface through the polarization effect of the material. In the scheme of deep etching or traditional etching, since the etching depth is less than the thickness of the barrier layer, the 2DEG is located below the source and drain electrodes. Therefore, the ohmic contact in the prior art only needs to ensure that the bottom of the source and drain electrodes and the material have good contact to form a good ohmic contact. The source electrode 4 and the drain electrode 5 of the RF device provided in this embodiment are prepared by an over-etching scheme, and the source electrode 4 and the drain electrode 5 extend to the inside of the first semiconductor layer 2, and the side walls of the source electrode 4 and the drain electrode 5 are in contact with the 2DEG. Therefore, it is required that the side walls of the source electrode 4 and the drain electrode 5 have good contact with the material to form a good ohmic contact. This embodiment improves the structure of the source electrode 4 and the drain electrode 5 to provide a cap-shaped source electrode 4 and a drain electrode 5. The side walls of the cap-shaped source electrode 4 and the drain electrode 5 have good contact with the heterostructure material and can form a good ohmic contact.

[0037] Furthermore, the cap-type structure includes: a first electrode portion and a second electrode portion. The first electrode portion extends from the upper surface of the second semiconductor layer 3 to the inside of the first semiconductor layer 2. The second electrode portion extends from the upper surface of the first electrode portion to the upper surfaces of the second semiconductor layer 3 on both sides of the first electrode portion. Specifically, taking the source electrode 4 as an example for further explanation, the portion of the source electrode 4 extending in the vertical direction is the first electrode portion, and the portion of the source electrode 4 extending in the horizontal direction is the second electrode portion. 2DEG is formed between the first electrode portion of the source electrode 4 and the first electrode portion of the drain electrode 5. The length of the second electrode portion is greater than the length of the first electrode portion, and the width of the second electrode portion is greater than the width of the first electrode portion. In this embodiment, the length direction is the direction from left to right in the horizontal plane, and the width direction is the direction perpendicular to the length direction in the horizontal plane.

[0038] In this embodiment, the angle between the side wall of the first electrode portion and the vertical direction is 0 to 10 degrees. Specifically, when the angle between the first electrode portion and the vertical direction is 0 degrees, the cross-sectional shape of the first electrode portion is a rectangle. When the angle between the first electrode portion and the vertical direction is greater than 0 degrees, the cross-sectional shape of the first electrode portion is an inverted trapezoid. Figure 1 and Figure 2 , Figure 2 It is a top view of a source electrode and a drain electrode of a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention. Figure 2 The cap-type structure is further described by taking the case where the angle between the first electrode portion and the vertical direction is greater than 0° as an example. Figure 2In the figure, the dotted box is the top contour of the first electrode part, the solid box is the bottom contour of the first electrode part, and the distances between the four sides of the top of the first electrode part and the four sides of the second electrode part are I1, I2, I3, and I4, respectively. I1, I2, I3, and I4 are greater than 0 and less than 4 μm. I1, I2, I3, and I4 can be equal, that is, the first electrode part and the second electrode part are coaxial; I1, I2, I3, and I4 can also be unequal, that is, the first electrode part and the second electrode part are not coaxial. When the angle between the first electrode part and the vertical direction is 0°, Figure 2 The dotted frame and the solid frame in the figure overlap.

[0039] In this embodiment, the material of the substrate layer 1 includes: one of silicon (Si), silicon carbide (SiC), sapphire, diamond and aluminum nitride (AlN). The material of the first semiconductor layer 2 includes GaN, and the thickness of the first semiconductor layer 2 is 200nm to 2000nm. The material of the second semiconductor layer 3 includes: one of AlGaN, InAlN and AlN, and the thickness of the second semiconductor layer 3 is 10nm to 30nm. The gold-free ohmic electrode metal includes: one of Ti / Al / Ti / W laminated metal, Ti / Al / Ti laminated metal, Ti / Al / W laminated metal, Ti / Al / Ti / TiN laminated metal. The material of the passivation layer 6 includes: SiN x The passivation layer 6 has a thickness of 60-120 nm. The gold-free gate metal includes one of TiN, W and Cu. In this embodiment, the thickness direction is the vertical direction.

[0040] This embodiment improves the structure of the source electrode 4 and the drain electrode 5 to propose a cap-type source electrode 4 and a drain electrode 5. The side walls of the cap-type source electrode 4 and the drain electrode 5 have good contact with the heterostructure material and can form a good ohmic contact, which effectively solves the ohmic contact problem of the over-etching scheme. The device provided by this embodiment has low requirements on etching accuracy and good ohmic contact, and realizes the application of gold-free electrode process in radio frequency devices at low cost.

[0041] The second aspect of this embodiment also provides a method for preparing a radio frequency device without a gold electrode process, see Figure 3 , Figure 4a to Figure 4f , Figure 3 It is a flowchart of the steps of a method for preparing a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention. Figure 4a to Figure 4f It is a step structure diagram of a method for preparing a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention;

[0042] The second aspect of the present embodiment also provides a method for preparing a radio frequency device using a gold-free electrode process, which is used to prepare the radio frequency device using a gold-free electrode process provided by the first aspect of the present embodiment. The method comprises the following steps:

[0043] S1: A first semiconductor layer 2 and a second semiconductor layer 3 are sequentially prepared from bottom to top on the surface of a substrate layer 1. The first semiconductor layer 2 and the second semiconductor layer 3 form a heterostructure.

[0044] In this embodiment, the material of the substrate layer 1 includes: one of silicon (Si), silicon carbide (SiC), sapphire, diamond and aluminum nitride (AlN). Since the RF device of this embodiment is a gold-free electrode process, the device provided by this embodiment can be adapted to a Si substrate and is compatible with a CMOS process.

[0045] Specifically, the substrate layer 1 provides physical support for material growth and subsequent processes. A suitable substrate layer can improve the quality of epitaxially grown crystals, thereby improving reliability. The size and material of the substrate are selected according to usage requirements after comprehensively considering factors such as cost, lattice mismatch, and thermal mismatch. After obtaining the substrate layer 1, the first semiconductor layer 2 and the second semiconductor layer 3 are grown on the substrate layer 1 by MOCVD, MBE and other technologies. The first semiconductor layer 2 and the second semiconductor layer 3 are III-V group semiconductor materials, and the first semiconductor layer 2 and the second semiconductor layer 3 form a heterostructure, and a two-dimensional electron gas 2DEG is formed at the interface through the polarization effect of the material.

[0046] In this embodiment, the first semiconductor layer 2 and the second semiconductor layer 3 are a single-layer structure or a multi-layer structure. Figure 4a The first semiconductor layer 2 and the second semiconductor layer 3 are both single-layer structures, the first semiconductor layer 2 is GaN, and the second semiconductor layer 3 is AlGaN. The first semiconductor layer 2 and the second semiconductor layer 3 form a GaN / AlGaN heterojunction. The thickness of the first semiconductor layer 2 is 200nm to 2000nm, and the thickness of the second semiconductor layer 3 is 10nm to 30nm.

[0047] S2: over-etching is performed on both ends of the second semiconductor layer 3 to form a source groove 41 and a drain groove 51 extending from the upper surface of the second semiconductor layer 3 to the inside of the first semiconductor layer 2 .

[0048] Specifically, see Figure 4b , a first photolithography window is formed at both ends of the second semiconductor layer 3, etching is performed in the first photolithography window, the etching depth is greater than the thickness of the second semiconductor layer 3, and less than the total thickness of the first semiconductor layer 2 and the second semiconductor layer 3, to form a source groove 41 and a drain groove 51 with the bottom located inside the second semiconductor layer 3. It should be understood that after the etching is completed, the photoresist needs to be washed off.

[0049] Furthermore, the etching angle of the overetching is 0-10°, that is, the angle between the side of the source groove 41 and the drain groove 51 and the vertical direction is 0-10°. When the angle between the side of the source groove 41 and the drain groove 51 and the vertical direction is 0°, the cross-sectional shape of the source groove 41 and the drain groove 51 is a rectangle. When the angle between the side of the source groove 41 and the drain groove 51 and the vertical direction is greater than 0°, the cross-sectional shape of the source groove 41 and the drain groove 51 is an inverted trapezoid.

[0050] In this embodiment, the etching method includes ICP etching technology or ALE etching technology.

[0051] S3: Depositing gold-free ohmic electrode metal at the source groove 41 and the drain groove 51 to form a cap-shaped source electrode 4 and a cap-shaped drain electrode 5. The deposition area of ​​the gold-free ohmic electrode metal deposition is larger than the overetched area.

[0052] Specifically, see Figure 4c , a second photolithography window is formed at the position of the first photolithography window, and a gold-free ohmic electrode metal is deposited in the second photolithography window to form a source electrode 4 of a cap-shaped structure and a drain electrode 5 of a cap-shaped structure, and an ohmic contact is formed after low-temperature annealing. The length of the second photolithography window is greater than the length of the first photolithography window, and the width of the second photolithography window is greater than the width of the first photolithography window. The length of the first photolithography window is the length of the source groove 41 and the drain groove 51, and the length of the second photolithography window is the length of the second electrode portion of the source electrode 4 and the drain electrode 5. Since 2DEG is formed at the interface between the first semiconductor layer 2 and the second semiconductor layer 3, the bottom of the source groove 41 and the drain groove 51 is located inside the second semiconductor layer 3, so the side walls of the source electrode 4 and the drain electrode 5 are in contact with 2DEG. It should be understood that the second photolithography window covers the position of the first photolithography window, so that the area of ​​the gold-free ohmic electrode metal deposition is greater than the etching area of ​​the overetching. It should be understood that after the gold-free ohmic electrode metal deposition is completed, it is necessary to strip off, remove the photoresist, and then perform low-temperature annealing. The cross-sectional shapes of the source electrode 4 and the drain electrode 5 are the same as the cross-sectional shapes of the source groove 41 and the drain groove 51. Figure 2 , Figure 4b and Figure 4c , the preparation process of the source electrode 4 and the drain electrode 5 is further described, Figure 2The position of the dotted box is the position of the first photolithography window, the maximum outline of the source electrode 4 and the drain electrode 5 is the position of the second photolithography window, and the distances between the four sides of the first photolithography window and the four sides of the second photolithography window are I1, I2, I3, and I4, respectively. When the gold-free ohmic electrode metal is deposited, the gold-free ohmic electrode metal is filled in the source groove 41 and the drain groove 51 to form a first electrode portion of a cap-shaped structure; the gold-free ohmic electrode metal in the second photolithography window covers the surface of the first electrode portion and the second semiconductor layer 3 to form a second electrode portion of a cap-shaped structure. The length of the first photolithography window is the length of the first electrode portion of the source electrode 4 and the drain electrode 5, the width of the first photolithography window is the width of the first electrode portion of the source electrode 4 and the drain electrode 5, the length of the second photolithography window is the length of the second electrode portion of the source electrode 4 and the drain electrode 5, and the width of the second photolithography window is the width of the second electrode portion of the source electrode 4 and the drain electrode 5.

[0053] Furthermore, in the prior art, the steps for forming an ohmic contact are photolithography, etching, deposition of ohmic metal, and annealing. In the scheme of deep etching or conventional etching, since the etching depth is less than the thickness of the barrier layer, the 2DEG is located below the source and drain electrodes. Therefore, in the prior art, the ohmic contact only needs to ensure that the bottom of the source and drain electrodes and the material have good contact to form a good ohmic contact. When the over-etching scheme is adopted, since the side walls of the source electrode 4 and the drain electrode 5 are in contact with the 2DEG, it is required that the side walls of the source electrode 4 and the drain electrode 5 have good contact with the material to form a good ohmic contact. The present embodiment adopts an over-etching scheme to prepare the source electrode 4 and the drain electrode 5, thereby reducing the device's requirements for etching accuracy, and realizes a cap-type source electrode 4 and a cap-type drain electrode 5 through a two-step photolithography process to improve the electrical sidewall contact. More specifically, the present embodiment forms a first photolithography window by performing a first photolithography, etches in the first photolithography window to form an electrode groove, and then performs a second photolithography to form a second photolithography window having a length greater than the first photolithography window. When deposition is performed in the second photolithography window, the deposition area can fully cover the electrode groove, so that the gold-free ohmic electrode metal is fully filled in the electrode groove to form a cap-type source electrode 4 and a cap-type drain electrode 5, thereby improving the sidewall contact of the gold-free ohmic electrode metal and forming a good ohmic contact after annealing.

[0054] In this embodiment, the deposition process of the gold-free ohmic electrode metal includes magnetron sputtering growth or electron beam evaporation technology. The temperature of low-temperature annealing is 500-600° C., and the annealing atmosphere is H2 or O3 or air atmosphere. The gold-free ohmic electrode metal includes: one of Ti / Al / Ti / W laminated metal, Ti / Al / Ti laminated metal, Ti / Al / W laminated metal, and Ti / Al / Ti / TiN laminated metal.

[0055] In this embodiment, between step S3 and step S4, active area isolation is also included.

[0056] Specifically, etching is performed at both ends of the device through ICP etching or ALE etching technology to form mesa isolation; or, ion implantation is performed at both ends of the device through ion implantation technology to form implantation isolation.

[0057] S4: preparing a passivation layer 6 on the upper surface of the second semiconductor layer 3 , the surface of the source electrode 4 , and the surface of the drain electrode 5 .

[0058] Specifically, see Figure 4d , deposited on the device surface as a whole: SiN x , Al2O3, SiO2, HfO2, and the deposition thickness is 60-120nm to form a passivation layer 6. The passivation layer 6 can increase the 2DEG density, reduce the leakage level, and improve the reliability of the device.

[0059] S5 : etching the upper surface of the passivation layer 6 between the source electrode 4 and the drain electrode 5 to form a gate groove 71 extending from the upper surface of the passivation layer 6 to the upper surface of the second semiconductor layer 3 .

[0060] Specifically, see Figure 4e A gate photolithography window is formed on the upper surface of the passivation layer 6 between the source electrode 4 and the drain electrode 5 , and etching is performed in the gate photolithography window with an etching depth equal to the thickness of the passivation layer 6 to form a gate groove 71 .

[0061] S6: See Figure 4f , gold-free gate metal is deposited in the gate groove 71 to form the gate electrode 7.

[0062] In this embodiment, the gold-free gate metal includes one of TiN, W and Cu.

[0063] The method for preparing a radio frequency device with a gold-free electrode process provided in this embodiment optimizes the ohmic contact formation step so that the deposition area of ​​the gold-free ohmic electrode metal deposition is larger than the over-etched etching area, thereby ensuring that the gold-free ohmic electrode metal is fully filled in the electrode groove to form a cap-type source electrode 4 and a cap-type drain electrode 5, thereby improving the side wall contact of the gold-free ohmic electrode metal and forming a good ohmic contact after annealing.

[0064] The third aspect of the present embodiment provides a chip, which is a radio frequency chip, including the radio frequency device with gold-free electrode process provided by the first aspect of the present embodiment. Exemplarily, the chip is a radio frequency PA chip.

[0065] The fourth aspect of the present embodiment provides a device, including the chip provided by the third aspect of the present embodiment. Exemplarily, the device is a router device including the above-mentioned radio frequency PA chip.

[0066] The present embodiment provides a radio frequency device with a gold-free electrode process, which realizes the gold-free electrode process through an over-etching scheme, and proposes a source electrode 4 and a drain electrode 5 of a cap-type structure by improving the structure of the source electrode 4 and the drain electrode 5. The sidewalls of the source electrode 4 and the drain electrode 5 of the cap-type structure have good contact with the heterostructure material and can form a good ohmic contact. The radio frequency device with a gold-free electrode process provided in the present embodiment can achieve compatibility with the production of Si-CMOS and GaN devices, and replace the traditional SiC substrate with a Si substrate, which is conducive to the integration, miniaturization and portability of the device, significantly reducing the manufacturing cost, simplifying the production process, reducing the overall manufacturing cost, and improving the feasibility of mass production. The preparation method provided in the present embodiment reduces the annealing temperature of the formed ohmic contact, which is conducive to improving the performance of Si-based heterogeneous integrated III-V compound semiconductor devices and improving the reliability of the device. The present embodiment applies the gold-free electrode process to radio frequency devices, modules and equipment, improves the electrical properties of radio frequency devices, and broadens the application scenarios of the gold-free electrode process.

[0067] Embodiment 2

[0068] Based on the first embodiment, this embodiment provides another RF device without gold electrode process and its preparation method. Figure 5 , Figure 6a to Figure 6g , Figure 5 is a schematic structural diagram of another radio frequency device without gold electrode process provided by an embodiment of the present invention, Figure 6a to Figure 6g It is a step structure diagram of another method for preparing a radio frequency device using a gold-free electrode process provided by an embodiment of the present invention.

[0069] The radio frequency device of the gold-free electrode process provided in this embodiment includes: a substrate layer 1, a first semiconductor layer 2, a second semiconductor layer 3, a source electrode 4, a drain electrode 5, a passivation layer 6, a gate electrode 7 and a metal interconnection layer 8.

[0070] In this embodiment, the material of the substrate layer 1 is Si. The first semiconductor layer 2 is a two-layer structure, including: a GaN buffer layer 21 and a GaN channel layer 22. The second semiconductor layer 3 is a single-layer structure, including an AlGaN barrier layer. The source electrode 4 and the drain electrode 5 are made of Ti / Al / Ti / TiN laminated metal. The angle between the first electrode portion of the source electrode 4 and the drain electrode 5 and the vertical direction is 0°, that is, the cross-sectional shape of the first electrode portion is rectangular. The material of the passivation layer 6 is SiN. The gate electrode 7 is a T-type gate, the gate foot extends from the upper surface of the passivation layer 6 to the upper surface of the second semiconductor layer 3, the gate cap is located on the upper surface of the passivation layer 6, and the material of the gate electrode 7 is TiN. The metal interconnect layer 8 extends from the upper surface of the passivation layer 6 to the upper surfaces of the source electrode 4, the drain electrode 5 and the gate electrode 7.

[0071] The method for preparing a radio frequency device using a gold-free electrode process provided in this embodiment comprises the following steps:

[0072] Step 1: If Figure 6a As shown, Si material is obtained as substrate layer 1. GaN buffer layer 21 and GaN channel layer 22 are sequentially prepared from bottom to top on the surface of substrate layer 1 to obtain first semiconductor layer 2. AlGaN barrier layer is grown on the upper surface of first semiconductor layer 2 to obtain second semiconductor layer 3.

[0073] Step 2: If Figure 6b As shown, ICP etching is performed on the second semiconductor layer 3 to form a source groove 41 and a drain groove 51 .

[0074] Step 2a: Place the epitaxial substrate obtained in step 1 on a hot plate for baking.

[0075] Step 2b: Apply glue and spin glue on the second semiconductor layer 3, and place the sample after applying glue and spinning glue on a hot plate for baking.

[0076] Step 2c: Use photolithography technology to define the source and drain regions, i.e., the first photolithography window, on the second semiconductor layer 3, and use ICP etching equipment to perform Cl-based etching in the source and drain regions. The etching depth reaches the GaN channel layer 22, and the etching angle is 0°, forming a rectangular source groove 41 and a drain groove 51.

[0077] Step 2d: Clean the etched sample to remove the photoresist, then rinse the sample with ultrapure water and blow dry with nitrogen.

[0078] Step 3: If Figure 6c As shown, Ti / Al / Ti / TiN stacked metal is evaporated by electron beam at the positions of the source groove 41 and the drain groove 51 to form the source electrode 4 and the drain electrode 5 of the hat type structure.

[0079] Step 3a: forming a second photolithography window on the second semiconductor layer 3 by photolithography.

[0080] Step 3a1: Place the epitaxial substrate obtained in step 2d on a hot plate for baking.

[0081] Step 3a2: Apply peeling glue and spin glue on the second semiconductor layer 3, and place the sample on a hot plate for baking.

[0082] Step 3a3: Apply and spin photoresist on the stripping glue, and place the sample on a hot plate for baking.

[0083] Step 3a4: Place the sample that has been coated and spun into a photolithography machine to expose the coated surface, and place the exposed sample into a developer to remove the photoresist, and then rinse it with ultrapure water and blow it with nitrogen to form a second photolithography window. The length of the second photolithography window is greater than the length of the first photolithography window, the width of the second photolithography window is greater than the width of the first photolithography window, and the second photolithography window covers the first photolithography window.

[0084] Step 3b: Evaporate gold-free ohmic electrode metal Ti / Al / Ti / TiN on the sample to obtain a cap-shaped source electrode 4 and a cap-shaped drain electrode 5. The length of the first photolithography window is the length of the first electrode portion of the source electrode 4 and the drain electrode 5, the width of the first photolithography window is the width of the first electrode portion of the source electrode 4 and the drain electrode 5, the length of the second photolithography window is the length of the second electrode portion of the source electrode 4 and the drain electrode 5, and the width of the second photolithography window is the width of the second electrode portion of the source electrode 4 and the drain electrode 5.

[0085] Step 3b1: Place the sample with the second photolithography window into a plasma stripper for bottom film treatment.

[0086] Step 3b2: Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 Torr, the gold-free ohmic electrode metal Ti / Al / Ti / TiN is evaporated on the sample. Ti / Al / Ti / TiN is a metal stack structure composed of four layers of metals, Ti, Al, Ti, and TiN, from bottom to top.

[0087] Step 3b3: After the ohmic metal is evaporated, a stripping process is performed on the sample to remove the ohmic metal, photoresist and stripping glue outside the second photolithography window, and then the sample is rinsed with ultrapure water and blown dry with nitrogen.

[0088] Step 3b4: Place the sample after ohmic metal evaporation and stripping in an annealing device for low-temperature annealing to form an ohmic contact between the source electrode 4 and the drain electrode 5 and the GaN channel layer 22. The low-temperature annealing temperature is 500° C., the annealing time is 90 seconds, and the atmosphere is O2.

[0089] Step 4: Use ICP etching equipment to form mesa isolation.

[0090] Step 4a: Photolithography isolation regions are formed at both ends of the device.

[0091] Step 4a1: Place the sample on a hot plate for baking.

[0092] Step 4a2: Apply and spin the photoresist, and bake the sample on a hot plate.

[0093] Step 4a3: Place the sample in a photolithography machine to expose the photoresist in the electrical isolation area, then place the exposed sample in a developer to remove the photoresist in the electrical isolation area, and rinse it with ultrapure water and blow dry it with nitrogen.

[0094] Step 4b: Etching mesa isolation in the isolation area.

[0095] Step 4b1: Place the photolithography-finished sample into an ICP etching device for etching until the GaN buffer layer 21 is formed.

[0096] Step 4b2: The sample was sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an isopropanol solution for cleaning to remove the photoresist outside the electrical isolation area. Finally, the sample was rinsed with ultrapure water and dried with nitrogen gas.

[0097] Step 5: Figure 6d As shown, the growth of the passivation layer 6 is performed using PECVD.

[0098] Step 5a: Perform an organic wash on the sample.

[0099] Step 5a1: Place the sample in an acetone solution and ultrasonically clean it for 10 minutes.

[0100] Step 5a2: Place the sample in an isopropanol solution and ultrasonically clean it for 3 minutes.

[0101] Step 5a3: Rinse the sample with ultrapure water and blow dry with nitrogen.

[0102] Step 5b: Perform inorganic cleaning on the sample that underwent organic cleaning.

[0103] Step 5b1: Place the sample in a 55°C ammonia:water solution (1:6) and treat for 5 min.

[0104] Step 5b2: Rinse the sample with ultrapure water and blow dry with nitrogen.

[0105] Step 5c: Use PECVD to grow SiN on the entire wafer with a growth thickness of 60 nm to obtain a passivation layer 6.

[0106] Step 6: Figure 6eAs shown, a gate foot (GRSS) region is photolithographically formed on the passivation layer 6, and the GRSS region is etched using an ICP etching device.

[0107] Step 6a: Photolithography a GRSS region on the passivation layer 6 to form a gate photolithography window. The length of the gate photolithography window is the length of the T-type gate foot.

[0108] Step 6a1: Place the sample on a hot plate and bake.

[0109] Step 6a2: Apply glue and spin glue on the sample and place the sample on a hot plate for baking.

[0110] Step 6a3: Place the sample that has been coated and spun into a photolithography machine to expose the coated surface, and place the exposed sample into a developer to remove the photoresist, and then rinse it with ultrapure water and blow dry it with nitrogen.

[0111] Step 6b: Use ICP etching equipment to etch in the GRSS region to remove the passivation layer 6 in the GRSS region and form a gate groove 71 .

[0112] Step 6b1: Place the developed sample into an ICP etching device to etch away the passivation layer 6 in the GRSS region.

[0113] Step 6b2: The sample is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an isopropanol solution for cleaning.

[0114] Step 7: Figure 6f As shown, a gold-free gate metal deposition area is photolithographically formed on the passivation layer 6, and an electron beam evaporation device is used to form a T-shaped gate electrode 7.

[0115] Step 7a: Photolithography a gold-free gate metal deposition area on the passivation layer 6 to form a gate cap photolithography window. The length of the gate cap photolithography window is the length of the T-shaped gate cap.

[0116] Step 7a1: Bake the sample on a hot plate.

[0117] Step 7a2: Apply glue and spin glue on the sample and place the sample on a hot plate for baking.

[0118] Step 7a3: Apply and spin photoresist on the stripping glue, and place the sample on a hot plate for baking.

[0119] Step 7a4: Place the sample that has been coated and spun into a photolithography machine to expose the coated surface, and place the exposed sample into a developer to remove the photoresist, and then rinse it with ultrapure water and blow dry it with nitrogen.

[0120] Step 7b: Deposit gold-free gate metal in the gate cap lithography window using an electron beam evaporation method to form a T-type gate electrode 7:

[0121] Step 7b: Perform base film treatment on the developed sample.

[0122] Step 7b2: Place the cleaned sample into an electron beam evaporation device to evaporate and grow TiN gold-free gate metal.

[0123] Step 7b3: After the ohmic metal is evaporated, the sample is subjected to a lift-off process, and then rinsed with ultrapure water and blown dry with nitrogen.

[0124] Step 8: Figure 6g As shown, a metal interconnection layer opening area is photolithographically formed on the passivation layer 6, and the passivation layer 6 in the interconnection opening area is etched away using an ICP process, and a metal interconnection layer 8 is manufactured using an electron beam evaporation process.

[0125] Step 8a: Photolithography a metal interconnection layer opening region on the passivation layer 6. Specifically, the metal interconnection layer opening region is located on the source electrode 4, the drain electrode 5 and the gate electrode 7.

[0126] Step 8a1: Bake the sample on a hot plate.

[0127] Step 8a2: Apply and spin the photoresist, and bake the sample on a hot plate.

[0128] Step 8a3: Place the sample in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnection layer.

[0129] Step 8a4: Place the exposed sample in a developer to remove the photoresist in the interconnect opening area, and rinse with ultrapure water and blow dry with nitrogen.

[0130] Step 8b: Remove the passivation layer 6 in the interconnect opening area using an ICP etching process.

[0131] Step 8b1: ​​Perform interconnect area lithography on the sample.

[0132] Step 8b2: Place the sample after the metal interconnect hole etching is completed on a hot plate for baking.

[0133] Step 8b3: Apply and spin the peeling glue to the entire sample, and place the sample on a hot plate for baking.

[0134] Step 8b4: Coating and spinning of photoresist on the stripping glue is performed and the sample is baked on a hot plate.

[0135] Step 8b5: Place the sample that has been coated and spun into a photolithography machine to expose the photoresist in the metal interconnection area, then place the exposed sample into a developer to remove the photoresist and stripping glue in the metal interconnection area, and rinse it with ultrapure water and blow dry it with nitrogen.

[0136] Step 8c: evaporating a metal interconnection layer 8 on the electrodes in the metal interconnection region and the photoresist in the inactive region.

[0137] Step 8c1: Place the sample after photolithography into a plasma stripper for bottom film treatment.

[0138] Step 8c2: Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 -6 After the evaporation of the metal interconnection layer 8, the interconnection metal is evaporated on the electrodes and the inactive area in the metal interconnection area and the photoresist outside the metal interconnection area to form a metal interconnection layer 8.

[0139] Step 8c3: Stripping the sample after interconnect metal evaporation to remove the metal, photoresist and stripping glue outside the interconnect opening area, and rinse the sample with ultrapure water and blow dry with nitrogen to complete device manufacturing.

[0140] Embodiment 3

[0141] Based on the first embodiment, this embodiment provides another RF device without gold electrode process and its preparation method. Figure 7 , Figure 7 It is a schematic structural diagram of another radio frequency device using a gold-free electrode process provided in an embodiment of the present invention.

[0142] The radio frequency device of the gold-free electrode process provided in this embodiment includes: a substrate layer 1, a first semiconductor layer 2, a second semiconductor layer 3, a source electrode 4, a drain electrode 5, a passivation layer 6, a gate electrode 7 and a metal interconnection layer 8.

[0143] In this embodiment, the material of the substrate layer 1 is Si. The first semiconductor layer 2 is a two-layer structure, including: a GaN buffer layer 21 and a GaN channel layer 22. The second semiconductor layer 3 is a single-layer structure, including an AlGaN barrier layer. The material of the source electrode 4 and the drain electrode 5 is Ti / Al / Ti / W laminated metal. The angle between the first electrode portion of the source electrode 4 and the drain electrode 5 and the vertical direction is 10°, and the cross-sectional shape of the first electrode portion is an inverted trapezoid. The material of the passivation layer 6 is SiN. The gate electrode 7 is a T-type gate, and the material is Cu. The metal interconnection layer 8 extends from the upper surface of the passivation layer 6 to the upper surfaces of the source electrode 4, the drain electrode 5 and the gate electrode 7.

[0144] The method for preparing a radio frequency device without a gold electrode process provided in this embodiment includes:

[0145] Step 1: A GaN buffer layer 21 and a GaN channel layer 22 are sequentially prepared from bottom to top on the surface of the substrate layer 1 to obtain a first semiconductor layer 2. An AlGaN barrier layer is grown on the upper surface of the first semiconductor layer 2 to obtain a second semiconductor layer 3. The GaN channel layer 22 and the second semiconductor layer 3 form a heterostructure.

[0146] Step 2: Over-etching is performed on both ends of the second semiconductor layer 3 by using an ALE etching device to form a source groove 41 and a drain groove 51 extending from the upper surface of the second semiconductor layer 3 to the inside of the first semiconductor layer 2 .

[0147] Specifically, the etching angle of the over-etching is 10°, forming the source groove 41 and the drain groove 51 with an inverted trapezoidal cross-sectional shape.

[0148] Step 3: Through magnetron sputtering process, gold-free ohmic electrode metal is deposited at the positions of source groove 41 and drain groove 51 to form a cap-shaped source electrode 4 and a cap-shaped drain electrode 5, and ohmic contact is formed after low-temperature annealing. The deposition area of ​​gold-free ohmic electrode metal deposition is larger than the etched area of ​​over-etching.

[0149] In this embodiment, the low temperature annealing temperature is 600° C., the annealing atmosphere is air atmosphere, the annealing time is 90 seconds, and the gold-free ohmic electrode metal is Ti / Al / Ti / W laminated metal.

[0150] Step 4: Through ion implantation technology, use large beam ion implantation equipment to perform ion implantation at both ends of the device to form implantation isolation.

[0151] Step 5: Using MOCVD technology, a 120 nm SIN is grown on the upper surface of the second semiconductor layer 3 , the surface of the source electrode 4 , and the surface of the drain electrode 5 to form a passivation layer 6 .

[0152] Step six: Etching is performed on the upper surface of the passivation layer 6 between the source electrode 4 and the drain electrode 5 by using an ALE etching device to form a gate groove 71 extending from the upper surface of the passivation layer 6 to the upper surface of the second semiconductor layer 3 .

[0153] Step seven: depositing gold-free gate metal in the gate groove 71 by magnetron sputtering equipment to form the gate electrode 7 .

[0154] In this embodiment, the gold-free gate metal is Cu. The gate electrode 7 is a T-shaped gate.

[0155] Step eight: photolithography a metal interconnection layer opening area on the passivation layer 6, etching away the passivation layer 6 in the interconnection opening area using an ALE process, and forming a metal interconnection layer 8 using a magnetron sputtering process.

[0156] Embodiment 4

[0157] Based on the first embodiment, this embodiment provides another RF device without gold electrode process and its preparation method. Figure 8 , Figure 8 It is a structural schematic diagram of another radio frequency device with a gold-free electrode process provided by an embodiment of the present invention.

[0158] The radio frequency device of the gold-free electrode process provided in this embodiment includes: a substrate layer 1, a first semiconductor layer 2, a second semiconductor layer 3, a source electrode 4, a drain electrode 5, a passivation layer 6, a gate electrode 7 and a metal interconnection layer 8.

[0159] In this embodiment, the material of the substrate layer 1 is Si. The first semiconductor layer 2 is a two-layer structure, including: a GaN buffer layer 21 and a GaN channel layer 22. The second semiconductor layer 3 is a single-layer structure, including an AlGaN barrier layer. The source electrode 4 and the drain electrode 5 are made of Ti / Al / Ti / W laminated metal. The angle between the side of the source electrode 4 and the drain electrode 5 and the vertical direction is 0°, and the cross-sectional shape of the source electrode 4 and the drain electrode 5 is rectangular. The material of the passivation layer 6 is SiN. The cross-sectional shape of the gate electrode 7 is rectangular, and the gate electrode 7 extends from the upper surface of the passivation layer 6 to the upper surface of the second semiconductor layer 3, and the material of the gate electrode 7 is Cu. The metal interconnect layer 8 extends from the upper surface of the passivation layer 6 to the upper surfaces of the source electrode 4, the drain electrode 5 and the gate electrode 7.

[0160] The method for preparing a radio frequency device without a gold electrode process provided in this embodiment includes:

[0161] Step 1: A GaN buffer layer 21 and a GaN channel layer 22 are sequentially prepared from bottom to top on the surface of the substrate layer 1 to obtain a first semiconductor layer 2. An AlGaN barrier layer is grown on the upper surface of the first semiconductor layer 2 to obtain a second semiconductor layer 3. The GaN channel layer 22 and the second semiconductor layer 3 form a heterostructure.

[0162] Step 2: Over-etching is performed on both ends of the second semiconductor layer 3 by using an ALE etching device to form a source groove 41 and a drain groove 51 extending from the upper surface of the second semiconductor layer 3 to the inside of the first semiconductor layer 2 .

[0163] Specifically, the etching angle of the over-etching is 0°, and a source groove 41 and a drain groove 51 with a rectangular cross-sectional shape are formed.

[0164] Step 3: Through magnetron sputtering process, gold-free ohmic electrode metal is deposited at the positions of source groove 41 and drain groove 51 to form a cap-shaped source electrode 4 and a cap-shaped drain electrode 5, and ohmic contact is formed after low-temperature annealing. The deposition area of ​​gold-free ohmic electrode metal deposition is larger than the etched area of ​​over-etching.

[0165] Step 4: Through ion implantation technology, use large beam ion implantation equipment to perform ion implantation at both ends of the device to form implantation isolation.

[0166] Step 5: Using MOCVD technology, a 120 nm SIN is grown on the upper surface of the second semiconductor layer 3 , the surface of the source electrode 4 , and the surface of the drain electrode 5 to form a passivation layer 6 .

[0167] Step six: forming a gate photolithography window on the upper surface of the passivation layer 6 between the source electrode 4 and the drain electrode 5 , and performing etching in the gate photolithography window to a depth equal to the thickness of the passivation layer 6 , so as to form a gate groove 71 .

[0168] Step 7: Using magnetron sputtering equipment, a gold-free gate metal is deposited in the gate lithography window to form a gate electrode 7.

[0169] In this embodiment, the gold-free gate metal is Cu. The gate electrode 7 is a T-shaped gate.

[0170] Step eight: photolithography a metal interconnection layer opening area on the passivation layer 6, etching away the passivation layer 6 in the interconnection opening area using an ALE process, and forming a metal interconnection layer 8 using a magnetron sputtering process.

[0171] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A radio frequency device without gold electrode process, characterized in that: include: A substrate layer, a first semiconductor layer, a second semiconductor layer, a source electrode, a drain electrode, a passivation layer and a gate electrode, wherein: The substrate layer, the first semiconductor layer and the second semiconductor layer are arranged in sequence from bottom to top; the first semiconductor layer and the second semiconductor layer form a heterostructure; The source electrode and the drain electrode are respectively located at two ends of the second semiconductor layer and extend into the first semiconductor layer; the materials of the source electrode and the drain electrode are both gold-free ohmic electrode metals, and the source electrode and the drain electrode are both cap-shaped structures; The passivation layer covers the surfaces of the second semiconductor layer, the source electrode and the drain electrode; The gate electrode is located between the source electrode and the drain electrode, and extends from the passivation layer to the upper surface of the second semiconductor layer; the material of the gate electrode is a gold-free gate metal.

2. The radio frequency device with gold-free electrode process according to claim 1, characterized in that: The cap-shaped structure comprises: a first electrode portion and a second electrode portion; The first electrode portion extends from the upper surface of the second semiconductor layer to the interior of the first semiconductor layer; The second electrode portion extends from an upper surface of the first electrode portion to upper surfaces of the second semiconductor layer at both sides of the first electrode portion.

3. The radio frequency device with gold-free electrode process according to claim 2, characterized in that: The included angle between the side wall of the first electrode portion and the vertical direction is 0-10°.

4. The radio frequency device with gold-free electrode process according to claim 1, characterized in that: The material of the substrate layer includes: one of Si, SiC, sapphire, diamond and AlN; The material of the passivation layer includes: SiN x , One of Al2O3, SiO2, and HfO2.

5. The radio frequency device with gold-free electrode process according to claim 1, characterized in that: The gold-free ohmic electrode metal comprises: one of Ti / Al / Ti / W laminated metal, Ti / Al / Ti laminated metal, Ti / Al / W laminated metal, and Ti / Al / Ti / TiN laminated metal; The gold-free gate metal includes one of TiN, W and Cu.

6. The radio frequency device with gold-free electrode process according to claim 1, characterized in that: The first semiconductor layer includes a GaN buffer layer and a GaN channel layer arranged sequentially from bottom to top; The material of the second semiconductor layer includes: one of AlGaN, InAlN and AlN.

7. A method for preparing a radio frequency device without gold electrode technology, characterized in that: The method for preparing a radio frequency device using a gold-free electrode process as claimed in any one of claims 1 to 6 comprises the following steps: A first semiconductor layer and a second semiconductor layer are sequentially prepared from bottom to top on the surface of the substrate layer; the first semiconductor layer and the second semiconductor layer form a heterostructure; Over-etching is performed at both ends of the second semiconductor layer to form a source groove and a drain groove extending from the upper surface of the second semiconductor layer to the inside of the first semiconductor layer; Depositing a gold-free ohmic electrode metal at the source groove and the drain groove to form a source electrode of a cap-shaped structure and a drain electrode of a cap-shaped structure; the deposition area of ​​the gold-free ohmic electrode metal deposition is larger than the etching area of ​​the overetching; preparing a passivation layer on the upper surface of the second semiconductor layer, the surface of the source electrode and the surface of the drain electrode; Etching the upper surface of the passivation layer between the source electrode and the drain electrode to form a gate groove extending from the upper surface of the passivation layer to the upper surface of the second semiconductor layer; A gold-free gate metal is deposited in the gate groove to form a gate electrode.

8. The method for preparing a radio frequency device without gold electrode process according to claim 7, characterized in that: Over-etching is performed at two ends of the second semiconductor layer, including: Forming first photolithography windows at two ends of the second semiconductor layer, and performing etching in the first photolithography windows; The step of depositing a gold-free ohmic electrode metal at the source groove and the drain groove comprises: A second photolithography window is formed at the position of the first photolithography window, and gold-free ohmic electrode metal deposition is performed in the second photolithography window; the length of the second photolithography window is greater than the length of the first photolithography window, and the width of the second photolithography window is greater than the width of the first photolithography window.

9. A chip, characterized in that: A radio frequency device comprising the gold-free electrode process as described in any one of claims 1 to 6.

10. A device, characterized in that: Comprising the chip as claimed in claim 9.

Images