4kV low-resistance super-junction planar gate SiC VDMOS device structure and preparation method thereof

Abstract

The invention discloses a 4kV low-resistance super-junction planar gate SiC VDMOS device structure and a preparation method thereof, and relates to the technical field of silicon carbide power devices, the 4kV low-resistance super-junction planar gate SiC VDMOS device structure comprises drain electrode metal, an n + SiC substrate and an n-type drift layer are arranged above the drain electrode metal, an n-type region is arranged in the middle of the n-type drift layer, a p-type shielding layer is arranged below the n-type region, p-type regions are arranged on two sides of the n-type drift layer, and the n + SiC substrate is arranged above the n-type region. A p-type well region is arranged above the p-type region; strip-shaped Schottky metal and strip-shaped polycrystalline silicon are arranged in the p-type well region, and an n + source region, source electrode metal, an insulating medium and grid electrode metal are arranged above the p-type well region; and the device is prepared. By constructing the transverse and longitudinal double-space charge region structure, the doping concentration of the n-type drift layer of the device is higher, the on-resistance of the device is reduced, the ohmic contact resistance and the body diode on-resistance of the device can be effectively reduced by the Schottky metal and polycrystalline silicon structure, and the follow current loss of the device is further reduced.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide power device technology, specifically to a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure and its fabrication method. Background Technology

[0002] Due to its wide bandgap characteristics, SiC VDMOS devices naturally have higher voltage withstand capability compared to Si VDMOS devices. As the voltage withstand capability continues to increase, under voltage withstand conditions above 3kV, the increased thickness of the n-type drift layer will introduce on-resistance and body diode freewheeling loss, affecting the conduction characteristics of the device. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure and its fabrication method, thereby solving the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure, including a drain metal located at the bottom of the device, an n+SiC substrate and an n-type drift layer disposed above the drain metal, an n-type region disposed in the middle of the n-type drift layer, a p-type shielding layer disposed below the n-type region, p-type regions disposed on both sides of the n-type drift layer, and a p-type well region disposed above the p-type region; The p-type well region contains strips of Schottky metal and strips of polysilicon. An n+ source region is disposed above the p-type well region. A source metal is disposed above the n+ source region. An insulating dielectric is disposed above the source metal. A gate metal is disposed above the insulating dielectric.

[0005] To further optimize this technical solution, the doping concentration of the n+SiC substrate is 2×10⁻⁶. 17 Up to 8×10 17 cm -3 The doping concentration of the n-type drift layer is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type region is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type shielding layer is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type well region is 1×10⁻⁶. 17 Up to 5×10 17 cm-3 The doping concentration of the n-type region is 6 × 10⁻⁶. 17 Up to 10×10 17 cm -3 The doping concentration of the n+ source region is 2×10⁻⁶. 17 Up to 8×10 17 cm -3 .

[0006] To further optimize this technical solution, the insulating medium is silicon dioxide, and the gate metal is one of aluminum, nickel, and copper, or an alloy of the above metals.

[0007] To further optimize this technical solution, the thickness of the n-type SiC substrate is 0.6 μm; the thickness of the n-type drift layer is 50 μm; the width of the p-type region is 1.2 μm and the thickness is 35 μm; the width of the p-type well region is 2.5 μm and the maximum thickness is 1 μm, with the p-type well region located near the gate side of the n+ source region having a width of 200 nm; the width of the insulating medium is 1.8 μm and the thickness is 50 nm; the width of the gate metal is 1.6 μm and the thickness is 300 nm; the width of the p-type shielding layer is 1 μm and the thickness is 200 nm, with its top edge 2 μm from the bottom edge of the insulating medium; and the width of the n+ source region is 500 nm and the thickness is 300 nm.

[0008] To further optimize this technical solution, the width of the polycrystalline silicon is 200nm, the spacing between the strip-shaped polycrystalline silicon is 200nm, the distance between the outermost polycrystalline silicon and the edge of the device cell is 200nm, and the distance between the outermost polycrystalline silicon and the Schottky metal is 300nm.

[0009] To further optimize this technical solution, the width of the device cell is 6μm; the total width of the p-type well regions located on the left and right sides of the device is 5μm; and the width of the n-type region is 300nm and the thickness is 1μm.

[0010] To further optimize this technical solution, the Schottky metal has a width of 300 nm and a thickness of 1 μm, and the Schottky metal is in direct contact with the n-type drift layer to form a Schottky diode.

[0011] To further optimize this technical solution, the n-type drift layer, n-type region, p-type region, and p-type well region form a transverse withstand voltage structure inside the n-type drift layer, thereby forming a superjunction structure of the device.

[0012] A method for fabricating a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure, based on the above-mentioned device, includes the following specific steps: S1. Epitaxial growth of an n-type drift layer on an n+SiC substrate; S2. Deposit a barrier layer above the n-type drift layer, etch through-holes in the p-type region, and implant ions to form the p-type region; S3. Remove the barrier layer formed in step S2, deposit a new barrier layer above the n-type drift layer, etch the vias of the p-type shielding layer, and ion implant to form the p-type shielding layer. S4. Remove the barrier layer formed in step S3, deposit a new barrier layer above the n-type drift layer, etch the vias in the p-type well region, and implant ions to form the p-type well region. S5. Remove the barrier layer formed in step S4, deposit a new barrier layer, etch the Schottky metal via, use RIE (Reactive Ion Etching) to form Schottky metal trenches, and deposit Schottky metal. S6. Remove the barrier layer formed in step S5, deposit a new barrier layer, etch polysilicon vias, use RIE (Reactive Ion Etching) to form polysilicon trenches, and deposit polysilicon. S7. Remove the barrier layer formed in step S6, deposit a new barrier layer, etch the via in the n+ source region, and implant ions to form the n+ source region. S8. Remove the barrier layer formed in step S7, deposit a new barrier layer, etch the n-type region via, and implant ions to form the n-type region. S9. Remove the barrier layer formed in step S8, deposit a new barrier layer, etch to form an insulating dielectric via, and deposit to form an insulating dielectric. S10. Remove the barrier layer formed in step S9, deposit a new barrier layer, etch the gate metal via, and deposit the gate metal through the via. S11. Remove the barrier layer formed in step S10, deposit a new barrier layer, etch the source metal via, and deposit the source metal through the via. S12. Remove the barrier layer formed in step S11, deposit a new barrier layer, and form a protective layer on top of the device. S13. Flip the device over and grind the n+SiC substrate of the device; S14. Deposit drain metal on the n+SiC substrate of the device to form a complete device structure.

[0013] To further optimize this technical solution, the initial thickness of the n+SiC substrate in step S1 is 1.5 μm, and the thickness of the n+SiC substrate in step S13 is reduced to 0.6 μm by grinding.

[0014] Compared with the prior art, the present invention provides a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure and its fabrication method, which has the following beneficial effects: The structure and fabrication method of this 4kV low-resistivity superjunction planar gate SiC VDMOS device, by constructing a horizontal and vertical dual space charge region structure, enable a higher doping concentration of the n-type drift layer of the device, thereby reducing the on-resistance of the device. The Schottky metal and polysilicon structure can effectively reduce the ohmic contact resistance and the on-state voltage drop of the body diode, further reducing the freewheeling loss of the device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a cross-sectional schematic diagram of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention; Figure 2 This is a schematic cross-sectional view of the device in step S1 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 3 This is a schematic cross-sectional view of the device in step S2 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 4 This is a schematic cross-sectional view of the device in step S3 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 5 This is a schematic cross-sectional view of the device in step S4 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention; Figure 6-7 This is a schematic cross-sectional view of the device in step S5 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 8-9 This is a schematic cross-sectional view of the device in step S6 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 10 This is a schematic cross-sectional view of the device in step S7 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 11 This is a schematic cross-sectional view of the device in step S8 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 12This is a schematic cross-sectional view of the device in step S9 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 13 This is a schematic cross-sectional view of the device in step S10 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 14 This is a schematic cross-sectional view of the device in step S11 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 15 This is a schematic cross-sectional view of the device in step S12 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 16 This is a schematic cross-sectional view of the device in step S13 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention. Figure 17 This is a schematic cross-sectional view of the device in step S14 of the fabrication method of a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure proposed in this invention.

[0017] In the figure: 1. Drain metal; 2. n+SiC substrate; 3. n-type drift layer; 4. Polysilicon; 5. Insulating dielectric; 6. Gate metal; 7. Source metal; 8. n-type region; 9. n+ source region; 10. p-type well region; 11. Schottky metal; 12. p-type shielding layer; 13. p-type region. Detailed Implementation

[0018] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0019] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0020] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it constitute a separate or selective embodiment that is mutually exclusive with other embodiments. Example 1:

[0021] Reference Figure 1This is the first embodiment of the present invention. This embodiment provides a 4kV low-resistivity superjunction planar gate SiCVDMOS device structure, including a drain metal 1 located at the bottom of the device. An n+SiC substrate 2 and an n-type drift layer 3 are disposed above the drain metal 1. An n-type region 8 is disposed in the middle of the n-type drift layer 3. A p-type shielding layer 12 is disposed below the n-type region 8. P-type regions 13 are disposed on both sides of the n-type drift layer 3. A p-type well region 10 is disposed above the p-type regions 13.

[0022] The p-type well region 10 is provided with a strip of Schottky metal 11 and a strip of polysilicon 4. An n+ source region 9 is provided above the p-type well region 10. A source metal 7 is provided above the n+ source region 9. An insulating medium 5 is provided above the source metal 7. A gate metal 6 is provided above the insulating medium 5.

[0023] The insulating medium 5 is silicon dioxide, and the gate metal 6 is one of aluminum, nickel, and copper, or an alloy of the above metals.

[0024] The doping concentration of the n+SiC substrate 2 is 2×10⁻⁶. 17 Up to 8×10 17 cm -3 In order to ensure a low-resistance ohmic contact with the drain metal 1 and reduce the overall on-resistance of the device.

[0025] The doping concentration of the n-type drift layer 3 is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type region 13 is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The setting of doping concentration is a trade-off between reverse breakdown voltage and on-resistance of the device. Its concentration relationship can ensure the lateral and longitudinal diffusion relationship of the space charge region of the pn junction of the device, realize the superjunction structure of the device (since the p-type region 13 in the device structure can realize the lateral expansion of the space charge region of the device, the doping concentration of the n-type drift layer 3 of the device can be increased, thereby reducing the on-resistance of the device), and ensure that the device has both breakdown voltage and low on-resistance.

[0026] The doping concentration of the p-type shielding layer 12 is 1×10⁻⁶. 17 Up to 5×10 17 cm -3The doping concentration represents a trade-off between the shielding effect of the gate-drain capacitance and the on-resistance of the device. Higher doping concentration results in higher on-resistance and better shielding, while lower doping concentration results in lower on-resistance and poorer shielding. The doping concentration setting represents a trade-off between the device's switching and conducting characteristics. Effective shielding of the gate-drain capacitance can reduce the device's Miller capacitance, gate charge, and switching speed.

[0027] The doping concentration of the p-type well region 10 is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 In order to ensure the withstand voltage and gate control characteristics of the device.

[0028] The doping concentration of the n-type region 8 is 6 × 10⁸. 17 Up to 10×10 17 cm -3 It represents a trade-off between the device's on-resistance and gate control capability.

[0029] The doping concentration of the n+ source region 9 is 2 × 10⁻⁶. 17 Up to 8×10 17 cm -3 In order to form a low-resistance ohmic contact with the source metal 7.

[0030] The thickness of the n-type drift layer 3 is 50 μm, which is a trade-off between the device and the doping concentration in terms of on-resistance and epitaxial thickness.

[0031] The p-type region 13 has a width of 1.2 μm and a thickness of 35 μm in order to form a superjunction structure of the device and ensure the 4kV withstand voltage characteristic of the device.

[0032] The p-type well region 10 has a width of 2.5 μm and a maximum thickness of 1 μm. In order to ensure the device's withstand voltage characteristics and short-time drain voltage surge capability, the p-type well region 10 located near the gate side of the n+ source region 9 has a width of 200 nm. This is a trade-off between the device's gate control capability and leakage current.

[0033] The insulating medium 5 has a width of 1.8 μm and a thickness of 50 nm. The width is designed to ensure that the insulating medium 5 fully covers the p-type well region 10 near the gate, and to avoid the gate control region not covering the p-type well region 10 to the right of the n+ source region 9 due to process errors, which would affect the gate control capability and on-resistance of the device.

[0034] The gate metal 6 has a width of 1.6 μm and a thickness of 300 nm. Its size not only forms a full coverage of the p-type well region 10 of the gate control region, but also partially covers the n+ source region 9 of the device, so as to avoid the influence of process errors on the device characteristics and ensure the gate control capability of the device.

[0035] The p-type shielding layer 12 has a width of 1 μm and a thickness of 200 nm. The distance between its top and the bottom of the insulating medium 5 is 2 μm, which is a trade-off between the device's on-resistance and switching characteristics.

[0036] The width of the polysilicon 4 is 200nm, the spacing between the strip-shaped polysilicon 4 is 200nm, the distance between the outermost polysilicon 4 and the edge of the device cell is 200nm, and the distance between the outermost polysilicon 4 and the Schottky metal 11 is 300nm.

[0037] The width of the device cell is 6 μm; the total width of the p-type well regions 10 located on the left and right sides of the device is 5 μm; the width of the n-type region 8 is 300 nm and the thickness is 1 μm, which is a trade-off between the device's on-resistance and gate control capability.

[0038] The n+ source region 9 has a width of 500nm and a thickness of 300nm. This is a trade-off between reducing the source ohmic contact resistance of the device and ensuring the high current density of the device cells.

[0039] The Schottky metal 11 has a width of 300 nm and a thickness of 1 μm. The Schottky metal 11 directly contacts the n-type drift layer 3 to form a Schottky diode. The direct contact between the Schottky metal 11 and the n+ source region 9 increases the effective contact area between the source metal 7 and the n+ source region 9, reducing ohmic contact resistance. This effectively reduces the parasitic body diode forward voltage drop. The strip-shaped polysilicon 4, while ensuring the withstand voltage of the p-type well region 10, reduces the thickness of the p-type well region 10 from the source to the n-type drift region, thereby reducing the voltage drop of the p-type well region 10 during body diode freewheeling and improving the diode's freewheeling capability.

[0040] The n-type drift layer 3, n-type region 8, p-type region 13, and p-type well region 10 are described. The p-type region 13 is connected to the p-type well region 10 of the device, forming a lateral breakdown voltage structure inside the n-type drift layer 3, thereby forming a superjunction structure of the device, improving the breakdown voltage and reducing the on-resistance of the device. The n-type region 8 is distributed between the left and right p-type well regions 10. It increases the doping concentration of the JFET region of the device without affecting the gate control capability of the p-type well region 10, reducing the JFET resistance of the device, and thus reducing the on-resistance of the device. Example 2:

[0041] This embodiment provides a method for fabricating a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure, based on the device described in Embodiment 1, and includes the following specific steps: S1, such as Figure 2 As shown, an n-type drift layer 3 is epitaxially grown on an n+SiC substrate 2.

[0042] S2, such as Figure 3As shown, a barrier layer is deposited above the n-type drift layer 3, a via is etched in the p-type region 13, and ion implantation is used to form the p-type region 13.

[0043] S3, such as Figure 4 The barrier layer formed in step S2 is removed, a new barrier layer is deposited on top of the n-type drift layer 3, the vias of the p-type shielding layer 12 are etched, and the p-type shielding layer 12 is formed by ion implantation.

[0044] S4, such as Figure 5 As shown, the barrier layer formed in step S3 is removed, a new barrier layer is deposited above the n-type drift layer 3, the via of the p-type well region 10 is etched, and the p-type well region 10 is formed by ion implantation.

[0045] S5, such as Figure 6-7 As shown, the barrier layer formed in step S4 is removed, a new barrier layer is deposited, the Schottky metal 11 via is etched, the Schottky metal 11 trench is formed by RIE reactive ion etching, and the Schottky metal 11 is deposited.

[0046] S6, such as Figure 8-9 As shown, the barrier layer formed in step S5 is removed, a new barrier layer is deposited, the polysilicon 4 via is etched, the polysilicon 4 trench is formed by RIE reactive ion etching, and the polysilicon 4 is deposited.

[0047] S7, such as Figure 10 As shown, the barrier layer formed in step S6 is removed, a new barrier layer is deposited, the via in the n+ source region 9 is etched, and the n+ source region 9 is formed by ion implantation.

[0048] S8, such as Figure 11 As shown, the barrier layer formed in step S7 is removed, a new barrier layer is deposited, the n-type region 8 via is etched, and the n-type region 8 is formed by ion implantation.

[0049] S9, such as Figure 12 As shown, the barrier layer formed in step S8 is removed, a new barrier layer is deposited, an insulating dielectric 5 through-hole is formed by etching, and an insulating dielectric 5 is formed by deposition.

[0050] S10, such as Figure 13 As shown, the barrier layer formed in step S9 is removed, a new barrier layer is deposited, the gate metal 6 via is etched, and the gate metal 6 is deposited through the via.

[0051] S11, such as Figure 14 As shown, the barrier layer formed in step S10 is removed, a new barrier layer is deposited, the source metal 7 via is etched, and the source metal 7 is deposited through the via.

[0052] S12, such as Figure 15As shown, the barrier layer formed in step S11 is removed, and a new barrier layer is deposited to form a protective layer on top of the device.

[0053] S13, such as Figure 16 As shown, the device is flipped over and the n+SiC substrate 2 of the device is polished.

[0054] S14, such as Figure 17 As shown, drain metal 1 is deposited on the n+SiC substrate 2 of the device to form a complete device structure.

[0055] In step S1, the initial thickness of the n+SiC substrate 2 is 1.5 μm. In step S13, the thickness of the n+SiC substrate 2 is reduced to 0.6 μm by grinding, which is used to reduce the on-resistance of the device and also to improve the support of the SiC VDMOS epitaxial fabrication process.

[0056] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A 4kV low-resistivity superjunction planar gate SiC VDMOS device structure, characterized in that, It includes a drain metal located at the bottom of the device. An n+SiC substrate and an n-type drift layer are disposed above the drain metal. An n-type region is disposed in the middle of the n-type drift layer. A p-type shielding layer is disposed below the n-type region. P-type regions are disposed on both sides of the n-type drift layer. A p-type well region is disposed above the p-type region. The p-type well region contains strips of Schottky metal and strips of polysilicon. An n+ source region is disposed above the p-type well region. A source metal is disposed above the n+ source region. An insulating dielectric is disposed above the source metal. A gate metal is disposed above the insulating dielectric.

2. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 1, characterized in that, The doping concentration of the n+SiC substrate is 2×10⁻⁶. 17 Up to 8×10 17 cm -3 The doping concentration of the n-type drift layer is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type region is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type shielding layer is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the p-type well region is 1×10⁻⁶. 17 Up to 5×10 17 cm -3 The doping concentration of the n-type region is 6 × 10⁻⁶. 17 Up to 10×10 17 cm -3 The doping concentration of the n+ source region is 2×10⁻⁶. 17 Up to 8×10 17 cm -3 .

3. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 1, characterized in that, The insulating medium is silicon dioxide, and the gate metal is one of aluminum, nickel, and copper, or an alloy of the above metals.

4. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 1, characterized in that, The n-type SiC substrate has a thickness of 0.6 μm; the n-type drift layer has a thickness of 50 μm; the p-type region has a width of 1.2 μm and a thickness of 35 μm; the p-type well region has a width of 2.5 μm and a maximum thickness of 1 μm, with the p-type well region located near the gate side of the n+ source region having a width of 200 nm; the insulating medium has a width of 1.8 μm and a thickness of 50 nm; the gate metal has a width of 1.6 μm and a thickness of 300 nm; the p-type shielding layer has a width of 1 μm and a thickness of 200 nm, with its top edge 2 μm from the bottom edge of the insulating medium; and the n+ source region has a width of 500 nm and a thickness of 300 nm.

5. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 1, characterized in that, The width of the polycrystalline silicon is 200nm, the spacing between the strips of polycrystalline silicon is 200nm, the distance between the outermost polycrystalline silicon and the edge of the device cell is 200nm, and the distance between the outermost polycrystalline silicon and the Schottky metal is 300nm.

6. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 5, characterized in that, The width of the device cell is 6 μm; the total width of the p-type well regions located on the left and right sides of the device is 5 μm; the width of the n-type region is 300 nm and the thickness is 1 μm.

7. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 1, characterized in that, The Schottky metal has a width of 300 nm and a thickness of 1 μm. The Schottky metal is in direct contact with the n-type drift layer to form a Schottky diode.

8. The 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 1, characterized in that, The n-type drift layer, n-type region, p-type region, and p-type well region form a transverse withstand voltage structure inside the n-type drift layer, thereby forming a superjunction structure of the device.

9. A method for fabricating a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure, fabricated based on the device according to any one of claims 1-8, characterized in that, The specific steps include the following: S1. Epitaxial growth of an n-type drift layer on an n+SiC substrate; S2. Deposit a barrier layer above the n-type drift layer, etch through-holes in the p-type region, and implant ions to form the p-type region; S3. Remove the barrier layer formed in step S2, deposit a new barrier layer above the n-type drift layer, etch the vias of the p-type shielding layer, and ion implant to form the p-type shielding layer. S4. Remove the barrier layer formed in step S3, deposit a new barrier layer above the n-type drift layer, etch the vias in the p-type well region, and implant ions to form the p-type well region. S5. Remove the barrier layer formed in step S4, deposit a new barrier layer, etch the Schottky metal via, use RIE (Reactive Ion Etching) to form Schottky metal trenches, and deposit Schottky metal. S6. Remove the barrier layer formed in step S5, deposit a new barrier layer, etch polysilicon vias, use RIE (Reactive Ion Etching) to form polysilicon trenches, and deposit polysilicon. S7. Remove the barrier layer formed in step S6, deposit a new barrier layer, etch the via in the n+ source region, and implant ions to form the n+ source region. S8. Remove the barrier layer formed in step S7, deposit a new barrier layer, etch the n-type region via, and implant ions to form the n-type region. S9. Remove the barrier layer formed in step S8, deposit a new barrier layer, etch to form an insulating dielectric via, and deposit to form an insulating dielectric. S10. Remove the barrier layer formed in step S9, deposit a new barrier layer, etch the gate metal via, and deposit the gate metal through the via. S11. Remove the barrier layer formed in step S10, deposit a new barrier layer, etch the source metal via, and deposit the source metal through the via. S12. Remove the barrier layer formed in step S11, deposit a new barrier layer, and form a protective layer on top of the device. S13. Flip the device over and grind the n+SiC substrate of the device; S14. Deposit drain metal on the n+SiC substrate of the device to form a complete device structure.

10. The method for fabricating a 4kV low-resistivity superjunction planar gate SiC VDMOS device structure according to claim 9, characterized in that, In step S1, the initial thickness of the n+SiC substrate is 1.5 μm, and in step S13, the thickness of the n+SiC substrate is reduced to 0.6 μm by grinding.

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