Semiconductor device, preparation method and chip

Abstract

The invention provides a semiconductor device, a preparation method and a chip, and relates to the technical field of semiconductors. Comprising a substrate; the first trench gate is arranged in the substrate; the first trench gate is arranged in the substrate, and the second trench gate and the first trench gate are arranged at intervals; and the first conductive type source region is arranged in the substrate and is arranged on at least one side of the first trench gate, so that when the semiconductor device is switched on, the concentration of carriers passing through at least one side of the second trench gate in the substrate is greater than that of carriers passing through at least one side of the first trench gate. When the semiconductor device is switched on, most of carriers flow through the vicinity of the second trench gate, and a small part of carriers flow through the vicinity of the first trench gate, so that a parasitic transistor close to the vicinity of the first trench gate cannot be switched on, and the problem that the semiconductor device is easy to latch under high current density is solved to a great extent; and the reliability of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and a chip. Background Art

[0002] The trench semiconductor structure has become the current mainstream trend because it does not have a JFET (Junction Field-Effect Transistor) region of a planar structure, but has higher current density and lower conduction loss.

[0003] In order to reduce gate capacitance, increase the switching rate of the trench semiconductor structure, and further reduce conduction loss, a second trench gate (Dummy Gate) structure is often designed in the trench semiconductor structure. When the current density is too large, the trench semiconductor structure is prone to latch-up due to the presence of parasitic transistors. Due to the presence of the second trench gate structure, it is easier to turn on the parasitic transistors in the trench semiconductor structure, causing the gate to lose control, thereby increasing the probability of latch-up. Summary of the invention

[0004] The present application provides a semiconductor device, a preparation method and a chip, which are used to provide a technical solution that can effectively improve the latch-up effect of a semiconductor device and enhance the reliability of the device while ensuring that other parameters of the semiconductor device remain unchanged.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] substrate;

[0007] A first trench gate, the first trench gate is arranged in the substrate;

[0008] A second trench gate is disposed in the substrate and spaced apart from the first trench gate;

[0009] A first conductive type source region is arranged in the substrate and connected to a portion of the side wall of at least one side of the first trench gate, so that when the semiconductor device is turned on, the concentration of carriers passing through at least one side of the second trench gate in the substrate is greater than the concentration of carriers passing through at least one side of the first trench gate.

[0010] In an optional implementation, the semiconductor device further includes: a second conductivity type doping region;

[0011] Along a spacing direction between the first trench gate and the second trench gate, the second conductive type doping region is disposed between the first trench gate and the second trench gate.

[0012] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type doping region is connected to the first trench gate and the second trench gate.

[0013] In an optional implementation, along the thickness direction of the substrate, the second conductivity type doping region is connected to the first conductivity type source region.

[0014] In an optional implementation, the semiconductor device further includes a first electrode;

[0015] The first electrode is disposed on a first side of the substrate along a thickness direction of the substrate.

[0016] In an optional embodiment, the first electrode has an extension portion extending into the substrate;

[0017] Along a spacing direction between the first trench gate and the second trench gate, the extension portion is disposed between the first trench gate and the second trench gate.

[0018] In an optional embodiment, along the spacing direction between the first trench gate and the second trench gate, the extension portion is disposed on both sides of the first trench gate, and the first conductive type source region is connected to part of the side walls on both sides of the first trench gate.

[0019] In an optional embodiment, along the spacing direction between the first trench gate and the second trench gate, the extension portion is arranged on one side of the first trench gate, and the first conductive type source region is connected to a portion of the side wall of the first trench gate close to the side of the extension portion.

[0020] In an optional implementation, the first conductivity type source region is connected to at least a portion of the sidewall of the extension portion close to a side of the first trench gate.

[0021] In an optional implementation, the second conductive type doping region is connected to a side wall of the extension portion close to the second trench gate.

[0022] In an optional implementation, the second conductivity type doping region is connected to at least a portion of the bottom of the extension portion.

[0023] In an optional implementation, the first conductivity type source region is connected to a portion of the bottom of the extension portion;

[0024] The second conductive type doping region is connected to a portion of the bottom of the extension portion.

[0025] In an optional embodiment, the second conductive type doped region includes a second conductive type contact region;

[0026] Along the thickness direction of the substrate, the second conductive type contact region is connected to at least a portion of the bottom of the extension portion.

[0027] In an optional implementation, the second conductive type contact region is connected to the first conductive type source region.

[0028] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type contact region is connected to a portion of a side wall of the extension portion.

[0029] In an optional implementation, the second conductive type contact region is connected to the entire bottom of the extension portion.

[0030] In an optional implementation, the second conductive type contact region is adjacent to a portion of the sidewall of the extension portion on one side of the first trench gate.

[0031] In an optional implementation, the second conductive type contact region is connected to the entire sidewall of the extension portion close to a side of the second trench gate.

[0032] In an optional implementation, the second conductive type contact region is connected to a portion of the sidewall of the extension portion close to a side of the first trench gate.

[0033] In an optional implementation, the second conductive type contact region is connected to a portion of the sidewall of the extension portion close to one side of the second trench gate.

[0034] In an optional implementation, the second conductive type contact region is connected to a portion of the bottom of the extension portion close to one side of the first trench gate.

[0035] In an optional implementation, the second conductive type contact region is connected to a portion of the sidewall of the extension portion close to a side of the first trench gate.

[0036] In an optional embodiment, the second conductivity type doped region further includes a second conductivity type well region;

[0037] Along the spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to the first trench gate, the second trench gate and the second conductive type contact region.

[0038] In an optional implementation, along the thickness direction of the substrate, the second conductivity type well region is connected to both the second conductivity type contact region and the first conductivity type source region.

[0039] In an optional implementation, the second conductivity type well region is connected to the second conductivity type contact region on a side away from the first electrode.

[0040] In an optional implementation, along the thickness direction of the substrate, the second conductive type well region is connected to a bottom surface of the second conductive type contact region.

[0041] In an optional implementation, along the thickness direction of the substrate, the second conductivity type well region is connected to a bottom surface of the first conductivity type source region.

[0042] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to at least a portion of a side surface of the second conductive type contact region.

[0043] In a possible implementation manner, along a spacing direction between the first trench gate and the second trench gate, the second conductivity type well region is connected to a portion of a side wall of the first trench gate.

[0044] In a possible implementation manner, along a spacing direction between the first trench gate and the second trench gate, the second conductivity type well region is connected to a portion of a side wall of the second trench gate.

[0045] In an optional implementation, the second conductivity type well region is connected to a portion of a side surface of the second conductivity type contact region close to a side of the first trench gate.

[0046] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second trench gate is connected to one side of the extension portion.

[0047] In an optional implementation, along the thickness direction of the substrate, the second trench gate is connected to a portion of the bottom of the extension portion.

[0048] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to at least a portion of a side surface of the second conductive type contact region close to a side of the second trench gate.

[0049] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to a portion of a side surface of the second conductive type contact region close to one side of the first trench gate.

[0050] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to all side surfaces of the second conductive type contact region close to one side of the second trench gate.

[0051] In an optional embodiment, the second conductivity type doped region further includes a second conductivity type heavily doped region;

[0052] Along the spacing direction between the first trench gate and the second trench gate, the second conductive type heavily doped region is disposed between the extension portion and the second trench gate.

[0053] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type heavily doped region is connected to both the extension portion and the second trench gate.

[0054] In an optional implementation, along the thickness direction of the substrate, the second conductivity type heavily doped region is connected to both the second conductivity type well region and the second conductivity type contact region.

[0055] In an optional implementation, the second conductivity type heavily doped region is connected to a portion of the sidewall of the extension portion close to the second trench gate.

[0056] In an optional implementation, along the spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to a portion of a side surface of the second conductive type contact region close to one side of the first trench gate.

[0057] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to a portion of a side surface of the second conductive type contact region close to one side of the second trench gate.

[0058] In an optional implementation, the doping ion concentration of the second conductivity type heavily doped region is greater than the doping ion concentration of the first conductivity type source region.

[0059] In an optional embodiment, the doping ion concentration of the second conductive type heavily doped region is 10 18 ~10 21 cm -3 , and / or, the doping ion concentration of the first conductive type source region is 10 18 ~10 21 cm -3 .

[0060] In an optional implementation, the ion doping concentration of the second conductive type well region is less than the ion doping concentration of the second conductive type contact region.

[0061] In an optional embodiment, the ion doping concentration of the second conductive type well region is 10 16 ~10 18 cm -3 , and / or, the ion doping concentration of the second conductive type contact region is 10 18 ~10 21 cm -3 .

[0062] In an optional implementation, the semiconductor device further includes a first conductivity type drift region (103);

[0063] The first conductive type drift region is disposed in the substrate and on a side of the second conductive type well region away from the first electrode.

[0064] In an optional implementation, the first conductive type drift region covers the bottom and a portion of the sidewalls of the first trench gate and the second trench gate.

[0065] In an optional embodiment, the ion doping concentration of the first conductive type drift region is 10 13 ~10 15 cm -3 .

[0066] In an optional embodiment, the semiconductor device further includes a second electrode;

[0067] Along the thickness direction of the substrate, the second electrode is arranged on the second side of the substrate and is located on a side of the first conductive type drift region away from the second conductive type well region.

[0068] In an optional implementation, the semiconductor device further includes a first conductive type buffer region (104);

[0069] The first conductive type buffer region is disposed in the substrate and between the first conductive type drift region and the second electrode.

[0070] In an optional implementation, the semiconductor device further includes a second conductivity type collector region (105);

[0071] The second conductive type collector region is disposed between the first conductive type buffer region and the second electrode.

[0072] In an optional embodiment, the ion doping concentration of the second conductive type collector region is 10 18~10 21 cm -3 .

[0073] In an optional embodiment, the ion doping concentration of the first conductive type buffer region is 10 14 ~10 16 cm -3 .

[0074] In an optional embodiment, the semiconductor device further includes an isolation layer;

[0075] Along the thickness direction of the substrate, the isolation layer is disposed on the first side of the substrate and is at least disposed between the first trench gate, the second trench gate and the first electrode.

[0076] In an optional embodiment, the conductive ions in the first conductive type are N-type ions, and the conductive ions in the second conductive type are P-type ions;

[0077] Alternatively, the conductive ions in the first conductive type are P-type ions, and the conductive ions in the second conductive type are N-type ions.

[0078] In a second aspect, the present application also provides a method for preparing a semiconductor device, the method comprising: providing a substrate;

[0079] forming a first trench gate and a second trench gate; the first trench gate and the second trench gate are spaced apart and arranged in the substrate;

[0080] A first conductive type source region is formed; the first conductive type source region is arranged in the substrate and connected to a portion of the side wall of at least one side of the first trench gate, so that when the semiconductor device is turned on, the concentration of carriers passing through at least one side of the second trench gate in the substrate is greater than the concentration of carriers passing through at least one side of the first trench gate.

[0081] In an optional implementation, the forming of the first trench gate and the second trench gate includes:

[0082] etching the substrate at a first side of the substrate to form a trench structure in the substrate;

[0083] The first trench gate and the second trench gate are formed in the trench structure.

[0084] In an optional implementation, after forming the first trench gate and the second trench gate, the method further includes:

[0085] Ion implantation is performed at least twice on the substrate from the first side of the substrate to form a second conductive type doped region; along the spacing direction of the first trench gate and the second trench gate, the second conductive type doped region is arranged between the first trench gate and the second trench gate.

[0086] In an optional implementation, along a spacing direction between the first trench gate and the second trench gate, the second conductive type doping region is connected to both the first trench gate and the second trench gate.

[0087] In an optional implementation, along the thickness direction of the substrate, the second conductivity type doping region is connected to the first conductivity type source region.

[0088] In an optional embodiment, before forming the first conductive type source region, performing at least two ion implantations on the substrate from the first side of the substrate to form the second conductive type doping region comprises:

[0089] The substrate is first ion-implanted from the first side of the substrate to form a second conductive type well region. Along the spacing direction of the first trench gate and the second trench gate, the second conductive type well region is connected to the first trench gate, the second trench gate and the second conductive type contact region.

[0090] In an optional implementation, along the thickness direction of the substrate, the second conductivity type well region is connected to both the second conductivity type contact region and the first conductivity type source region.

[0091] In an optional implementation, forming a first conductivity type source region includes:

[0092] A second ion implantation is performed on the substrate from a first designated area on a first side of the substrate to form a source region of the first conductivity type.

[0093] In an optional implementation, after forming the first conductivity type source region, the method further includes:

[0094] forming a first electrode on a first side of the substrate along a thickness direction of the substrate;

[0095] The first electrode has an extension portion extending into the substrate; along a spacing direction between the first trench gate and the second trench gate, the extension portion is located between the first trench gate and the second trench gate.

[0096] In an optional embodiment, forming a first electrode on the first side of the substrate includes:

[0097] forming an isolation layer on a first side of the substrate;

[0098] forming a contact hole at least in the isolation layer and the substrate;

[0099] The first electrode is formed on the isolation layer and in the contact hole.

[0100] In an optional embodiment, after forming the contact hole in the isolation layer and the substrate and before forming the first electrode on the isolation layer and in the contact hole, the step of performing at least two ion implantations on the substrate from the first side of the substrate to form the second conductive type doped region further comprises:

[0101] Performing a third ion implantation on the substrate from the first side of the substrate along the thickness direction of the substrate to form a second conductive type contact region;

[0102] Along the thickness direction of the substrate, the second conductive type contact region is connected to at least a portion of the bottom of the extension portion and the first conductive type source region.

[0103] In an optional embodiment, after performing a third ion implantation on the substrate from the first side of the substrate to form a second conductive type contact region, performing at least two ion implantations on the substrate from the first side of the substrate to form a second conductive type doped region further comprises:

[0104] Performing a fourth ion implantation on the substrate from a second designated area on the first side of the substrate along the thickness direction of the substrate to form a heavily doped region of the second conductivity type;

[0105] Along a spacing direction between the first trench gate and the second trench gate, the second conductive type heavily doped region is connected to the extension portion and the second trench gate.

[0106] In an optional implementation, along the thickness direction of the substrate, the second conductivity type heavily doped region is connected to both the second conductivity type well region and the second conductivity type contact region.

[0107] In an optional embodiment, the method further includes:

[0108] A second electrode is formed on a second side of the substrate along a thickness direction of the substrate.

[0109] In an optional embodiment, before forming the second electrode on the second side of the substrate, the method further includes:

[0110] Performing a fifth ion implantation on the substrate from the second side of the substrate to form a first conductive type buffer zone;

[0111] The first conductive type buffer zone is located between the first conductive type drift region and the second electrode.

[0112] In an optional embodiment, after the fifth ion implantation is sequentially performed on the substrate from the second side of the substrate and before the second electrode is formed on the second side of the substrate, the method further comprises:

[0113] Performing a sixth ion implantation on the substrate from the second side of the substrate to form a collector region of a second conductivity type;

[0114] The second conductive type collector region is located between the second conductive type buffer region.

[0115] In a third aspect, an embodiment of the present application further provides a chip, comprising the semiconductor device described in any one of the first aspects.

[0116] In the technical solution provided by the present application, a first conductive type source region is only provided on at least one side of the first trench gate, so the semiconductor device in the present application will not form a parasitic transistor near the second trench gate, and due to the effect of the electric field generated by the first conductive type source region, when the semiconductor device is turned on, most of the carriers flow through the vicinity of the second trench gate, and a small part of the carriers flow through the vicinity of the first trench gate. At this time, the parasitic transistor near the first trench gate will not be turned on, which largely solves the problem of latch-up of semiconductor devices at high current density and improves the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0117] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0118] Figure 1 A structural diagram of a semiconductor device provided in an embodiment of the present application;

[0119] Figure 2 Another semiconductor device provided in an embodiment of the present application;

[0120] Figure 3 Another semiconductor device provided in an embodiment of the present application;

[0121] Figure 4 A schematic diagram of the structure of a substrate provided in an embodiment of the present application;

[0122] Figure 5 A schematic diagram of a structure after a first trench gate and a second trench gate are formed in a substrate provided in an embodiment of the present application;

[0123] Figure 6A schematic diagram of a structure after a first trench gate, a second trench gate and a first conductive type source region are formed in a substrate provided in an embodiment of the present application;

[0124] Figure 7 A schematic diagram of a structure after forming a first electrode provided in an embodiment of the present application.

[0125] 100: substrate; 101: first conductivity type source region; 102: second conductivity type doped region; 1021: second conductivity type well region; 1022: second conductivity type contact region; 1023: second conductivity type heavily doped region; 103: first conductivity type drift region; 104: first conductivity type buffer region; 105: second conductivity type collector region;

[0126] 200: first trench gate; 201: first gate dielectric layer; 202: first gate;

[0127] 300: second trench gate; 301: second gate dielectric layer; 202, second gate;

[0128] 400: first electrode; 401: extension portion; 402: base portion; 410: isolation layer;

[0129] 500: second electrode.

[0130] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0131] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0132] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. It is understood that the terms "first", "second", etc. used in the present application can be used to describe various information or data in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first information from another information. For example, without departing from the scope of the present application, the first action information can be referred to as the second action information, and similarly, the second action information can be referred to as the first action information. Both the first action information and the second action information are action information, but they are not the same action information.

[0133] The trench semiconductor structure has become the current mainstream trend because it does not have a JFET (Junction Field-Effect Transistor) region of a planar structure, but has higher current density and lower conduction loss.

[0134] In order to reduce gate capacitance, increase the switching rate of the trench semiconductor structure, and further reduce conduction loss, a second trench gate (Dummy Gate) structure is often designed in the trench semiconductor structure. When the current density is too large, the trench semiconductor structure is prone to latch-up due to the presence of parasitic transistors. Due to the presence of the second trench gate structure, it is easier to turn on the parasitic transistors in the trench semiconductor structure, causing the gate to lose control, thereby increasing the probability of latch-up.

[0135] Based on this, the technical concept of the present application is: to eliminate the parasitic transistor near the second trench gate without completely eliminating the N+ source region, so that when the semiconductor device is turned on, most of the holes flow through the second trench gate, and a small part of the holes flow through the first trench gate. This will not cause the parasitic transistor near the first trench gate to be turned on, thereby solving the problem of latch-up in semiconductor devices under high current density.

[0136] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0137] In a first aspect, an embodiment of the present application provides a semiconductor device, which may be an IGBT (Insulated Gate Bipolar Transistor) or other semiconductor devices with a trench gate structure, and the embodiment of the present application does not make any specific limitation on this.

[0138] The semiconductor device can be applied to chips for new energy vehicles, smart home appliances, rail transit, aerospace, and can also be applied to chips in other fields. The embodiments of the present application do not impose any special limitations on this.

[0139] Please refer to Figure 1-Figure 3 , the semiconductor device may include:

[0140] Substrate 100: The substrate 100 can provide a stable support structure for the semiconductor device, which is used to carry subsequent process steps such as thin film deposition, photolithography, and etching, thereby ensuring the stability and integrity of the entire device. In some examples, the substrate 100 can be a doped semiconductor structure doped with ions. The ions doped with the substrate 100 can include one conductivity type or two conductivity types. It should be understood that when the doped ions are of two conductivity types, the two conductivity types of doped ions are partitioned and arranged in different areas of the substrate 100.

[0141] The material of the substrate may be silicon, but is not limited to silicon. It may also be any other material suitable for power devices, such as silicon carbide, gallium nitride, diamond, etc. The embodiment of the present application does not make any specific limitation on this.

[0142] The first trench gate 200 is formed in the substrate 100 and may include a first gate dielectric layer 201 and a first gate electrode 202. The specific formation process may include: forming a trench by etching the substrate, then depositing a gate dielectric layer in the trench, and forming a gate electrode on the gate dielectric layer, and the gate electrode may fill the entire trench. The gate electrode may be a polysilicon gate electrode.

[0143] The second trench gate 300 is formed in the substrate 100 and may include a second gate dielectric layer 301 and a second gate 302. The structure and preparation method of the second trench gate 300 may be the same as the first trench gate 200, so that the second trench gate 300 can be formed at the same stage, saving process steps and process time.

[0144] A first conductive type source region 101 is disposed in the substrate and connected to a portion of a sidewall of at least one side of the first trench gate.

[0145] The first conductive type source region 101 is spaced apart from the second trench gate. That is, the first conductive type source region 101 is not disposed on at least one side of the second trench gate. The first conductive type source region 101 may be a heavily doped region, and during the conduction process of the IGBT, carriers may be injected from the first conductive type source region into the channel to participate in conduction.

[0146] The first conductive type source region 101 may be an N+ source region or a P+ source region, depending on the design and conductive type of the semiconductor device.

[0147] In some examples, the first conductive type source region 101 may be an N+ source region, which is a heavily doped region doped with N-type ions and is used to provide electrons as carriers. During the conduction process of the IGBT, electrons are injected from the N+ source region into the channel to participate in conduction.

[0148] In other examples, the first conductive type source region 101 may be a P+ source region, which is a heavily doped region doped with P-type ions and used to provide holes as majority carriers. In an IGBT, the P+ source region may be used to inject holes to support bipolar conduction of current.

[0149] According to the above description, the first conductive type source region 101 is only arranged on at least one side of the first trench gate 200, and the first conductive type source region is not arranged on at least one side of the second trench gate 300. Therefore, the semiconductor device in the present application will not form a parasitic transistor near the second trench gate 300. When the semiconductor device is turned on, under the action of the electric field generated by the first conductive type source region, most of the carriers in the substrate 100 flow through the vicinity of the second trench gate, and a small part of the carriers flow through the vicinity of the first trench gate. At this time, since the current formed by a small part of the carriers is small, the parasitic transistor near the first trench gate will not be turned on, which largely solves the problem of latch-up of semiconductor devices under high current density and improves the reliability of the device.

[0150] Compared with the design structure of completely removing the first conductive type source region of the semiconductor device in the related art, the embodiment of the present application does not completely eliminate the first conductive type source region. Based on this, the present application has lower requirements on the precision of lithography, is easy to implement technically and can reduce manufacturing costs. Based on this, the emitter electrode (the first electrode described below) can form a good ohmic contact with the first conductive type source region, thereby reducing the contact resistance of the semiconductor device, and further reducing the conduction loss of the semiconductor device.

[0151] Optionally, the semiconductor device provided in the embodiment of the present application may further include a first electrode 400, which is disposed on a first side of the substrate 100 along the thickness direction of the substrate 100, and has an extension portion 401 extending into the substrate 100 and a base portion 402 located on the first side of the substrate 100. The extension portion 401 is located between the first trench gate 200 and the second trench gate 300.

[0152] As an example, along the spacing direction of the first trench gate 200 and the second trench gate 300 , the extension portion 401 is disposed on both sides of the first trench gate 200 , and the first conductive type source region 101 is connected to part of the sidewalls on both sides of the first trench gate 200 .

[0153] As another example, along the spacing direction of the first trench gate 200 and the second trench gate 300 , the extension portion 401 is disposed on one side of the first trench gate 200 , and the first conductive type source region 101 is connected to a portion of the side wall of the first trench gate 200 close to the extension portion 401 .

[0154] According to the above two examples, whether the first conductive type source region is connected to part of the sidewall on one side or the sidewalls on both sides of the first trench gate 200 depends on whether the first electrode is provided on one side or on both sides of the first trench gate 200.

[0155] When a first electrode is provided on one side of the first trench gate, when the device is turned on, carriers will flow through one side of the first trench gate. At this time, a first conductive type source region needs to be provided on one side of the first trench gate so that under the action of the electric field generated by the first conductive type source region, most of the carriers flow through the vicinity of the second trench gate, and a small part of the carriers flow through one side of the first trench gate, thereby avoiding the parasitic transistor from being turned on.

[0156] The principle of providing the first electrodes on both sides of the first trench gate is the same as the principle of providing the first electrode on one side of the first trench gate, which will not be repeated here.

[0157] Optionally, the first conductivity type source region 101 is connected to at least a portion of the sidewall of the extension portion on a side close to the first trench gate 200 .

[0158] The first electrode 400 may be an emitter electrode, and the first conductive type source region 101 is connected to at least a portion of the sidewall of the extension portion facing the first trench gate 200 to ensure the inflow or outflow of current. The connection may be an electrical connection to form a conductive path when the device is turned on. The first trench gate 200 controls the formation of a channel between the first conductive type source region 101 and the adjacent base region through a gate voltage to adjust the on and off of the device.

[0159] It should be understood that in order to achieve electrical isolation between the first electrode 400 and the first trench gate 200 and the second trench gate 300 and prevent current leakage, the semiconductor device provided in the embodiment of the present application may further include an isolation layer 410. The isolation layer 410 is disposed on the first side of the substrate along the thickness direction of the substrate 100, and is at least disposed between the first trench gate 200 and the second trench gate 300 and the first electrode 400. Moreover, based on this structure, different first trench gates and second trench gates can be isolated from the first electrode to reduce the influence of parasitic capacitance and parasitic current, thereby improving the switching speed and performance of the device.

[0160] Optionally, the material of the isolation layer may be materials such as USG, borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), and no specific limitation is made here.

[0161] The above part is mainly used to illustrate the positional relationship between the first conductive type source region 101 and the first electrode 400 and the first trench gate 200. Optionally, in order to achieve effective control of the semiconductor device, the semiconductor device provided in the embodiment of the present application may further include a second conductive type doping region 102.

[0162] Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type doping region 102 is disposed between the first trench gate 200 and the second trench gate 300 .

[0163] Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type doping region 102 is connected to the first trench gate 200 and the second trench gate 300 .

[0164] And along the thickness direction of the substrate, the second conductive type doping region 102 is connected to the first conductive type source region 101 .

[0165] It should be understood that the second conductivity type is opposite to the doping ions of the first conductivity type. For example, if the first conductivity type is N-type, then the second conductivity type is P-type, and vice versa. The second conductivity type doping region 102 is disposed in the substrate and connected to at least part of the sidewalls of the first trench gate 200 and the second trench gate 300. When the semiconductor device is turned on, the second conductivity type doping region 102 forms a conductive path with part of the sidewalls of the first trench gate 200 and part of the sidewalls of the second trench gate 300, which can be used to adjust the electric field distribution of the semiconductor device and the movement path of the carriers.

[0166] Optionally, the second conductive type doping region 102 is connected to a side wall of the extension portion 401 close to one side of the second trench gate 300 .

[0167] Optionally, the second conductivity type doping region 102 may also be connected to at least a portion of the bottom of the extension portion 401 .

[0168] Based on this, the effect of the electric field generated in the first conductive type source region can be ensured so that when the semiconductor device is turned on, most carriers flow through the vicinity of the second trench gate, and a small number of carriers flow through the vicinity of the first trench gate.

[0169] In some cases, the first conductive type source region 101 is connected to a portion of the bottom of the extension portion 401; in this case, the second conductive type doping region 102 is connected to a portion of the bottom of the extension portion 401. In other words, the first conductive type source region 101 and the second conductive type doping region 102 are connected to the bottom of the extension portion 401 together.

[0170] The above-mentioned second conductive type doped region 102 covers at least part of the bottom and part of the side wall of the extension portion 401 and is connected to the first conductive type source region 101, which can improve the electric field distribution in the substrate 100, reduce the electric field concentration effect, and improve the breakdown voltage and reliability of the device; the second conductive type doped region can also suppress the generation of parasitic transistors near the second trench gate, thereby suppressing the parasitic bipolar effect and improving the performance and stability of the device.

[0171] Optionally, the second conductive type doping region 102 may include a second conductive type contact region 1022 . Along the thickness direction of the substrate 100 , the second conductive type contact region 1022 is connected to at least a portion of the bottom of the extension portion 401 and the first conductive type source region 101 .

[0172] Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type contact region 1022 is connected to a portion of the sidewall of the extension portion 401 .

[0173] In one example, referring to Figure 1 and Figure 3 , the second conductive type contact area 1022 is connected to the entire bottom of the extension portion 401 .

[0174] Optional, see Figure 1 The second conductive type contact region 1022 is connected to a portion of the sidewall of the extension portion 401 close to the first trench gate 200 and the entire sidewall close to the second trench gate 300 .

[0175] Optional, see Figure 3 The second conductive type contact region 1022 is connected to a portion of the sidewall of the extension portion 401 close to the first trench gate 200 and a portion of the sidewall close to the second trench gate 300 .

[0176] In one example, referring to Figure 2 The second conductive type contact region 1022 is connected to a portion of the bottom of the extension portion 401 close to one side of the first trench gate 200 .

[0177] The second conductive type contact region 1022 is connected to a portion of the sidewall of the extension portion 401 close to a side of the first trench gate 200 .

[0178] The above examples are used to illustrate the connection between the second conductive type contact region 1022 and the extension portion 401 .

[0179] The second conductive type contact region is used to form an ohmic contact with the extension portion to reduce the contact resistance with the first electrode and improve the conductive performance of the device. The second conductive type contact region is connected to the bottom and at least part of the sidewall of the extension portion 401, which helps to form a low-resistance electrical contact and ensure good current conduction.

[0180] Reference Figure 1 , Figure 2 and Figure 3 The second conductive type doped region 102 further includes a second conductive type well region 1021 .

[0181] Along the spacing direction of the first trench gate 200 and the second trench gate 300, the second conductive type well region 1021 is connected to the first trench gate 200, the second trench gate 300 and the second conductive type contact region 1022. The connection here can be understood as an electrical connection to form a conductive path when the semiconductor device is turned on.

[0182] And / or, along the thickness direction of the substrate 100, the second conductivity type well region 1021 is connected to the second conductivity type contact region 1022 and the first conductivity type source region 101. Here, connection can be understood as electrical connection to form a conductive path when the semiconductor device is turned on.

[0183] Reference Figure 1 , Figure 2 and Figure 3 It can be seen that the second conductive type well region 1021 is connected to the second conductive type contact region 1022 on the side away from the first electrode 400 .

[0184] As an optional example, along the thickness direction of the substrate 100 , the second conductive type well region 1021 is connected to the bottom surface of the second conductive type contact region 1022 and the bottom surface of the first conductive type source region 101 .

[0185] Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type well region 1021 is connected to at least part of the side surface of the second conductive type contact region 1022 , part of the sidewall of the first trench gate 200 , and part of the sidewall of the second trench gate 300 .

[0186] Reference Figure 1 and Figure 3 Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type well region 1021 is connected to at least a portion of the side surface of the second conductive type contact region 1022 close to the second trench gate 300 .

[0187] Optional, see Figure 1 , along the spacing direction between the first trench gate 200 and the second trench gate 300, the second conductive type well region 1021 is connected to a portion of the side surface of the second conductive type contact region 1022 close to the first trench gate 200. Optionally, the second conductive type well region 1021 may also be connected to the entire side surface of the second conductive type contact region 1022 close to the second trench gate 300.

[0188] Optional, see Figure 3 The second conductive type doped region 102 further includes a second conductive type heavily doped region 1023. Along the spacing direction between the first trench gate 200 and the second trench gate 300, the second conductive type heavily doped region 1023 is disposed between the extension portion 401 and the second trench gate 300.

[0189] Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type heavily doped region 1023 is connected to both the extension portion 401 and the second trench gate 300 .

[0190] And / or, along the thickness direction of the substrate 100 , the second conductivity type heavily doped region 1023 is connected to both the second conductivity type well region 1021 and the second conductivity type contact region 1022 .

[0191] Reference Figure 3 The second conductive type heavily doped region 1023 is connected to a portion of the sidewall of the extension portion 401 close to one side of the second trench gate 300 .

[0192] Reference Figure 3 Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type well region 1021 is connected to a portion of the side surface of the second conductive type contact region 1022 close to the first trench gate 200 .

[0193] Reference Figure 3 Optionally, along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second conductive type well region 1021 is connected to a portion of the side surface of the second conductive type contact region 1022 close to one side of the second trench gate 300 .

[0194] Based on this, even if the first conductive type source region is formed near the second trench gate due to lithography bias or lateral diffusion of impurities when the first conductive type source region is injected, the second conductive type heavily doped region 1023 is formed by injecting P-type impurities again, the N-type impurities are inverted, and the first conductive type source region near the second trench gate is eliminated, thereby further improving the reliability of the device. Among them, the doping concentration of the second conductive type heavily doped region 1023 needs to be higher than the doping concentration of the first conductive type source region 101. Based on this, the first conductive type region near the second trench gate 300 can be completely inverted.

[0195] For example, the doping ion concentration of the second conductive type heavily doped region is 10 18 ~10 21 cm -3 , and / or, the doping ion concentration of the first conductive type source region is 10 18 ~10 21 cm -3 .

[0196] For example: the doping ion concentration of the second conductivity type heavily doped region is 10 19 cm -3 , and / or, the doping ion concentration of the first conductive type source region is 10 18 cm -3 .

[0197] For another example, the doping ion concentration of the second conductivity type heavily doped region is 10 20 cm -3 , and / or, the doping ion concentration of the first conductive type source region is 10 19 cm -3 .

[0198] For another example, the doping ion concentration of the second conductivity type heavily doped region is 10 21 cm -3 , and / or, the doping ion concentration of the first conductive type source region is 10 19 cm -3 .

[0199] Reference Figure 1-Figure 3Based on the above description, the second conductive type well region 1021 is disposed between the first trench gate 200 and the second trench gate 300, and is connected to the second conductive type contact region 1022, the first conductive type source region 101, the first trench gate 200, and the second trench gate 300. Based on this structure, there are regions with two conductive types near the first trench gate 200, and there is a region with one conductive type near the second trench gate 300, so that no parasitic transistor structure is formed near the second trench gate 300, thereby suppressing parasitic effects and improving the stability and performance of the device.

[0200] Based on the above description, it can be known that the embodiment of the present application divides the second conductivity type doped region 102 into a second conductivity type well region 1021 and a second conductivity type contact region 1022. The second conductivity type well region 1021 and the second conductivity type contact region 1022 may have different doping concentrations, so as to effectively control the distribution of the electric field, reduce the electric field concentration effect, and improve the withstand voltage capability of the device by precisely controlling the doping concentration of each region.

[0201] The optional ion doping concentration of the second conductive type well region 1021 is less than the ion doping concentration of the second conductive type contact region 1022 .

[0202] In this embodiment, the ion doping of the second conductive type well region 1021 can be set to be relatively low, on the one hand, to expand the electric field distribution, reduce the electric field concentration effect, thereby improving the breakdown voltage of the device, and on the other hand, to provide better channel control. The ion doping concentration of the second conductive type contact region 1022 is set to be relatively high, in order to form a low-resistance ohmic contact with the first electrode, reduce the contact resistance, improve the current conduction efficiency, and enhance the carrier injection efficiency, thereby improving the conduction performance of the device.

[0203] In some examples, the ion doping concentration of the second conductivity type well region is 10 16 ~10 18 cm -3 The ion doping concentration of the second conductive type contact region is 10 18 ~10 21 cm -3 It should be understood that the specific ion doping concentration of the second conductive type well region and the specific ion doping concentration of the second conductive type contact region can be set according to actual needs, and the embodiments of the present application do not specifically limit this. The actual needs may include the breakdown voltage of the device, the current conduction efficiency, etc.

[0204] For example: the ion doping concentration of the second conductivity type well region is 10 16 cm -3 , and / or, the ion doping concentration of the second conductive type contact region is 1018 cm -3 .

[0205] For another example, the ion doping concentration of the second conductivity type well region is 10 17 cm -3 , and / or, the ion doping concentration of the second conductive type contact region is 10 19 cm -3 .

[0206] In some possible examples, in order to reduce the accuracy requirements for lithography equipment, make the technology easier to implement and reduce manufacturing costs, it is prevented that the first click and the first trench gate are short-circuited due to the low accuracy of the lithography equipment, resulting in device failure. Figure 2 , the second trench gate 300 in the embodiment of the present application is connected to a portion of the sidewall and a portion of the bottom of the extension portion 401 .

[0207] Based on this structure, the second conductive type well region 1021 is connected to a portion of the side surface of the second conductive type contact region 1022 close to the first trench gate 200 .

[0208] Along the spacing direction between the first trench gate 200 and the second trench gate 300 , the second trench gate 300 is connected to one side of the extension portion 401 .

[0209] Along the thickness direction of the substrate 100 , the second trench gate 300 is connected to a portion of the bottom of the extension portion.

[0210] Based on this structure, the second conductive contact region is connected to the bottom and side portions of the extension portion 401 that are not covered by the second trench gate 300, so as to form an ohmic contact with the first electrode, thereby reducing the contact resistance with the first electrode. The second conductive type and the surrounding contact with the extension portion are helpful to form a low-resistance electrical contact and ensure good current conduction.

[0211] It should be understood that in the above structure, the contact hole of the first electrode can be designed to be larger to reduce the aspect ratio of the contact hole, which is more conducive to the filling of the first electrode metal. The spacing between the adjacent first trench gate and the second trench gate can also be further reduced, thereby reducing the chip cell size, increasing the current density, and achieving improved device performance and reduced costs.

[0212] In the embodiments of this application, refer to Figure 1-Figure 3 The semiconductor device may further include a first conductive type drift region 103, wherein the first conductive type drift region 103 is disposed in the substrate 100 and disposed on a side of the second conductive type well region 1021 away from the first electrode 400;

[0213] In some examples, the first conductive type drift region 103 is connected to the bottom of the first trench gate 200 and the second trench gate 300 .

[0214] In some other examples, the first conductive type drift region 103 is connected to a portion of the sidewalls of the first trench gate 200 and the second trench gate 300 .

[0215] Based on this, the bottom and part of the sidewalls of the first trench gate 200 and the second trench gate 300 are both arranged in the first conductivity type drift region, which can better control the channel formation and electric field distribution to optimize the switching speed and efficiency of the device.

[0216] It should be understood that the drift region can expand the electric field distribution when the device is turned off, increase the breakdown voltage, and thus enhance the withstand voltage. Through appropriate doping and structural design, the drift region can be kept stable under high voltage and the breakdown risk can be reduced. Generally, the resistance of the drift region affects the on-resistance of the device. In order to maintain a low on-resistance under high voltage, the drift region usually has a lower doping concentration.

[0217] Optionally, the ion doping concentration of the first conductive type drift region 103 is 10 13 cm -3 ~10 15 cm -3 At this ion doping concentration, the electronic performance of the first conductive type drift region can be guaranteed.

[0218] For example, the ion doping concentration of the first conductive type drift region 103 is 10 13 cm -3 .

[0219] For another example, the ion doping concentration of the first conductive type drift region 103 is 10 14 cm -3 .

[0220] For another example, the ion doping concentration of the first conductive type drift region 103 is 10 15 cm -3 .

[0221] In IGBT devices, the drift region is the key voltage-bearing area.

[0222] In an embodiment of the present application, the first conductive type drift region is used to limit the conductive type of the drift region. When the first type source region is an N-type source region, the first conductive type drift region is an N-type drift region to ensure that the device can effectively conduct current when in the on state. Such a setting helps to form a low-impedance path between the source region and the drift region, so that the current can flow smoothly from the source region to the drift region.

[0223] Continue to refer to Figure 1-Figure 3 The semiconductor device may further include a first conductive type buffer region 104, a second conductive type collector region 105, and a second electrode 500. The second electrode 500 is disposed on the second side of the substrate 100 and is located on the side of the first conductive type drift region 103 away from the second conductive type well region 102. The first conductive type buffer region 104 and the second conductive type collector region 105 are disposed in the substrate 100 and are sequentially disposed between the first conductive type drift region 103 and the second electrode 500.

[0224] The above-mentioned first conductive type buffer is arranged in the substrate and is located between the first conductive type drift region and the second conductive type collector region, and is used to smooth the electric field distribution and reduce the electric field concentration phenomenon, so as to improve the voltage resistance of the device and reduce the risk of breakdown. And due to the existence of the first conductive type buffer, the transition of the electric field between the drift region and the collector region can be better controlled. Furthermore, it should be understood that there will be a lattice mismatch problem between regions of different conductive types, which may cause defects and stress. The first conductive type buffer is used to reduce interface defects, thereby improving the manufacturing yield and long-term reliability of the device.

[0225] The second conductive type collector region is used to collect or distribute current, ensuring that the current is effectively transmitted from the first conductive type drift region to the second electrode.

[0226] The second conductive type collector region is different from the first conductive type drift region in conductivity type, and is used to form a PN junction between the drift region and the collector layer to provide a higher voltage blocking capability to improve the reliability of the device in high voltage applications. The presence of the pn junction can also effectively reduce the leakage current during reverse bias, thereby improving the efficiency and stability of the device.

[0227] The second electrode may be a collector electrode, which is a main current collection terminal. After electrons or holes pass through the base region, they are finally collected by the collector, thereby completing the flow path of the current.

[0228] Optionally, the ion doping concentration of the first conductive type buffer region is 10 14 ~10 16 cm -3 It should be understood that since the first conductive type buffer region is used to provide a transition between the first conductive type drift region and the second conductive type collector region, its doping concentration can be set to be higher than the first conductive type drift region but lower than the second conductive type collector region to help smooth the electric field distribution, reduce the electric field concentration phenomenon, and improve current flow. Such a setting helps to improve the voltage resistance and overall performance of the device.

[0229] For example, the ion doping concentration of the first conductive type buffer zone is 10 14cm -3 .

[0230] For another example, the ion doping concentration of the first conductive type buffer region is 10 15 cm -3 .

[0231] For another example, the ion doping concentration of the first conductive type buffer region is 10 16 cm -3 .

[0232] The ion doping concentration of the second conductive type collector region is 10 18 ~10 21 cm -3 The second conductivity type collector region is used to efficiently collect and transmit current. The high doping concentration ensures low resistance in this region, enabling efficient conduction and forming a good ohmic contact.

[0233] For example, the ion doping concentration of the second conductive type collector region is 10 18 cm -3 .

[0234] For another example, the ion doping concentration of the second conductive type collector region is 10 19 cm -3 .

[0235] For another example, the ion doping concentration of the second conductive type collector region is 10 21 cm -3 .

[0236] It is worth noting that the above-mentioned first conductivity type and second conductivity type are used to define different types of conductive ions in each region, while the conductive ion types in different regions of the same conductivity type are the same. However, it should be understood that the concentrations of conductive ions in different regions of the same conductivity type may be different or the same. No special limitation is made here, and the specific description above shall prevail.

[0237] In one example, the conductive ions in the first conductive type are N-type ions, and the conductive ions in the second conductive type are P-type ions.

[0238] In another example, the conductive ions in the first conductive type are P-type ions, and the conductive ions in the second conductive type are N-type ions.

[0239] The above content describes in detail the structure and function of each part of the structure of the semiconductor device provided in the embodiment of the present application. The following content describes the semiconductor device provided in the present application as a whole with several specific embodiments.

[0240] As a specific embodiment, refer to Figure 1 , showing a schematic structural diagram of an N-type IGBT device; from bottom to top: a second electrode 500 (collector), a second conductive type collector region 105 (P+ collector region) is provided on the upper surface of the collector, a first conductive type buffer region 104 (N+ buffer layer) is provided on the upper surface of the P+ collector region, the upper surface of the N+ buffer layer contacts the first conductive type drift region 103 (N-drift region), a true gate and a false gate trench are formed by etching the N-drift region, a gate dielectric layer (201 and 301) and a polysilicon gate electrode (202 and 302) are provided in the trenches, a second conductive type well region 1021 (P-type well region) is formed between the trenches by ion implantation, and the second conductive type contact region 1022 (P+ contact region) and the first conductive type source region 101 (N+ source region) are in contact with the upper surface of the P-type well region, respectively, and the polysilicon gate electrode is isolated from the first electrode 400 by an insulating dielectric isolation layer 410.

[0241] In the above structure, the first trench gate 200 is respectively on the left and right of the second trench gate 300, the N+ source region 101 is only arranged on both sides of the first trench gate, and the emitter metal contact hole is arranged in the middle position between the two true second trench gates. The size of the contact hole is designed differently according to the photolithography equipment and the emitter metal filling capacity, generally about 0.2-0.8um, and the distance from the trenches on both sides is greater than 0.2um, to ensure that the emitter and the gate are short-circuited due to the photolithography bias and cause the device to fail. In order to reduce the current gain of the NPN parasitic transistor near the first trench gate, P-type impurities are injected near the N+ source region to form a P+ contact region 1022, and the P+ contact region 1022 is injected using the emitter contact hole, which can save a layer of mask and reduce costs.

[0242] Compared with the existing traditional IGBT technology, in this embodiment, when the IGBT device is turned on, the P-type well region 1021 can form an N-type conductive channel along the first trench gate, and a large number of electrons are injected into the N-drift region 103 through the conductive channel to form an electron current. This current is equivalent to the base current of the PNP transistor, driving the PNP transistor to turn on. At this time, a large number of holes are injected from the back collector region through the N+ buffer layer into the N-drift region 103, flow through the P-type well region 1021 and finally flow into the emitter 400. Because the present invention does not inject N+ source regions on both sides of the second trench gate, an NPN transistor structure will not be formed near the second trench gate, and P-type impurities are injected through the emitter contact hole to form a P+ contact region. When the device is turned on, most of the holes flow through the vicinity of the second trench gate, and a small number of holes flow through the vicinity of the first trench gate. The hole current flows through the P-type well region, and the voltage drop generated is very small, which is less than the turn-on voltage of the P-type well region and the N-drift region to form a PN. This will not cause the NPN transistor near the first trench gate to be turned on, thereby avoiding the latch effect of the IGBT device and improving the reliability of the device.

[0243] Compared with the design structure of completely removing the N+ source region in the IGBT structure, this embodiment, on the one hand, has lower requirements on the precision of the lithography equipment, is easy to implement and can reduce manufacturing costs; if the N+ source region is completely removed, the precision of the lithography equipment will be extremely high and it will be difficult to achieve mass production, because if the emitter metal and the P-type well region are not completely in contact during lithography, then even if the applied gate voltage is greater than the device threshold voltage, the IGBT device will not turn on, resulting in device failure; on the other hand, because the emitter metal forms a good ohmic contact with the heavily doped N+ source region, the contact resistance is low, which can reduce the conduction loss of the IGBT device.

[0244] As another specific example, refer to Figure 2 , which is different from the previous specific embodiment, in this embodiment, the contact hole position of the emitter is designed to contact the second trench gate and the substrate at the same time. The size of the contact hole is designed differently according to the photolithography equipment and the emitter metal filling capacity, generally about 0.2-0.8um, and the distance from the first trench gate is greater than 0.2um. Based on this, the contact hole size can be designed to be larger in this embodiment, which can reduce the precision requirements for the photolithography equipment. The technology is easy to implement and can reduce the manufacturing cost, and prevent the short circuit between the emitter and the gate caused by the low precision of the photolithography equipment, which leads to device failure. The contact hole size is designed to be larger, which can reduce the depth-to-width ratio of the contact hole, which is more conducive to the filling of the emitter metal; it can also further reduce the distance between adjacent trenches, thereby reducing the chip cell size, increasing the current density, and achieving device performance improvement and cost reduction.

[0245] As another specific example, refer to Figure 3 The difference between this embodiment and the first specific embodiment is that after forming the P+ contact region, the second conductive type impurities are injected through a layer of mask to form the second conductive type heavily doped region 1023. Based on this, even if the first conductive type source region is formed near the second trench gate due to lithography bias or lateral diffusion of impurities during the injection of the first conductive type source region, the second conductive type heavily doped region 1023 is formed by injecting P-type impurities again, the N-type impurities are inverted, and the first conductive type source region near the second trench gate is eliminated, thereby further improving the reliability of the device. Among them, the doping concentration of the second conductive type heavily doped region 1023 needs to be higher than the doping concentration of the first conductive type source region 101.

[0246] In a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising:

[0247] Reference Figure 4 , step A1, providing a substrate 100; the substrate 100 can provide a stable supporting structure for the semiconductor device, used to carry out subsequent thin film deposition, photolithography, etching and other process steps, ensuring the stability and integrity of the entire device.

[0248] In some examples, the substrate 100 may be a doped semiconductor structure doped with ions. The ions doped with the substrate 100 may include one conductivity type or two conductivity types. It should be understood that when the doped ions are of two conductivity types, the doped ions of the two conductivity types are partitioned and arranged in different regions of the substrate 100.

[0249] The material of the substrate may be silicon, but is not limited to silicon. It may also be any other material suitable for power devices, such as silicon carbide, gallium nitride, diamond, etc. The embodiment of the present application does not make any specific limitation on this.

[0250] Reference Figure 5 , step A2, forming a first trench gate 200 and a second trench gate 300; the first trench gate and the second trench gate are arranged in the substrate at intervals; the specific formation process may include: forming a trench by etching the substrate, then depositing a gate dielectric layer in the trench, and forming a gate on the gate dielectric layer, and the gate may fill the entire trench. Wherein, the gate may be a polysilicon gate. The first trench gate 200 may include a first gate dielectric layer 201 and a first gate 202. The second trench gate 300 may include a second gate dielectric layer 301 and a second gate 302.

[0251] Reference Figure 6 , step A3, forming a first conductive type source region; the first conductive type source region is arranged in the substrate and connected to a portion of the sidewall of at least one side of the first trench gate, so that when the semiconductor device is turned on, the concentration of carriers passing through at least one side of the second trench gate in the substrate is greater than the concentration of carriers passing through at least one side of the first trench gate. That is to say, the first conductive type source region is not arranged on both sides of the second trench gate. The first conductive type source region can be a heavily doped region, and during the conduction process of the IGBT, carriers can be injected from the first conductive type source region into the channel to participate in conduction.

[0252] In some examples, the first conductive type source region may be an N+ source region, which is a heavily doped region doped with N-type ions and is used to provide electrons as carriers. During the conduction process of the IGBT, electrons are injected from the N+ source region into the channel to participate in conduction.

[0253] According to the above description, it can be seen that the first conductive type source region is only arranged on at least one side of the first trench gate, and the first conductive type source region is not arranged on both sides of the second trench gate. Therefore, the semiconductor device in the present application will not form a parasitic transistor near the second trench gate, so that when the semiconductor device is turned on, most of the carriers flow through the second trench gate, and a small part of the carriers flow through the first trench gate. At this time, the parasitic transistor near the first trench gate will not be turned on, which largely solves the problem of latch-up of semiconductor devices under high current density and improves the reliability of the device.

[0254] Moreover, compared with the design structure of completely removing the first conductive type source region of the semiconductor device in the related art, the embodiment of the present application does not completely eliminate the first conductive type source region. Based on this, the present application has lower requirements on the precision of lithography, is easy to implement technically and can reduce manufacturing costs. Based on this, the emitter metal can form a good ohmic contact with the first conductive type source region, thereby reducing the contact resistance of the semiconductor device, and further reducing the conduction loss of the semiconductor device.

[0255] Specifically, the above step A2 of forming the first trench gate and the second trench gate may include:

[0256] Step A21, etching the substrate at the first side of the substrate to form a trench structure in the substrate;

[0257] Step A22, forming a first trench gate and a second trench gate in the trench structure.

[0258] As a specific example, after forming the first trench gate and the second trench gate in step A22, the semiconductor manufacturing method provided in the embodiment of the present application may further include:

[0259] Reference Figure 6 , step A23, performing at least two ion implantations on the substrate from the first side of the substrate to form a second conductive type doping region 102. Along the spacing direction of the first trench gate and the second trench gate, the second conductive type doping region 102 is disposed between the first trench gate and the second trench gate.

[0260] Along the spacing direction between the first trench gate and the second trench gate, the second conductive type doping region is connected to both the first trench gate and the second trench gate;

[0261] And / or, along the thickness direction of the substrate, the second conductive type doped region is connected to the first conductive type source region.

[0262] It should be understood that the second conductivity type doping region 102 is a doping region opposite to the first conductivity type. For example, if the first conductivity type is N-type, then the second conductivity type is P-type, and vice versa. The second conductivity type doping region is disposed in the substrate and is located between the first trench gate and the second trench gate, and can be used to adjust the electric field distribution and carrier movement of the semiconductor device.

[0263] Furthermore, the second conductive type doped region 102 surrounds the bottom surface and at least part of the side surface of one end of the first electrode 400 and is connected to the first conductive type source region 101 , thereby improving the electric field uniformity and enhancing the device stability.

[0264] As a further explanation, the above-mentioned second conductive type doping region 102 improves the electric field distribution, reduces the electric field concentration effect, and improves the breakdown voltage and reliability of the device by connecting different regions; the second conductive type doping region can also suppress the generation of parasitic transistors near the second trench gate, thereby suppressing the parasitic bipolar effect and improving the performance and stability of the device.

[0265] Optionally, before forming the first conductive type source region, step A23 performs at least two ion implantations on the substrate from the first side of the substrate to form the second conductive type doped region, including:

[0266] Reference Figure 6 , step A231, performing a first ion implantation on the substrate from the first side of the substrate to form a second conductive type well region 1021. Along the spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to the first trench gate, the second trench gate and the second conductive type contact region;

[0267] And / or, along the thickness direction of the substrate, the second conductivity type well region is connected to both the second conductivity type contact region and the first conductivity type source region.

[0268] Afterwards, step A3 of forming a first conductivity type source region comprises:

[0269] Reference Figure 6 In step A31, a second ion implantation is performed on the substrate from a first designated area on a first side of the substrate to form a first conductive type source region 101; wherein the first designated area is located on at least one side of the first trench gate.

[0270] Optionally, after forming the first conductivity type source region in step A3, the method for preparing a semiconductor provided in an embodiment of the present application further includes:

[0271] Reference Figure 7, step A41, forming a first electrode 40 on a first side of a substrate; the first electrode has an extension portion extending into the substrate; along the spacing direction of the first trench gate and the second trench gate, the extension portion is located between the first trench gate and the second trench gate.

[0272] The first conductive type source region is arranged between the extension part and the first trench gate, and is connected to the extension part and the first trench gate; the second conductive type doped region is connected to the bottom surface and at least part of the side surface of the extension part, and is also connected to the first conductive type source region.

[0273] The first conductive type source region is located between one end of the first electrode and the first trench gate, and is connected to one end of the first electrode and the first trench gate.

[0274] The first electrode may be an emitter electrode connected to the first conductive type source region to ensure current inflow or outflow. The first trench gate controls the channel formation between the first conductive type source region and the adjacent base region through a gate voltage to adjust the on and off of the device.

[0275] Specifically, step A41 of forming a first electrode on the first side of the substrate may include:

[0276] Step A411, forming an isolation layer on the first side of the substrate.

[0277] The isolation layer is used to achieve electrical isolation between the first electrode and the first trench gate and the second trench gate to prevent current leakage.

[0278] Step A412, forming a contact hole at least in the isolation layer and the substrate; the bottom of the contact hole is disposed between the first trench gate and the second trench gate, the first conductive type source region is disposed between the contact hole and the first trench gate, and is connected to the contact hole and the first trench gate; the second conductive type doped region surrounds the bottom and at least part of the side of the contact hole, and is connected to the first conductive type source region;

[0279] Step A413, forming a first electrode 40 on the isolation layer and in the contact hole.

[0280] Optionally, after forming a contact hole in the isolation layer 410 and the substrate 10 in step A412 and before forming a first electrode on the isolation layer 410 and in the contact hole in step A413, step A23 performs at least two ion implantations on the substrate from the first side of the substrate to form the second conductive type doping region further includes:

[0281] Reference Figure 7, step A232, performing a third ion implantation on the substrate from the first side of the substrate along the thickness direction of the substrate to form a second conductive type contact region 1022; along the thickness direction of the substrate, the second conductive type contact region is connected to at least part of the bottom of the extension portion and the first conductive type source region.

[0282] The second conductive type contact area 1022 is used to form an ohmic contact with the first electrode to reduce the contact resistance with the first electrode and improve the conductive performance of the device. The connection between the second conductive type contact area and the extension portion helps to form a low-resistance electrical contact and ensure good current conduction.

[0283] The second conductive type well region 1021 obtained in the above steps is connected to the bottom surface and part of the bottom surface of the second conductive type contact region 1022 , and is connected to the first conductive type source region, the first trench gate, and the second trench gate.

[0284] The second conductive type well region is arranged between the first trench gate and the second trench gate, and is connected to the second conductive type contact region, the first conductive type source region, the first trench gate and the second trench gate. Based on this structure, there are regions with two conductive types near the first trench gate, and there is a region with one conductive type near the second trench gate, so that no parasitic transistor structure is formed near the second trench gate, thereby suppressing parasitic effects and improving the stability and performance of the device.

[0285] Based on the above description, it can be known that the embodiment of the present application divides the above-mentioned second conductivity type doped region into a second conductivity type well region and a second conductivity type contact region. And the second conductivity type well region and the second conductivity type contact region can have different doping concentrations, so as to effectively control the distribution of the electric field by accurately controlling the doping concentration of each region, reduce the electric field concentration effect, and improve the withstand voltage capability of the device.

[0286] For example, the ion doping concentration of the second conductive type well region is lower than the ion doping concentration of the second conductive type contact region.

[0287] The ion doping concentration of the second conductive type well region is 10 16 ~10 18 cm -3 The ion doping concentration of the second conductive type contact region is 10 18 ~10 21 cm -3 .

[0288] Optionally, a bottom portion of the contact hole is disposed in the second trench gate.

[0289] The second conductive type contact region surrounds the bottom of the contact hole and is arranged on the bottom surface and at least a part of the side surface outside the second trench gate.

[0290] Based on the above description, the semiconductor manufacturing method provided in the embodiment of the present application can design the contact hole of the first electrode to be larger, reduce the aspect ratio of the contact hole, and be more conducive to the filling of the first electrode metal. It can also further reduce the spacing between the adjacent first trench gate and the second trench gate, thereby reducing the chip cell size, increasing the current density, and achieving device performance improvement and cost reduction.

[0291] After the above step A232, step A23 may further include: performing a fourth ion implantation on the substrate from a second designated area on the first side of the substrate along the thickness direction of the substrate to form a second conductive type heavily doped region; along the spacing direction of the first trench gate and the second trench gate, the second conductive type heavily doped region is connected to the extension portion and the second trench gate. The second designated area is the area between the contact hole and the second trench gate; and the doping ion concentration of the second conductive type heavily doped region is greater than the doping ion concentration of the first conductive type source region.

[0292] Based on this, it is possible to avoid the formation of a first conductive type source region near the second trench gate due to lithography bias or lateral diffusion of impurities when forming a first conductive type source region. The embodiment of the present application forms a second conductive type heavily doped region between the second trench gate and the first electrode to invert the first conductive type ions and eliminate the existing first conductive type region near the second trench gate, thereby further improving the reliability of the device.

[0293] The doping ion concentration of the second conductive type heavily doped region is 10 18 ~10 21 cm -3 The doping ion concentration of the first conductive type source region is 10 18 ~10 21 cm -3 .

[0294] In some examples, reference Figure 1 , Figure 2 or Figure 3 , the semiconductor preparation method may further include:

[0295] Step A6: forming a second electrode 500 on the second side of the substrate along the thickness direction of the substrate.

[0296] Before step A6, the semiconductor manufacturing method may further include:

[0297] Step A5, along the thickness direction of the substrate, from the second side of the substrate, the substrate is sequentially subjected to the fifth and sixth ion implantations to form a first conductive type buffer region 104 and a second conductive type collector region 105 ; the second conductive type collector region 105 is located between the second electrode and the first conductive type buffer region 104 .

[0298] The above-mentioned first conductive type buffer is arranged in the substrate and is located between the first conductive type drift region and the second conductive type collector region, and is used to smooth the electric field distribution and reduce the electric field concentration phenomenon, so as to improve the voltage resistance of the device and reduce the risk of breakdown. And due to the existence of the first conductive type buffer, the transition of the electric field between the drift region and the collector region can be better controlled. Furthermore, it should be understood that there will be a lattice mismatch problem between regions of different conductive types, which may cause defects and stress. The first conductive type buffer is used to reduce interface defects, thereby improving the manufacturing yield and long-term reliability of the device.

[0299] The second conductive type collector region is used to collect or distribute current, ensuring that the current is effectively transmitted from the first conductive type drift region to the second electrode.

[0300] The second conductive type collector region is different from the first conductive type drift region in conductivity type, and is used to form a PN junction between the drift region and the collector layer to provide a higher voltage blocking capability to improve the reliability of the device in high voltage applications. The presence of the pn junction can also effectively reduce the leakage current during reverse bias, thereby improving the efficiency and stability of the device.

[0301] The second electrode may be a collector electrode, which is a main current collection terminal. After electrons or holes pass through the base region, they are finally collected by the collector, thereby completing the flow path of the current.

[0302] The ion doping concentration of the first conductive type buffer is 10 14 ~10 16 cm -3 ;

[0303] And / or, the ion doping concentration of the second conductive type collector region is 10 18 ~10 21 cm -3 .

[0304] It is worth noting that the above-mentioned first conductivity type and second conductivity type are used to define different types of conductive ions in each region, while the conductive ion types in different regions of the same conductivity type are the same. However, it should be understood that the concentrations of conductive ions in different regions of the same conductivity type may be different or the same. No special limitation is made here, and the specific description above shall prevail.

[0305] In one example, the conductive ions in the first conductive type are N-type ions, and the conductive ions in the second conductive type are P-type ions.

[0306] In another example, the conductive ions in the first conductive type are P-type ions, and the conductive ions in the second conductive type are N-type ions.

[0307] In a third aspect, an embodiment of the present application further provides a chip, which includes the semiconductor device described in any one of the first aspects.

[0308] In actual applications, the chip is used in new energy vehicles, smart home appliances, rail transportation, and aerospace.

[0309] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: Base (100); A first trench gate (200), wherein the first trench gate (200) is disposed in the substrate (100); A second trench gate (300), the second trench gate (300) being arranged in the substrate (100) and spaced apart from the first trench gate (200); A first conductive type source region (101) is arranged in the substrate (100) and connected to a portion of the side wall of at least one side of the first trench gate (200), so that when the semiconductor device is turned on, the concentration of carriers passing through at least one side of the second trench gate (300) in the substrate (100) is greater than the concentration of carriers passing through at least one side of the first trench gate (200).

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a second conductive type doping region (102) disposed in the substrate (100); Along the spacing direction of the first trench gate (200) and the second trench gate (300), the second conductive type doping region (102) is arranged between the first trench gate (200) and the second trench gate (300).

3. The semiconductor device according to claim 2, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type doping region (102) is connected to both the first trench gate (200) and the second trench gate (300).

4. The semiconductor device according to claim 3, wherein: Along the thickness direction of the substrate, the second conductive type doping region (102) is connected to the first conductive type source region (101).

5. The semiconductor device according to claim 4, characterized in that The semiconductor device further comprises a first electrode (400); Along the thickness direction of the substrate (100), the first electrode (400) is arranged on a first side of the substrate (100).

6. The semiconductor device according to claim 5, characterized in that The first electrode (400) has an extension portion (401) extending into the substrate (100); Along the spacing direction of the first trench gate (200) and the second trench gate (300), the extension portion (401) is arranged between the first trench gate (200) and the second trench gate (300).

7. The semiconductor device according to claim 6, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the extension portion (401) is arranged on both sides of the first trench gate (200), and the first conductive type source region (101) is connected to part of the side walls on both sides of the first trench gate (200).

8. The semiconductor device according to claim 6, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the extension portion (401) is arranged on one side of the first trench gate (200), and the first conductive type source region (101) is connected to a portion of the side wall of the first trench gate (200) close to the side of the extension portion (401).

9. The semiconductor device according to claim 6, characterized in that The first conductive type source region (101) is connected to at least a portion of the side wall of the extension portion (401) close to a side of the first trench gate (200).

10. The semiconductor device according to claim 6, wherein: The second conductive type doping region (102) is connected to a side wall of the extension portion (401) close to a side of the second trench gate (300).

11. The semiconductor device according to claim 6, characterized in that The second conductive type doping region (102) is connected to at least a portion of the bottom of the extension portion (401).

12. The semiconductor device according to claim 11, characterized in that The first conductive type source region (101) is connected to a portion of the bottom of the extension portion (401); The second conductive type doping region (102) is connected to a portion of the bottom of the extension portion (401).

13. The semiconductor device according to claim 6, characterized in that The second conductive type doping region (102) includes a second conductive type contact region (1022); Along the thickness direction of the substrate (100), the second conductive type contact area (1022) is connected to at least a portion of the bottom of the extension portion (401).

14. The semiconductor device according to claim 13, characterized in that Along the thickness direction of the substrate (100), the second conductive type contact region (1022) is connected to the first conductive type source region (101).

15. The semiconductor device according to claim 13, wherein: Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type contact region (1022) is connected to a portion of the side wall of the extension portion (401).

16. The semiconductor device according to claim 15, characterized in that The second conductive type contact region (1022) is connected to the entire bottom of the extension portion (401).

17. The semiconductor device according to claim 16, characterized in that The second conductive type contact region (1022) is connected to a portion of the side wall of the extension portion (401) close to one side of the first trench gate (200).

18. The semiconductor device according to claim 17, wherein: The second conductive type contact region (1022) is connected to the entire sidewall of the extension portion (401) close to a side of the second trench gate (300).

19. The semiconductor device according to claim 16, wherein: The second conductive type contact region (1022) is connected to a portion of the side wall of the extension portion (401) close to one side of the first trench gate (200).

20. The semiconductor device according to claim 19, characterized in that The second conductive type contact region (1022) is connected to a portion of the side wall of the extension portion (401) close to one side of the second trench gate (300).

21. The semiconductor device according to claim 15, characterized in that The second conductive type contact region (1022) is connected to a portion of the bottom of the extension portion (401) close to one side of the first trench gate (200).

22. The semiconductor device according to claim 21, characterized in that The second conductive type contact region (1022) is connected to a portion of the side wall of the extension portion (401) close to one side of the first trench gate (200).

23. The semiconductor device according to claim 12, wherein: The second conductive type doped region (102) further includes a second conductive type well region (1021); Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to the first trench gate (200), the second trench gate (300) and the second conductive type contact region (1022).

24. The semiconductor device according to claim 23, characterized in that Along the thickness direction of the substrate (100), the second conductive type well region (1021) is connected to both the second conductive type contact region (1022) and the first conductive type source region (101).

25. The semiconductor device according to claim 23, characterized in that The second conductive type well region (1021) is connected to the second conductive type contact region (1022) on a side away from the first electrode (400).

26. The semiconductor device according to claim 23, characterized in that Along the thickness direction of the substrate (100), the second conductive type well region (1021) is connected to the bottom surface of the second conductive type contact region (1022).

27. The semiconductor device according to claim 26, characterized in that Along the thickness direction of the substrate (100), the second conductive type well region (1021) is connected to the bottom surface of the first conductive type source region (101).

28. The semiconductor device according to claim 26, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to at least part of the side surface of the second conductive type contact region (1022).

29. The semiconductor device according to claim 28, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to a portion of the side wall of the first trench gate (200).

30. The semiconductor device according to claim 28 or 29, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to a portion of the side wall of the second trench gate (300).

31. The semiconductor device according to claim 28, characterized in that The second conductive type well region (1021) is connected to a portion of the side surface of the second conductive type contact region (1022) close to one side of the first trench gate (200).

32. The semiconductor device according to claim 31, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second trench gate (300) is connected to one side of the extension portion (401).

33. The semiconductor device according to claim 32, characterized in that Along the thickness direction of the substrate (100), the second trench gate (300) is connected to a portion of the bottom of the extension portion.

34. The semiconductor device according to claim 28, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to at least part of the side surface of the second conductive type contact region (1022) close to one side of the second trench gate (300).

35. The semiconductor device according to claim 34, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to a portion of the side surface of the second conductive type contact region (1022) close to one side of the first trench gate (200).

36. The semiconductor device according to claim 35, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to all side surfaces of the second conductive type contact region (1022) close to one side of the second trench gate (300).

37. The semiconductor device according to claim 35, characterized in that The second conductive type doped region (102) further includes a second conductive type heavily doped region (1023); Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type heavily doped region (1023) is arranged between the extension portion (401) and the second trench gate (300).

38. The semiconductor device according to claim 37, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type heavily doped region (1023) is connected to both the extension portion (401) and the second trench gate (300).

39. The semiconductor device according to claim 37 or 38, characterized in that: Along the thickness direction of the substrate (100), the second conductive type heavily doped region (1023) is connected to both the second conductive type well region (1021) and the second conductive type contact region (1022).

40. The semiconductor device according to claim 37, characterized in that The second conductivity type heavily doped region (1023) is connected to a portion of the side wall of the extension portion (401) close to the second trench gate (300).

41. The semiconductor device according to claim 40, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to a portion of the side surface of the second conductive type contact region (1022) close to one side of the first trench gate (200).

42. The semiconductor device according to claim 41, characterized in that Along the spacing direction between the first trench gate (200) and the second trench gate (300), the second conductive type well region (1021) is connected to a portion of the side surface of the second conductive type contact region (1022) close to one side of the second trench gate (300).

43. The semiconductor device according to claim 37, characterized in that The doping ion concentration of the second conductive type heavily doped region (1023) is greater than the doping ion concentration of the first conductive type source region (101).

44. The semiconductor device according to claim 43, characterized in that The doping ion concentration of the second conductive type heavily doped region (1023) is 10 18 ~10 21 cm -3 , and / or, the doping ion concentration of the first conductive type source region (101) is 10 18 ~10 21 cm -3 .

45. The semiconductor device according to claim 23, characterized in that The ion doping concentration of the second conductive type well region (1021) is lower than the ion doping concentration of the second conductive type contact region (1022).

46. ​​The semiconductor device according to claim 45, characterized in that The ion doping concentration of the second conductive type well region (1021) is 10 16 ~10 18 cm -3 , and / or, the ion doping concentration of the second conductive type contact region (1022) is 10 18 ~10 21 cm -3 .

47. The semiconductor device according to claim 23, wherein: The semiconductor device also includes a first conductivity type drift region (103); The first conductive type drift region (103) is arranged in the substrate (100), and is arranged on a side of the second conductive type well region (1021) away from the first electrode (400).

48. The semiconductor device according to claim 47, characterized in that The first conductive type drift region (103) is connected to the bottom of both the first trench gate (200) and the second trench gate (300).

49. The semiconductor device according to claim 48, characterized in that The first conductive type drift region (103) is connected to part of the side walls of both the first trench gate (200) and the second trench gate (300).

50. The semiconductor device according to claim 49, wherein: The ion doping concentration of the first conductive type drift region (103) is 10 13 ~10 15 cm -3 .

51. The semiconductor device according to claim 23, wherein: The semiconductor device further comprises a second electrode (500); Along the thickness direction of the substrate (100), the second electrode (500) is arranged on the second side of the substrate (100) and is located on a side of the first conductive type drift region (103) away from the second conductive type well region (1021).

52. The semiconductor device according to claim 51, characterized in that: The semiconductor device also includes a first conductive type buffer region (104); The first conductive type buffer region (104) is disposed in the substrate (100) and between the first conductive type drift region (103) and the second electrode (500).

53. The semiconductor device according to claim 52, characterized in that The semiconductor device further comprises a second conductivity type collector region (105); The second conductive type collector region (105) is arranged between the first conductive type buffer region (104) and the second electrode (500).

54. The semiconductor device according to claim 53, characterized in that: The ion doping concentration of the second conductive type collector region (105) is 10 18 ~10 21 cm -3 .

55. The semiconductor device according to claim 52, characterized in that The ion doping concentration of the first conductive type buffer zone (104) is 10 14 ~10 16 cm -3 .

56. The semiconductor device according to any one of claims 5 to 55, characterized in that: The semiconductor device further comprises an isolation layer (410); Along the thickness direction of the substrate (100), the isolation layer (410) is arranged on a first side of the substrate (100), and is at least arranged between the first trench gate (200), the second trench gate (300) and the first electrode (400).

57. The semiconductor device according to any one of claims 2 to 55, characterized in that: The conductive ions of the first conductive type are N-type ions, and the conductive ions of the second conductive type are P-type ions; Alternatively, the conductive ions in the first conductive type are P-type ions, and the conductive ions in the second conductive type are N-type ions.

58. A method for preparing a semiconductor device, characterized in that: The method comprises: providing a substrate; forming a first trench gate and a second trench gate; the first trench gate and the second trench gate are spaced apart and arranged in the substrate; A first conductive type source region is formed; the first conductive type source region is arranged in the substrate and connected to a portion of the side wall of at least one side of the first trench gate, so that when the semiconductor device is turned on, the concentration of carriers passing through at least one side of the second trench gate in the substrate is greater than the concentration of carriers passing through at least one side of the first trench gate.

59. The method according to claim 58, characterized in that The forming of the first trench gate and the second trench gate comprises: etching the substrate at a first side of the substrate to form a trench structure in the substrate; The first trench gate and the second trench gate are formed in the trench structure.

60. The method of claim 58, wherein: After forming the first trench gate and the second trench gate, the method further includes: Performing at least two ion implantations on the substrate from the first side of the substrate to form a second conductive type doping region; Along a spacing direction between the first trench gate and the second trench gate, the second conductive type doping region is disposed between the first trench gate and the second trench gate.

61. The method according to claim 60, characterized in that: Along a spacing direction between the first trench gate and the second trench gate, the second conductive type doping region is connected to both the first trench gate and the second trench gate.

62. The method according to claim 61, characterized in that Along the thickness direction of the substrate, the second conductive type doping region is connected to the first conductive type source region.

63. The method according to claim 60, characterized in that Before forming the first conductive type source region, performing at least two ion implantations on the substrate from the first side of the substrate to form the second conductive type doping region comprises: Performing a first ion implantation on the substrate from a first side of the substrate to form a well region of a second conductivity type; Along the spacing direction between the first trench gate and the second trench gate, the second conductive type well region is connected to the first trench gate, the second trench gate and the second conductive type contact region.

64. The method according to claim 63, characterized in that Along the thickness direction of the substrate, the second conductive type well region is connected to both the second conductive type contact region and the first conductive type source region.

65. The method according to claim 63, characterized in that The forming of the first conductivity type source region comprises: A second ion implantation is performed on the substrate from a first designated area on a first side of the substrate to form a source region of the first conductivity type.

66. The method according to claim 65, characterized in that After forming the first conductivity type source region, the method further comprises: forming a first electrode on a first side of the substrate along a thickness direction of the substrate; The first electrode has an extension portion extending into the substrate; along a spacing direction between the first trench gate and the second trench gate, the extension portion is located between the first trench gate and the second trench gate.

67. The method according to claim 66, characterized in that The forming of a first electrode on the first side of the substrate comprises: forming an isolation layer on a first side of the substrate; forming a contact hole at least in the isolation layer and the substrate; The first electrode is formed on the isolation layer and in the contact hole.

68. The method according to claim 67, characterized in that After forming a contact hole in the isolation layer and the substrate, and before forming the first electrode on the isolation layer and in the contact hole, the step of performing at least two ion implantations on the substrate from the first side of the substrate to form a second conductive type doped region further comprises: Performing a third ion implantation on the substrate from the first side of the substrate along the thickness direction of the substrate to form a second conductive type contact region; Along the thickness direction of the substrate, the second conductive type contact region is connected to at least a portion of the bottom of the extension portion and the first conductive type source region.

69. The method according to claim 68, characterized in that After performing a third ion implantation on the substrate from the first side of the substrate to form a second conductive type contact region, performing at least two ion implantations on the substrate from the first side of the substrate to form a second conductive type doped region further comprises: Performing a fourth ion implantation on the substrate from a second designated area on the first side of the substrate along the thickness direction of the substrate to form a heavily doped region of the second conductivity type; Along a spacing direction between the first trench gate and the second trench gate, the second conductive type heavily doped region is connected to both the extension portion and the second trench gate.

70. The method according to claim 69, characterized in that Along the thickness direction of the substrate, the second conductivity type heavily doped region is connected to both the second conductivity type well region and the second conductivity type contact region.

71. The method according to any one of claims 58 to 70, characterized in that The method further comprises: A second electrode is formed on a second side of the substrate along a thickness direction of the substrate.

72. The method according to claim 71, characterized in that Before forming the second electrode on the second side of the substrate, the method further includes: Performing a fifth ion implantation on the substrate from the second side of the substrate along the thickness direction of the substrate to form a first conductive type buffer zone; The first conductive type buffer zone is located between the first conductive type drift region and the second electrode.

73. The method according to claim 72, characterized in that After sequentially performing a fifth ion implantation on the substrate from the second side of the substrate and before forming a second electrode on the second side of the substrate, the method further includes: Performing a sixth ion implantation on the substrate from the second side of the substrate along the thickness direction of the substrate to form a second conductivity type collector region; The second conductive type collector region is located between the second conductive type buffer region.

74. A chip, characterized in that: A semiconductor device comprising any one of claims 1-57.

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