A packaging method for a third-generation semiconductor device packaging structure

Abstract

This invention discloses a packaging method for a third-generation semiconductor device packaging structure. The packaging structure includes a frame carrier, a silicon-based chip and one of its components, either a gallium nitride (GaN) chip or a silicon carbide (SiC) chip, as well as a ceramic substrate and / or a capacitor. This packaging method achieves high performance and high reliability after packaging, improving the stability and durability of the device and ensuring stable operation even under high-voltage environments. Gallium nitride (GaN) hybrid packaged devices consume less energy during use, thus reducing overall energy consumption. Simultaneously, the highly integrated circuit design reduces the number of components, making debugging faster and more convenient, significantly contributing to cost optimization. Silicon carbide (SiC) hybrid packaged devices, with their high-voltage and high-temperature resistance, enable stable operation in harsh environments, improving overall reliability and lifespan, and showing broad application prospects in various fields such as new energy vehicles and photovoltaic power generation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hybrid packaging of power device chips, in particular to the combination packaging of silicon-based chips, ceramic substrates and the like in third-generation semiconductor devices. BACKGROUND

[0002] As a core component in the electronic industry chain, the development of power devices is not only closely related to technological progress, but also inseparable from the continuous expansion of market demand. Third-generation semiconductor devices are chips manufactured based on third-generation semiconductor materials (also known as wide-bandgap semiconductor materials), which mainly include silicon carbide (SiC) and gallium nitride (GaN) and the like. The emergence of third-generation wide-bandgap semiconductor materials such as silicon carbide and gallium nitride provides power devices with higher voltage resistance and high-temperature resistance, as well as lower on-resistance and faster switching speed.

[0003] With the development of packaging technology, power devices have evolved towards low impedance, high power and high frequency characteristics, and traditional packaging technology has been difficult to meet the reliability requirements under fast switching characteristics and high temperature working conditions, which has prompted the innovation and development of packaging technology. At the same time, in order to improve the performance and reliability of power devices, the manufacturing process is also being optimized, such as using halogen-free and antimony oxide and other environmentally friendly materials, as well as using special materials and processes such as roughening or glue spraying. The driving force of market demand, the rise of new energy vehicles, and the significant increase in the demand for power semiconductors by new energy vehicles have promoted the development of power devices towards high efficiency and high stability.

[0004] With the continuous progress of power electronics technology, the performance requirements for power devices are becoming higher and higher. Traditional single-material packaging methods have been unable to meet the needs of modern power electronic systems. Therefore, a new type of hybrid packaging technology is needed to integrate the excellent properties of different materials and improve the overall performance of power devices. SUMMARY

[0005] In view of the above problems, the present application aims to provide a packaging method for third-generation semiconductor devices, which provides both side-by-side packaging and stacked packaging processes, and uses laser slotting technology and special glue spraying process materials to meet the packaging technology requirements of high performance and high reliability, improving the stability and durability of the device and ensuring stable operation in a high-voltage environment.

[0006] To achieve the above purpose, the technical solution adopted by the present application is as follows: a packaging structure for third-generation semiconductor devices, comprising a frame carrier, a silicon-based chip and one of a gallium nitride chip or a silicon carbide chip, and further comprising a ceramic substrate and / or a capacitor;

[0007] The silicon-based chip, one of the gallium nitride chip or the silicon carbide chip are arranged and bonded together on the frame carrier.

[0008] or a gallium nitride chip or a silicon carbide chip and a ceramic substrate are arranged and bonded on the frame carrier, and a silicon-based chip is bonded on the ceramic substrate;

[0009] or a gallium nitride chip or a silicon carbide chip and a ceramic substrate are arranged and bonded on the frame carrier, and a capacitor and a silicon-based chip are arranged and bonded on the ceramic substrate.

[0010] Preferably, the bonding material between the frame carrier and the silicon-based chip, the gallium nitride chip or the silicon carbide chip, the ceramic substrate, and the capacitor is one or more of soft solder, conductive glue, insulating glue, or nano-sintered silver.

[0011] Preferably, the bonding material between the silicon-based chip, the gallium nitride chip or the silicon carbide chip, the ceramic substrate, and the capacitor is one or more of aluminum wire, gold-copper wire, or gold-palladium-copper wire.

[0012] A packaging method of a third-generation semiconductor device packaging structure, the semiconductor device including a silicon-based chip, a gallium nitride chip or a silicon carbide chip, the semiconductor device further including a ceramic substrate and / or a capacitor, the packaging method mainly comprising the following steps:

[0013] S1, laser grooving: after thinning and back gold processing, grooving is performed by laser;

[0014] S2, dicing: the semiconductor wafer after laser grooving is diced into individual chips;

[0015] S3, chip mounting: the individual chips after dicing are arranged and bonded on the frame carrier;

[0016] S4, plasma cleaning: the chips after baking are subjected to plasma cleaning

[0017] S5, pressure welding: the semiconductor device after plasma cleaning is bonded using metal solder wire to form an electrical connection;

[0018] S6, plasma cleaning: the semiconductor device after pressure welding is subjected to plasma cleaning;

[0019] S7, glue spraying: the semiconductor device after plasma cleaning is subjected to glue spraying, so that a uniform thin film is formed on the frame carrier, the pins, and the chip surface.

[0020] Preferably, the silicon-based chip, the gallium nitride chip or the silicon carbide chip are arranged and bonded together on the frame carrier;

[0021] or a gallium nitride chip or a silicon carbide chip and a ceramic substrate are arranged and bonded on the frame carrier, and a silicon-based chip is bonded on the ceramic substrate;

[0022] Or its one gallium nitride chip or silicon carbide chip and ceramic substrate are arranged and bonded on the frame carrier, and the capacitor and silicon-based chip are arranged and bonded on the ceramic substrate.

[0023] Preferably, the bonding material between the frame carrier and the silicon-based chip, its one gallium nitride chip or silicon carbide chip, and the ceramic substrate adopts one or more of soft solder, conductive glue, insulating glue, or nano-sintered silver.

[0024] Preferably, the welding material between the silicon-based chip, its one gallium nitride chip or silicon carbide chip, the ceramic substrate, and the capacitor adopts one or more of aluminum wire, gold-copper wire, or gold-palladium-copper wire.

[0025] The beneficial effects of the present application are: according to the characteristics and application fields of the products, different performance bonding materials and metal wires are selected for electrical connection, laser slotting technology and special glue spraying materials and processes (such as AP8000 adhesion promoter glue spraying for gallium nitride (GaN) products, baking temperature 70℃, baking time 3min; GC-3688 adhesion promoter glue spraying for silicon carbide (SiC) products, without baking) are used to realize the packaging technology requirements of high performance and high reliability, improve the stability and durability of the device, and ensure stable operation in high pressure environment.

[0026] Gallium nitride (GaN) hybrid packaged devices can consume less energy during use (packaged devices can achieve higher energy conversion efficiency, reduce power loss, and have fast switching speed, thereby reducing switching loss and energy consumption), thereby reducing overall energy consumption, and highly integrated circuit design (by integrating multiple devices in one package, the number of peripheral devices is greatly reduced, and the circuit design is simplified), reducing the number of components, making the debugging process more rapid and convenient, and playing a significant role in cost optimization.

[0027] Silicon carbide (SiC) hybrid packaged devices have the characteristics of high pressure and high temperature resistance (such as the attached Figure 12 The reliability test results are shown in the figure, which can pass HTRB 1000 hours and HTGB 1000 hours, so that the device can work stably in harsh environment, improve the overall reliability and life, and show broad application prospects in new energy vehicles, photovoltaic power generation and other fields. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a side-by-side packaging structure diagram of the chip of the present application.

[0029] Figure 2 It is a chip stack packaging structure diagram of the present application.

[0030] Figure 3The side-by-side packaging plan view of the chip of the present application.

[0031] Figure 4 The stacked packaging plan view of the chip of the present application.

[0032] Figure 5 The process flow chart of the gallium nitride (GaN) hybrid packaging technology of the present application.

[0033] Figure 6 The process flow chart of the silicon carbide (SiC) hybrid packaging technology of the present application.

[0034] Figure 7 The key technical effect diagram of the gallium nitride (GaN) wafer laser grooving of the present application.

[0035] Figure 8 The process bonding schematic diagram of the BBOS and BSOB of the present application.

[0036] Figure 9 The diagram showing that the third generation chip is prone to breakage after being bonded.

[0037] Figure 10 The diagram showing that there is no delamination phenomenon between the third generation chip and the plastic sealing material, between the chip and the glue layer, and between the glue layer and the frame carrier after being packaged.

[0038] Figure 11 The laser grooving process diagram of the present application.

[0039] Figure 12 The reliability test results of the 1200V product of the present application.

[0040] In the figure: 1-wire; 2-lead frame pin; 3-frame carrier; 4-gallium nitride chip; 5-silicon-based chip; 6-ceramic substrate; 7-capacitor; 8-silicon carbide chip. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the technical solutions of the present application, the technical solutions of the present application will be further described below in combination with the drawings and examples.

[0042] Referring to the drawings Figures 1-8 The packaging structure of a third generation semiconductor device shown in the drawings includes a frame carrier 3, a silicon-based chip 5, a gallium nitride chip 4 or a silicon carbide chip 8 thereof, and a ceramic substrate 6 and / or a capacitor 7. The ceramic substrate 6 is mainly an aluminum oxide (Al2O3) ceramic substrate, and the main function of the ceramic substrate 6 is to connect the external element circuit. The capacitor increases the reliability of the product compared to the components. The packaging structure has two processes of side-by-side packaging and stacked packaging. The side-by-side packaging process structure Figure 1 、 3As shown in the figure, one of the chips is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5. On the surface of the lead frame, soft solder, conductive glue, insulating glue or nano-sintered silver die bonding material is used in sequence for die bonding. The die bonding sequence is: first, the chip using high-temperature material or the chip with a higher baking curve temperature is bonded, and then the chip using low-temperature material or the chip with a lower baking curve temperature is bonded.

[0043] Figure 1 As shown in the figure, after the chip bonding is completed, according to the characteristics and application fields of the product, a metal wire with excellent electrical performance such as an aluminum wire, a gold-copper wire or a gold-palladium-copper wire is selected to form precise electrical welding between the chip and the lead frame pin 2 and between the chips.

[0044] The stacked packaging process structure, one of the chips is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5, or an additional ceramic substrate 6 and a capacitor 7.

[0045] Figure 2 In a and Figure 4 As shown in the figure, in a product without using a ceramic substrate 6, the silicon carbide chip 8 and the silicon-based chip 5 can also be directly stacked, and the process structure is to bond the silicon carbide chip 8 first, and then bond the silicon-based chip 5.

[0046] Figure 2 In b and Figure 4 As shown in the figure, on the surface of the heat dissipation substrate, a soft solder or nano-sintered silver is used to fix the ceramic substrate 6 on the heat dissipation substrate, and then the gallium nitride chip 4 or the silicon carbide chip 8 is bonded on the other side of the ceramic substrate 6, and finally the silicon-based chip 5 stacked on the ceramic substrate 6 is bonded.

[0047] After the above three-chip or two-chip chip stacking and bonding is completed, a suitable metal wire (such as an aluminum wire, a gold-copper wire or a gold-palladium-copper wire) is selected to form precise electrical welding between the chip and the lead frame pin 2, between the chip and the lead frame carrier 3, and between the chip and the ceramic substrate 6. The advantages of gallium nitride chip 4 and power chip, silicon carbide chip 8 and silicon-based chip 5, and ceramic substrate 6 can be effectively combined, and precise electrical connection is achieved by using an aluminum wire, a gold-copper wire or a gold-palladium-copper wire, so as to realize efficient heat management and excellent electrical performance.

[0048] Based on the above packaging structure, the application also provides a packaging method of a third-generation semiconductor device packaging structure, comprising the following steps:

[0049] 1) Thinning process: Gallium nitride (GaN) wafers are relatively brittle, and the initial thickness of the wafer is generally 1000 um. Thinning process is needed to be done on the back of the wafer before packaging. The back of the wafer is thinned by In-Feed (feed) grinding method, and the gallium nitride (GaN) wafer is thinned to 250-300 um to improve the chip heat diffusion efficiency, electrical performance, mechanical performance, etc. Silicon carbide (SiC) wafers are relatively hard due to their inherent hardness, and the thickness of the wafer is generally between 150-250 um, and no thinning process is needed.

[0050] 2) Back gold process: According to the characteristics of the die bonding material, the gallium nitride (GaN) wafer using soft solder or nano-sintered silver die bonding has micro-damage on the back of the wafer after thinning. In order to eliminate the damage and further roughen, provide a good evaporation environment for the back metal, chemical etching is needed on the back of the wafer. After etching, the wafer is cleaned and the surface has residual water, which needs to be dehydrated with isopropyl alcohol and dried with nitrogen. Back gold uses electron beam to generate high temperature (up to 1000℃) to evaporate metal, so that metal atoms move straight in vacuum and deposit on the wafer to realize the metallization of the back of the wafer. The back gold material of gallium nitride (GaN) wafer is generally titanium (Ti) nickel (Ni) silver (Ag), and the evaporation sequence is titanium (Ti) -> nickel (Ni) -> silver (Ag).

[0051] 3) Laser grooving process: After the gallium nitride (GaN) wafer is thinned and gold plated, in order to reduce the cutting stress and reduce the risk of chip edge collapse, laser grooving process is used to groove through the gallium nitride (GaN) layer in the scribe lane, and then mechanical cutting is performed with a blade, Figure 11 As shown in the figure, this kind of distributed scribing technology greatly improves the yield of chip cutting.

[0052] 4) Scribing process: The gallium nitride (GaN) wafer after laser grooving has not been cut into single chips, and the conventional scribing knife is used to cut in the middle of the scribe groove after grooving. Since the GaN layer has been penetrated, the cutting stress is reduced during scribing, and the chip cutting yield is improved. Silicon carbide (SiC) wafers have high Mohs hardness, making the scribing process more difficult. Compared with traditional diamond mechanical scribing, ultrasonic scribing technology uses ultrasonic high-frequency oscillation to reduce the sawing force in the scribing process, thereby greatly reducing the back collapse of silicon carbide (SiC) wafers, and the UPH is increased by 10 times, as shown in the following table 1:

[0053]

[0054] 5) Chip mounting process: After scribing, the gallium nitride chip 4 and the silicon carbide chip 8 are bonded with nano-sintered silver, conductive adhesive or soft solder with high thermal conductivity during packaging to maintain good thermal contact. Figure 1 ,3 As shown in the side-by-side packaging structure, the gallium nitride chip 4 is parallelly bonded with the silicon-based chip 5, the gallium nitride chip 4 generally selects nano-sintered silver or conductive adhesive as the bonding material, and the silicon-based chip 5 generally selects insulating adhesive for bonding, which plays a role in controlling driving.

[0055] Figure 2 、 4 As shown in the stacked packaging structure, the gallium nitride chip 4 can be mixedly packaged with the ceramic substrate 6, the capacitor 7 and the silicon-based chip 5. The bonding mode is to first bond and fix the ceramic substrate 6 on the lead frame, then bond the gallium nitride chip 4 or the silicon carbide chip 8 on the other side of the substrate, and after bonding, stack the capacitor 7 or the silicon-based chip 5 on the ceramic substrate 6. The chips stacked on top need to strictly control the overflow amount of the bonding material, so nano-sintered silver is often selected as the bonding material of the silicon-based chip 5. After the chips using nano-sintered silver, conductive adhesive and insulating adhesive are bonded, an oven needs to be used for baking to fix the position of the chips. Different bonding materials have different baking curves, if different bonding materials are used for the same product, the chips need to be baked in sequence after bonding, and then the next chip can be bonded.

[0056] 6) Plasma cleaning process: the product after baking is subjected to plasma cleaning before pressure welding, which removes the organic solvent volatilized in the baking process of various bonding materials and remains on the surface of the chip. After plasma cleaning, the chip can greatly improve the bonding strength in the next pressure welding process.

[0057] 7) Pressure welding process: in the third generation of semiconductor mixed packaging technology, the selection of metal wire and the adjustment of bonding parameters are extremely important. There are differences between the physical properties and flexibility of different metal wires, which result in different welding strengths between the bonding wire 1 and the chip and the substrate. The gallium nitride chip 4 is more sensitive to temperature and packaging stress due to its brittle material, and chip cracking is a common packaging technical problem. For the mixed packaging of the gallium nitride chip 4, gold-copper wire or gold-palladium-copper wire is selected as the welding material, and gold-palladium-copper wire as the bonding wire 1 has better flexibility than copper wire, which can effectively overcome the chip cracking caused by packaging stress, and the price is lower than that of gold-copper wire, so it becomes the first choice in material selection.

[0058] In the welding process, in order to ensure the reliability of the metal wire welding, the bonding wire 1 between the chip and the lead frame pin 2 and between the chips can be selected in BSOB and BBOS welding mode (as shown). Figure 8 For the mixed packaging of the silicon carbide chip 8, aluminum wire is selected as the welding material. In the stacking process, the chip and the ceramic substrate 6 are connected by aluminum wire bonding, and the ceramic substrate 6 as the second welding point needs to use a rear cutter and an outer "eight" character wire bonding mode to prevent the chip from being cut when the cutter cuts the wire.

[0059] 8) cratering experiment: As an effective means of rapid inspection of cracks after bonding, the solution used and the ratio are different for wafers of different materials. For example, for GaN chips 4 with CuNiAu RDL surface metal, aqua regia and hydrogen peroxide solution are used to remove the plating layer on the surface of the chip; for non-RDL GaN chips 4 with AlCu surface metal, pure phosphoric acid is used to remove the plating layer on the surface of the chip.

[0060] 9) glue spraying process: In order to enhance the mechanical stability and environmental resistance of the package, the third generation semiconductor hybrid packaging technology uses a special packaging material coating technology, glue spraying process, which mainly coats a layer of adhesion promoter on the surface of the chip, carrier and pin after soldering, forming a uniform film, thereby increasing the bonding force between the chip and the epoxy molding compound and the frame or substrate. All glue spraying products need to be plasma cleaned before processing to remove contaminants and oxidation on the surface of the chip and frame.

[0061] For GaN chip 4 hybrid packaging process, for products with silver-plated substrate material, AP8000 adhesion promoter can effectively isolate the silver-plated surface from the epoxy molding compound, enhancing the adhesion between the epoxy molding compound and the frame and the chip. The glue spraying material needs to be baked after spraying, and the baking temperature is generally 70°C, and the time is 3 minutes. For SiC chip 8 hybrid packaging, for products with nickel-plated substrate material, GC-3688 adhesion promoter significantly improves the delamination after reliability. The material needs to be diluted before glue spraying according to (95% isopropyl alcohol: 5% water): tackifier = 9:1. The product does not need to be baked after glue spraying, but needs to be left for at least 2 hours before the subsequent process.

[0062] 10) compression molding process: After glue spraying, the product needs to be plasma cleaned before compression molding to remove contaminants on the mixed and bonded chip, wire 1, and pin, carrier part of the lead frame. The cleaned product can be well combined with the epoxy resin molding compound during compression molding, reducing the delamination rate of the product. The mixed and bonded chip, wire 1, and pin, carrier part of the lead frame are molded, and then sequentially post-cured, tinned, and separated into individual devices.

[0063] 11) post-curing process: The molded product needs to be baked in an oven to make the epoxy resin molding compound more firmly combined with the chip and wire 1, lead frame pin 2, and carrier after heating, further improving the delamination performance of the product.

[0064] 12) Tin process: After curing, the whole product of the heat sink and the pin is brass color, tin process is to plate a layer of tin on the heat sink and the pin, to form a layer of metal protective layer, to improve its corrosion resistance and electrical performance, to avoid the oxidation and damage of the pin. In this process, the purity of tin ball is 99.99%.

[0065] 13) Cutting process: the product after tin is the whole lead frame cutting rib forming, cutting off the rib, so that it is separated into a single power device, according to the application of the product, it is formed into a plug-in or a label device.

[0066] Figure 9 As shown in the figure, the nano silver glue layer at the chip and the carrier appears the fracture phenomenon after 2000 cycles of TCT (temperature cycle test) using the Kyocera CT2700R7S full sintering nano silver for the gallium nitride sealing chip.

[0067] Figure 10 As shown in the figure, the nano silver glue layer fracture anomaly is solved, and there is no delamination phenomenon between the chip and the plastic sealing material, between the chip and the glue layer, and between the glue layer and the carrier after using the Han Gao ABP 8068TB half sintering nano silver die bonding and increasing the plasma cleaning and AP8000 glue spraying process during packaging.

[0068] The principle of the present application is: providing side-by-side packaging and stacked packaging two processes when bonding the third generation chip, in the side-by-side packaging process structure, one of the chips is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5. On the surface of the lead frame, soft solder, conductive glue, insulating glue or nano sintered silver die bonding material is used in turn. The bonding sequence is: first bond the chip using high temperature material or higher temperature baking curve, and then bond the chip using low temperature material or lower temperature baking curve. After completing the chip bonding, according to the characteristics and application field of the product, the aluminum wire, gold copper wire or gold palladium copper wire with the best electrical performance is selected to form precise electrical welding between the chip and the lead frame pin 2, and between the chips.

[0069] In the stacked packaging process structure, one of the chips is a gallium nitride chip 4 or a silicon carbide chip 8, and the other is a silicon-based chip 5, or an additional ceramic substrate 6 and a capacitor 7. On the surface of the heat dissipation substrate, the ceramic substrate 6 is fixed on the heat dissipation substrate using soft solder or nano sintered silver, and then the gallium nitride chip 4 or the silicon carbide chip 8 is bonded on the other side of the ceramic substrate 6, and finally the silicon-based chip 5 stacked on the ceramic substrate 6 is bonded.

[0070] In the product without using the ceramic substrate 6, the silicon carbide chip 8 and the silicon-based chip 5 can also be directly stacked, and the process structure is to bond the silicon carbide chip 8 first, and then bond the silicon-based chip 5.

[0071] After the three-chip or two-chip chip stack bonding is completed, appropriate metal wires are selected to form precise electrical welding between the chip and the lead frame pin 2, between the chip and the lead frame carrier 3, and between the chip and the ceramic substrate 6, which can effectively combine the advantages of the gallium nitride chip 4 and the power chip, the silicon carbide chip 8 and the silicon-based chip 5, and the ceramic substrate 6, and through the use of aluminum wires, gold-copper wires, and gold-palladium-copper wires for precise electrical connection, high-efficiency thermal management and excellent electrical performance can be achieved.

[0072] According to the characteristics and application fields of the product, different performance adhesive materials and metal wires are selected for electrical connection, and advanced laser slotting technology and special glue spraying process materials are used to realize the packaging technology requirements of high performance and high reliability, which is an advanced packaging technology, improves the stability and durability of the device, and ensures that it can still work stably in a high-pressure environment.

[0073] The basic principles, main features and advantages of the present application are shown and described above. Various changes and improvements can be made to the present application without departing from the spirit and scope of the present application, and these changes and improvements all fall within the scope of the claimed present application.

Claims

1. A packaging method of a third generation semiconductor device package structure, the semiconductor device including a silicon-based chip, a gallium nitride chip or a silicon carbide chip, the method comprising: The semiconductor device also comprises a ceramic substrate and / or a capacitor, and the packaging method mainly comprises the following steps: ​ S1, laser grooving: after thinning and back gold process, grooving is performed by laser; Back gold process: before chip bonding using soft solder or nano-sintered silver paste, the micro-damage existing on the back of the gallium nitride wafer after thinning is treated in advance, and the back of the wafer is further roughened, including chemical etching of the back of the wafer, dehydration with isopropyl alcohol, and back gold after nitrogen drying; Back gold uses electron beam to generate 1000℃ high temperature to evaporate metal titanium, nickel and silver in turn, so that metal atoms move linearly in vacuum and are deposited on the wafer in turn to realize wafer back metallization; S2, dicing: the semiconductor wafer after laser grooving is diced into single chips by ultrasonic dicing; S3, chip mounting: the single chips after dicing are arranged or stacked and bonded on the frame carrier; S4, plasma cleaning: the chips after baking are cleaned by plasma; S5, pressure welding: the semiconductor device after plasma cleaning is bonded using metal wires to form electrical connection; The chip and the ceramic substrate are connected by aluminum wire bonding, the ceramic substrate is used as a second welding point, and a rear cutter is used to prevent the chip from being cut when the cutter cuts the wire in the "eight" wire bonding mode; The soldering wires between the silicon-based chip and the gallium nitride chip or the silicon carbide chip, and between the silicon-based chip, the gallium nitride chip or the silicon carbide chip and the pins of the lead frame are selected by BSOB and / or BBOS soldering mode; S6, cratering experiment: the gallium nitride chip with copper-nickel-gold RDL surface metal uses aqua regia and hydrogen peroxide solution to remove the plating layer on the surface of the chip; the non-RDL gallium nitride chip with aluminum-copper surface metal uses pure phosphoric acid to remove the plating layer on the surface of the chip; S7, plasma cleaning: the semiconductor device after pressure welding is cleaned by plasma; S8, glue spraying: the semiconductor device after plasma cleaning is sprayed with glue to form a uniform film on the surface of the frame carrier, pins and chips; For gallium nitride chip hybrid packaging, AP8000 adhesion promoter is selected as the glue spraying material to isolate the silver-plated surface of the back gold metal from the epoxy encapsulating material, thereby enhancing the adhesion between the epoxy encapsulating material and the frame and the chip; after glue spraying, baking is performed at a temperature of 70℃ for 3 minutes; For silicon carbide chip hybrid packaging, nickel-plated substrate material and GC-3688 adhesion promoter are used to significantly improve the layering, and the material needs to be diluted with (95% isopropyl alcohol: 5% water): tackifier = 9:1 before glue spraying; the product is not baked after glue spraying, and is left to stand for at least 2 hours for subsequent processes.

2. The packaging method of a third-generation semiconductor device packaging structure according to claim 1, wherein: The silicon-based chip, the gallium nitride chip or the silicon carbide chip are arranged and bonded on the frame carrier; Or the gallium nitride chip or the silicon carbide chip and the ceramic substrate are arranged and bonded on the frame carrier, and the silicon-based chip is arranged and bonded on the ceramic substrate; Or the gallium nitride chip or the silicon carbide chip and the ceramic substrate are arranged and bonded on the frame carrier, and the capacitor and the silicon-based chip are arranged and bonded on the ceramic substrate.

3. The packaging method of a third-generation semiconductor device packaging structure according to claim 2, wherein: The bonding material between the frame carrier and the silicon-based chip, the gallium nitride chip or the silicon carbide chip, the ceramic substrate and the capacitor is one or more of solder, conductive glue, insulating glue and nano-sintered silver.

4. The packaging method of a third-generation semiconductor device packaging structure according to claim 3, wherein: The bonding material between the silicon-based chip, the gallium nitride chip or the silicon carbide chip, the ceramic substrate and the capacitor is one or more of aluminum wire, gold-copper wire and gold-palladium-copper wire.

Images