Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel includes a substrate; a driving transistor and a first capacitor; the active layer is arranged on the substrate, the active layer comprises a first active region, and the channel region of the driving transistor is located in the first active region; the first conducting layer is arranged on the side, away from the substrate, of the active layer, the first conducting layer comprises a first polar plate of the first capacitor and a first scanning signal line extending in the first direction, and the first scanning signal line is located on one side of the first polar plate of the first capacitor; the orthographic projection of a first polar plate of the first capacitor on the substrate at least partially covers the orthographic projection of a channel region of the driving transistor on the substrate; the second conducting layer is arranged on the side, away from the substrate, of the first conducting layer, the second conducting layer comprises a first conducting part, the first conducting part is connected with the first polar plate of the first capacitor, and the orthographic projection of the first conducting part on the substrate is overlapped with the orthographic projection of the first scanning signal line on the substrate. The flicker phenomenon of the display panel can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of display, and in particular, to a display panel and a display device. Background Art

[0002] The display panel can use low-temperature polycrystalline silicon and oxide (Low Temperature Polycrystalline Oxide, LTPO) circuits to drive the light-emitting devices to emit light, which can improve the flickering phenomenon caused by leakage of the display panel at a low refresh rate. Summary of the invention

[0003] The present invention provides a display panel and a display device, so that the display panel can take into account both the manufacturing cost and the display effect under a low refresh rate.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] substrate;

[0006] a driving transistor and a first capacitor;

[0007] An active layer, disposed on one side of the substrate, the active layer comprising a first active region, and a channel region of the driving transistor is located in the first active region;

[0008] a first conductive layer, arranged on a side of the active layer away from the substrate, the first conductive layer comprising a first electrode plate of the first capacitor and a first scanning signal line extending along a first direction, the first scanning signal line being located on one side of the first electrode plate of the first capacitor; an orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially covering an orthographic projection of a channel region of the driving transistor on the substrate;

[0009] The second conductive layer is arranged on a side of the first conductive layer away from the substrate, the second conductive layer includes a first conductive portion, the first conductive portion is connected to the first plate of the first capacitor, and the orthographic projection of the first conductive portion on the substrate overlaps with the orthographic projection of the first scanning signal line on the substrate.

[0010] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect.

[0011] The technical solution of the embodiment of the present invention is to overlap the orthographic projection of the first conductive part on the substrate with the orthographic projection of the first scanning signal line on the substrate, so that a parasitic capacitance is provided between the first conductive part and the first scanning signal line. In the light-emitting stage, when the light-emitting reverse control signal jumps from a low level to a high level, the parasitic capacitance between the first conductive part and the first scanning signal line can increase the gate potential of the driving transistor through coupling, thereby reducing the degree of increase in the gate potential of the driving transistor caused by leakage in the light-emitting stage, improving the brightness reduction phenomenon caused by the change in the gate potential of the driving transistor during the light-emitting process, improving the flickering phenomenon of the display panel, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of the structure of an active layer provided by an embodiment of the present invention;

[0014] Figure 3 A schematic structural diagram of a first conductive layer provided by an embodiment of the present invention;

[0015] Figure 4 A schematic structural diagram of a second conductive layer provided by an embodiment of the present invention;

[0016] Figure 5 A schematic structural diagram of a third conductive layer provided by an embodiment of the present invention;

[0017] Figure 6 A schematic structural diagram of a combination of an active layer and a first conductive layer provided in an embodiment of the present invention;

[0018] Figure 7 A schematic structural diagram of a combination of an active layer, a first conductive layer and a third conductive layer provided in an embodiment of the present invention;

[0019] Figure 8 A schematic structural diagram of a combination of an active layer, a first conductive layer, a second conductive layer and a third conductive layer provided in an embodiment of the present invention;

[0020] Fig. 9 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0021] Fig.10 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting a cross section along a first direction at a first via hole;

[0022] Fig.11A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting the display panel at a third via hole along a first direction;

[0023] Fig.12 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0024] Fig.13 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting the display panel along a first direction at a fourth via hole and a fifth via hole;

[0025] Fig.14 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting a third conductive portion along an extension direction;

[0026] Fig.15 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0027] Fig.16 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0028] Fig.17 A schematic structural diagram of a fourth conductive layer and an anode structure provided by an embodiment of the present invention;

[0029] Fig.18 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting the display panel along a first direction at an eighth via hole and a ninth via hole;

[0030] Fig.19 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0031] Fig. 20 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting the display panel along a second direction at a tenth via hole;

[0032] Fig.21 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0033] Fig. 22 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting a fourth conductive portion along an extension direction;

[0034] Fig.23 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting a fifth conductive portion along an extension direction;

[0035] Fig.24A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention taken along section AA';

[0036] Fig.25 A schematic diagram of a partial structure of another display panel provided by an embodiment of the present invention;

[0037] Fig.26 A timing waveform diagram of a scanning signal provided by an embodiment of the present invention;

[0038] Fig. 27 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting the display panel along a first direction at a nineteenth via hole;

[0039] Fig.28 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting the display panel along a second direction at the twentieth via hole and the twenty-first via hole;

[0040] Fig.29 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0042] Figure 1 A schematic diagram of a partial structure of a display panel provided by an embodiment of the present invention, Figure 2 A schematic diagram of the structure of an active layer provided by an embodiment of the present invention, Figure 3 A schematic diagram of the structure of a first conductive layer provided in an embodiment of the present invention, Figure 4 A schematic diagram of the structure of a second conductive layer provided in an embodiment of the present invention, Figure 5 A schematic diagram of the structure of a third conductive layer provided in an embodiment of the present invention, Figure 6 A schematic structural diagram of a combination of an active layer and a first conductive layer provided in an embodiment of the present invention, Figure 7 A schematic structural diagram of a combination of an active layer, a first conductive layer and a third conductive layer provided in an embodiment of the present invention, Figure 8 A schematic structural diagram of a combination of an active layer, a first conductive layer, a second conductive layer and a third conductive layer provided in an embodiment of the present invention, Fig. 9 FIG. 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figures 1 to 9 As shown, the display panel includes:

[0043] Substrate 110;

[0044] A driving transistor Tdr and a first capacitor C1;

[0045] An active layer 120 is disposed on one side of the substrate 110. The active layer 120 includes a first active region 121. The channel region of the driving transistor Tdr is located in the first active region 121.

[0046] The first conductive layer M1 is disposed on a side of the active layer 120 away from the substrate 110. The first conductive layer M1 includes a first electrode C11 of the first capacitor C1 and a first scanning signal line S1 extending along the first direction X. The first scanning signal line S1 is located on one side of the first electrode C11 of the first capacitor C1. The orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate 110 at least partially covers the orthographic projection of the channel region of the driving transistor Tdr on the substrate 110.

[0047] The second conductive layer M2 is arranged on a side of the first conductive layer M2 away from the substrate 110. The second conductive layer M2 includes a first conductive portion M21. The first conductive portion 131 is connected to the first electrode C11 of the first capacitor C1. The orthographic projection of the first conductive portion M21 on the substrate 110 overlaps with the orthographic projection of the first scanning signal line S1 on the substrate 110.

[0048] Specifically, the display panel includes a pixel circuit for driving the light-emitting device to emit light. Fig. 9 As shown, the pixel circuit may include a driving transistor Tdr, a first capacitor C1 and 10 switching transistors, which are the first transistor T1 to the tenth transistor T10. Both the driving transistor Tdr and the switching transistor may be P-type transistors. The first conductive layer M1 and the second conductive layer M2 may be metal layers, which are used to form devices in the pixel circuit and connecting lines between devices. In the manufacturing process of the display panel, it is possible to avoid adding additional masks, thereby reducing the manufacturing cost of the display panel. Exemplarily, both the driving transistor Tdr and the switching transistor may be (Low Temperature Poly-silicon, LTPS) transistors. The switching transistor is used to write the data voltage into the gate of the driving transistor Tdr, and write the positive power signal provided by the first power line VDD1 into the first electrode of the driving transistor Tdr during the light emitting stage, so that the driving transistor Tdr forms a driving current according to the positive power signal and the data voltage, and transmits it to the anode of the light emitting device through the switching transistor, and the cathode of the light emitting device is connected to another power line VSS to drive the light emitting device to emit light.

[0049] The first scanning signal provided by the first scanning signal line S1 can be a light-emitting anti-control signal, that is, the first scanning signal and the light-emitting control signal have opposite levels and the same timing. The positive projection of the first conductive part M21 on the substrate 110 overlaps with the positive projection of the first scanning signal line S1 on the substrate 110, so that there is a parasitic capacitance between the first conductive part M21 and the first scanning signal line S1. And one plate of the parasitic capacitance is equivalent to being connected to the first scanning signal line S1. In the light-emitting stage of the pixel circuit, the light-emitting control signal jumps from a high level to a low level, and the switch tube is controlled to be turned on to form a current path. At this time, the first scanning signal jumps from a low level to a high level. The parasitic capacitance between the first conductive part M21 and the first scanning signal line S1 can increase the potential of the first conductive part M21 through coupling, that is, increase the gate potential of the driving transistor Tdr, thereby reducing the degree of increase in the gate potential of the driving transistor Tdr caused by leakage in the light-emitting stage, improving the brightness reduction phenomenon caused by the change in the gate potential of the driving transistor Tdr during the light-emitting process, improving the flickering phenomenon of the display panel, and improving the display effect of the display panel. Exemplarily, the capacitance value of the parasitic capacitor between the first conductive portion M21 and the first scanning signal line S1 may range from 2.2f to 3.0f. Preferably, the capacitance value of the parasitic capacitor between the first conductive portion M21 and the first scanning signal line S1 may be 2.6f.

[0050] The technical solution of this embodiment is to overlap the orthographic projection of the first conductive part on the substrate with the orthographic projection of the first scanning signal line on the substrate, so that there is a parasitic capacitance between the first conductive part and the first scanning signal line. In the light-emitting stage, when the light-emitting reverse control signal jumps from a low level to a high level, the parasitic capacitance between the first conductive part and the first scanning signal line can increase the gate potential of the driving transistor through coupling, thereby reducing the degree of increase in the gate potential of the driving transistor caused by leakage in the light-emitting stage, improving the brightness reduction phenomenon caused by the change of the gate potential of the driving transistor during the light-emitting process, improving the flickering phenomenon of the display panel, and improving the display effect of the display panel.

[0051] Continue to refer Figures 1 to 8 The first scanning signal line S1 is located at one side of the first electrode plate C11 of the first capacitor C1 along the second direction Y, and the first direction X and the second direction Y intersect.

[0052] Specifically, the first scan signal line S1 is located on the side of the first plate C11 of the first capacitor C1 facing the second direction Y, so as to avoid the first scan signal line S1 overlapping with the first plate C11 of the first capacitor C1 when extending in the first direction X and causing a short circuit.

[0053] Continue to refer Figures 1 to 8The channel region of the driving transistor Tdr is located at the positive projection position Tr of the first plate C11 of the first capacitor C1 on the first active region 121 , and the first plate C11 of the first capacitor C1 is multiplexed as the gate of the driving transistor Tdr.

[0054] Specifically, Figure 1 As shown, the first plate C11 of the first capacitor C1 overlaps with the first active area 121 to form a driving transistor Tdr, so that the first plate C11 of the first capacitor C1 reuses the gate of the driving transistor Tdr, which can improve the space utilization of the display panel and is beneficial to improving the pixel density of the display panel.

[0055] Continue to refer Figures 1 to 8 The display panel also includes a third conductive layer M3, which is located between the first conductive layer M1 and the second conductive layer M2. The third conductive layer M3 includes a first power line VDD1 and a second electrode plate C12 of the first capacitor C1. The first power line VDD1 and the second electrode plate C12 of the first capacitor C1 are connected and integrally formed.

[0056] Specifically, Figure 1 As shown, the third conductive layer M3 can be a metal layer. An insulating layer is provided between the first conductive layer M1 and the third conductive layer M3 to prevent the first conductive layer M1 and the third conductive layer M3 from short-circuiting. The orthographic projection of the second plate C12 of the first capacitor C1 on the substrate 110 overlaps with the orthographic projection of the first plate C11 on the substrate 110, so that the first plate C11, the second plate C12 and the insulating layer therebetween form the first capacitor C1. The first power supply line VDD1 is used to provide a fixed potential signal, and the second plate C12 of the first capacitor C1 is connected to the first power supply line VDD1, so that the potential of the second plate C12 of the first capacitor C1 is fixed. At the same time, the first plate C11 of the first capacitor C1 serves as the gate of the driving transistor Tdr, so that the first capacitor C1 can store the gate potential of the driving transistor Tdr, and ensure the light-emitting stability of the display panel during the light-emitting stage of the pixel circuit. Exemplarily, the capacitance value of the first capacitor C1 can range from 50f to 54f, and preferably, the capacitance value of the first capacitor C1 is 52f. The fixed potential signal provided by the first power line VDD1 can be a positive power signal of the pixel circuit, ensuring the potential stability of the second plate C12 of the first capacitor C1. For example, the positive power signal can be +7V. The first power line VDD1 and the second plate C12 of the first capacitor C1 are connected and integrally formed, which simplifies the manufacturing process of the display panel while meeting the connection requirements of the pixel circuit.

[0057] Continue to refer Figure 1 and Figure 8 , the first power line VDD1 extends along the first direction X.

[0058] Specifically, the first power line VDD1 extends along the first direction X, and the second plates C12 of the first capacitors C1 in different pixel circuits can be connected, so that the second plates C12 of the first capacitors C1 in different pixel circuits serve as part of the first power line VDD1, and a continuous first power line VDD1 is formed on the third conductive layer M3 along the first direction X, which is used to provide the first power signal to different pixel circuits, which is conducive to achieving consistency of the first power signal, thereby improving the brightness consistency of the display panel.

[0059] Fig.10 The cross-sectional structure diagram of the display panel provided by the embodiment of the present invention is obtained by cutting the display panel along the first direction at the first via hole. Figure 1 , Figure 4 and Fig.10 As shown, the second electrode plate C12 of the first capacitor C1 is provided with a first via hole DL1 , and the first conductive portion M21 passes through the first via hole DL1 and is connected to the first electrode plate C11 of the first capacitor C1 .

[0060] Specifically, the first conductive portion M21 is disposed on a side of the second electrode plate C12 away from the first electrode plate C11. By providing a first via hole DL1 on the second electrode plate C12 of the first capacitor C1, the first conductive portion M21 can be connected to the first electrode plate C11 of the first capacitor C1 through the first via hole DL1, thereby avoiding a short circuit between the first conductive portion M21 and the second electrode plate C12 of the first capacitor C1, thereby ensuring the reliability of the pixel circuit.

[0061] Continue to refer Figure 1 and Fig.10 A first insulating layer P1 is arranged between the first conductive layer M1 and the second conductive layer M2, and a second via DL2 is arranged on the first insulating layer P1. The orthographic projection of the second via DL2 on the substrate 110 is located within the orthographic projection of the first via DL1 on the substrate 110, and the orthographic projection of the second via DL2 on the substrate 110 overlaps with the orthographic projection of the first conductive portion M21 on the substrate 110 and the orthographic projection of the first electrode plate C11 of the first capacitor C1 on the substrate 110 respectively, and the first conductive portion M21 is connected to the first electrode plate C11 of the first capacitor C1 through the second via DL2.

[0062] Specifically, the first insulating layer P1 may include two insulating layers, namely, a first interlayer insulating layer P11 and a second interlayer insulating layer P12. The first interlayer insulating layer P11 is disposed between the first conductive layer M1 and the third conductive layer M3, and the second interlayer insulating layer P12 is disposed between the third conductive layer M3 and the second conductive layer M2. The second via DL2 penetrates the first insulating layer P1, and its orthographic projection on the substrate 110 overlaps with the orthographic projection of the first conductive portion M21 on the substrate 110 and the orthographic projection of the first electrode plate C11 of the first capacitor C1 on the substrate 110, respectively, so that the first conductive portion M21 can be connected to the first electrode plate C11 of the first capacitor C1 through the second via DL2. Exemplarily, in the process of manufacturing the display panel, when the first conductive portion M21 is formed, the first conductive portion M21 can extend to the first electrode plate C11 of the first capacitor C1 through the second via DL2, so that the first conductive portion M21 is in contact with the first electrode plate C11 of the first capacitor C1. At the same time, the orthographic projection of the second via DL2 on the substrate 110 is located within the orthographic projection of the first via DL1 on the substrate 110. When the first conductive portion M21 passes through the second via DL2, the first conductive portion M21 is prevented from short-circuiting with the second plate C12 of the first capacitor C1, thereby ensuring the reliability of the pixel circuit.

[0063] Continue to refer Figure 1 , the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 110 is located within the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate 110 .

[0064] Specifically, the area of ​​the second plate C12 of the first capacitor C1 is larger than the area of ​​the first plate C11 of the first capacitor C1, and the second plate C12 of the first capacitor C1 completely covers the first plate C11 of the first capacitor C1, so that the capacitance value of the first capacitor C1 can be increased as much as possible when the area of ​​the first plate C11 of the first capacitor C1 is constant, further improving the flicker phenomenon of the display panel and improving the display effect of the display panel.

[0065] Continue to refer Figure 1 The orthographic projection of the first via hole DL1 on the substrate 110 is located within the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 110 .

[0066] Specifically, the orthographic projection of the first via hole DL1 on the substrate 110 is located within the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 110, which can ensure that the first conductive part M21 contacts the first plate C11 of the first capacitor C1 when passing through the first via hole DL1, thereby realizing the connection between the first conductive part M21 and the first plate C11 of the first capacitor C1, avoiding the additional setting of connecting lines, and simplifying the line layout of the display panel.

[0067] Continue to refer Figures 1 to 8The display panel further includes a first transistor T1 , and a channel region of the first transistor T1 is located at a first orthographic projection position 1211 of the first scan signal line S1 on the first active region 121 .

[0068] Specifically, the channel region of the first transistor T1 is located at the first positive projection position 1211 of the first scanning signal line S1 on the first active area 121, so that the gate of the first transistor T1 is connected to the first scanning signal line S1. In the light-emitting stage of the pixel circuit, the first scanning signal line S1 jumps from a low level to a high level, and the first transistor T1 is turned off. The first electrode of the first transistor T1 is connected to the gate of the driving transistor Tdr, so that the gate potential of the driving transistor Tdr can be prevented from leaking through the first transistor T1 in the light-emitting stage, thereby improving the stability of the gate potential of the driving transistor Tdr, and thus improving the flickering phenomenon of the display panel.

[0069] Continue to refer Figure 1 One end of the first conductive portion M21 is connected to the first electrode C11 of the first capacitor C1 , and the other end of the first conductive portion M21 is connected to the first electrode of the first transistor T1 through the first active region 121 .

[0070] Specifically, Figure 1 As shown, one end of the first conductive part M21 is connected to the first electrode C11 of the first capacitor C1 through the first via DL1 and the second via DL2, and the other end of the first conductive part M21 is connected to the first electrode of the first transistor T1 through the first active area 121, so that the first conductive part M21 can be set on the second conductive layer M2 to realize the connection between the first electrode C11 of the first capacitor C1 and the first electrode of the first transistor T1, reduce the line layout of the first conductive layer M1 and the third conductive layer M3, and simplify the manufacturing process of the display panel.

[0071] Fig.11 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, obtained by cutting a cross section along a first direction at a third via hole, as shown in FIG. Figure 1 and Fig.11 As shown, a second insulating layer P2 is arranged between the first conductive layer M1 and the active layer 120, and a third via hole DL3 is arranged on the first insulating layer P1 and the second insulating layer P2. The third via hole DL3 penetrates the first insulating layer P1 and the second insulating layer P2, and the orthographic projection of the third via hole DL3 on the substrate 110 overlaps with the orthographic projection of the first conductive part M21 on the substrate 110 and the orthographic projection of the first active area 121 on the substrate 110, respectively, and the first conductive part M21 is connected to the first active area 121 through the third via hole DL3.

[0072] Specifically, Figure 1As shown, the third via hole DL3 penetrates the first insulating layer P1 and the second insulating layer P2, so that there is a through hole between the second conductive layer M2 and the active layer 120 at the position of the third via hole DL3. At the same time, the orthographic projection of the third via hole DL3 on the substrate 110 overlaps with the orthographic projection of the first conductive part M21 on the substrate 110 and the orthographic projection of the first active area 121 on the substrate 110 respectively. In the manufacturing process of the display panel, the first conductive part M21 extends to the surface of the first active area 121 through the third via hole DL3, so as to realize the connection between the first conductive part M21 and the first active area 121. At the same time, the active layer 120 between the overlapping position of the third via hole DL3 and the first active area 121 and the channel area of ​​the first transistor can be a heavily doped semiconductor material, which can be used as a wire to connect the first conductive part M21 at the third via hole DL3 and the first electrode of the first transistor T1, so as to realize the connection between the other end of the first conductive part M21 and the first electrode of the first transistor T1.

[0073] Continue to refer Figures 1 to 8 The display panel further includes a second transistor T2 , and a channel region of the second transistor T2 is located at a second orthographic projection position 1212 of the first scan signal line S1 on the first active region 121 .

[0074] Specifically, the channel region of the second transistor T2 is located at the second positive projection position 1212 of the first scanning signal line S1 on the first active area 121, so that the gate of the second transistor T2 is connected to the first scanning signal line S1. In the light-emitting stage of the pixel circuit, the first scanning signal line S1 jumps from a low level to a high level, and the second transistor T2 is turned off. The first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor Tdr through the fifth transistor T5, so that the gate potential of the driving transistor Tdr can be prevented from leaking through the first transistor T1, the second transistor T2 and the fifth transistor T5 in the light-emitting stage, which is conducive to improving the stability of the gate potential of the driving transistor Tdr.

[0075] Continue to refer Figures 1 to 8 The display panel further includes a third transistor T3 , and a channel region of the third transistor T3 is located at a third orthographic projection position 1213 of the first scan signal line S1 on the first active region 121 .

[0076] Specifically, the channel region of the third transistor T3 is located at the third positive projection position 1213 of the first scanning signal line S1 on the first active area 121, so that the gate of the third transistor T3 is connected to the first scanning signal line S1. In the light-emitting stage of the pixel circuit, the first scanning signal line S1 jumps from a low level to a high level, and the third transistor T3 is turned off. The first electrode of the third transistor T3 is connected to the second electrode of the first transistor T1, so that the probability of the gate potential of the driving transistor Tdr leaking through the first transistor T1 and the third transistor T3 can be further reduced in the light-emitting stage, and the stability of the gate potential of the driving transistor Tdr is further improved.

[0077] Continue to refer Figures 1 to 8 The second electrode of the first transistor T1 , the first electrode of the second transistor T2 , and the first electrode of the third transistor T3 are connected through the first active region 121 .

[0078] Specifically, the first scan signal line S1 extends along the first direction X, so that the first transistor T1, the second transistor T2 and the third transistor T3 are arranged along the first direction X. The second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode of the third transistor T3 are all located in the active layer 120, so that the first active area 121 can be set to extend along the first direction X, and the active layer 120 between the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode of the third transistor T3 can be a heavily doped semiconductor material, so that the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode of the third transistor T3 are connected through the first active area 121.

[0079] Fig.12 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.12 As shown, the display panel also includes a second capacitor C2, a first electrode plate C21 of the second capacitor C2 is located in the first conductive layer M1, and the first electrode plate C21 of the second capacitor C2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 through the second conductive portion M22.

[0080] Specifically, the second capacitor C2 has a first plate C21 and a second plate C22, and the first plate C21 of the second capacitor C2 is connected to the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode of the third transistor T3, so that the first plate C21 of the second capacitor C2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode of the third transistor T3, that is, the first plate C21 of the second capacitor C2 is connected to the first node N1 of the pixel circuit. The second plate C22 of the second capacitor C2 can be used to access a fixed potential signal, so that the potential of the first node N1 can be stabilized by the second capacitor C2. In the light-emitting stage of the pixel circuit, the potential change of the first node N1 can be avoided to affect the gate potential change of the driving transistor Tdr, further improving the gate potential stability of the driving transistor Tdr, and improving the flickering phenomenon of the display panel. Exemplarily, the display panel includes a first power line VDD1, and the first power line VDD1 is used to provide a positive power signal of the pixel circuit. The second plate C22 of the second capacitor C2 can be connected to the first power line VDD1, so that the second plate C22 of the second capacitor C2 has a fixed potential signal. The capacitance value of the second capacitor C2 can range from 60f to 64f, and preferably, the capacitance value of the second capacitor C2 is 62f.

[0081] Continue to refer Figure 4 and Fig.12 The shapes of the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 are irregular, which is beneficial to improving the compactness of different structures in the pixel circuit, increasing the capacitance value of the second capacitor C2, saving the occupied space of the pixel circuit, and is beneficial to improving the pixel density of the display panel.

[0082] Continue to refer Figure 4 and Fig.12 The second conductive part M22 is located in the second conductive layer M2, one end of the second conductive part M22 is connected to the first electrode C21 of the second capacitor C2, and the other end of the second conductive part M2 is connected to the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3.

[0083] For example, Fig.13 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention, obtained by cutting a cross section along a first direction at a fourth via hole and a fifth via hole. Figure 4 , Fig.12 and Fig.13As shown, a fourth via DL4 is provided on the first insulating layer P1, and a fifth via DL5 is provided on the first insulating layer P1 and the second insulating layer P2, and the fifth via DL5 penetrates the first insulating layer P1 and the second insulating layer P2; the orthographic projection of the fourth via DL4 on the substrate 110 overlaps with the orthographic projection of the second conductive portion M22 on the substrate 110 and the orthographic projection of the first electrode plate C21 of the second capacitor C2 on the substrate 110, respectively, and the second conductive portion M22 is connected to the first electrode plate C21 of the second capacitor C2 through the fourth via DL4; the orthographic projection of the fifth via DL5 on the substrate 110 overlaps with the orthographic projection of the second conductive portion M22 on the substrate 110 and the orthographic projection of the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 on the substrate 110, respectively, and the second conductive portion M22 is connected to the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 through the fifth via DL5.

[0084] Specifically, the fifth via hole DL5 penetrates the first insulating layer P1 and the second insulating layer P2, so that a through hole is provided between the second conductive layer M2 and the active layer 120 at the fifth via hole DL5. At the same time, the orthographic projection of the fifth via hole DL5 on the substrate 110 overlaps with the orthographic projection of the second conductive portion M22 on the substrate 110 and the orthographic projection of the connection path of the second pole of the first transistor T1, the first pole of the second transistor T2, and the first pole of the third transistor T3 on the substrate 110. In the manufacturing process of the display panel, the second conductive portion M22 extends to the connection path of the second pole of the first transistor T1, the first pole of the second transistor T2, and the first pole of the third transistor T3 through the fifth via hole DL5, so that the other end of the second conductive portion M22 is in contact with and connected to the connection path of the second pole of the first transistor T1, the first pole of the second transistor T2, and the first pole of the third transistor T3. At the same time, the orthographic projection of the fourth via hole DL4 on the substrate 110 overlaps with the orthographic projection of the second conductive portion M22 on the substrate 110 and the orthographic projection of the first electrode plate C21 of the second capacitor C2 on the substrate 110, respectively, so that a through hole is provided between the second conductive layer M2 and the first conductive layer M1 at the fourth via hole DL4. During the manufacturing process of the display panel, the second conductive portion M22 can extend to the first electrode plate C21 of the second capacitor C2 through the fourth via hole DL4, so that the second conductive portion M22 is in contact with and connected to the first electrode plate C21 of the second capacitor C2.

[0085] Preferably, the second plate C22 of the second capacitor C2 is located in the third conductive layer M3 , and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate 110 at least partially covers the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate 110 .

[0086] Specifically, there is a first interlayer insulating layer P11 between the first conductive layer M1 and the third conductive layer M3, and when the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate 110 at least partially covers the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate 110, the second plate C22 of the second capacitor C2, the first plate C21 of the second capacitor C2 and the first interlayer insulating layer P11 therebetween form the second capacitor C2.

[0087] Preferably, the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate 110 at least partially covers the orthographic projection of the connection path of the second electrode of the first transistor T1 , the first electrode of the second transistor T2 , and the first electrode of the third transistor T3 on the substrate 110 .

[0088] For details, please refer to Fig.12 , the second plate C22 of the second capacitor C2 has a fixed potential. By setting the positive projection of the second plate C22 of the second capacitor C2 on the substrate 110 to at least partially cover the positive projection of the connection path of the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the third transistor T3 on the substrate 110, the second plate C22 of the second capacitor C2 can be extended between the first scanning signal line S1 and the first node N1, thereby reducing the parasitic capacitance between the first scanning signal line S1 and the first node N1. In the light-emitting stage of the pixel circuit, when the first scanning signal line S1 jumps from a low level to a high level, the potential of the first node N1 can be reduced, thereby reducing the potential difference between the gate of the driving transistor Tdr and the first node N1, and further reducing the leakage current of the gate of the driving transistor Tdr through the first transistor T1, thereby improving the gate potential stability of the driving transistor Tdr and improving the flickering phenomenon of the display panel. Exemplarily, the capacitance value of the parasitic capacitor between the first scan signal line S1 and the first node N1 may range from 0.6f to 1.0f. Preferably, the capacitance value of the parasitic capacitor between the first scan signal line S1 and the first node N1 is 0.8f.

[0089] Continue to refer Fig.12 and Figure 4 The second electrode plate C22 of the second capacitor C2 is connected to the second electrode plate C12 of the first capacitor C1 through the third conductive portion M23.

[0090] Specifically, when the second plate C12 of the first capacitor C1 is connected to the first power supply line VDD1 and the second plate C22 of the second capacitor C2 is connected to the second plate C12 of the first capacitor C1 through the third conductive portion M23, the second plate C22 of the second capacitor C2 can be connected to the first power supply line VDD1 through the second plate C12 of the first capacitor C1, thereby providing a fixed potential signal to the second plate C22 of the second capacitor C2 through the first power supply line VDD1.

[0091] Continue to refer Fig.12 and Figure 4 The third conductive portion M23 is located in the second conductive layer M2, one end of the third conductive portion M23 is connected to the second electrode plate C22 of the second capacitor C2, and the other end of the third conductive portion M23 is connected to the second electrode plate C12 of the first capacitor C1.

[0092] Specifically, the third conductive portion M23 is located in the second conductive layer M2, so that the connection line between the second electrode plate C22 of the second capacitor C2 and the second electrode plate C12 of the first capacitor C1 is located in the second conductive layer M2, which can simplify the wiring of the first conductive layer M1 and the second conductive layer M2.

[0093] For example, Fig.14 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting the third conductive portion along the extension direction. Figure 4 , Fig.12 and Fig.14 As shown, the first insulating layer P1 includes a second interlayer insulating layer P12 arranged between the third conductive layer M3 and the second conductive layer M2, and a sixth via DL6 and a seventh via DL7 are provided on the second interlayer insulating layer P12. The orthographic projection of the sixth via DL6 on the substrate 110 overlaps with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode plate C12 of the first capacitor C1 on the substrate 110, respectively, and the third conductive part M23 is connected to the second electrode plate C12 of the first capacitor C1 through the sixth via DL6; the orthographic projection of the seventh via DL7 on the substrate 110 overlaps with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate 110, respectively, and the third conductive part M23 is connected to the second electrode plate C22 of the second capacitor C2 through the seventh via DL7.

[0094] Specifically, the sixth via hole DL6 and the seventh via hole DL7 penetrate the second interlayer insulating layer P12, so that there are through holes between the third conductive layer M3 and the second conductive layer M2 at the sixth via hole DL6 and the seventh via hole DL7. In the manufacturing process of the display panel, by setting the orthographic projection of the sixth via hole DL6 on the substrate 110 to overlap with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode plate C12 of the first capacitor C1 on the substrate 110, the other end of the third conductive part M23 can be extended to the surface of the second electrode plate C12 of the first capacitor C1 through the sixth via hole DL6, so as to achieve contact connection between the other end of the third conductive part M23 and the second electrode plate C12 of the first capacitor C1. By setting the orthographic projection of the seventh via DL7 on the substrate 110 to overlap with the orthographic projection of the third conductive part M23 on the substrate 110 and the orthographic projection of the second electrode plate C22 of the second capacitor C2 on the substrate 110, one end of the third conductive part M23 can be extended to the surface of the second electrode plate C22 of the second capacitor C2 through the seventh via DL7, thereby achieving contact connection between one end of the third conductive part M23 and the second electrode plate C22 of the second capacitor C2.

[0095] Fig.15 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 3 and Fig.15 As shown, the first conductive layer M1 further includes a second scanning signal line S2 , which extends along the first direction X and is located between the first scanning signal line S1 and the first electrode plate C11 of the first capacitor C1 .

[0096] Specifically, Figure 3 and Fig.15 As shown, the second scan signal line S2 is used to provide a second scan signal to the pixel circuit to control the state of the switch connected to the second scan signal line S2 in the pixel circuit. The second scan signal line S2 extends along the first direction X, which can avoid the second scan signal line S2 from intersecting and short-circuiting with the first scan signal line S1, thereby ensuring the reliability of the pixel circuit. At the same time, the second scan signal line S2 is located between the first scan signal line S1 and the first electrode plate C11 of the first capacitor C1, so that the switch connected to the second scan signal line S2 can be close to the driving transistor Tdr, which can simplify the connection line with the driving transistor Tdr and simplify the wiring of the pixel circuit.

[0097] Continue to refer Figure 3 , Fig. 9 and Fig.15The display panel also includes a fourth transistor T4 and a fifth transistor T5, the channel region of the fourth transistor T4 is located at a first orthographic projection position 1214 of the second scan signal line S2 in the first active area 121, and the channel region of the fifth transistor T5 is located at a second orthographic projection position 1215 of the second scan signal line S2 in the first active area 121.

[0098] Specifically, the channel region of the fourth transistor T4 is located at the first positive projection position 1214 of the second scan signal line S2 on the first active area 121, so that the gate of the fourth transistor T4 is connected to the second scan signal line S2. When the second scan signal provided by the second scan signal line S2 is at a high level, the fourth transistor T4 is turned off, and when the second scan signal is at a low level, the fourth transistor T4 is turned on. The channel region of the fifth transistor T5 is located at the second positive projection position 1215 of the second scan signal line S2 on the first active area 121, so that the gate of the fifth transistor T5 is connected to the second scan signal line S2. When the second scan signal provided by the second scan signal line S2 is at a high level, the fifth transistor T5 is turned off, and when the second scan signal is at a low level, the fifth transistor T5 is turned on. Thus, the states of the fourth transistor T4 and the fifth transistor T5 can be controlled by the second scan signal.

[0099] Continue to refer Figure 3 and Fig.15 The first electrode of the driving transistor Tdr and the first electrode of the fourth transistor T4 are connected through the first active region 121 , and the second electrode of the driving transistor Tdr and the first electrode of the fifth transistor T5 are connected through the first active region 121 .

[0100] Specifically, Figure 3 As shown, the first active region 121 can extend from the first electrode of the driving transistor Tdr to the first electrode of the fourth transistor T4, and the active layer 120 between the first electrode of the driving transistor Tdr and the first electrode of the fourth transistor T4 can be a heavily doped semiconductor material, so that the first electrode of the driving transistor Tdr and the first electrode of the fourth transistor T4 can be directly connected through the first active region 121, simplifying the wiring of the display panel. Similarly, the first active region 121 can extend from the second electrode of the driving transistor Tdr to the first electrode of the fifth transistor T5, and the active layer 120 between the second electrode of the driving transistor Tdr and the first electrode of the fifth transistor T5 can be a heavily doped semiconductor material, so that the second electrode of the driving transistor Tdr and the first electrode of the fifth transistor T5 can be directly connected through the first active region 121, simplifying the wiring of the display panel.

[0101] Continue to refer Figure 3 and Fig.15 The second electrode of the fifth transistor T5 and the second electrode of the second transistor T2 are connected through the first active region 121 .

[0102] Specifically, the first active region 121 can extend from the second electrode of the fifth transistor T5 to the second electrode of the second transistor T2, and the active layer 120 between the second electrode of the fifth transistor T5 and the second electrode of the second transistor T2 can be a heavily doped semiconductor material, so that the second electrode of the fifth transistor T5 and the second electrode of the second transistor T2 can be connected through the first active region 121, thereby simplifying the wiring of the display panel.

[0103] Fig.16 A partial structural diagram of another display panel provided by an embodiment of the present invention, Fig.17 A schematic diagram of a fourth conductive layer and an anode structure provided by an embodiment of the present invention. Fig.16 and Fig.17 As shown, the display panel further includes a fourth conductive layer M4, which is located on a side of the second conductive layer M3 away from the first conductive layer M2, and includes a data signal line DATA connected to the second electrode of the fourth transistor T4.

[0104] Specifically, when the second scan signal controls the fourth transistor T4 to turn on, the data voltage provided by the data signal line DATA can be transmitted to the first electrode of the driving transistor Tdr through the fourth transistor T4. When the driving transistor Tdr is turned on, it can be transmitted to the gate of the driving transistor Tdr through the driving transistor Tdr, the fifth transistor T5, the second transistor T2 and the first transistor T1 to realize the writing of the data voltage.

[0105] Continue to refer Fig.17 , the data signal line DATA extends along the second direction Y.

[0106] Specifically, the data signal line DATA extends along the second direction Y and can provide voltage for a column of pixel circuits. Meanwhile, the data signal line DATA is arranged in the fourth conductive layer M4 to avoid the data signal line DATA and the signal lines extending along the first direction X of other conductive layers from intersecting and short-circuiting, thereby ensuring the reliability of the pixel circuit.

[0107] Continue to refer Figure 2 , Figure 4 , Fig.16 and Fig.17 , the data signal line DATA is connected to the second electrode of the fourth transistor T4 through the first active area 121.

[0108] Specifically, the first active region 121 can be heavily doped to form a conductive line for connecting the data signal line DATA and the second electrode of the fourth transistor T4 , thereby simplifying the wiring of the pixel circuit.

[0109] Fig.18A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention, obtained by cutting the display panel along a first direction at an eighth via hole and a ninth via hole. Figure 2 , Figure 4 , Fig.16 , Fig.17 and Fig.18 A third insulating layer P3 is arranged between the second conductive layer M2 and the fourth conductive layer M4, an eighth via DL8 is arranged on the third insulating layer P3, a ninth via DL9 is arranged on the first insulating layer P1 and the second insulating layer P2, and the ninth via DL9 penetrates the first insulating layer P1 and the second insulating layer P2; the orthographic projection of the eighth via DL8 on the substrate 110 overlaps with the orthographic projection of the data signal line DATA on the substrate 110, the orthographic projection of the eighth via DL8 on the substrate 110 overlaps with the orthographic projection of the ninth via DL9 on the substrate 110, the orthographic projection of the ninth via DL9 on the substrate 110 overlaps with the orthographic projection of the first active area 121 on the substrate 110, and the data signal line DATA is connected to the first active area 121 through the eighth via DL8 and the ninth via DL9.

[0110] Specifically, the eighth via hole DL8 may penetrate the fourth conductive layer M4 and the second conductive layer M2. During the manufacturing process of the display panel, the data signal line DATA may extend to the first active area 121 through the eighth via hole DL8 and the ninth via hole DL9, so that the data signal line DATA may be connected to the first active area 121. Then the first active area 121 extends to the second electrode of the fourth transistor T4, so that the data signal line DATA may be connected to the second electrode of the fourth transistor T4, so as to provide a data voltage for the fourth transistor T4.

[0111] Fig.19 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.19 and Figure 3 As shown, the first conductive layer M1 further includes a third scan signal line S3 , which extends along the first direction X and is located on a side of the first scan signal line S1 away from the first electrode plate C11 of the first capacitor C1 .

[0112] Specifically, Figure 3 and Fig.19As shown, the third scan signal line S3 is used to provide a third scan signal to the pixel circuit to control the state of the switch connected to the third scan signal line S3 in the pixel circuit. The third scan signal line S3 extends along the first direction X, which can avoid the third scan signal line S3 and the first scan signal line S1 from intersecting and short-circuiting, thereby ensuring the reliability of the pixel circuit. At the same time, the third scan signal line S3 is located on the side of the first scan signal line S1 away from the first electrode plate C11 of the first capacitor C1, so that the switch connected to the third scan signal line S3 can be located on one side of the third transistor T3, which can simplify the connection wiring between it and the third transistor T3.

[0113] Continue to refer Figures 2 to 4 as well as Fig.19 The display panel further includes a sixth transistor T6 , and a channel region of the sixth transistor T6 is located at a positive projection position 1216 of the third scan signal line S3 on the first active region 121 .

[0114] Specifically, the channel region of the sixth transistor T6 is located at the positive projection position 1216 of the third scan signal line S3 on the first active area 121, so that the gate of the sixth transistor T6 is connected to the third scan signal line S3. When the third scan signal provided by the third scan signal line S3 is at a high level, the sixth transistor T6 is turned off, and when the third scan signal is at a low level, the sixth transistor T6 is turned on.

[0115] Continue to refer Figures 2 to 4 as well as Fig.19 , a first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3 through the first active region 121 .

[0116] Specifically, Fig.19 As shown, the first active area 121 extends from the second electrode of the third transistor T3 to the first electrode of the sixth transistor T6, and the active layer 120 between the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 is a heavily doped semiconductor material, so that the first electrode of the sixth transistor T6 is directly connected to the second electrode of the third transistor T3 through the first active area 121, which can simplify the wiring of the display panel.

[0117] Continue to refer Figures 2 to 4 as well as Fig.19 , a second electrode of the sixth transistor T6 is connected to the first initialization signal line VREF1 through the first active area 121 .

[0118] Specifically, the second electrode of the sixth transistor T6 is connected to the first initialization signal line VREF1. In the gate initialization stage of the pixel circuit, when the third scan signal controls the sixth transistor T6 to be turned on, the first initialization signal provided by the first initialization signal box VREF1 can be transmitted to the gate of the driving transistor Tdr through the sixth transistor T6, the third transistor T3 and the first transistor T1, and the gate of the driving transistor Tdr is initialized, so that the driving transistor Tdr is in a conducting state. The starting time of the third scan signal is one row of scanning time earlier than the starting time of the second scan signal, so that the pixel circuit first initializes the gate of the driving transistor Tdr in the gate initialization stage, and then controls the fourth transistor T4 and the fifth transistor T5 to be turned on by the second scan signal in the data writing stage of the pixel circuit, and writes the data voltage into the gate of the driving transistor Tdr to achieve the writing of the data voltage.

[0119] Fig. 20 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting a cross section along a second direction at a tenth via hole. Figure 2 , Figure 4 , Fig.19 and Fig. 20 As shown, the first initialization signal line VREF1 is located in the second conductive layer M2, and a tenth via hole DL10 is provided on the first insulating layer P1 and the second insulating layer P2. The tenth via hole DL10 penetrates the first insulating layer P1 and the second insulating layer P2, and the first initialization signal line VREF1 is connected to the second electrode of the sixth transistor T6 through the tenth via hole DL10 and the first active area 121.

[0120] Specifically, the tenth via hole DL10 penetrates the first insulating layer P1 and the second insulating layer P2, so that a through hole is provided between the second conductive layer M2 and the active layer 120 at the tenth via hole DL10. In the manufacturing process of the display panel, the orthographic projection of the first initialization signal line VREF1 on the substrate 110 overlaps with the orthographic projection of the tenth via hole DL10 on the substrate 10, and the orthographic projection of the tenth via hole DL10 on the substrate 10 overlaps with the orthographic projection of the first active area 121 on the substrate 110, so that the first initialization signal line VREF1 extends to the first active area 121 through the tenth via hole DL10, that is, the first initialization signal line VREF1 is connected to the first active area 121, and then the first active area 121 extends to the second electrode of the sixth transistor T6 at the tenth via hole DL10, and the active layer 120 between the tenth via hole DL10 and the second electrode of the sixth transistor T6 can be a heavily doped semiconductor material, so that the first initialization signal line VREF1 can be connected to the second electrode of the sixth transistor T6 through the first active area 121.

[0121] Preferably, the first initialization signal line VREF1 is disposed between the third scanning signal line S3 and the first scanning signal line S1 , and extends along the first direction X to avoid the first initialization signal line VREF1 from intersecting and short-circuiting with other structures, thereby ensuring the reliability of the display panel.

[0122] Fig.21 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.21 and Figure 3 As shown, the first conductive layer M1 further includes a light emitting control signal line EM, which extends along the first direction X and is located at the other side of the first electrode plate C11 of the first capacitor C1.

[0123] Specifically, Figure 3 and Fig.21 As shown, the light-emitting control signal line EM is used to provide a light-emitting control signal for the pixel circuit. The light-emitting control signal line EM extends along the first direction X, which can avoid the light-emitting control signal line EM from intersecting with other signal lines and short-circuiting, thereby ensuring the reliability of the display panel. At the same time, the light-emitting control signal line EM is located on the other side of the first electrode plate C11 of the first capacitor C1, so that the switch tube connected to the light-emitting control signal line EM can be located on one side of the driving transistor Tdr, which can simplify the connection wiring between it and the driving transistor Tdr.

[0124] Continue to refer Figures 2 to 4 as well as Fig.21 The display panel further includes a seventh transistor T7 , and a channel region of the seventh transistor T7 is located at a positive projection position 1217 of the light emitting control signal line EM on the first active region 121 .

[0125] Specifically, the channel region of the seventh transistor T7 is located at the positive projection position 1217 of the light emitting control signal line EM on the first active area 121, so that the gate of the seventh transistor T7 is connected to the light emitting control signal line EM. When the light emitting control signal provided by the light emitting control signal line EM is at a high level, the seventh transistor T7 is turned off, and when the light emitting control signal is at a low level, the seventh transistor T7 is turned on.

[0126] Continue to refer Figures 2 to 4 as well as Fig.21 , a first electrode of the seventh transistor T7 is connected to a second electrode of the driving transistor Tdr through the first active region 121 .

[0127] Specifically, the first active area 121 can extend from the first electrode of the seventh transistor T7 to the second electrode of the driving transistor Tdr, and the active layer 120 between the first electrode of the seventh transistor T7 and the second electrode of the driving transistor Tdr is a heavily doped semiconductor material, so that the first electrode of the seventh transistor T7 is directly connected to the second electrode of the driving transistor Tdr through the first active area 121, which can simplify the wiring of the display panel.

[0128] Continue to refer Figures 2 to 4 as well as Fig.21 The display panel also includes an eighth transistor T8, the active layer 120 also includes a second active area 122, the second active area 122 is in the same layer as the first active area 121 and is not connected, and the channel region of the eighth transistor T8 is located at a positive projection position 1221 of the light emitting control signal line EM in the second active area 122.

[0129] Specifically, the second active area 122 is in the same layer as the first active area 121 and is not connected. The first active area 121 and the second active area 122 can be formed simultaneously by patterning when forming the active layer 120. The channel region of the eighth transistor T8 is located at the positive projection position 1221 of the light emitting control signal line EM on the second active area 122, so that the gate of the eighth transistor T8 is connected to the light emitting control signal line EM. When the light emitting control signal provided by the light emitting control signal line EM is at a high level, the eighth transistor T8 is turned off, and when the light emitting control signal is at a low level, the eighth transistor T8 is turned on.

[0130] Continue to refer Figures 2 to 4 as well as Fig.21 , the first electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor Tdr through the fourth conductive portion M24.

[0131] Specifically, a light emitting control signal line EM is provided between the first electrode of the driving transistor Tdr and the first electrode of the eighth transistor T8 along the second direction Y. At this time, the first electrode of the driving transistor Tdr and the first electrode of the eighth transistor T8 are connected through the fourth conductive portion M24 to prevent the second active area 122 from overlapping with the light emitting control signal line EM to form another transistor.

[0132] Continue to refer Figures 2 to 4 as well as Fig.21 The fourth conductive portion M24 is located in the second conductive layer M2 , one end of the fourth conductive portion M24 is connected to the first electrode of the eighth transistor T8 through the second active region 122 , and the other end of the fourth conductive portion M24 is connected to the first electrode of the driving transistor Tdr through the second active region 122 .

[0133] Specifically, Figures 2 to 4 as well as Fig.21As shown, along the second direction Y, there is a light-emitting control signal line EM between the first electrode of the driving transistor Tdr and the second electrode of the eighth transistor T8. At this time, the first electrode of the driving transistor Tdr and the second electrode of the eighth transistor T8 are connected through the fourth conductive portion M24 to prevent the second active area 122 from overlapping with the light-emitting control signal line EM to form another transistor.

[0134] Fig. 22 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting a fourth conductive portion along an extension direction. Figures 2 to 4 as well as Fig.21 and Fig. 22 As shown, an eleventh via hole DL11 and a twelfth via hole DL12 are provided on the first insulating layer P1 and the second insulating layer P2, and the eleventh via hole DL11 and the twelfth via hole DL12 penetrate the first insulating layer P1 and the second insulating layer P2; one end of the fourth conductive portion M24 is connected to the first electrode of the eighth transistor T8 through the eleventh via hole DL11 and the second active area 122, and the other end of the fourth conductive portion is connected to the first electrode of the driving transistor Tdr through the twelfth via hole and the second active area.

[0135] Continue to refer Figures 2 to 4 as well as Fig.21 The second electrode of the eighth transistor T8 is connected to the second electrode plate C12 of the first capacitor C1 through the fifth conductive portion M25.

[0136] Specifically, the second electrode plate C12 of the first capacitor C1 is connected to the first power supply line VDD1, and the second electrode of the eighth transistor T8 is connected to the second electrode plate C12 of the first capacitor C1 through the fifth conductive portion M25, so that the second electrode of the eighth transistor T8 can be connected to the first power supply line VDD1 through the second electrode plate C12 of the first capacitor C1, so that the positive power supply signal of the pixel circuit can be provided to the second electrode of the eighth transistor T8 through the first power supply line VDD1. In the light-emitting stage of the pixel circuit, the light-emitting control signal controls the seventh transistor T7 and the eighth transistor T8 to be turned on, so that the positive power supply signal can be transmitted to the first electrode of the driving transistor Tdr through the eighth transistor T8, so that the driving transistor Tdr can form a driving current according to the data voltage of the gate of the positive power supply signal, and transmit it to the light-emitting device through the seventh transistor T7, so as to realize the display of the display panel.

[0137] Continue to refer Figures 2 to 4 as well as Fig.21 The fifth conductive part M25 is located in the second conductive layer M2, one end of the fifth conductive part M25 is connected to the second electrode of the eighth transistor T8, and the other end of the fifth conductive part M25 is connected to the second electrode plate C12 of the first capacitor C1.

[0138] Specifically, along the second direction Y, there is a light-emitting control signal line EM between the second electrode plate C12 of the first capacitor C1 and the second electrode of the eighth transistor T8. At this time, the second electrode plate C12 of the first capacitor C1 and the second electrode of the eighth transistor T8 are connected through the fifth conductive portion M25 to prevent the second active area 122 from overlapping with the light-emitting control signal line EM to form another transistor.

[0139] Fig.23 This is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention, obtained by cutting the fifth conductive portion along the extension direction. Figures 2 to 4 as well as Fig.21 and Fig.23 A thirteenth via DL13 is provided on the first insulating layer P1 and the second insulating layer P2, a fourteenth via DL14 is provided on the second interlayer insulating layer P12, one end of the fifth conductive part M25 is connected to the second electrode of the eighth transistor T8 through the thirteenth via DL13, and the other end of the fifth conductive part M25 is connected to the second electrode plate C12 of the first capacitor C1 through the fourteenth via DL14.

[0140] Specifically, the thirteenth via hole DL13 penetrates the first insulating layer P1 and the second insulating layer P2, so that there is a through hole between the second conductive layer M2 and the active layer 120 at the thirteenth via hole DL13. At the same time, the orthographic projection of the thirteenth via hole DL13 on the substrate 110 overlaps with the orthographic projection of the second electrode of the eighth transistor T8 on the substrate 110 and the orthographic projection of the fifth conductive part M25 on the substrate 110, respectively, so that in the manufacturing process of the display panel, the fifth conductive part M25 extends to the second electrode of the eighth transistor T8 through the thirteenth via hole DL13, so that one end of the fifth conductive part M25 is connected to the second electrode of the eighth transistor T8. The sixth via hole DL6 can be reused as the fourteenth via hole DL14. The orthographic projection of the fourteenth via DL14 on the substrate 110 overlaps with the orthographic projection of the fifth conductive part M25 on the substrate 110 and the orthographic projection of the second electrode plate C12 of the first capacitor C1 on the substrate 110, respectively, so that in the manufacturing process of the display panel, the fifth conductive part M25 extends to the second electrode plate C12 of the first capacitor C1 through the fourteenth via DL14, so that one end of the fifth conductive part M25 is connected to the second electrode plate C12 of the first capacitor C1. At the same time, the second electrode plate C12 of the first capacitor C1 is connected to the first power supply line VDD1, so that the second electrode of the eighth transistor T8 can be connected to the first power supply line VDD1 through the second electrode plate C12 of the first capacitor C1, providing the second electrode of the eighth transistor T8 with a positive power supply signal of the pixel circuit.

[0141] Continue to refer Fig.17 and Fig.21 The fourth conductive layer further includes a second power supply line VDD2, and the second power supply line VDD2 is connected to the second electrode plate C12 of the first capacitor C1.

[0142] Specifically, the second power line VDD2 is connected to the second plate C12 of the first capacitor C1, that is, the second power line VDD2 is connected to the first power line VDD1, so that the second power line VDD2 can provide a positive power signal to the first power line VDD1.

[0143] Continue to refer Fig.17 and Fig.21 The second power line VDD2 is arranged on one side of the data signal line DATA, and extends along the second direction Y to avoid intersecting and short-circuiting with the data signal line DATA. At the same time, it can form a power signal line that is staggered horizontally and vertically with the first power line VDD1, which can reduce the line impedance of the power signal line, which is beneficial to improving the uniformity of the positive power signal, and further improve the brightness uniformity of the display panel.

[0144] Continue to refer Fig.17 , Fig.18 and Fig.23 A fifteenth via DL15 is provided on the third insulating layer P3, and the orthographic projection of the fifteenth via DL15 on the substrate 110 overlaps with the orthographic projection of the fourteenth via DL14 on the substrate 110, and the second power line VDD2 is connected to the second plate C12 of the first capacitor C1 through the fifteenth via DL15 and the fourteenth via DL14.

[0145] Specifically, the fifteenth via DL15 penetrates the fourth conductive layer M4 and the second conductive layer M2. The orthographic projection of the fifteenth via DL15 on the substrate 110 overlaps with the orthographic projection of the fourteenth via DL14 on the substrate 110, and the orthographic projection of the fourteenth via DL14 on the substrate 110 overlaps with the orthographic projection of the fifth conductive portion M25 on the substrate 110, so that the second power supply line VDD2 can be connected to the fifth conductive portion M25 in the fourteenth via DL14 through the fifteenth via DL15, and the fifth conductive portion M25 is connected to the second electrode plate C12 of the first capacitor C1 through the fourteenth via DL14, so that the second power supply line VDD2 is connected to the second electrode plate C12 of the first capacitor C1 through the fifteenth via DL15 and the fourteenth via DL14.

[0146] Continue to refer Fig.17 and Fig.21 The display panel further includes an anode structure Anode, which is disposed on a side of the fourth conductive layer M4 away from the substrate 110 ; a second electrode of the seventh transistor T7 is connected to the anode structure Anode through the first active region 121 .

[0147] Specifically, the anode structure Anode serves as the anode of the light-emitting device in the pixel circuit. The second electrode of the seventh transistor T7 is connected to the anode structure Anode, and in the light-emitting stage of the pixel circuit, when the seventh transistor T7 is turned on, the driving current provided by the driving transistor Tdr is transmitted to the anode of the light-emitting device through the seventh transistor T7, driving the light-emitting device to emit light.

[0148] Fig.24 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention, obtained by taking a cross section along AA'. Fig.17 , Fig.21 and Fig.24 As shown, a fourth insulating layer P4 is arranged between the anode structure Anode and the fourth conductive layer M4, a sixteenth via DL16 is arranged on the fourth insulating layer P4, a seventeenth via DL17 is arranged on the first insulating layer P1 and the second insulating layer P2, the seventeenth via DL17 penetrates the first insulating layer P1 and the second insulating layer P2, an eighteenth via DL18 is arranged on the third insulating layer P3, the orthographic projection of the sixteenth via DL16 on the substrate 110 overlaps with the orthographic projection of the anode structure Anode on the substrate 110 and the orthographic projection of the eighteenth via DL18 on the substrate 110 respectively, the orthographic projection of the eighteenth via DL18 on the substrate 110 overlaps with the orthographic projection of the seventeenth via DL17 on the substrate 110, the orthographic projection of the seventeenth via DL17 on the substrate 110 overlaps with the orthographic projection of the first active area 121 on the substrate 110, and the anode structure Anode is connected to the first active area 121 through the sixteenth via DL16, the eighteenth via DL18 and the seventeenth via DL17.

[0149] Specifically, the sixteenth via DL16 penetrates the anode structure Anode and the fourth conductive layer M4. During the manufacturing process of the display panel, the anode structure Anode can extend to the fourth conductive layer M4 through the sixteenth via DL16, and extend to the second conductive layer M2 through the eighteenth via DL18 on the fourth conductive layer M4, and then extend to the first active area 121 through the seventeenth via DL17 to connect with the first active area 121. The first active area 121 extends to the second electrode of the seventh transistor T7, so that the second electrode of the seventh transistor T7 can be connected to the anode structure Anode.

[0150] Fig.25 A partial structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Fig.25 and Figure 3 As shown, the first conductive layer M1 further includes a fourth scanning signal line S4 , which extends along the first direction X and is located on a side of the light emitting control signal line EM away from the first electrode plate C11 of the first capacitor C1 .

[0151] Specifically, the fourth scan signal line S4 is used to provide a fourth scan signal to the pixel circuit to control the state of the switch connected to the fourth scan signal line S4 in the pixel circuit. The fourth scan signal line S4 extends along the first direction X, which can avoid the fourth scan signal line S4 from intersecting with other signal lines and short-circuiting, thereby ensuring the reliability of the pixel circuit. At the same time, the fourth scan signal line S4 is located on the side of the light emitting control signal line EM away from the first electrode plate C11 of the first capacitor C1, which is conducive to the fourth scan signal line S4 being connected to the transistors in the upper and lower rows of pixel circuits at the same time, thereby helping to improve the pixel density of the display panel.

[0152] In some embodiments, Fig.26 The timing waveform diagram of a scanning signal provided by an embodiment of the present invention. Among them, s2 is the timing of the second scanning signal provided by the second scanning signal line S2, s3 is the timing of the third scanning signal provided by the third scanning signal line S3, and s4 is the timing of the fourth scanning signal provided by the fourth scanning signal line S4. Fig.26 As shown, the signal waveform in the fourth scan signal line S4 is the same as the signal waveform in the third scan signal line S3, and the signal start time in the fourth scan signal line S4 is later than the signal start time in the third scan signal line S3 by one line of scanning time.

[0153] Specifically, the signal waveform in the fourth scan signal line S4 is the same as the signal waveform in the third scan signal line S3, so that the fourth scan signal provided by the fourth scan signal line S4 can initialize the anode of the light-emitting device and the first electrode of the driving transistor Tdr in the anode initialization stage of the pixel circuit, thereby ensuring the reliability of the initialization. At the same time, the signal start time in the fourth scan signal line S4 is later than the signal start time in the third scan signal line S3 by one row of scanning time, so that pixel circuits in different rows can be driven row by row.

[0154] In some embodiments, the signal in the fourth scan signal line S4 of the previous row is multiplexed into the signal in the third scan signal line S3 of the current row.

[0155] Specifically, the fourth scan signal line S4 of the previous row can be multiplexed as the third scan signal line S3 of the current row, which can simplify the structure of the display panel and is beneficial to improving the pixel density of the display panel.

[0156] Continue to refer Figures 2 to 4 as well as Fig.25 The display panel also includes a ninth transistor T9 and a tenth transistor T10, wherein a channel region of the ninth transistor T9 is located at a positive projection position 1222 of the fourth scan signal line S4 in the second active area 122, and a channel region of the tenth transistor T10 is located at a positive projection position 1218 of the fourth scan signal line S4 in the first active area 121.

[0157] Specifically, the channel region of the ninth transistor T9 is located at the positive projection position 1222 of the fourth scan signal line S4 on the second active area 122, so that the gate of the ninth transistor T9 is connected to the fourth scan signal line S4. The channel region of the tenth transistor T10 is located at the positive projection position 1218 of the fourth scan signal line S4 on the first active area 121, so that the gate of the tenth transistor T10 is connected to the fourth scan signal line S4. When the fourth scan signal provided by the fourth scan signal line S4 is at a high level, the ninth transistor T9 and the tenth transistor T10 are turned off, and when the fourth scan signal is at a low level, the ninth transistor T9 and the tenth transistor T10 are turned on.

[0158] Continue to refer Figures 2 to 4 as well as Fig.25 The first electrode of the ninth transistor T9 is connected to the first electrode of the eighth transistor T8 through the second active area 122 , and the first electrode of the tenth transistor T10 is connected to the second electrode of the seventh transistor T7 through the first active area 121 .

[0159] Specifically, when the first electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor Tdr, and the first electrode of the ninth transistor T9 is connected to the first electrode of the eighth transistor T8, the first electrode of the ninth transistor T9 can be connected to the first electrode of the driving transistor Tdr. When the ninth transistor T9 outputs the second initialization signal, the first electrode of the driving transistor Tdr can be initialized.

[0160] Continue to refer Figures 2 to 4 as well as Fig.25 The second conductive layer M2 further includes a second initialization signal line VREF2 , and the second electrode of the ninth transistor T9 is connected to the second initialization signal line VREF2 through the second active region 122 .

[0161] Specifically, the second initialization signal line VREF2 is used to provide a second initialization signal. In the anode initialization stage of the pixel circuit, the fourth scanning signal line S4 provides a low level, the ninth transistor T9 and the tenth transistor T10 are turned on, and are used to provide a second initialization signal to the first electrode of the driving transistor Tdr.

[0162] Fig. 27 A schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present invention obtained by cutting the display panel along a first direction at a nineteenth via hole. Figures 2 to 4 as well as Fig.25 and Fig. 27 As shown, a nineteenth via hole DL19 is provided on the first insulating layer P1 and the second insulating layer P2. The nineteenth via hole DL19 penetrates the first insulating layer P1 and the second insulating layer P2. The second initialization signal line VREF2 passes through the nineteenth via hole DL19 and is connected to the second electrode of the ninth transistor T9 through the second active layer 122.

[0163] Specifically, the nineteenth via hole DL19 penetrates the first insulating layer P1 and the second insulating layer P2, so that there is a through hole between the second conductive layer M2 and the active layer 120 at the nineteenth via hole DL19. In the manufacturing process of the display panel, the orthographic projection of the nineteenth via hole DL19 on the substrate overlaps with the orthographic projection of the second active area 122 on the substrate 110, and the orthographic projection of the first initialization signal line VREF2 on the substrate 110 overlaps with the orthographic projection of the nineteenth via hole DL19 on the substrate 110. The second initialization signal line VREF2 extends to the second active area 122 through the nineteenth via hole DL19, so that the second initialization signal line VREF2 is connected to the second active area 122. At the same time, the second active area 122 extends to the second electrode of the ninth transistor T9, so that the second initialization signal line VREF2 can be connected to the second electrode of the ninth transistor T9, and the second initialization signal is provided to the first electrode of the driving transistor Tdr through the ninth transistor T9 in the anode initialization stage of the pixel circuit.

[0164] Continue to refer Figure 4 as well as Fig.25 The second initialization signal line VREF2 is arranged on a side of the fourth scanning signal line S4 away from the driving transistor Tdr, and the second initialization signal line VREF2 extends along the first direction X, so as to avoid the second initialization signal line VREF2 from contacting and connecting with other conductive structures on the second conductive layer M2, thereby ensuring the reliability of the display panel.

[0165] Continue to refer Figures 2 to 5 , Fig.17 and Fig.25 The fourth conductive layer M4 further includes a third initialization signal line VREF3 , and the third initialization signal line VREF3 is connected to the second electrode of the tenth transistor T10 through the first active region 121 .

[0166] Specifically, the third initialization signal line VREF3 is used to provide a third initialization signal. In the anode initialization stage of the pixel circuit, the fourth scanning signal line S4 provides a low level, and the tenth transistor T10 is turned on to provide the third initialization signal to the anode of the light emitting device.

[0167] Continue to refer Figures 2 to 5 , Fig.17 and Fig.25 The third initialization signal line VREF3 is arranged on a side of the second power line VDD2 away from the data signal line DATA, and the third initialization signal line VREF3 extends along the second direction Y to avoid the third initialization signal line VREF3 from intersecting and short-circuiting with the data signal line DATA or the second power line VDD2.

[0168] Fig.28A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention obtained by cutting along a second direction at the 20th via hole and the 21st via hole. Figures 2 to 5 , Fig.17 , Fig.25 and Fig.28 As shown, a twentieth via hole DL20 is provided on the first insulating layer P1 and the second insulating layer P2, and the twentieth via hole DL20 penetrates the first insulating layer P1 and the second insulating layer P2, and a twenty-first via hole DL21 is provided on the third insulating layer P3, and the orthographic projection of the twenty-first via hole DL21 on the substrate 110 overlaps with the orthographic projection of the third initialization signal line VREF3 on the substrate 110 and the orthographic projection of the twentieth via hole DL20 on the substrate 110, respectively, and the orthographic projection of the twentieth via hole DL20 on the substrate 110 overlaps with the orthographic projection of the first active area 121 on the substrate 110, and the third initialization signal line VREF3 is connected to the first active area 121 through the twenty-first via hole DL21 and the twentieth via hole DL20.

[0169] Specifically, the twentieth via hole DL20 penetrates the first insulating layer P1 and the second insulating layer P2, so that a through hole is provided between the second conductive layer M2 and the active layer 120 at the twentieth via hole DL20. The twenty-first via hole DL21 penetrates the fourth conductive layer M4 and the second conductive layer M2, and overlaps with the twentieth via hole DL20, so that the third initialization signal line VREF3 extends to the second conductive layer M2 through the twenty-first via hole DL21, and then extends to the first active area 121 through the twentieth via hole DL20. The first active area 121 extends from the twentieth via hole DL20 to the second electrode of the tenth transistor T10, so that the third initialization signal line VREF3 can be connected to the second electrode of the tenth transistor T10.

[0170] On the basis of the above technical solutions, the first scanning signal line S1 extends in a zigzag manner along the first direction X, which can save the area occupied by the pixel circuit layout according to the spatial layout of the display panel, thereby facilitating the improvement of the pixel density of the display panel. Fig.25 As shown, between the first capacitor C1 and the second capacitor C2, the first scanning signal line S1 extends in a zigzag manner along the first direction X, so that the extension shape of the first scanning signal line S1 matches the edge of the second capacitor C2, and the space between the first capacitor C1 and the second capacitor C2 can be fully utilized to form the first transistor T1, the second transistor T2 and the third transistor T3. On the basis of satisfying the pixel circuit layout, it is beneficial to reduce the distance between the first capacitor C1 and the second capacitor C2 along the second direction Y, thereby saving the area occupied by the pixel circuit layout, which is beneficial to improving the pixel density of the display panel.

[0171] An embodiment of the present invention further provides a display device. Fig.29FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present invention. Fig.29 As shown, the display device 100 includes the display panel 10 provided by any embodiment of the present invention. Since the display device 100 includes the display panel 10 provided by any embodiment of the present invention, it has the same beneficial effects as the display panel 10 provided by any embodiment of the present invention, and will not be repeated here. The display device 100 can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a smart wearable device, an information inquiry machine in a public place hall, and any other product or component with a display function.

[0172] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; a driving transistor and a first capacitor; An active layer, disposed on one side of the substrate, the active layer comprising a first active region, and a channel region of the driving transistor is located in the first active region; a first conductive layer, arranged on a side of the active layer away from the substrate, the first conductive layer comprising a first electrode plate of the first capacitor and a first scanning signal line extending along a first direction, the first scanning signal line being located on one side of the first electrode plate of the first capacitor; an orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially covering an orthographic projection of a channel region of the driving transistor on the substrate; The second conductive layer is arranged on a side of the first conductive layer away from the substrate, the second conductive layer includes a first conductive portion, the first conductive portion is connected to the first plate of the first capacitor, and the orthographic projection of the first conductive portion on the substrate overlaps with the orthographic projection of the first scanning signal line on the substrate.

2. The display panel according to claim 1, characterized in that: The first scanning signal line is located at one side of the first electrode plate of the first capacitor along a second direction, and the first direction intersects with the second direction; Preferably, the channel region of the driving transistor is located at a positive projection position of the first plate of the first capacitor on the first active region, and the first plate of the first capacitor is reused as a gate of the driving transistor.

3. The display panel according to claim 1, characterized in that: The display panel further includes a third conductive layer, the third conductive layer is located between the first conductive layer and the second conductive layer, the third conductive layer includes a first power supply line and a second electrode plate of a first capacitor, the first power supply line and the second electrode plate of the first capacitor are connected and integrally formed; Preferably, the first power line extends along the first direction; Preferably, the second electrode plate of the first capacitor is provided with a first via hole, and the first conductive portion passes through the first via hole and is connected to the first electrode plate of the first capacitor; Preferably, a first insulating layer is provided between the first conductive layer and the second conductive layer, a second via is provided on the first insulating layer, an orthographic projection of the second via on the substrate is located within an orthographic projection of the first via on the substrate, and the orthographic projection of the second via on the substrate overlaps with an orthographic projection of the first conductive portion on the substrate and an orthographic projection of the first electrode plate of the first capacitor on the substrate, respectively, and the first conductive portion is connected to the first electrode plate of the first capacitor through the second via; Preferably, the orthographic projection of the first electrode plate of the first capacitor on the substrate is located within the orthographic projection of the second electrode plate of the first capacitor on the substrate; Preferably, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first plate of the first capacitor on the substrate.

4. The display panel according to claim 3, characterized in that: The display panel further comprises a first transistor, wherein a channel region of the first transistor is located at a first orthogonal projection position of the first scanning signal line on the first active region; Preferably, one end of the first conductive portion is connected to the first electrode of the first capacitor, and the other end of the first conductive portion is connected to the first electrode of the first transistor through the first active area; Preferably, a second insulating layer is arranged between the first conductive layer and the active layer, and a third via is provided on the first insulating layer and the second insulating layer, and the third via penetrates the first insulating layer and the second insulating layer, and the orthographic projection of the third via on the substrate overlaps with the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first active area on the substrate respectively, and the first conductive part is connected to the first active area through the third via.

5. The display panel according to claim 4, characterized in that: The display panel further comprises a second transistor, wherein a channel region of the second transistor is located at a second positive projection position of the first scanning signal line on the first active region; Preferably, the display panel further comprises a third transistor, a channel region of the third transistor being located at a third orthographic projection position of the first scanning signal line on the first active region; Preferably, the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor are connected through the first active region.

6. The display panel according to claim 5, characterized in that: The display panel further includes a second capacitor, a first electrode plate of the second capacitor is located in the first conductive layer, and the first electrode plate of the second capacitor is connected to a connection path of a second electrode of the first transistor, a first electrode of the second transistor, and a first electrode of the third transistor through a second conductive portion; Preferably, the second conductive portion is located in the second conductive layer, one end of the second conductive portion is connected to the first electrode plate of the second capacitor, and the other end of the second conductive portion is connected to a connection path between the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor; Preferably, a fourth via hole is provided on the first insulating layer, and a fifth via hole is provided on the first insulating layer and the second insulating layer, and the fifth via hole penetrates the first insulating layer and the second insulating layer; The orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first electrode plate of the second capacitor on the substrate, respectively, and the second conductive portion is connected to the first electrode plate of the second capacitor through the fourth via; the orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor on the substrate, respectively, and the second conductive portion is connected to the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor through the fifth via; Preferably, the second electrode plate of the second capacitor is located on the third conductive layer, and the orthographic projection of the second electrode plate of the second capacitor on the substrate at least partially covers the orthographic projection of the first electrode plate of the second capacitor on the substrate; Preferably, the orthographic projection of the second electrode plate of the second capacitor on the substrate at least partially covers the orthographic projection of the connection path of the second electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor on the substrate; Preferably, the second electrode plate of the second capacitor is connected to the second electrode plate of the first capacitor via a third conductive portion; Preferably, the third conductive portion is located in the second conductive layer, one end of the third conductive portion is connected to the second electrode plate of the second capacitor, and the other end of the third conductive portion is connected to the second electrode plate of the first capacitor; Preferably, the first insulating layer includes an interlayer insulating layer arranged between the third conductive layer and the second conductive layer, and a sixth via and a seventh via are provided on the interlayer insulating layer, the orthographic projection of the sixth via on the substrate overlaps with the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate, respectively, and the third conductive part is connected to the second plate of the first capacitor through the sixth via; the orthographic projection of the seventh via on the substrate overlaps with the orthographic projection of the third conductive part on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate, respectively, and the third conductive part is connected to the second plate of the second capacitor through the seventh via.

7. The display panel according to claim 5, characterized in that: The first conductive layer further includes a second scanning signal line, the second scanning signal line extends along the first direction, and the second scanning signal line is located between the first scanning signal line and the first electrode plate of the first capacitor.

8. The display panel according to claim 7, characterized in that: The display panel further includes a fourth transistor and a fifth transistor, wherein a channel region of the fourth transistor is located at a first orthogonal projection position of the second scan signal line on the first active region, and a channel region of the fifth transistor is located at a second orthogonal projection position of the second scan signal line on the first active region; Preferably, the first electrode of the driving transistor and the first electrode of the fourth transistor are connected through the first active region, and the second electrode of the driving transistor and the first electrode of the fifth transistor are connected through the first active region; Preferably, the second electrode of the fifth transistor and the second electrode of the second transistor are connected through the first active region.

9. The display panel according to claim 8, characterized in that: The display panel further includes a fourth conductive layer, the fourth conductive layer is located on a side of the second conductive layer away from the first conductive layer, the fourth conductive layer includes a data signal line, and the data signal line is connected to the second electrode of the fourth transistor; Preferably, the data signal line extends along the second direction; Preferably, the data signal line is connected to the second electrode of the fourth transistor through the first active area; Preferably, a third insulating layer is provided between the second conductive layer and the fourth conductive layer, an eighth via hole is provided on the third insulating layer, a ninth via hole is provided on the first insulating layer and the second insulating layer, and the ninth via hole penetrates the first insulating layer and the second insulating layer; The orthographic projection of the eighth via on the substrate overlaps with the orthographic projection of the data signal line on the substrate, the orthographic projection of the eighth via on the substrate overlaps with the orthographic projection of the ninth via on the substrate, the orthographic projection of the ninth via on the substrate overlaps with the orthographic projection of the first active area on the substrate, and the data signal line is connected to the first active area through the eighth via and the ninth via.

10. The display panel according to claim 9, characterized in that: The first conductive layer further includes a third scanning signal line, the third scanning signal line extends along the first direction, and the third scanning signal line is located on a side of the first scanning signal line away from the first electrode plate of the first capacitor.

11. The display panel according to claim 10, characterized in that: The display panel further includes a sixth transistor, wherein a channel region of the sixth transistor is located at a positive projection position of the third scanning signal line on the first active region; Preferably, the first electrode of the sixth transistor is connected to the second electrode of the third transistor through the first active region; Preferably, the second electrode of the sixth transistor is connected to the first initialization signal line through the first active area; Preferably, the first initialization signal line is located in the second conductive layer, a tenth via hole is provided on the first insulating layer and the second insulating layer, the tenth via hole penetrates the first insulating layer and the second insulating layer, and the first initialization signal line is connected to the second electrode of the sixth transistor through the tenth via hole and the first active area; Preferably, the orthographic projection of the tenth via hole on the substrate overlaps with the orthographic projection of the first active area on the substrate, and the orthographic projection of the first initialization signal line on the substrate overlaps with the orthographic projection of the tenth via hole on the substrate; Preferably, the first initialization signal line is disposed between the third scanning signal line and the first scanning signal line, and the first initialization signal line extends along the first direction.

12. The display panel according to claim 11, characterized in that: The first conductive layer further includes a light-emitting control signal line, the light-emitting control signal line extends along the first direction, and the light-emitting control signal line is located at the other side of the first electrode plate of the first capacitor; Preferably, the display panel further comprises a seventh transistor, and a channel region of the seventh transistor is located at a positive projection position of the light emitting control signal line on the first active region; Preferably, the first electrode of the seventh transistor is connected to the second electrode of the driving transistor through the first active area; Preferably, the display panel further includes an eighth transistor, the active layer further includes a second active area, the second active area is in the same layer as the first active area and is not connected, and the channel area of ​​the eighth transistor is located at the positive projection position of the light emitting control signal line on the second active area; Preferably, the first electrode of the eighth transistor is connected to the first electrode of the driving transistor through a fourth conductive portion; Preferably, the fourth conductive portion is located in the second conductive layer, one end of the fourth conductive portion is connected to the first electrode of the eighth transistor through the second active region, and the other end of the fourth conductive portion is connected to the first electrode of the driving transistor through the second active region; Preferably, an eleventh via hole and a twelfth via hole are provided on the first insulating layer and the second insulating layer, and the eleventh via hole and the twelfth via hole penetrate the first insulating layer and the second insulating layer; One end of the fourth conductive portion is connected to the first electrode of the eighth transistor through the eleventh via hole and the second active area, and the other end of the fourth conductive portion is connected to the first electrode of the driving transistor through the twelfth via hole and the second active area; Preferably, the second electrode of the eighth transistor is connected to the second electrode plate of the first capacitor through a fifth conductive portion; Preferably, the fifth conductive portion is located in the second conductive layer, one end of the fifth conductive portion is connected to the second electrode of the eighth transistor, and the other end of the fifth conductive portion is connected to the second electrode plate of the first capacitor; Preferably, a thirteenth via is provided on the first insulating layer and the second insulating layer, a fourteenth via is provided on the interlayer insulating layer, one end of the fifth conductive portion is connected to the second electrode of the eighth transistor through the thirteenth via, and the other end of the fifth conductive portion is connected to the second electrode plate of the first capacitor through the fourteenth via.

13. The display panel according to claim 12, characterized in that: The fourth conductive layer further includes a second power supply line, and the second power supply line is connected to the second plate of the first capacitor; Preferably, the second power line is arranged at one side of the data signal line, and the second power line extends along the second direction; Preferably, a fifteenth via is provided on the third insulating layer, the orthographic projection of the fifteenth via on the substrate overlaps with the orthographic projection of the fourteenth via on the substrate, and the second power supply line is connected to the second plate of the first capacitor through the fifteenth via and the fourteenth via.

14. The display panel according to claim 12, characterized in that: The display panel further comprises an anode structure, wherein the anode structure is arranged on a side of the fourth conductive layer away from the substrate; the second electrode of the seventh transistor is connected to the anode structure through the first active region; Preferably, a fourth insulating layer is arranged between the anode structure and the fourth conductive layer, a sixteenth via is arranged on the fourth insulating layer, a seventeenth via is arranged on the first insulating layer and the second insulating layer, the seventeenth via passes through the first insulating layer and the second insulating layer, an eighteenth via is arranged on the third insulating layer, the orthographic projection of the sixteenth via on the substrate overlaps with the orthographic projection of the anode structure on the substrate and the orthographic projection of the eighteenth via on the substrate respectively, the orthographic projection of the eighteenth via on the substrate overlaps with the orthographic projection of the seventeenth via on the substrate, the orthographic projection of the seventeenth via on the substrate overlaps with the orthographic projection of the first active area on the substrate, and the anode structure is connected to the first active area through the sixteenth via, the eighteenth via and the seventeenth via.

15. The display panel according to claim 12, characterized in that: The first conductive layer further includes a fourth scanning signal line, the fourth scanning signal line extends along the first direction, and the fourth scanning signal line is located at a side of the light emitting control signal line away from the first electrode plate of the first capacitor; Preferably, the signal waveform of the fourth scanning signal line is the same as the signal waveform of the third scanning signal line, and the signal start time of the fourth scanning signal line is later than the signal start time of the third scanning signal line by one scanning time of one row; Preferably, the signal in the fourth scanning signal line of the previous row is multiplexed into the signal in the third scanning signal line of the current row.

16. The display panel according to claim 15, characterized in that: The display panel further includes a ninth transistor and a tenth transistor, wherein a channel region of the ninth transistor is located at a positive projection position of the fourth scan signal line on the second active region, and a channel region of the tenth transistor is located at a positive projection position of the fourth scan signal line on the first active region; Preferably, the first electrode of the ninth transistor is connected to the first electrode of the eighth transistor through the second active region, and the first electrode of the tenth transistor is connected to the second electrode of the seventh transistor through the first active region.

17. The display panel according to claim 16, characterized in that: The second conductive layer further includes a second initialization signal line, and the second electrode of the ninth transistor is connected to the second initialization signal line through the second active area; Preferably, the second initialization signal line is arranged on a side of the fourth scanning signal line away from the driving transistor, and the second initialization signal line extends along the first direction; Preferably, a nineteenth via hole is provided on the first insulating layer and the second insulating layer, the nineteenth via hole penetrates the first insulating layer and the second insulating layer, and the second initialization signal line passes through the nineteenth via hole and is connected to the second electrode of the ninth transistor through the second active layer; Preferably, the orthographic projection of the nineteenth via hole on the substrate overlaps with the orthographic projection of the second active region on the substrate, and the orthographic projection of the first initialization signal line on the substrate overlaps with the orthographic projection of the nineteenth via hole on the substrate.

18. The display panel according to claim 16, characterized in that: The fourth conductive layer further includes a third initialization signal line, and the third initialization signal line is connected to the second electrode of the tenth transistor through the first active area; Preferably, the third initialization signal line is arranged on a side of the second power line away from the data signal line, and the third initialization signal line extends along the second direction; Preferably, a twentieth via is provided on the first insulating layer and the second insulating layer, the twentieth via penetrates the first insulating layer and the second insulating layer, a twenty-first via is provided on the third insulating layer, the orthographic projection of the twenty-first via on the substrate overlaps with the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the twentieth via on the substrate respectively, the orthographic projection of the twentieth via on the substrate overlaps with the orthographic projection of the first active area on the substrate, and the third initialization signal line is connected to the first active area through the twenty-first via and the twentieth via.

19. The display panel according to claim 1, characterized in that: The first scanning signal line extends in a zigzag manner along the first direction.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

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