Display panel and display terminal

Abstract

The present application relates to a display panel and a display terminal. The display panel includes a plurality of thin film transistors, each of which includes a first electrode, a first insulating portion, an active portion, and a second electrode; an opening is provided on the first insulating portion; the active portion is at least provided in the opening and is provided in contact with the first electrode; the second electrode is provided in contact with the active portion; the display panel also includes a scan line extending along a first direction and a data line extending along a second direction, the thin film transistor is connected to the scan line and the data line, and the size of the thin film transistor in the second direction is less than or equal to its size in the first direction. By providing the active layer in the opening, the electrical properties of the thin film transistor can be ensured without increasing the footprint of the active layer. By providing the size of the thin film transistor in the second direction to be less than or equal to the size of the thin film transistor in the first direction, the thin film transistor can be prevented from occupying too much area in the second direction, thereby improving the aperture ratio of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] A display panel has multiple sub-pixels, each of which includes a displayable area and a non-display area. The non-display area is equipped with driving components such as thin-film transistors, which drive the sub-pixel to display. The ratio of the displayable area of ​​a sub-pixel to its total area is called the aperture ratio.

[0003] In the related art, thin film transistors occupy a large area, which makes it difficult to increase the aperture ratio of the display panel.

[0004] Therefore, it is urgent to solve the above technical problems. Summary of the Invention

[0005] The embodiments of the present application provide a display panel to improve the technical problem that the aperture ratio of the display panel is difficult to increase due to the large area occupied by thin film transistors.

[0006] To achieve the above object, according to a first aspect of the present application, a display panel is provided, comprising a substrate and a plurality of thin film transistors disposed on the substrate, wherein the thin film transistors include:

[0007] a first electrode;

[0008] a first insulating portion, disposed on a side of the first electrode facing away from the substrate, the first insulating portion being provided with openings corresponding to portions of the first electrode;

[0009] an active portion, at least disposed in the opening and in contact with the first electrode;

[0010] a second electrode disposed on a side of the first insulating portion away from the substrate, and the second electrode is disposed in contact with an end of the active portion away from the substrate;

[0011] The display panel further includes a scan line extending along a first direction and a data line extending along a second direction, the thin film transistor is connected to the scan line and the data line, and the size of the thin film transistor in the second direction is smaller than or equal to the size of the thin film transistor in the first direction.

[0012] Optionally, a size of the thin film transistor in the second direction is less than or equal to twice the width of the scan line.

[0013] Optionally, the thin film transistor includes a gate and a gate insulating layer, the gate insulating layer is located on a side of the second electrode and the active portion facing away from the substrate, the gate is provided on a side of the gate insulating layer facing away from the substrate, and the gate covers at least a sidewall of the opening;

[0014] The gate and the scan line are in the same layer and are connected thereto, and a size of the gate in the second direction is smaller than a size of the gate in the first direction.

[0015] Optionally, the display panel includes a plurality of sub-pixels, at least two scan lines are arranged between two adjacent rows of sub-pixels, and at least two columns of sub-pixels are arranged between two adjacent data lines;

[0016] Wherein, one of the scan lines is connected to one of the sub-pixels through one of the thin film transistors, one of the data lines is connected to the thin film transistor through a connecting segment extending along the first direction, and one of the connecting segments is correspondingly connected to one of the thin film transistors.

[0017] Optionally, the display panel includes a pixel electrode and a common electrode, the pixel electrode is arranged on a surface of the first electrode close to the substrate and in contact with the first electrode, and the common electrode is arranged on a side of the gate away from the substrate.

[0018] Optionally, the connecting segment is provided in the same layer as the second electrode and is connected thereto.

[0019] Optionally, the display panel includes a pixel electrode and a common electrode, the pixel electrode is arranged on a side of the gate away from the substrate, and the pixel electrode is electrically connected to the second electrode through a via hole, and the common electrode is arranged in the same layer as the gate.

[0020] Optionally, the connecting segment is provided in the same layer as the first electrode and is connected thereto.

[0021] Optionally, a size of the thin film transistor in the second direction is less than or equal to 9 micrometers.

[0022] According to a second aspect of the present application, a display terminal is provided, comprising the above-mentioned display panel.

[0023] In the display panel of the embodiment of the present application, by setting the active layer in the opening and in contact with the first electrode, the electrical properties of the thin film transistor can be guaranteed without increasing the footprint of the active layer. By setting the size of the thin film transistor in the second direction to be less than or equal to the size of the thin film transistor in the first direction, the thin film transistor can be prevented from occupying too much area in the second direction, thereby reducing the footprint of the thin film transistor and improving the aperture ratio of the display panel.

[0024] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0026] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0027] Figure 1 is a bottom-view structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0028] Figure 2A yes Figure 1 A schematic diagram of an enlarged structure of a sub-pixel in FIG.

[0029] Figure 2B yes Figure 1 A schematic diagram of an enlarged structure of another sub-pixel;

[0030] Figure 3 yes Figure 2B A schematic diagram of a local enlarged structure in FIG;

[0031] Figure 4 yes Figure 3 A schematic diagram of a cross-sectional structure at CC in the middle;

[0032] Figure 5 yes Figure 3 Another cross-sectional structural diagram at CC in the middle;

[0033] Figure 6 This is a diagram illustrating the principle of GRB-GBR's driving method;

[0034] Figure 7A yes Figure 2A The corresponding flip drive principle diagram;

[0035] Figure 7B yes Figure 2B The corresponding flip drive principle diagram;

[0036] Figures 8A to 8G A process flow chart of a thin film transistor provided in an embodiment of the present application;

[0037] Figure 92 is a schematic structural diagram of a display terminal provided in an exemplary embodiment of the present disclosure.

[0038] Description of reference numerals:

[0039] Display panel 1, display area AA, non-display area NA;

[0040] substrate 10;

[0041] Thin film transistor 20, first electrode 21, first insulating portion 22, opening 22a, active portion 23, second electrode 24, gate 25, gate insulating layer 26;

[0042] Sub-pixel 31, scan line 32, data line 33, connecting segment 331, signal line 34;

[0043] Pixel electrode 41, common electrode 42, second insulating portion 43;

[0044] Photoresist pattern 50, active material layer 230, second electrode layer 240;

[0045] First direction D1, second direction D2;

[0046] Display terminal 2, terminal body 3. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0048] According to the first aspect of this application, Figures 1 to 5As shown, a display panel 1 is provided, which includes a substrate 10 and a plurality of thin film transistors 20 arranged on the substrate 10, the thin film transistor 20 including a first electrode 21, a first insulating portion 22, an active portion 23, and a second electrode 24; the first insulating portion 22 is arranged on a side of the first electrode 21 away from the substrate 10, and the first insulating portion 22 is provided with an opening 22a corresponding to a portion of the first electrode 21; the active portion 23 is at least arranged in the opening 22a and is in contact with the first electrode 21; the second electrode 24 is arranged on a side of the first insulating portion 22 away from the substrate 10, and the second electrode 24 is in contact with an end of the active portion 23 away from the substrate 10; wherein, the display panel 1 further includes a scan line 32 extending along a first direction D1 and a data line 33 extending along a second direction D2, the thin film transistor 20 is connected to the scan line 32 and the data line 33, and a size s2 of the thin film transistor 20 in the second direction D2 is less than or equal to a size s1 of the thin film transistor 20 in the first direction D1.

[0049] The display panel 1 may be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0050] The substrate 10 may be a flexible substrate or a rigid substrate. The flexible substrate may be made of polyimide, polycarbonate, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyarylate, or glass fiber reinforced plastic. The rigid substrate may be made of glass.

[0051] like Figure 4 and Figure 5 As shown, the thin film transistor 20 is disposed on one side surface of the substrate 10, and other film layers (not shown) may be disposed between the thin film transistor 20 and the substrate 10. For example, a buffer layer may be disposed between the thin film transistor 20 and the substrate 10. The material of the buffer layer may be a stack of one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0052] The materials of the first electrode 21 and the second electrode 24 are both conductive materials. For example, the materials of the first electrode 21 and the second electrode 24 can be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0053] The material of the active portion 23 is a semiconductor, such as single crystal silicon, polycrystalline silicon, metal oxide, etc., but not limited thereto.

[0054] The first insulating portion 22 is made of a material having insulating properties. The first insulating portion 22 can be an inorganic insulating material or an organic insulating material. Inorganic insulating materials include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride. Organic insulating materials include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and the like.

[0055] like Figure 4 and Figure 5 As shown, the first insulating portion 22 covers the first electrode 21 and is provided with an opening 22a. The opening 22a extends through the first insulating portion 22 along the thickness direction of the display panel 1, exposing the first electrode 21 through the opening 22a. The active portion 23 is disposed within the opening 22a and contacts the first electrode 21. The active portion 23 may cover the bottom wall and side walls of the opening 22a. The second electrode 24 is disposed on the upper surface of the first insulating portion 22 and contacts the end of the active portion 23 away from the substrate 10. One of the first electrode 21 and the second electrode 24 is a source electrode, and the other is a drain electrode.

[0056] like Figure 2A 、 Figure 2B and Figure 3 As shown, the scan lines 32 extend along a first direction D1, which is the row direction of the display panel 1. The data lines 33 extend along a second direction D2, which is the column direction of the display panel 1. The first direction D1 may be perpendicular to the second direction D2, but is not limited thereto.

[0057] Scan lines 32 and data lines 33 are wires used to transmit signals. Scan lines 32 can transmit scan signals, while data lines 33 transmit data signals. Both scan lines 32 and data lines 33 are connected to thin-film transistors 20. Driven by scan and data signals, thin-film transistors 20 control the display of display panel 1.

[0058] like Figure 2B and Figure 3As shown, the dimension s2 of the thin-film transistor 20 in the second direction D2 refers to the maximum dimension of the thin-film transistor 20 in the second direction D2, and the dimension s1 of the thin-film transistor 20 in the first direction D1 refers to the maximum dimension of the thin-film transistor 20 in the first direction D1. By setting the dimension s2 of the thin-film transistor 20 in the second direction D2 to be less than or equal to the dimension s1 of the thin-film transistor 20 in the first direction D1, the dimension s2 of the thin-film transistor 20 in the second direction D2 can be reduced, thereby reducing the footprint of the thin-film transistor 20 in the second direction D2. The dimension s1 of the thin-film transistor 20 in the first direction D1 refers to the dimension in the direction in which the scan line 32 extends, and the dimension s1 of the thin-film transistor 20 in the first direction D1 does not increase the footprint. By reducing the dimension s2 of the thin-film transistor 20 in the second direction D2, the size of the non-display area in the second direction D2 can be reduced, thereby improving the aperture ratio of the display panel 1.

[0059] The non-display area refers to an area of ​​the sub-pixel 31 that cannot emit light and is disposed between two adjacent rows of sub-pixels 31. The non-display area is used to dispose components such as the scan line 32 and the thin film transistor 20.

[0060] Alternatively, as Figure 2B and Figure 3 As shown, the size s2 of the thin film transistor 20 in the second direction D2 is less than or equal to twice the width w of the scan line 32 .

[0061] The width w of the scan line 32 refers to the dimension of the scan line 32 in a direction perpendicular to the extension direction of the scan line 32. The dimension s2 of the thin film transistor 20 in the second direction D2 is less than or equal to twice the width w of the scan line 32, thereby reducing the dimension s2 of the thin film transistor 20 in the second direction D2.

[0062] Alternatively, as Figures 3 to 5 As shown, the thin film transistor 20 includes a gate 25 and a gate insulating layer 26. The gate insulating layer 26 is located on the side of the second electrode 24 and the active portion 23 away from the substrate 10. The gate 25 is arranged on the side of the gate insulating layer 26 away from the substrate 10. The gate 25 at least covers the side wall of the opening 22a; wherein the gate 25 is in the same layer as the scanning line 32 and is connected thereto, and the size of the gate 25 in the second direction D2 is smaller than the size of the gate 25 in the first direction D1.

[0063] The gate insulating layer 26 is made of a material having insulating properties. The gate insulating layer 26 may be made of an inorganic insulating material. The inorganic insulating material may refer to the arrangement of the inorganic insulating material in the first insulating portion 22 .

[0064] The gate 25 is made of a conductive material and can be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0065] like Figures 3 to 5 As shown, a gate insulating layer 26 covers the upper surface of the active portion 23 and the second electrode 24, and a gate electrode 25 covers the upper surface of the gate insulating layer 26. The gate electrode 25 covers at least the sidewalls of the opening 22a. The portion of the active portion 23 located on the sidewalls of the opening 22a constitutes the channel of the thin film transistor 20.

[0066] like Figures 3 to 5 As shown, the gate 25 can be disposed corresponding to the opening 22a. For example, the gate 25 can cover the sidewalls and bottom wall of the opening 22a. To enhance the gate 25's ability to control the active portion 23, the gate 25 can also cover the opening edge of the opening 22a. To reduce the footprint of the thin film transistor 20, the shape of the gate 25 can match the shape of the opening 22a, that is, the outline of the gate 25 can be the same as the outline of the opening 22a in any direction.

[0067] like Figure 2B and Figure 3 As shown, the gate 25 and the scan line 32 are arranged in the same layer and connected. The gate 25 and the scan line 32 can be made of the same material, so the gate 25 and the scan line 32 can be formed using the same patterning process. The patterning process includes applying photoresist, exposing and developing, etching, removing the photoresist, etc. The patterning process is conventional in the art and will not be described in detail here.

[0068] like Figure 3 As shown, the size of the gate 25 in the second direction D2 affects the footprint of the thin film transistor 20. Therefore, by setting the size of the gate 25 in the second direction D2 to be smaller than the size of the gate 25 in the first direction D1, the size of the gate 25 in the second direction D2 can be reduced. The size of the gate 25 in the first direction D1 is the size of the scan line 32 in the extension direction. The size of the gate 25 in the first direction D1 can be set by adjusting the length of the scan line 32. Therefore, the size of the gate 25 in the first direction D1 has little effect on the aperture ratio.

[0069] Alternatively, as Figure 1 and Figure 2BAs shown, the display panel 1 includes a plurality of sub-pixels 31, at least two scan lines 32 are arranged between two adjacent rows of sub-pixels, and at least two columns of sub-pixels are arranged between two adjacent data lines 33; wherein, a scan line 32 is connected to a sub-pixel 31 through a thin film transistor 20, and a data line 33 is connected to the thin film transistor 20 through a connecting segment 331 extending along the first direction D1, and a connecting segment 331 is correspondingly connected to a thin film transistor 20.

[0070] like Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA disposed outside the display area AA. The display area AA is provided with a plurality of sub-pixels 31, and the display area AA is used to display images. The sub-pixels 31 can be red sub-pixels, green sub-pixels, and blue sub-pixels, thereby achieving color display. The non-display area NA can be provided with a driving circuit, which is used to drive the sub-pixels 31 for display. The driving circuit includes a gate driving circuit, etc. The gate driving circuit is connected to the scan line 32 and is used to provide a scanning signal to the scan line 32.

[0071] The non-display area NA may also be provided with a binding member (not shown), which may include a driver chip, a cover film, a flexible circuit board, etc. The binding member may be connected to the data line 33 via a fan-out trace to provide a data signal to the data line 33.

[0072] For ease of description, the first direction D1 is defined as the row direction of the display panel 1, and the multiple sub-pixels 31 arranged along the first direction D1 are a row of sub-pixels. The second direction D2 is defined as the column direction of the display panel 1, and the multiple sub-pixels 31 arranged along the second direction D2 are a column of sub-pixels.

[0073] In some embodiments, the display panel 1 is an LCD panel. At least two scan lines 32 are provided between two adjacent rows of sub-pixels. At least two columns of sub-pixels are provided between two adjacent data lines 33.

[0074] For example, Figure 2A As shown, two scan lines 32 are provided between two adjacent rows of sub-pixels, and two columns of sub-pixels are provided between two adjacent data lines 33. Figure 2B As shown, three scan lines 32 are arranged between two adjacent rows of sub-pixels, and three columns of sub-pixels are arranged between two adjacent data lines 33. This arrangement reduces the number of data lines 33, thereby reducing the cost of the binding components. The increased number of scan lines 32 can be adjusted accordingly through the gate drive circuit without increasing the cost of the display panel 1.

[0075] like Figure 6As shown, according to the arrangement order of the scan lines 32, the scan lines 32 are referred to as the nth scan line, the n+1th scan line, ..., the n+11th scan line. The four adjacent data lines 33 are referred to as the mth data line, the m+1th data line, the m+2th data line, and the m+3th data line, respectively. The four adjacent rows of sub-pixels are referred to as the i-th row of sub-pixels, the i+1th row of sub-pixels, the i+2th row of sub-pixels, and the i+3th row of sub-pixels, respectively. Here, m, n, and i are all positive integers. The following describes the connection relationship between the sub-pixels 31 and the scan lines 32 and data lines 33.

[0076] For ease of description, R refers to a red sub-pixel, G refers to a green sub-pixel, and B refers to a blue sub-pixel.

[0077] In some embodiments, the sub-pixels 31 in the same row are arranged in the order of RGB, and the sub-pixels 31 in the same row have the same color. For example, the first sub-pixel 31 in the i-th row is R, the second sub-pixel 31 in the i-th row is G, and the third sub-pixel 31 in the i-th row is B.

[0078] In some embodiments, the display panel 1 can adopt a GRB-GBR driving mode, so that the number of lightly loaded sub-pixels 31 in the RGB three-color sub-pixels corresponding to the same data line 33 is consistent with the number of heavily loaded sub-pixels 31, thereby improving the color shift problem in the mixed color image and realizing a flip driving mode, which can improve the image quality of the display panel 1. A mixed color image refers to an image in which two RGB color sub-pixels 31 are illuminated simultaneously, and the sub-pixels 31 of the other color are not illuminated.

[0079] It should be noted that a heavily loaded sub-pixel is a sub-pixel that requires a longer time to increase the pixel voltage of the sub-pixel 31 to a preset value, and a lightly loaded sub-pixel is a sub-pixel that requires a shorter time to increase the pixel voltage of the sub-pixel 31 to the preset value than a heavily loaded sub-pixel. For example, it takes longer for the pixel voltage to increase from 0 volts to 5 volts than it does for the pixel voltage to increase from 3 volts to 5 volts. The sub-pixel that requires the longer time is the heavily loaded sub-pixel, and the sub-pixel that requires the shorter time is the lightly loaded sub-pixel.

[0080] The following combination Figure 6 The driving method of GRB-GBR is described. Figure 6 The mixed color screen displayed in the figure can be a screen in which R is not lit and GB is lit. Figure 6 (a) shows the waveforms of pixel voltages of a plurality of sub-pixels 31 corresponding to the same data line 33; Figure 6 (b) in FIG. 3 shows the connection relationship between the plurality of sub-pixels 31 and the data lines 33 and the scan lines 32 .

[0081] like Figure 6As shown in (b), a scan line 32 is connected to a sub-pixel 31 through a thin film transistor 20. Optionally, the nth scan line is connected to the G of the i-th row through the thin film transistor 20, the n+1th scan line is connected to the R of the i-th row through the thin film transistor 20, and the n+2th scan line is connected to the B of the i-th row through the thin film transistor 20. The n+3th scan line is connected to the G of the i+1th row through the thin film transistor 20, the n+4th scan line is connected to the B of the i+1th row through the thin film transistor 20, and the n+5th scan line is connected to the R of the i+1th row through the thin film transistor 20, that is, the six adjacent scan lines are connected to GRB-GBR in sequence. The connection method of the subsequent scan lines 32 is repeated. Wherein, n and i are both positive integers.

[0082] like Figure 6 As shown in (a), the m+1th data line 33 corresponds to GRBGBR in sequence. Among them, the first G and the first B are heavily loaded sub-pixels, and the second G and the second B are lightly loaded sub-pixels. That is, the same data line 33 corresponds to 2 heavily loaded sub-pixels and 2 lightly loaded sub-pixels. The difference between the pixel voltage of the previous sub-pixel 31 of the heavily loaded sub-pixel and the preset voltage of the heavily loaded sub-pixel is large, and the heavily loaded sub-pixel is more difficult to reach the preset voltage; the difference between the pixel voltage of the previous sub-pixel 31 of the lightly loaded sub-pixel and the preset voltage of the lightly loaded sub-pixel is small, and it is easier to reach the preset voltage. The vertical axis of the curve shows the magnitude relationship of the pixel voltage. This is because in the mixed color picture, R is not lit, as shown by the thick black curve in (a), and the vertical axis of R is 0; GB is lit, and the vertical axis of GB is the preset voltage. The pixel voltage of B following the first R needs to be increased from 0 volts to the preset voltage, and the pixel voltage of the first B is difficult to reach the preset value. The pixel voltages of the second G and the second B only need to be increased from the pixel voltage of the first B to the preset voltages of the second G and the second B. The voltage increase is small and can basically reach the preset value.

[0083] The following combination Figure 6 and Figure 7B The flip driving method is described below, taking the (m+1)th data line as an example, and the settings of other data lines 33 are the same.

[0084] like Figure 6 As shown, a data line 33 is connected to the thin film transistor 20 via a connecting segment 331 extending along the first direction D1, and a connecting segment 331 is correspondingly connected to a thin film transistor 20. It should be noted that, as Figure 2B As shown, when the extension directions of two adjacent connecting segments 331 are the same and the two connecting segments 331 are connected to the same data line 33, the two adjacent connecting segments 331 can be connected to each other, thereby reducing the occupied area of ​​the connecting segments 331 in the second direction D2.

[0085] Alternatively, the (m+1)th data line can be connected to the G adjacent to the left side of the i-th row, the R adjacent to the right side of the i-th row, the B adjacent to the right side of the i-th row, the G adjacent to the right side of the i+1-th row, the B adjacent to the left side of the i+1-th row, and the R adjacent to the left side of the i+1-th row through the thin film transistors 20 in order from top to bottom. The connection method of subsequent data lines 33 is repeated in this way. By connecting the data lines 33 to the sub-pixels 31 adjacent to the left and right sides respectively, the image quality of the display panel 1 can be improved.

[0086] like Figure 7B As shown, Figure 7B Shown Figure 2B The corresponding flip driving principle diagram is that the same data line 33 is connected to the sub-pixels 31 on both sides of the data line 33 respectively. Through the above setting, the image quality of the display panel 1 can be improved.

[0087] In other embodiments, Figure 7A Shown Figure 2A The corresponding flip driving principle diagram is that the same data line 33 is connected to the sub-pixels 31 on both sides of the data line 33 respectively. Through the above setting, the image quality of the display panel 1 can be improved. Figure 7A and Figure 7B The difference is that Figure 7A There are two scanning lines 32 between two adjacent rows of sub-pixels 31. Figure 7B Three scan lines 32 are arranged between two adjacent rows of sub-pixels.

[0088] In other embodiments, the sub-pixels 31 connected to the same data line may be different from those in the above embodiment. The sub-pixels 31 connected to the same scan line 32 may be different from those in the above embodiment. In other words, the order of the sub-pixels 31 connected to the nth scan line, the n+1th scan line, and the n+2th scan line may be swapped.

[0089] In some embodiments, three scan lines 32 disposed between two adjacent rows of sub-pixels are referred to as a group of scan lines, and the order of the sub-pixels 31 connected to the two adjacent groups of scan lines may be different. That is, the order of the sub-pixels 31 connected to the (n-1)th scan line, the (n)th scan line, and the (n+1)th scan line may be different from the order of the sub-pixels 31 connected to the (n+2)th scan line, the (n+3)th scan line, and the (n+4)th scan line.

[0090] In some embodiments, as Figure 2B As shown, the connecting segment 331 can be provided in the same layer and connected to the data line 33. The connecting segment 331 can be made of the same material as the data line 33, so that the same patterning process can be used to form the connecting segment 331, thereby simplifying the manufacturing process of the display panel 1.

[0091] like Figure 2B As shown, the data line 33 and the scan line 32 are arranged in different layers. The orthographic projection of the connecting segment 331 on the substrate 10 can be arranged between two adjacent scan lines, thereby reducing the coupling capacitance between the connecting segment 331 and the scan line 32.

[0092] like Figure 2B As shown, when three scan lines are arranged adjacent to each other, a certain distance must be set between adjacent lines to prevent short circuits between two adjacent lines. Therefore, the solution of arranging three scan lines between two adjacent rows of sub-pixels occupies a larger area of ​​the non-display area, which is not conducive to improving the aperture ratio of the display panel 1. In this scenario, by reducing the dimension s2 of the thin film transistor 20 in the second direction D2, the dimension of the non-display area in the second direction D2 can be significantly reduced.

[0093] Alternatively, as Figure 2B As shown, the spacing between the orthographic projection patterns of any two adjacent traces on the substrate 10 is equal and is the minimum value achievable within the process range, thereby further reducing the size of the non-display area in the second direction D2.

[0094] Alternatively, as Figure 4 As shown, in a display panel 1 of an embodiment of the present application, the display panel 1 includes a pixel electrode 41 and a common electrode 42. The pixel electrode 41 is arranged on a side surface of the first electrode 21 close to the substrate 10 and contacts the first electrode 21. The common electrode 42 is arranged on a side of the gate 25 away from the substrate 10.

[0095] The LCD panel includes a substrate 10, an opposing substrate (not shown), and a liquid crystal layer disposed between the substrate 10 and the opposing substrate. Liquid crystal molecules in the liquid crystal layer are deflected by the electric field formed by the pixel electrodes 41 and the common electrode 42, thereby controlling the transmittance of light.

[0096] In some embodiments, as Figure 4 As shown, the pixel electrode 41 and the common electrode 42 are both disposed on the substrate 10. The pixel electrode 41 is disposed on the surface of the first electrode 21 close to the substrate 10, and the common electrode 42 is disposed on the surface of the gate 25 away from the substrate 10. The pixel electrode 41 is electrically connected to the first electrode 21.

[0097] like Figure 4 As shown, a second insulating portion 43 may be provided between the gate 25 and the common electrode 42. The second insulating portion 43 may be made of a material having insulating properties. The material of the second insulating portion 43 may be set with reference to the material of the first insulating portion 22. The second insulating portion 43 may be made of the same material as or different from the first insulating portion 22.

[0098] The common electrode 42 can be electrically connected to the signal line 34 through a via hole that passes through the second insulating portion 43. The signal line 34 is used to transmit a signal to the common electrode 42. The signal line 34 can be provided on the same layer as the gate 25. The signal line 34 and the gate 25 can be made of the same material and can be formed using the same patterning process, thereby simplifying the manufacturing process of the display panel 1.

[0099] Optionally, the connecting segment 331 is provided in the same layer and connected to the second electrode 24. That is, the connecting segment 331 can be made of the same material as the second electrode 24 and can be formed using the same patterning process as the second electrode 24, thereby simplifying the manufacturing process of the display panel 1.

[0100] like Figure 2B and Figure 4 As shown, the data line 33 transmits the data signal to the second electrode 24 through the connecting segment 331. The second electrode 24 serves as the source of the thin film transistor 20. The first electrode 21 transmits the data signal to the pixel electrode 41. The first electrode 21 serves as the drain of the thin film transistor 20.

[0101] It should be noted that Figure 2A 、 Figure 2B and Figure 3 The viewing direction is a bottom view of the display panel, that is, a view from the substrate 10 of the display panel to the direction of the thin film transistor 20. In this way, the shape and size relationship of the first electrode 21, the second electrode 24, the gate 25, etc. can be shown. The film layer sequence of the first electrode 21, the second electrode 24, and the gate 25 can be referred to. Figure 4 and Figure 5 .

[0102] In other embodiments, the pixel electrode 41 and the common electrode 42 may be disposed on the substrate 10 and the opposite substrate, respectively. In this case, the liquid crystal layer is located between the pixel electrode 41 and the common electrode 42 .

[0103] The pixel electrode 41 and the common electrode 42 are transparent conductive materials, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0104] Alternatively, as Figure 5 As shown, a display panel 1 provided by another embodiment is shown. Figure 5 and Figure 4The difference lies in the position and connection method of the pixel electrode 41 and the common electrode 42. The pixel electrode 41 is arranged on the side of the gate 25 away from the substrate 10, and the pixel electrode 41 is electrically connected to the second electrode 24 through a via hole. The common electrode 42 is arranged on the same layer as the gate 25.

[0105] In some embodiments, as Figure 5 As shown, a second insulating portion 43 may be provided between the pixel electrode 41 and the gate electrode 25, and a via hole penetrates the second insulating portion 43 and the gate insulating layer 26. The pixel electrode 41 is electrically connected to the second electrode 24 through the via hole.

[0106] Alternatively, as Figure 2B As shown, the connecting segment 331 is provided in the same layer and connected to the first electrode 21. That is, the connecting segment 331 can be made of the same material as the first electrode 21 and can be formed using the same patterning process as the first electrode 21, thereby simplifying the manufacturing process of the display panel 1.

[0107] The data line 33 transmits data signals to the first electrode 21 through the connection segment 331 . The first electrode 21 serves as the source of the thin film transistor 20 . The second electrode 24 transmits data signals to the pixel electrode 41 . The second electrode 24 serves as the drain of the thin film transistor 20 .

[0108] The common electrode 42, the gate electrode 25, and the signal line 34 can be arranged and connected in the same layer. The common electrode 42 is connected to the signal line 34, and the signal line 34 is used to transmit signals to the common electrode 42. The signal line 34 can be made of the same material as the gate electrode 25, so that it can be formed using the same patterning process, thereby simplifying the manufacturing process of the display panel 1.

[0109] Optionally, a dimension s2 of the thin film transistor 20 in the second direction D2 is less than or equal to 9 micrometers.

[0110] In some embodiments, as Figure 2B As shown, the footprint of the thin-film transistor 20 depends on the footprint of the gate 25. This is because the gate 25 is provided on the same layer as the scan lines 32, and the other film layers of the thin-film transistor 20 do not affect the spacing between two adjacent scan lines 32. When the size of the gate 25 in the second direction D2 is reduced, the spacing between two adjacent scan lines 32 can be reduced accordingly, thereby reducing the size of the non-display area in the second direction D2 and improving the aperture ratio of the display panel 1. Furthermore, reducing the size of the non-display area in the second direction D2 can also reduce the risk of horizontal stripes.

[0111] For example, the size of the gate 25 in the second direction D2 is less than or equal to 9 microns, thereby reducing the distance between the gate 25 and the adjacent scan line 32. In particular, when multiple scan lines 32 are provided between two adjacent rows of sub-pixels 31, by reducing the size of the gate 25 in the second direction D2, the area occupied by each group of scan lines 32 in the second direction D2 can be reduced, thereby improving the aperture ratio of the display panel 1.

[0112] This application provides a comparative example in which the size of the thin-film transistors in the second direction D2 is 23 microns, the size of each group of scan lines 32 in the second direction D2 is 67 microns, and the transmittance of the display panel 1 is 5.2%. In contrast, in an embodiment of the present application, the size s2 of the thin-film transistors 20 in the second direction D2 is 9 microns, the size of each group of scan lines 32 in the second direction D2 is 47.5 microns, and the transmittance of the display panel 1 is 6.12%. Compared to the comparative example, the transmittance of the display panel 1 of the present application is improved by 18%.

[0113] It should be noted that the higher the aperture ratio, the higher the light transmittance. The aperture ratio and light transmittance are positively correlated. That is, the aperture ratio of this application is also improved.

[0114] like Figures 8A to 8G As shown, a process flow chart of an embodiment of the present application is shown.

[0115] like Figure 8A As shown, a first electrode 21 is formed on a substrate 10, a first insulating portion 22 is formed on the first electrode 21, an opening 22a is formed on the first insulating portion 22 using a patterning process, and an active material layer 230 is formed on the first insulating portion 22. The active material layer 230 is provided in a region corresponding to the opening 22a and covers the opening edge of the opening 22a. A second electrode layer 240 is formed on the active material layer 230, and a photoresist pattern 50 is formed on the second electrode layer 240 in a region corresponding to the opening 22a.

[0116] like Figure 8B As shown, the second electrode layer 240 is etched to remove the portion of the second electrode layer 240 not covered by the photoresist pattern 50 .

[0117] like Figure 8C As shown, the active material layer 230 is patterned and etched to remove the portion of the active material layer 230 not covered by the photoresist pattern 50 .

[0118] like Figure 8D As shown, the photoresist pattern 50 is subjected to an ashing process to remove the portion of the photoresist pattern 50 corresponding to the opening 22 a.

[0119] like Figure 8EAs shown, the second electrode layer 240 is continuously etched to remove the portion of the second electrode layer 240 not covered by the photoresist pattern 50 .

[0120] like Figure 8F As shown, the active material layer 230 is continuously etched to thin the portion of the active material layer 230 not covered by the photoresist pattern 50 to form the active portion 23 .

[0121] like Figure 8G As shown, the photoresist pattern 50 is removed.

[0122] It should be noted that the above process flow chart does not show the process of forming the gate insulating layer 26 and the gate electrode 25 .

[0123] According to the second aspect of this application, Figure 9 As shown, a display terminal 2 is provided, and the display terminal 2 includes the above-mentioned display panel 1.

[0124] In this embodiment, if Figure 9 As shown, the display terminal 2 includes a display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one body.

[0125] In some embodiments, the display terminal 2 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0126] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0127] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0128] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0129] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a substrate and a plurality of thin film transistors arranged on the substrate, wherein the thin film transistors include: a first electrode; a first insulating portion, disposed on a side of the first electrode facing away from the substrate, the first insulating portion being provided with openings corresponding to portions of the first electrode; an active portion, at least disposed in the opening and in contact with the first electrode; a second electrode disposed on a side of the first insulating portion away from the substrate, and the second electrode is disposed in contact with an end of the active portion away from the substrate; The display panel further includes a scan line extending along a first direction and a data line extending along a second direction, the thin film transistor is connected to the scan line and the data line, and the size of the thin film transistor in the second direction is smaller than or equal to the size of the thin film transistor in the first direction.

2. The display panel according to claim 1, wherein: The size of the thin film transistor in the second direction is less than or equal to twice the width of the scan line.

3. The display panel according to claim 1, wherein: The thin film transistor includes a gate and a gate insulating layer, the gate insulating layer is located on a side of the second electrode and the active portion facing away from the substrate, the gate is provided on a side of the gate insulating layer facing away from the substrate, and the gate covers at least a sidewall of the opening; The gate and the scan line are in the same layer and are connected thereto, and a size of the gate in the second direction is smaller than a size of the gate in the first direction.

4. The display panel according to claim 3, wherein: The display panel includes a plurality of sub-pixels, at least two scan lines are arranged between two adjacent rows of sub-pixels, and at least two columns of sub-pixels are arranged between two adjacent data lines; Wherein, one of the scan lines is connected to one of the sub-pixels through one of the thin film transistors, one of the data lines is connected to the thin film transistor through a connecting segment extending along the first direction, and one of the connecting segments is correspondingly connected to one of the thin film transistors.

5. The display panel according to claim 4, wherein: The display panel includes a pixel electrode and a common electrode. The pixel electrode is arranged on a surface of the first electrode close to the substrate and in contact with the first electrode. The common electrode is arranged on a side of the gate electrode away from the substrate.

6. The display panel according to claim 5, wherein: The connecting segment is arranged in the same layer as the second electrode and is connected to the second electrode.

7. The display panel according to claim 4, wherein: The display panel includes a pixel electrode and a common electrode. The pixel electrode is arranged on a side of the gate away from the substrate and is electrically connected to the second electrode through a via hole. The common electrode is arranged in the same layer as the gate.

8. The display panel according to claim 7, wherein: The connecting segment is arranged in the same layer as the first electrode and is connected to the first electrode.

9. The display panel according to claim 1, wherein: A size of the thin film transistor in the second direction is less than or equal to 9 micrometers.

10. A display terminal, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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