Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate comprises a first transistor, the first transistor comprises a first conductor part, a second conductor part, a first semiconductor part, a first grid electrode, a first source electrode and a first drain electrode, and the first conductor part and the second conductor part are arranged at an interval; the first semiconductor part is at least connected between the first conductor part and the second conductor part, one end of the first semiconductor part is retracted to one end, far away from the second conductor part, of the first conductor part, and the other end of the first semiconductor part is retracted to one end, far away from the first conductor part, of the second conductor part; the first drain electrode is in lap joint with the second conductor part, and the part, located between the first conductor part and the second conductor part, of the first semiconductor part is a channel, so that the size of the first transistor can be reduced, and the stability of the first transistor can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, the requirements for the resolution and screen-to-body ratio of display panels are getting higher and higher. In order to improve the resolution and screen-to-body ratio of display panels, it is necessary to reduce the size of thin film transistors in the array substrate.

[0003] At present, the channel length of conventional thin film transistors is limited by the exposure accuracy and etching accuracy, which makes it difficult to further reduce the size and occupied area of ​​thin film transistors. If the channel length of thin film transistors is to be further reduced, the threshold voltage of the thin film transistor will be negatively biased, and even the thin film transistor may be turned on, resulting in reduced stability of the thin film transistor.

[0004] Therefore, it is necessary to provide an array substrate, a display panel and a display device to improve this defect. Summary of the invention

[0005] The embodiments of the present application provide an array substrate, a display panel and a display device, which can reduce the size of thin film transistors and improve the stability of thin film transistors.

[0006] In order to achieve the above object, according to a first aspect of the present application, an array substrate is provided, comprising a first transistor, wherein the first transistor comprises a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source and a first drain, and the array substrate further comprises:

[0007] substrate;

[0008] A conductor layer is provided on the substrate, the first conductor part and the second conductor part are provided on the conductor layer, and the first conductor part and the second conductor part are provided at intervals;

[0009] A semiconductor layer, disposed on the substrate, the semiconductor layer comprising the first semiconductor portion, the first semiconductor portion being at least connected between the first conductor portion and the second conductor portion;

[0010] a gate layer, disposed on a side of the semiconductor layer away from the substrate, the gate layer comprising the first gate; and

[0011] A source-drain electrode layer, disposed on a side of the semiconductor layer away from the substrate, the source-drain electrode layer comprising the first source electrode and the first drain electrode;

[0012] Among them, one end of the first semiconductor part is retracted into an end of the first conductor part away from the second conductor part, the other end of the first semiconductor part is retracted into an end of the second conductor part away from the first conductor part, the first source is overlapped with the first conductor part, and the first drain is overlapped with the second conductor part.

[0013] Optionally, along a direction from the first conductor portion to the second conductor portion, a distance between the first conductor portion and the second conductor portion is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

[0014] Optionally, the first semiconductor portion includes:

[0015] A first sub-semiconductor portion is disposed on a surface of the first conductor portion away from the substrate;

[0016] A second sub-semiconductor portion is disposed on a surface of the second conductor portion away from the substrate; and

[0017] a third sub-semiconductor portion connected between the first sub-semiconductor portion and the second sub-semiconductor portion, and the third sub-semiconductor portion is disposed between the first conductor portion and the second conductor portion;

[0018] The orthographic projection of the first sub-semiconductor portion on the first conductor portion is located in the first conductor portion, and the orthographic projection of the second sub-semiconductor portion on the second conductor portion is located in the second conductor portion.

[0019] Optionally, along a direction from the first conductor portion to the second conductor portion, a width of the first sub-semiconductor portion is smaller than a width of the first conductor portion, and a width of the second sub-semiconductor portion is smaller than a width of the second conductor portion.

[0020] Optionally, along the direction from the first conductor portion to the second conductor portion, a difference between the width of the first conductor portion and the width of the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers;

[0021] A difference between the widths of the second conductor portion and the second sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0022] Optionally, an orthographic projection of the first gate on the substrate covers an orthographic projection of the first semiconductor portion on the substrate.

[0023] Optionally, along a direction from the first conductor portion to the second conductor portion, a width of the first semiconductor portion is smaller than a width of the first gate.

[0024] Optionally, the array substrate further includes:

[0025] A gate insulating layer, disposed between the semiconductor layer and the gate layer, the gate insulating layer covering the semiconductor layer and the conductor layer;

[0026] An interlayer dielectric layer, disposed between the gate layer and the source and drain layer;

[0027] Among them, the array substrate includes a first via hole and a second via hole, the first via hole penetrates the interlayer dielectric layer and the gate insulation layer, and the first source electrode is overlapped with the first conductor part through the first via hole; the second via hole penetrates the interlayer dielectric layer and the gate insulation layer, and the first drain electrode is overlapped with the second conductor part through the second via hole.

[0028] Optionally, the array substrate further includes a second transistor, and the second transistor includes a second semiconductor portion;

[0029] The semiconductor layer includes the second semiconductor portion, and a maximum collector current of the first transistor is greater than a maximum collector current of the second transistor.

[0030] Optionally, the second transistor further includes a second gate, a second source and a second drain;

[0031] Wherein, the gate layer includes the second gate; and / or the source-drain layer includes the second source and the second drain.

[0032] Optionally, the array substrate includes a display area and a non-display area arranged around the display area, the first transistor is at least arranged in the non-display area, and the second transistor is at least arranged in the display area.

[0033] According to a second aspect of the present application, a display panel is provided, comprising the array substrate as described above.

[0034] According to a third aspect of the present application, a display device is provided, comprising the display panel as described above.

[0035] In the array substrate of the embodiment of the present application, the first conductor part and the second conductor part of the first transistor are arranged at intervals, and the first semiconductor part of the first transistor is at least connected between the first conductor part and the second conductor part, one end of the first semiconductor part is retracted to the end of the first conductor part away from the second conductor part, and the other end of the first semiconductor part is retracted to the end of the second conductor part away from the first conductor part, the first source is overlapped with the first conductor part, the first drain is overlapped with the second conductor part, and the part of the first semiconductor part located between the first conductor part and the second conductor part is the channel, so that the channel length of the first transistor can be reduced, so not only the size of the first transistor can be reduced, but also the current passing capacity of the first transistor can be improved, and the threshold voltage of the first transistor can be prevented from drifting negatively, thereby improving the stability of the first transistor.

[0036] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0038] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0039] Figure 1 A top view of an array substrate provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the film layer structure of an array substrate provided in an embodiment of the present application;

[0041] Figure 3a to Figure 3h A schematic diagram of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0044] Description of reference numerals:

[0045] 1. Substrate;

[0046] 2. conductor layer; 21. first conductor portion; 22. second conductor portion;

[0047] 3. semiconductor layer; 31. first semiconductor portion; 311. first sub-semiconductor portion; 312. second sub-semiconductor portion; 313. third sub-semiconductor portion; 32. second semiconductor portion; 321. source contact portion; 322. drain contact portion; 323. channel portion;

[0048] 4. gate layer; 41. first gate portion; 42. second gate portion;

[0049] 5. Source and drain electrode layer; 51. First source electrode; 52. First drain electrode; 53. Second source electrode; 54. Second drain electrode;

[0050] 6. light shielding layer; 61. first light shielding portion; 62. second light shielding portion;

[0051] 7. Buffer layer;

[0052] 8. Gate insulation layer;

[0053] 9. Interlayer dielectric layer;

[0054] 10. Passivation layer;

[0055] 11. Pixel electrode layer;

[0056] 101. gate driving circuit; 102. demultiplexer circuit; 103. pixel driving circuit;

[0057] 100, array substrate; 200, counter substrate; 300, liquid crystal layer;

[0058] 1000. display panel; 2000. housing; 10000. display device. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0060] The embodiment of the present application provides an array substrate, including a first transistor, the first transistor including a first conductor part, a second conductor part, a first semiconductor part, a first gate, a first source and a first drain, the array substrate also includes a substrate, a conductor layer, a semiconductor layer, a gate layer and a source-drain layer, the conductor layer is arranged on the substrate, the conductor layer includes a first conductor part and a second conductor part, the first conductor part and the second conductor part are arranged at intervals, the semiconductor layer is arranged on the substrate, the semiconductor layer includes a first semiconductor part, and the first semiconductor part is at least connected between the first conductor part and the second conductor part. The gate layer is arranged on a side of the semiconductor layer away from the substrate, the gate layer includes a first gate, the source-drain layer is arranged on a side of the semiconductor layer away from the substrate, the source-drain layer includes a first source and a first drain, one end of the first semiconductor part is retracted to one end of the first conductor part away from the second conductor part, the other end of the first semiconductor part is retracted to one end of the second conductor part away from the first conductor part, the first source is directly overlapped with the first conductor part, and the first drain is directly overlapped with the second conductor part.

[0061] In an embodiment of the present application, the first conductor portion and the second conductor portion of the first transistor are spaced apart, and the first semiconductor portion of the first transistor is at least connected between the first conductor portion and the second conductor portion, one end of the first semiconductor portion is retracted at an end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is retracted at an end of the second conductor portion away from the first conductor portion, the first source is directly overlapped with the first conductor portion, the first drain is directly overlapped with the second conductor portion, and the portion of the first semiconductor portion between the first conductor portion and the second conductor portion is the channel, so that the channel length of the first transistor can be reduced, thereby not only reducing the size of the first transistor, but also improving the current passing capacity of the first transistor, preventing the threshold voltage of the first transistor from drifting negatively, and thus improving the stability of the first transistor.

[0062] See also Figure 1 and Figure 2 , Figure 1 A top view of an array substrate provided in an embodiment of the present application, Figure 2 The schematic diagram of the film layer structure of the array substrate provided in the embodiment of the present application, the array substrate 100 includes a first transistor T1, and the first transistor T1 includes a first conductor portion 21, a second conductor portion 22, a first semiconductor portion 31, a first gate 41, a first source 51 and a first drain 52.

[0063] See also Figure 2, the array substrate 100 includes a substrate 1, a conductor layer 2, a semiconductor layer 3, a gate layer 4 and a source-drain electrode layer 5, the conductor layer 2 is arranged on the substrate 1, the first conductor portion 21 and the second conductor portion 22 are arranged on the conductor layer 2, and the first conductor portion 21 and the second conductor portion 22 are arranged at intervals. The semiconductor layer 3 is arranged on the substrate 1, and the semiconductor layer 3 includes a first semiconductor portion 31. The gate layer 4 is arranged on a side of the semiconductor layer 3 away from the substrate 1, and the gate layer 4 includes a first gate 41. In the film thickness direction of the gate layer 4, the first gate 41 is arranged in alignment with the first semiconductor portion 31, and the film thickness direction of the gate layer 4 is Figure 2 The third direction Z is shown.

[0064] See also Figure 2 The source-drain electrode layer 5 is arranged on the side of the semiconductor layer 3 away from the substrate 1, and the source-drain electrode layer 5 includes a first source electrode 51 and a first drain electrode 52. One end of the first semiconductor portion 31 is retracted to one end of the first conductor portion 21 away from the second conductor portion 22, and the other end of the first semiconductor portion 31 is retracted to one end of the second conductor portion 22 away from the first conductor portion 21. The first source electrode 51 overlaps the first conductor portion 21, and the first drain electrode 52 overlaps the second conductor portion 22.

[0065] See also Figure 2 , one end of the first semiconductor portion 31 is retracted to one end of the first conductor portion 21 away from the second conductor portion 22, the other end of the first semiconductor portion 31 is retracted to one end of the second conductor portion 22 away from the first conductor portion 21, the first source 51 is directly overlapped with the first conductor portion 21, and the first drain 52 is directly overlapped with the second conductor portion 22. By arranging the first conductor portion and the second conductor portion of the first transistor at intervals, and connecting the first semiconductor portion of the first transistor at least between the first conductor portion and the second conductor portion, one end of the first semiconductor portion is retracted to one end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is retracted to one end of the second conductor portion away from the first conductor portion, the first source is directly overlapped with the first conductor portion, the first drain is directly overlapped with the second conductor portion, and the portion of the first semiconductor portion located between the first conductor portion and the second conductor portion is the channel, so that the channel length of the first transistor can be reduced, so that not only the size of the first transistor can be reduced, but also the current passing capacity of the first transistor can be improved, and the threshold voltage of the first transistor can be prevented from drifting negatively, thereby improving the stability of the first transistor.

[0066] It should be noted that the conductor layer 2 is arranged on the substrate 1, which means that the conductor layer 2 is located above the substrate 1, and the conductor layer 2 and the substrate 1 are separated by the shading layer 6 and the buffer layer 7; the conductor layer 2 is arranged on the substrate 1, which means that the conductor layer 2 is located above the substrate 1, and the conductor layer 2 is in direct contact with the upper surface of the substrate 1.

[0067] In some embodiments, the substrate 1 is a hard substrate, and the material of the substrate 1 can be glass. In some other embodiments, the substrate 1 can also be a flexible substrate, and the substrate 1 can be a single-layer flexible substrate formed by an organic material, or a multi-layer flexible substrate formed by stacking an organic material and an inorganic material, wherein the organic material can be polyimide, and the inorganic material can be any one of silicon nitride, silicon oxide, or silicon oxynitride.

[0068] In some embodiments, see Figure 2 The array substrate 100 further includes a light shielding layer 6 and a buffer layer 7 . The light shielding layer 6 is disposed on the substrate 1 . The buffer layer 7 is disposed on a surface of the light shielding layer 6 away from the substrate 1 . The conductor layer 2 is disposed on a surface of the buffer layer 7 away from the light shielding layer 6 .

[0069] In some embodiments, the material of the light shielding layer 6 is selected from at least one of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the light shielding layer 6 may be a single-layer metal structure formed by metal materials such as molybdenum, copper, aluminum, and titanium. The light shielding layer 6 may also be a laminated structure formed by at least two of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the light shielding layer 6 may be any laminated structure of copper / aluminum, molybdenum / copper, molybdenum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, titanium / aluminum / titanium, titanium / copper / titanium, molybdenum / copper / indium zinc oxide, indium zinc oxide / copper / indium zinc oxide, and molybdenum / copper / indium tin oxide.

[0070] In some embodiments, the material of the buffer layer 7 is selected from at least one of silicon nitride, silicon oxide and silicon oxynitride. For example, the buffer layer 7 may be a single layer structure of silicon nitride or silicon oxide, or a stacked structure of silicon nitride and silicon oxide.

[0071] In the embodiment of the present application, the first conductor portion 21 and the second conductor portion 22 are part of the conductor layer 2. The first conductor portion 21 and the second conductor portion 22 are made of the same material as the conductor layer 2. The first conductor portion 21 and the second conductor portion 22 can be prepared through the process of the conductor layer 2.

[0072] In some embodiments, the material of the conductor layer 2 is selected from at least one of indium tin oxide, indium zinc oxide, tin zinc oxide, molybdenum, titanium, tantalum, and niobium. For example, the material of the conductor layer 2 is a metal or an alloy, and the conductor layer 2 can be a single-layer metal structure formed by at least one metal material among molybdenum, titanium, tantalum, and niobium, or a laminated structure formed by at least two materials among molybdenum, titanium, tantalum, and niobium. The material of the conductor layer 2 can also be an oxide conductive material, and the material of the conductor layer 2 can specifically be any one of indium tin oxide, indium zinc oxide, and tin zinc oxide. The conductor layer 2 can also be a laminated structure formed by a metal material and an oxide conductive material.

[0073] In some embodiments, along the channel length direction of the first semiconductor portion 31, the distance d1 between the first conductor portion 21 and the second conductor portion 22 is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers. For example, the distance d1 between the first conductor portion 21 and the second conductor portion 22 can be 0.5 micrometers, 0.7 micrometers, 1 micrometer, 1.2 micrometers, or 1.5 micrometers.

[0074] See also Figure 2 The first semiconductor portion 31 is connected between the first conductor portion 21 and the second conductor portion 22, and fills the gap between the first conductor portion 21 and the second conductor portion 22. The portion of the first semiconductor portion 31 between the first conductor portion 21 and the second conductor portion 22 can be regarded as the channel of the first semiconductor portion 31. Along the channel length direction of the first semiconductor portion 31, the distance d1 between the first conductor portion 21 and the second conductor portion 22 is the channel length of the first semiconductor portion 31. In this way, the first transistor T1 can have a sub-micron ultra-short channel, thereby not only reducing the size of the first transistor T1, but also improving the current passing capacity of the first transistor, preventing the threshold voltage of the first transistor from drifting negatively, and thus improving the stability of the first transistor.

[0075] It should be noted that the channel length direction of the first semiconductor portion 31 is the direction from the first conductor portion 21 to the second conductor portion 22, which can also be regarded as Figure 2 A first direction X is shown.

[0076] Combination Figure 1 and Figure 2 As shown, the bearing surface of the array substrate 100 is a plane defined by a first direction X and a second direction Y, the first direction X is perpendicular to the second direction Y, the third direction Z is perpendicular to the plane defined by the first direction X and the second direction Y, and the third direction Z is the film thickness direction of the array substrate.

[0077] In the embodiment of the present application, the first semiconductor portion 31 is a part of the semiconductor layer 3 , the first semiconductor portion 31 is made of the same material as the semiconductor layer 3 , and the first semiconductor portion 31 can be manufactured through the manufacturing process of the semiconductor layer 3 .

[0078] In some embodiments, the material of the semiconductor layer 3 is selected from one of a silicon semiconductor material and an oxide semiconductor material. For example, the material of the semiconductor layer 3 is a silicon semiconductor material, and the silicon semiconductor material may be polycrystalline silicon, which may be obtained by amorphous silicon laser annealing crystallization or other crystallization methods. The material of the semiconductor layer 3 may also be any one of indium gallium zinc oxide, indium gallium titanium oxide, indium gallium oxide, indium zinc oxide, aluminum indium zinc oxide, and aluminum tin co-doped zinc oxide.

[0079] In some embodiments, see Figure 2The first semiconductor portion 31 includes a first sub-semiconductor portion 311, a second sub-semiconductor portion 312 and a third sub-semiconductor portion 313. The first sub-semiconductor portion 311 is arranged on the surface of the first conductor portion 21 away from the substrate 1, the second sub-semiconductor portion 312 is arranged on the surface of the second conductor portion 22 away from the substrate 1, the third sub-semiconductor portion 313 is connected between the first sub-semiconductor portion 311 and the second sub-semiconductor portion 312, and the third sub-semiconductor portion 313 is arranged between the first conductor portion 21 and the second conductor portion 22. The third sub-semiconductor portion 313 can be regarded as a channel of the first semiconductor portion 31, and the orthographic projection of the first gate 41 on the substrate 1 covers the orthographic projection of the third sub-semiconductor portion 313 on the substrate 1.

[0080] It should be noted that the patterning processes of the first gate 41 and the first semiconductor portion 31 have certain deviations. If the first semiconductor portion 31 is only connected between the first conductor portion 21 and the second conductor portion 22, when the position of the first semiconductor portion 31 is offset, the first semiconductor portion 31 may not be connected between the first conductor portion 21 and the second conductor portion 22, so that the first semiconductor portion 31 cannot achieve the function of a channel, resulting in the array substrate 100 may have a poor display, and ultimately resulting in a reduction in the production yield of the array substrate. In this embodiment, by forming the first sub-semiconductor portion 311 and the second sub-semiconductor portion 312 of the first semiconductor portion 31 on the first conductor portion 21 and the second conductor portion 22 respectively, even if the position of the first semiconductor portion 31 is offset, it can be ensured that the first semiconductor portion 31 can fill the gap between the first conductor portion 21 and the second conductor portion 22, so as to ensure that the first semiconductor portion 31 can achieve the function of a channel, thereby improving the production yield of the array substrate.

[0081] In some embodiments, see Figure 2 The orthographic projection of the first sub-semiconductor portion 311 on the first conductor portion 21 is located in the first conductor portion 21, and the orthographic projection of the second sub-semiconductor portion 312 on the second conductor portion 22 is located in the second conductor portion 22, so that the first sub-semiconductor portion 311 can be prevented from blocking the first conductor portion 21, and the second sub-semiconductor portion 312 can be prevented from blocking the second conductor portion 22, so as to ensure that the first source 51 is directly overlapped with the first conductor portion 21, and the first drain 52 is directly overlapped with the second conductor portion 22. By making the first source 51 directly overlapped with the first conductor portion 21, and the first drain 52 directly overlapped with the second conductor portion 22, not only can the impedance between the first source 51 and the first conductor portion 21 and the impedance between the first drain 52 and the second conductor portion 22 be reduced, the maximum collector current of the first transistor T1 can be increased, the diffusion of the excessively high carrier concentration at the third sub-semiconductor portion 313 to both sides of the channel can be reduced, and the problem of plasma contamination existing in the opening at the first semiconductor portion 31 can be avoided.

[0082] In some embodiments, see Figure 2 , in the direction from the first conductor part 21 to the second conductor part 22, the width of the first sub-semiconductor part 311 is smaller than the width of the first conductor part 21, the end of the first sub-semiconductor part 311 away from the second sub-semiconductor part 312 is retracted at the end of the first conductor part 21 away from the second conductor part 22, and the first source 51 is directly overlapped with the end of the first conductor part 21 away from the second conductor part 22. The width of the second sub-semiconductor part 312 is smaller than the width of the second conductor part 22, the end of the second sub-semiconductor part 312 away from the first sub-semiconductor part 311 is retracted at the end of the second conductor part 22 away from the first conductor part 21, and the first drain 52 is directly overlapped with the end of the second conductor part 22 away from the first conductor part 21. In this way, the first sub-semiconductor part 311 can be prevented from blocking the first conductor part 21, and the second sub-semiconductor part 312 can be prevented from blocking the second conductor part 22, so as to ensure that the first source 51 is directly overlapped with the first conductor part 21, and the first drain 52 is directly overlapped with the second conductor part 22. By directly overlapping the first source 51 with the first conductor part 21 and the first drain 52 with the second conductor part 22, not only can the impedance between the first source 51 and the first conductor part 21 and the impedance between the first drain 52 and the second conductor part 22 be reduced, the maximum collector current of the first transistor T1 can be increased, the diffusion of excessively high carrier concentration in the third sub-semiconductor part 313 to both sides of the channel can be reduced, and the problem of plasma contamination in the opening in the first semiconductor part 31 can be avoided.

[0083] In some embodiments, along the direction from the first conductor portion 21 to the second conductor portion 22, the difference in width between the first conductor portion 21 and the first sub-semiconductor portion is greater than or equal to 1.5 microns and less than or equal to 5 microns. The difference in width between the second conductor portion 22 and the second sub-semiconductor portion 312 is greater than or equal to 1.5 microns and less than or equal to 5 microns.

[0084] It should be noted that, taking the first source 51 and the first conductor part 21 as an example, the first source 51 is connected to the first conductor part 21 through the first via hole V1. If the width of the first conductor part 21 beyond the first sub-semiconductor part 311 is too small, there is interference between the first via hole V1 and the first gate 41 or the first sub-semiconductor part 311. When the first via hole V1 is formed, the first gate 41 or the first sub-semiconductor part 311 may be etched, and the first source 51 formed subsequently may be directly overlapped with the first gate 41 or the first sub-semiconductor part 311, resulting in the electrical performance of the first transistor T1 being affected. By making the difference in width between the first conductor part 21 and the first sub-semiconductor part greater than or equal to 1.5 microns and less than or equal to 5 microns, the interference between the first via hole V1 and the first gate 41 or the first sub-semiconductor part 311 can be avoided, so as to ensure that the current passing capacity of the first transistor T1 is improved while reducing the size of the first transistor T1, and prevent the threshold voltage of the first transistor from drifting negatively, thereby improving the stability of the first transistor.

[0085] In some embodiments, see Figure 2 The orthographic projection of the first gate 41 on the substrate 1 covers the orthographic projection of the first semiconductor portion 31 on the substrate 1 , thereby ensuring that when the position of the first gate 41 or the first semiconductor portion 31 shifts, the first semiconductor portion 31 can also be located within the control range of the first gate 41 .

[0086] In some embodiments, see Figure 2 , along the direction from the first conductor portion 21 to the second conductor portion 22, the width of the first sub-semiconductor portion 311 is smaller than the width of the first gate 41, so that when the position of the first gate 41 or the first semiconductor portion 31 is offset, the first semiconductor portion 31 can also be located within the control range of the first gate 41.

[0087] In some embodiments, see Figure 2 , the array substrate 100 further includes a gate insulating layer 8 and an interlayer dielectric layer 9, the gate insulating layer 8 is disposed between the semiconductor layer 3 and the gate layer 4, and the gate insulating layer 8 covers the semiconductor layer 3 and the conductor layer 2. The interlayer dielectric layer 9 is disposed between the gate layer 4 and the source and drain electrode layer 5. The array substrate 100 includes a first via hole V1 and a second via hole V2, the first via hole V1 penetrates the interlayer dielectric layer 9 and the gate insulating layer 8, the first source electrode 51 is overlapped with the first conductor portion 21 through the first via hole V1, the second via hole V2 penetrates the interlayer dielectric layer 9 and the gate insulating layer 8, and the first drain electrode 52 is overlapped with the second conductor portion 22 through the second via hole V2.

[0088] In some embodiments, the material of the gate insulating layer 8 is selected from at least one of silicon nitride, silicon oxide, silicon oxynitride and aluminum oxide. For example, the gate insulating layer 8 may be a single-layer structure formed by silicon oxide material, or the gate insulating layer 8 may be a stacked structure formed by aluminum oxide, silicon nitride and silicon oxide stacked in sequence, or the gate insulating layer 8 may be a stacked structure formed by silicon oxide, silicon nitride and silicon oxide stacked in sequence.

[0089] In some embodiments, see Figure 2 The array substrate 100 further includes a second transistor T2 , the second transistor T2 includes a second semiconductor portion 32 , and the second semiconductor portion 32 is disposed in the semiconductor layer 3 .

[0090] It should be noted that the second semiconductor portion 32 is arranged in the semiconductor layer 3, which means that the second semiconductor portion 32 is a part of the semiconductor layer 3, the second semiconductor portion 32 and the semiconductor layer 3 are made of the same material, and the second semiconductor portion 32 and the semiconductor layer 3 are prepared by the same process, that is, the semiconductor layer 3 includes the second semiconductor portion 32.

[0091] In this embodiment, the first semiconductor portion 31 and the second semiconductor portion 32 are arranged in the same layer, and the materials of the first semiconductor portion 31 and the second semiconductor portion 32 are the same. The first semiconductor portion 31 and the second semiconductor portion 32 are prepared simultaneously through the process of the semiconductor layer 3. In this way, the size of the first transistor T1 is reduced and the current conduction capability and stability of the first transistor T1 are improved, while the number of process steps and masks is reduced, thereby reducing production costs.

[0092] In some embodiments, the maximum collector current of the first transistor T1 is greater than the maximum collector current of the second transistor T2 .

[0093] See also Figure 2 The second semiconductor portion 32 includes a source contact portion 321, a drain contact portion 322 and a channel portion 323, and the channel portion 323 is connected between the source contact portion 321 and the drain contact portion 322. Along the direction from the first conductor portion 21 to the second conductor portion 22, the width of the channel portion 323 is greater than the width of the third sub-semiconductor portion 313. The second transistor T2 is a conventional transistor, not a submicron ultra-short channel transistor. The maximum collector current is the maximum current that a transistor can pass, which is used to measure the large current passing capacity of the transistor. The large current passing capacity of the first transistor T1 is better than the large current passing capacity of the second transistor T2.

[0094] In some embodiments, the second transistor T2 further includes a second gate 42 , a second source 53 and a second drain 54 , the second gate 42 is disposed on the gate layer 4 ; and / or the second source 53 and the second drain 54 are disposed on the source-drain layer 5 .

[0095] In some embodiments, see Figure 2 The first gate 41 and the second gate 42 are arranged on the gate layer 4, the first gate 41 and the second gate 42 are arranged in the same layer, the first gate 41 and the second gate 42 are made of the same material, and the first gate 41 and the second gate 42 can be simultaneously prepared through the process of the gate layer 4, so that the size of the first transistor T1 can be reduced, and the current conduction capability and stability of the first transistor T1 can be improved, while simplifying the film layer structure of the array substrate, reducing the number of process steps and masks, thereby reducing the production cost.

[0096] In some embodiments, the material of the gate layer 4 is selected from at least one of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the gate layer 4 may be a single-layer metal structure formed by metal materials such as molybdenum, copper, aluminum, and titanium, or a stacked structure formed by at least two of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the gate layer 4 may be any stacked structure of copper / aluminum, molybdenum / copper, molybdenum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, titanium / aluminum / titanium, titanium / copper / titanium, molybdenum / copper / indium zinc oxide, indium zinc oxide / copper / indium zinc oxide, and molybdenum / copper / indium tin oxide.

[0097] In some other embodiments, the first gate 41 and the second gate 42 may also be arranged in different layers. For example, the gate layer 4 includes a first gate, and the array substrate 100 also includes a second gate layer. The second gate layer can be arranged on a side of the gate layer 4 close to or away from the substrate 1, and the second gate layer includes the second gate 42. In this way, the technical effect of improving the current conduction capability and stability of the first transistor T1 can also be achieved.

[0098] In some embodiments, see Figure 2 The first source 51, the first drain 52, the second source 53 and the second drain 54 are arranged in the source-drain layer 5, and the first source 51, the first drain 52, the second source 53 and the second drain 54 are arranged in the same layer. The materials of the first source 51, the first drain 52, the second source 53 and the second drain 54 are the same. The first source 51, the first drain 52, the second source 53 and the second drain 54 can be simultaneously prepared through the process of the source-drain layer 5. In this way, the size of the first transistor T1 can be reduced, and the current conduction capability and stability of the first transistor T1 can be improved, while simplifying the film structure of the array substrate, reducing the number of process steps and masks, and thus reducing the production cost.

[0099] In some embodiments, the material of the source-drain electrode layer 5 is selected from at least one of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the source-drain electrode layer 5 may be a single-layer metal structure formed by metal materials such as molybdenum, copper, aluminum, and titanium, and the source-drain electrode layer 5 may also be a stacked structure formed by at least two of molybdenum, aluminum, titanium, copper, indium tin oxide, and indium zinc oxide. For example, the source-drain electrode layer 5 may be any stacked structure of copper / aluminum, molybdenum / copper, molybdenum / titanium, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, titanium / aluminum / titanium, titanium / copper / titanium, molybdenum / copper / indium zinc oxide, indium zinc oxide / copper / indium zinc oxide, and molybdenum / copper / indium tin oxide.

[0100] In some other embodiments, the first source electrode 51 and the first drain electrode 52 are arranged in the source-drain electrode layer 5, and the array substrate 100 also includes a second source-drain electrode layer, and the second source-drain electrode layer includes a second source electrode 53 and a second drain electrode 54. The second source-drain electrode layer can be arranged on the side of the source-drain electrode layer 5 close to or away from the substrate 1. In this way, the technical effect of improving the current conduction capability and stability of the first transistor T1 can also be achieved.

[0101] In some embodiments, see Figure 2 The light shielding layer 6 includes a first light shielding portion 61 and a second light shielding portion 62 . The first light shielding portion 61 and the second light shielding portion 62 are arranged at intervals. The first source electrode 51 is connected to the first light shielding portion 61 . The second source electrode 53 is connected to the second light shielding portion 62 .

[0102] In some embodiments, see Figure 1 The array substrate 100 includes a display area AA and a non-display area NA disposed around the display area AA. The first transistor T1 is at least disposed in the non-display area NA, and the second transistor T2 is at least disposed in the display area AA.

[0103] In the present embodiment, the non-display area NA is provided with a driving circuit that is required to have a large current passing capability. In addition to the above-mentioned driving circuit, the non-display area may also be integrated with system functional elements, and the above-mentioned circuits and system functional elements have high requirements on the size of transistors and the large current passing capability. In the present embodiment, by arranging the first transistor T1 in the non-display area NA, not only the performance of the driving circuit and the system functional elements of the non-display area NA can be improved, but also the occupied area of ​​the driving circuit and the system functional elements of the non-display area NA can be reduced, so that the width of the non-display area NA can be reduced, thereby improving the screen-to-body ratio of the display panel to which the array substrate is applicable. In the present embodiment, by arranging the second transistor T2 in the display area AA, the display area AA is provided with a pixel driving circuit, and the pixel driving circuit includes the second transistor T2, and the second transistor T2 has high stability, which can ensure the stability of the display effect of the display area AA.

[0104] In some embodiments, see Figure 1 and Figure 2 The array substrate 100 includes a gate driving circuit 101. The gate driving circuit 101 is disposed in the non-display area NA. The gate driving circuit 101 includes a first transistor T1.

[0105] In some embodiments, the gate driving circuit 101 may include multiple transistors, at least one of the multiple transistors is a first transistor T1, and the multiple transistors may all be first transistors T1, so that the occupied area of ​​the gate driving circuit 101 can be reduced, thereby improving the performance of the gate driving circuit while improving the screen-to-body ratio of the display panel to which the array substrate is applicable. The circuit structure of the gate driving circuit 101 can be replaced with the circuit structure of the gate driving circuit in the known array substrate to achieve the same or similar function.

[0106] In some embodiments, see Figure 1 and Figure 2 The array substrate 100 includes a demultiplexer circuit 102 . The demultiplexer circuit 102 is disposed in the non-display area NA. The demultiplexer circuit 102 includes a first transistor T1 .

[0107] In some embodiments, the demultiplexer circuit 102 may include multiple transistors, at least one of the multiple transistors is a first transistor T1, and the multiple transistors may all be first transistors T1, so that the occupied area of ​​the demultiplexer circuit 102 can be reduced, thereby improving the performance of the demultiplexer circuit 102 while improving the screen-to-body ratio of the display panel to which the array substrate is applicable. The circuit structure of the demultiplexer circuit 102 can be replaced with the circuit structure of the demultiplexer circuit 102 in a known array substrate to achieve the same or similar function.

[0108] In some embodiments, see Figure 1 and Figure 2 The array substrate 100 includes a plurality of pixel driving circuits 103, and the pixel driving circuit 103 is disposed in the display area AA. The pixel driving circuit includes a second transistor T2, and the second transistor T2 has high stability, which can ensure the stability of the display effect of the display area AA.

[0109] In some embodiments, the display area AA and the non-display area NA are both provided with a first transistor T1. By replacing at least part of the transistors in the display area AA with the first transistor T1, the occupied area of ​​the circuit in the display area AA can be reduced to free up more space for placing sub-pixels. In this way, the pixel density per unit area in the display area AA can be increased, thereby improving the resolution of the display panel to which the array substrate is applicable.

[0110] In some embodiments, see Figure 1 and Figure 2The array substrate 100 includes a plurality of pixel driving circuits 103, and the pixel driving circuits 103 are arranged in the display area AA. The pixel driving circuits include a first transistor T1 and a second transistor T2. The first transistor T1 is used to replace some transistors in the pixel driving circuit, so that the occupied area of ​​the circuit in the display area AA can be reduced to free up more space for placing sub-pixels, so that the pixel density per unit area in the display area AA can be increased, thereby improving the resolution of the display panel to which the array substrate is applicable.

[0111] In some embodiments, the driving transistor in the pixel driving circuit can adopt the first transistor T1, and the other transistors in the pixel driving circuit can adopt the second transistor T2. In this way, the driving capability of the pixel driving circuit can be improved while ensuring the stability of the pixel driving circuit, thereby improving the display effect of the array substrate.

[0112] In some embodiments, see Figure 2 The array substrate 100 further includes a passivation layer 10 and a pixel electrode layer 11 . The passivation layer 10 is disposed on the source / drain electrode layer 5 and the interlayer dielectric layer 9 , and the pixel electrode layer 11 is disposed on the passivation layer 10 .

[0113] In some embodiments, the material of the passivation layer 10 is selected from at least one of silicon nitride, silicon oxide, silicon oxynitride and aluminum oxide. For example, the passivation layer 10 may be a single-layer structure formed by silicon oxide material, or the passivation layer 10 may be a laminated structure formed by aluminum oxide, silicon nitride and silicon oxide stacked in sequence, or the passivation layer 10 may be a laminated structure formed by silicon oxide, silicon nitride and silicon oxide stacked in sequence.

[0114] In some embodiments, the material of the pixel electrode layer 11 is selected from at least one of a metal and a transparent metal oxide, wherein the metal material may be at least one of copper, molybdenum, silver and titanium, and the transparent metal oxide may be at least one of indium tin oxide and indium zinc oxide. For example, the pixel electrode layer 11 may be a single-layer transparent conductive structure of indium tin oxide or indium zinc oxide, and the pixel electrode layer 11 may also be any one of a stacked structure of indium tin oxide / silver / indium tin oxide, indium zinc oxide / silver / indium zinc oxide, molybdenum / copper, molybdenum-titanium alloy / copper / molybdenum-titanium alloy, etc.

[0115] According to the array substrate provided in the above embodiments of the present application, the embodiments of the present application further provide a method for manufacturing an array substrate, which is used to manufacture an array substrate provided in any of the above embodiments, Figure 3a to Figure 3h As shown, Figure 3a to Figure 3h A schematic diagram of a method for manufacturing an array substrate provided in an embodiment of the present application, the method for manufacturing the array substrate comprising:

[0116] Step S1 , forming a layer of light-shielding material on a substrate 1 , and patterning the light-shielding material to form a light-shielding layer 6 .

[0117] like Figure 3a As shown, the light shielding layer 6 includes a first light shielding portion 61 and a second light shielding portion 62 , and the first light shielding portion 61 and the second light shielding portion 62 are arranged at intervals.

[0118] Step S2 , forming a buffer layer 7 on the substrate 1 , wherein the buffer layer 7 covers the light shielding layer 6 ; forming a layer of conductive material on the light shielding layer 6 , and patterning the conductive material to form a conductive layer 2 .

[0119] like Figure 3b As shown, the conductor layer 2 includes a first conductor portion 21 and a second conductor portion 22 , and the first conductor portion 21 and the second conductor portion 22 are arranged at an interval.

[0120] Step S3 , forming a layer of semiconductor material on the buffer layer 7 and the conductor layer 2 , and patterning the semiconductor material to form a semiconductor layer 3 .

[0121] like Figure 3c As shown, the semiconductor layer 3 includes a first semiconductor portion 31 and a second semiconductor portion 32, the first semiconductor portion 31 and the second semiconductor portion 32 are arranged at intervals, the first semiconductor portion 31 is arranged on the first conductor portion 21 and the second conductor portion 22, and fills the gap between the first conductor portion 21 and the second conductor portion 22. The second semiconductor portion 32 is arranged on the buffer layer 7.

[0122] Step S4 , forming a gate insulating layer 8 on the semiconductor layer 3 , forming a gate material on the gate insulating layer 8 , and patterning the gate material to form a gate layer 4 .

[0123] like Figure 3d As shown, the gate layer 4 includes a first gate 41 and a second gate 42 . In the film thickness direction of the gate layer 4 , the first gate 41 is aligned with the first semiconductor portion 31 , and the second gate 42 is aligned with the second semiconductor portion 32 .

[0124] Step S5 , forming an interlayer dielectric layer 9 on the gate layer 4 , and patterning the interlayer dielectric layer 9 to form a plurality of vias.

[0125] like Figure 3e As shown, the plurality of via holes include a first via hole V1 and a second via hole V2 . The first via hole V1 exposes the first conductor portion 21 , and the second via hole V2 exposes the second conductor portion 22 .

[0126] Step S6 , depositing source and drain electrode materials on the interlayer dielectric layer 9 , and patterning the source and drain electrode materials to form a source and drain electrode layer 5 .

[0127] like Figure 3fAs shown, the source-drain layer 5 includes a first source 51, a first drain 52, a second source 53 and a second drain 54. The first source 51 is directly overlapped with the first conductor portion 21 through a first via hole V1, the first drain 52 is directly overlapped with the second conductor portion 22 through a second via hole V2, the second source 53 is directly overlapped with the source contact portion 321, and the second drain 54 is directly overlapped with the drain contact portion 322.

[0128] Step S7: Figure 3g As shown, a passivation material is formed on the source-drain electrode layer 5 , and the passivation material is patterned to form a passivation layer 10 .

[0129] Step S8: Figure 3h As shown, a pixel electrode material is formed on the passivation layer 10 , and the pixel electrode material is patterned to form a pixel electrode layer 11 .

[0130] In some embodiments, see Figure 4 , Figure 4 A structural schematic diagram of a display panel provided for an embodiment of the present application, wherein the display panel provided for an embodiment of the present application is a liquid crystal display panel, wherein the display panel 1000 includes an array substrate 100, an opposing substrate 200 and a liquid crystal layer 300, wherein the array substrate 100 and the opposing substrate 200 are arranged opposite to each other, and the liquid crystal layer 300 is arranged between the array substrate 100 and the opposing substrate 200, and the opposing substrate 200 may be a color film substrate, and the array substrate 100 may be an array substrate provided by any one of the above-mentioned embodiments.

[0131] In some other embodiments, the type of the display panel 1000 is not limited to the liquid crystal display panel in the above embodiments. The display panel 1000 can also be any one of an organic light emitting diode display panel, a mini light emitting diode display panel and a micro light emitting diode display panel.

[0132] The display panel 1000 provided in the embodiment of the present application can achieve the same technical effect as the array substrate provided in any one of the above embodiments, which will not be described in detail here.

[0133] According to the array substrate provided in the above embodiment of the present application, the embodiment of the present application further provides a display device, see Figure 5 , Figure 5 The structural schematic diagram of the display device provided in the embodiment of the present application, the display device 10000 includes a display panel 1000 and a housing 2000, and the display panel 1000 is arranged on the housing 2000. The display panel 1000 can be the display panel provided in any of the above embodiments. The display device provided in the embodiment of the present application can achieve the same technical effect as the display panel provided in any of the above embodiments, which will not be described in detail here.

[0134] Beneficial effects of the embodiments of the present application: The present application provides an array substrate, a display panel and a display device, wherein the array substrate includes a first transistor, the first transistor includes a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source and a first drain, by arranging the first conductor portion and the second conductor portion at intervals, and connecting the first semiconductor portion at least between the first conductor portion and the second conductor portion, one end of the first semiconductor portion is retracted to an end of the first conductor portion away from the second conductor portion, the other end of the first semiconductor portion is retracted to an end of the second conductor portion away from the first conductor portion, the first source is directly overlapped with the first conductor portion, the first drain is directly overlapped with the second conductor portion, and the portion of the first semiconductor portion between the first conductor portion and the second conductor portion is a channel, thereby not only reducing the size of the first transistor but also improving the stability of the first transistor.

[0135] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0136] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0138] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate further comprises: a first transistor, wherein the first transistor comprises a first conductor portion, a second conductor portion, a first semiconductor portion, a first gate, a first source electrode, and a first drain electrode; and substrate; A conductor layer is arranged on the substrate, the conductor layer comprises the first conductor part and the second conductor part, the first conductor part and the second conductor part are arranged at intervals; A semiconductor layer, disposed on the substrate, the semiconductor layer comprising the first semiconductor portion, the first semiconductor portion being at least connected between the first conductor portion and the second conductor portion; a gate layer, disposed on a side of the semiconductor layer away from the substrate, the gate layer comprising the first gate; and A source-drain electrode layer, disposed on a side of the semiconductor layer away from the substrate, the source-drain electrode layer comprising the first source electrode and the first drain electrode; Among them, one end of the first semiconductor part is retracted into an end of the first conductor part away from the second conductor part, the other end of the first semiconductor part is retracted into an end of the second conductor part away from the first conductor part, the first source is overlapped with the first conductor part, and the first drain is overlapped with the second conductor part.

2. The array substrate according to claim 1, characterized in that: Along the direction from the first conductor portion to the second conductor portion, a distance between the first conductor portion and the second conductor portion is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

3. The array substrate according to claim 1, characterized in that: The first semiconductor portion includes: A first sub-semiconductor portion is disposed on a surface of the first conductor portion away from the substrate; A second sub-semiconductor portion is disposed on a surface of the second conductor portion away from the substrate; and a third sub-semiconductor portion connected between the first sub-semiconductor portion and the second sub-semiconductor portion, and the third sub-semiconductor portion is disposed between the first conductor portion and the second conductor portion; The orthographic projection of the first sub-semiconductor portion on the first conductor portion is located in the first conductor portion, and the orthographic projection of the second sub-semiconductor portion on the second conductor portion is located in the second conductor portion.

4. The array substrate according to claim 3, characterized in that: Along the direction from the first conductor portion to the second conductor portion, the width of the first sub-semiconductor portion is smaller than the width of the first conductor portion, and the width of the second sub-semiconductor portion is smaller than the width of the second conductor portion.

5. The array substrate according to claim 4, characterized in that: Along the direction from the first conductor portion to the second conductor portion, the difference between the width of the first conductor portion and the width of the first sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers; A difference between the widths of the second conductor portion and the second sub-semiconductor portion is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

6. The array substrate according to claim 1, characterized in that: An orthographic projection of the first gate on the substrate covers an orthographic projection of the first semiconductor portion on the substrate.

7. The array substrate according to claim 1, wherein: Along a direction from the first conductor portion to the second conductor portion, a width of the first semiconductor portion is smaller than a width of the first gate.

8. The array substrate according to claim 1, wherein: The array substrate further includes: A gate insulating layer, disposed between the semiconductor layer and the gate layer, the gate insulating layer covering the semiconductor layer and the conductor layer; An interlayer dielectric layer, disposed between the gate layer and the source and drain layer; Among them, the array substrate includes a first via hole and a second via hole, the first via hole penetrates the interlayer dielectric layer and the gate insulation layer, and the first source electrode is overlapped with the first conductor part through the first via hole; the second via hole penetrates the interlayer dielectric layer and the gate insulation layer, and the first drain electrode is overlapped with the second conductor part through the second via hole.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The array substrate further includes a second transistor, wherein the second transistor includes a second semiconductor portion; The semiconductor layer includes the second semiconductor portion, and a maximum collector current of the first transistor is greater than a maximum collector current of the second transistor.

10. The array substrate according to claim 9, characterized in that: The second transistor further includes a second gate, a second source and a second drain; Wherein, the gate layer includes the second gate; and / or the source-drain layer includes the second source and the second drain.

11. The array substrate according to claim 9, characterized in that: The array substrate includes a display area and a non-display area surrounding the display area. The first transistor is at least arranged in the non-display area, and the second transistor is at least arranged in the display area.

12. The array substrate according to claim 1, wherein: The material of the semiconductor layer is selected from one of a silicon semiconductor material and an oxide semiconductor material.

13. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 12.

14. A display device, characterized in that: Comprising the display panel as claimed in claim 13.

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