Array substrate, manufacturing method and display device

Abstract

The invention provides an array substrate, a manufacturing method and a display device, and the array substrate comprises a substrate which comprises a plurality of pixel circuits; the pixel circuit comprises a driving transistor and a first capacitor. A grid electrode of the driving transistor is electrically connected with a first pole plate of the first capacitor through a first switching part, a first pole of the driving transistor is electrically connected with the first node, and a second pole of the driving transistor is electrically connected with a second pole plate of the first capacitor through a second switching part; the first switching part, the grid electrode of the driving transistor and the second switching part are arranged on the same layer. The first switching part, the grid electrode of the driving transistor and the second switching part are arranged on the same layer, so that the utilization rate of the layer can be greatly improved, the number of times of the composition process can be reduced, the process cost is reduced, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a manufacturing method and a display device. Background Art

[0002] Light-emitting devices such as organic light emitting diodes (OLED), quantum dot light emitting diodes (QLED), micro light emitting diodes (Micro LED), and mini light emitting diodes (Mini LED) have the advantages of self-luminescence and low energy consumption, and are one of the hot topics in the current research field of display device applications. In general display devices, pixel circuits are used to drive light-emitting devices to emit light. Summary of the invention

[0003] The array substrate provided by the embodiment of the present disclosure includes: a base substrate including a plurality of pixel circuits;

[0004] The pixel circuit comprises: a driving transistor and a first capacitor; the gate of the driving transistor is electrically connected to the first plate of the first capacitor through a first switching portion, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second plate of the first capacitor through a second switching portion;

[0005] The first transfer portion, the gate of the driving transistor and the second transfer portion are arranged on the same layer.

[0006] In some possible implementations, the first transfer portion, the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor overlap with each other in their orthographic projections on the base substrate.

[0007] In some possible implementations, the second transfer portion, the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor overlap each other in orthographic projection on the base substrate.

[0008] In some possible implementations, an orthographic projection of the second transfer portion on the base substrate does not overlap with an orthographic projection of the first transfer portion and the gate of the driving transistor on the base substrate.

[0009] In some possible implementations, the pixel circuit further includes: a second capacitor;

[0010] The first electrode plate of the second capacitor is electrically connected to the first power signal line, and the second electrode plate of the second capacitor is electrically connected to the second electrode plate of the first capacitor through the second adapter;

[0011] The second transition portion and the first transition portion are located at the same layer.

[0012] In some possible implementations, the first electrode plate of the second capacitor, the first electrode plate of the first capacitor, and the first power signal line are located on the same layer;

[0013] The second plate of the second capacitor and the second plate of the first capacitor are located in the same layer.

[0014] In some possible implementations, an orthographic projection of the second transition portion on the base substrate overlaps with an orthographic projection of the first electrode plate of the second capacitor and an orthographic projection of the second electrode plate of the second capacitor on the base substrate.

[0015] In some possible implementations, the first plate of the second capacitor, the second plate of the second capacitor, and the gate of the driving transistor overlap each other in their orthographic projections on the substrate.

[0016] In some possible implementations, the pixel circuit further includes: a first transistor;

[0017] The gate of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initialization signal line through the third switching portion, and the second electrode of the first transistor is electrically connected to the gate of the driving transistor through the first switching portion;

[0018] The third transfer portion, the first reset signal line, and the first transfer portion are located in the same layer.

[0019] In some possible implementations, an orthographic projection of the third transition portion on the base substrate overlaps with an orthographic projection of the first initialization signal line on the base substrate.

[0020] In some possible implementations, the first initialization signal line and the first power signal line are located in the same layer.

[0021] In some possible implementations, the first capacitor further includes a third plate; the second electrode of the first transistor is reused as the third plate of the first capacitor, and the third plate is electrically connected to the first plate of the first capacitor through the first adapter.

[0022] In some possible implementations, the pixel circuit further includes: a second transistor;

[0023] The gate of the second transistor is electrically connected to the first scanning signal line, the first electrode of the second transistor is electrically connected to the gate of the driving transistor through the first switching portion, and the second electrode of the second transistor is electrically connected to the data signal line;

[0024] The first scanning signal line and the first switching portion are located in the same layer, and the first scanning signal line and the data signal line are located in different layers.

[0025] In some possible implementations, the pixel circuit further includes: a third transistor;

[0026] The gate of the third transistor is electrically connected to the first light emitting control signal line, the first electrode of the third transistor is electrically connected to the first power signal line through the fourth switching portion, and the second electrode of the third transistor is electrically connected to the first node;

[0027] The first transfer portion, the fourth transfer portion and the first light-emitting control signal line are located in the same layer.

[0028] In some possible implementations, an orthographic projection of the fourth transition portion on the base substrate overlaps with an orthographic projection of the first power signal line on the base substrate.

[0029] In some possible implementations, the pixel circuit further includes: a fourth transistor;

[0030] The gate of the fourth transistor is electrically connected to the second light emitting control signal line, the first electrode of the fourth transistor is electrically connected to the second electrode plate of the first capacitor through the fifth adapter, and the second electrode of the fourth transistor is electrically connected to the second node;

[0031] The first transfer portion, the fifth transfer portion and the second light-emitting control signal line are located in the same layer.

[0032] In some possible implementations, the orthographic projection of the fifth transfer portion on the base substrate is located between the orthographic projections of the first reset signal line and the first initialization signal line on the base substrate.

[0033] In some possible implementations, the pixel circuit further includes: a fifth transistor;

[0034] The gate of the fifth transistor is electrically connected to the second reset signal line, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the second initialization signal line through the sixth switching portion;

[0035] The fifth transfer portion, the sixth transfer portion and the second reset signal line are located in the same layer.

[0036] In some possible implementations, an orthographic projection of the sixth transition portion on the base substrate overlaps with an orthographic projection of the second initialization signal line on the base substrate.

[0037] In some possible implementations, the second initialization signal line and the second plate of the first capacitor are located in the same layer.

[0038] In some possible implementations, the first power signal line, the first light emitting control signal line, the first scan signal line, the first reset signal line, the first initialization signal line, the second light emitting control signal line, the second reset signal line, and the second initialization signal line all extend along a first direction;

[0039] The first power signal line, the first light emitting control signal line, the first scanning signal line, the first reset signal line, the first initialization signal line, the second light emitting control signal line, the second reset signal line and the second initialization signal line are sequentially arranged in a spaced relationship along a second direction;

[0040] The first direction and the second direction are arranged to intersect each other.

[0041] The display device provided by the embodiment of the present disclosure includes the above-mentioned array substrate.

[0042] The method for manufacturing the array substrate provided in the embodiment of the present disclosure includes:

[0043] Sequentially forming a first conductive layer, a second conductive layer, a semiconductor layer and a third conductive layer on the base substrate to form a pixel circuit on the base substrate;

[0044] Among them, the first conductive layer includes the first plate of the first capacitor; the second conductive layer includes the second plate of the first capacitor; the semiconductor layer includes the active layer of the driving transistor; and the third conductive layer includes the gate of the driving transistor, the first transition portion and the second transition portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Some structural schematic diagrams of array substrates in related technologies;

[0046] Figure 2 are other structural schematic diagrams of array substrates in related technologies;

[0047] Figure 3 Some structural schematic diagrams of array substrates provided in embodiments of the present disclosure;

[0048] Figure 4 Some other structural schematic diagrams of array substrates provided by embodiments of the present disclosure;

[0049] Figure 5 Some structural schematic diagrams of pixel circuits provided by embodiments of the present disclosure;

[0050] Figure 6 Some schematic diagrams of layout structures of pixel circuits provided in embodiments of the present disclosure;

[0051] Figure 7 Some other schematic diagrams of the layout structures of pixel circuits provided by the embodiments of the present disclosure;

[0052] Figure 8 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0053] Fig. 9 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0054] Fig.10 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0055] Fig.11 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0056] Fig.12 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0057] Fig.13 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0058] Fig.14 Some further layout structure schematic diagrams of pixel circuits provided in the embodiments of the present disclosure;

[0059] Fig.15 Some other structural schematic diagrams of pixel circuits provided in embodiments of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0061] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0062] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0063] In the related art, the specific process flow of patterning process and etching process required on the array substrate is shown in Table 1 below.

[0064] Gate1 Gate2 IGZO Gate3 ILD-L ILD-O SD1 PVX PLN1 SD2 PLN2 T-Mask Anode HPDL

[0065] Table 1

[0066] In related technologies, such as Figure 1As shown in Table 1, the manufacturing method of the array substrate generally includes: forming a first insulating layer 101 on a base substrate 100, forming a first conductive layer 102 (for example, Gate 1 in Table 1) on a side of the first insulating layer 101 facing away from the base substrate 100, forming a second insulating layer 103 on a side of the first conductive layer 102 (for example, Gate 1 in Table 1) facing away from the base substrate 100, forming a second conductive layer 104 (for example, Gate 2 in Table 1) on a side of the second insulating layer 103 facing away from the base substrate 100, forming a third insulating layer 105 on a side of the second conductive layer 104 (for example, Gate 2 in Table 1) facing away from the base substrate 100, and forming a semiconductor layer 106 on a side of the third insulating layer 105 facing away from the base substrate 100. 06 (for example, IGZO in Table 1), a fourth insulating layer 107 is formed on the side of the semiconductor layer 106 (for example, IGZO in Table 1) away from the substrate 100, a third conductive layer 108 (for example, Gate3 in Table 1) is formed on the side of the fourth insulating layer 107 away from the substrate 100, a fifth insulating layer 109 is formed on the side of the third conductive layer 108 (for example, Gate3 in Table 1) away from the substrate 100, and after the fifth insulating layer 109 is formed, a first via layer (for example, ILD-L in Table 1) and a second via layer (for example, ILD-O in Table 1) are sequentially formed according to design requirements, so that the third conductive layer 108 can be connected to the first conductive layer 108 through the first via layer (for example, ILD-L in Table 1). 2 or the second conductive layer 104 is electrically connected, the third conductive layer 108 can be electrically connected to the semiconductor layer 106 through a second via layer (for example, ILD-O in Table 1), a fourth conductive layer 110 (for example, SD1 in Table 1) is formed on a side of the fifth insulating layer 109 away from the substrate 100, and a sixth insulating layer 110 is formed on a side of the fourth conductive layer 110 (for example, SD1 in Table 1) away from the substrate 100; in the subsequent manufacturing method, exemplarily, it also includes: forming a passivation layer (for example, PVX in Table 1) on a side of the sixth insulating layer 110 away from the substrate 100, forming a first planarization layer (for example, PLN1 in Table 1) on a side of the passivation layer (for example, PVX in Table 1) away from the substrate 100, and forming a first planarization layer (for example, PLN1 in Table 1) on the first A fifth conductive layer (e.g., SD2 in Table 1) is formed on the side of the planarization layer (e.g., PLN1 in Table 1) facing away from the substrate 100, a second planarization layer (e.g., PLN2 in Table 1) is formed on the side of the fifth conductive layer (e.g., SD2 in Table 1) facing away from the substrate 100, a mask layer (e.g., T-Mask in Table 1) is formed on the side of the second planarization layer (e.g., PLN2 in Table 1) facing away from the substrate 100, an anode layer (e.g., Anode in Table 1) is formed on the side of the mask layer (e.g., T-Mask in Table 1) facing away from the substrate 100, and a pixel definition layer (e.g., HPDL in Table 1) is formed on the side of the anode layer (e.g., Anode in Table 1) facing away from the substrate 100.

[0067] It should be noted that if Figure 1 As shown in Table 1, a first conductive layer 102 (e.g., Gate1 in Table 1), a second conductive layer 104 (e.g., Gate2 in Table 1), a semiconductor layer 106 (e.g., IGZO in Table 1), a third conductive layer 108 (e.g., Gate3 in Table 1), a fourth conductive layer 110 (e.g., SD1 in Table 1), a passivation layer (e.g., PVX in Table 1), a first planarization layer (e.g., PLN1 in Table 1), a fifth conductive layer (e.g., SD2 in Table 1), a second planarization layer (e.g., PLN2 in Table 1), a mask layer (e.g., T-Mask in Table 1), an anode layer (e.g., Anode in Table 1), and a pixel definition layer (e.g., HPDL in Table 1) can be formed by a patterning process; and a first via layer (e.g., ILD-L in Table 1) and a second via layer (e.g., ILD-O in Table 1) can be formed by an etching process. For example, the patterning process may include only the photolithography process, or may include the photolithography process and the etching step, and may also include other processes such as printing and inkjetting for forming a predetermined pattern; the photolithography process refers to a process for forming a pattern using a photoresist, a mask, an exposure machine, etc., including the process of film formation, exposure, and development. In specific implementation, the corresponding patterning process may be selected according to the structure formed in the present invention.

[0068] For example, the array substrate in the related art generally needs to adopt 12 layers of patterning process and 2 layers of etching process. It can be seen that the array substrate manufacturing process is relatively complex and cumbersome, which is not conducive to production efficiency and production cost.

[0069] In addition, the array substrate in the related art has a large number of film layers, which results in a thick array substrate, which is not conducive to the realization of thinness. Therefore, the thickness of the array substrate is reduced by reducing the thickness of the third insulating layer 105 in the related art, such as Figure 1 and Figure 2 As shown, Figure 1 The thickness of the three insulating layers 105 is about 4000A. Figure 2 The thickness of the third insulating layer 105 is about 2500 Å, but even if the thickness of the third insulating layer 105 is reduced, the thinning effect of the entire array substrate is not obvious, that is, the thinning effect is small.

[0070] Based on the above problems, an embodiment of the present disclosure provides a method for manufacturing an array substrate. The specific process flow of the patterning process and the etching process required on the array substrate is shown in Table 2 or Table 3 below.

[0071] For example, the method for manufacturing the array substrate provided by the embodiment of the present disclosure may be flexibly changed and adjusted according to the design requirements of the pixel circuit.

[0072]

[0073]

[0074] Table 2

[0075] Gate2 IGZO ILD-1 Gate3 ILD-2 SD1 PLN1 Anode A-PDL HPDL

[0076] Table 3

[0077] like Figure 3As shown in Table 2, the manufacturing method of the array substrate in the embodiment of the present disclosure includes: forming a first insulating layer 101 on a base substrate 100, forming a first conductive layer 102 (for example, Gate1 in Table 2) on a side of the first conductive layer 101 facing away from the base substrate 100, forming a second insulating layer 103 on a side of the first conductive layer 102 (for example, Gate1 in Table 2) facing away from the base substrate 100, forming a second conductive layer 104 (for example, Gate2 in Table 2) on a side of the second conductive layer 103 facing away from the base substrate 100, forming a third insulating layer 105 on a side of the second conductive layer 104 (for example, Gate2 in Table 2) facing away from the base substrate 100, and A semiconductor layer 106 (for example, IGZO in Table 2) is formed on the side of the third insulating layer 105 facing away from the base substrate 100, a fourth insulating layer 107 is formed on the side of the semiconductor layer 106 (for example, IGZO in Table 2) facing away from the base substrate 100, and after the fourth insulating layer 107 is formed, a first via layer (for example, ILD-1 in Table 2) is formed according to design requirements, and a third conductive layer 108 (for example, Gate3 in Table 2) is formed on the side of the fourth insulating layer 107 facing away from the base substrate 100. Then, the third conductive layer 108 (for example, Gate3 in Table 2) can be connected to the first conductive layer 102 and the second conductive layer 102 through the first via layer (for example, ILD-1 in Table 2). 04 or the semiconductor layer 106 is electrically connected, a fifth insulating layer 109 is formed on the side of the third conductive layer 108 (for example, Gate3 in Table 2) away from the substrate 100, and a second via layer (for example, ILD2 in Table 2) is formed according to design requirements after the fifth insulating layer 109 is formed, and a fourth conductive layer 110 (for example, SD1 in Table 2) is formed on the side of the fifth insulating layer 109 away from the substrate 100, then the fourth conductive layer 110 (for example, SD1 in Table 2) can be electrically connected to the third conductive layer 108 (for example, Gate3 in Table 2) through the second via layer (for example, ILD2 in Table 2), and a second via layer (for example, ILD2 in Table 2) is formed on the side of the fourth conductive layer 110 (for example, SD1 in Table 2) away from the substrate 100. A sixth insulating layer 110 is formed on the side away from the base substrate 100; in the subsequent manufacturing method, exemplarily, it also includes: forming a first planarization layer (for example, PLN1 in Table 2) on the side of the sixth insulating layer 110 away from the base substrate 100, forming an anode layer (for example, Anode in Table 2) on the side of the first planarization layer (for example, PLN1 in Table 2) away from the base substrate 100, forming a blocking layer (for example, A-PDL in Table 2) on the side of the anode layer (for example, Anode in Table 2) away from the base substrate 100, and forming a pixel definition layer (for example, HPDL in Table 2) on the side of the blocking layer (for example, A-PDL in Table 2) away from the base substrate 100.

[0078] It should be noted that if Figure 3As shown in Table 2, a first conductive layer 102 (e.g., Gate1 in Table 2), a second conductive layer 104 (e.g., Gate2 in Table 2), a semiconductor layer 106 (e.g., IGZO in Table 2), a third conductive layer 108 (e.g., Gate3 in Table 2), a fourth conductive layer 110 (e.g., SD1 in Table 2), a first planarization layer (e.g., PLN1 in Table 2), an anode layer (e.g., Anode in Table 2), a barrier layer (e.g., A-PDL in Table 2), and a pixel definition layer (e.g., HPDL in Table 2) may be formed by a patterning process; and a first via layer (e.g., ILD-1 in Table 2) and a second via layer (e.g., ILD-2 in Table 2) may be formed by an etching process. For example, the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes such as printing and inkjetting for forming a predetermined pattern; a photolithography process refers to a process for forming a pattern using a photoresist, a mask, an exposure machine, etc., including processes such as film formation, exposure, and development. During specific implementation, a corresponding patterning process may be selected according to the structure formed in the present invention.

[0079] like Figure 4As shown in Table 3, the manufacturing method of the array substrate in the embodiment of the present disclosure may include: forming a second insulating layer 103 on a base substrate 100, forming a second conductive layer 104 (for example, Gate2 in Table 2) on a side of the second insulating layer 103 facing away from the base substrate 100, forming a third insulating layer 105 on a side of the second conductive layer 104 (for example, Gate2 in Table 2) facing away from the base substrate 100, forming a semiconductor layer 106 (for example, IGZO in Table 2) on a side of the third insulating layer 105 facing away from the base substrate 100, and forming a semiconductor layer 106 (for example, IGZO in Table 2) on a side of the semiconductor layer 106 (for example, IGZO in Table 2) facing away from the base substrate 100. A fourth insulating layer 107 is formed on one side of the substrate 100, and a first via layer (e.g., ILD-1 in Table 2) is formed according to design requirements after the fourth insulating layer 107 is formed, and a third conductive layer 108 (e.g., Gate3 in Table 2) is formed on the side of the fourth insulating layer 107 away from the substrate 100. Then, the third conductive layer 108 (e.g., Gate3 in Table 2) can be electrically connected to the first conductive layer 102, the second conductive layer 104, or the semiconductor layer 106 through the first via layer (e.g., ILD-1 in Table 2), and the third conductive layer 108 (e.g., Gate3 in Table 2) is away from the substrate 100. 0, a fifth insulating layer 109 is formed on a side of the substrate 100, a second via layer (e.g., ILD2 in Table 2) is formed according to design requirements after the fifth insulating layer 109 is formed, a fourth conductive layer 110 (e.g., SD1 in Table 2) is formed on a side of the fifth insulating layer 109 away from the substrate 100, then the fourth conductive layer 110 (e.g., SD1 in Table 2) can be electrically connected to the third conductive layer 108 (e.g., Gate3 in Table 2) through the second via layer (e.g., ILD2 in Table 2), and a sixth insulating layer 110 is formed on a side of the fourth conductive layer 110 (e.g., SD1 in Table 2) away from the substrate 100; In the subsequent manufacturing method, exemplary, it also includes: forming a first planarization layer (for example, PLN1 in Table 2) on the side of the sixth insulating layer 110 facing away from the base substrate 100, forming an anode layer (for example, Anode in Table 2) on the side of the first planarization layer (for example, PLN1 in Table 2) facing away from the base substrate 100, forming a blocking layer (for example, A-PDL in Table 2) on the side of the anode layer (for example, Anode in Table 2) facing away from the base substrate 100, and forming a pixel definition layer (for example, HPDL in Table 2) on the side of the blocking layer (for example, A-PDL in Table 2) facing away from the base substrate 100.

[0080] It should be noted that if Figure 4As shown in Table 3, a second conductive layer 104 (e.g., Gate2 in Table 2), a semiconductor layer 106 (e.g., IGZO in Table 2), a third conductive layer 108 (e.g., Gate3 in Table 2), a fourth conductive layer 110 (e.g., SD1 in Table 2), a first planarization layer (e.g., PLN1 in Table 2), an anode layer (e.g., Anode in Table 2), a barrier layer (e.g., A-PDL in Table 2), and a pixel definition layer (e.g., HPDL in Table 2) can be formed by a patterning process; and a first via layer (e.g., ILD-1 in Table 2) and a second via layer (e.g., ILD-2 in Table 2) can be formed by an etching process. For example, the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes such as printing and inkjetting for forming a predetermined pattern; a photolithography process refers to a process for forming a pattern using a photoresist, a mask, an exposure machine, etc., including processes such as film formation, exposure, and development. In a specific implementation, a corresponding patterning process may be selected according to the structure formed in the present invention.

[0081] Exemplarily, the thickness of the third insulating layer 105 in the actual example of the present disclosure is about 1000A.

[0082] Illustratively, the resistance of the conductive material used in the third conductive layer in the practical example of the present disclosure is smaller than the resistance of the conductive material used in the second conductive layer.

[0083] Exemplarily, the material of the semiconductor layer includes a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide), and of course, other metal oxide semiconductor materials may also be used, which is not limited here. It should be noted that the semiconductor layer includes a source region, a drain region, and a channel region located between the source region and the drain region; wherein the source region and the drain region may be conductive regions formed by doping with n-type impurities or p-type impurities.

[0084] Exemplarily, the material of the conductive layer may be a conductive material. For example, the conductive material may include metal materials or alloy materials such as aluminum, molybdenum, titanium, etc., or may include metal oxides such as indium tin oxide (ITO) and the like. The embodiments of the present disclosure do not limit the materials of each film layer.

[0085] Exemplarily, the above-mentioned insulating layer, planarizing layer, blocking layer and pixel definition layer are all formed of insulating materials. According to needs, organic insulating materials such as polyimide, resin materials and other materials can be selected, and inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride and other materials can also be selected. The embodiments of the present disclosure do not specifically limit the materials of each film layer.

[0086] In summary, the method for manufacturing the array substrate in the embodiment of the present disclosure only uses 9-layer patterning process and 2-layer etching process or 8-layer patterning process and 2-layer etching process, which shows that the process flow of manufacturing the array substrate is relatively simple, greatly improving the production efficiency and reducing the production cost. In addition, due to the reduction in the number of film layers on the array substrate and the further reduction in the thickness of the third insulating layer, the array substrate is greatly thinned, thereby further achieving lightness and thinness.

[0087] Based on the above-mentioned method for manufacturing an array substrate, an array substrate provided by an embodiment of the present disclosure is as follows: Figure 5 and Figure 6 As shown, it includes: a base substrate 100, including a plurality of pixel circuits 200;

[0088] The pixel circuit 200 includes: a driving transistor T0 and a first capacitor C1; the gate of the driving transistor T0 is connected to the first switching portion (eg Figure 6 Z1) and the first plate of the first capacitor C1 (eg Figure 6 The first electrode of the driving transistor T0 is electrically connected to the first node N1, and the second electrode of the driving transistor T0 is electrically connected to the first node N1 through the second switching portion (for example Figure 6 Z2) and the second plate of the first capacitor C1 (eg Figure 6 C1-2) electrical connection;

[0089] The first transition portion (eg Figure 6 Z1), the gate of the driving transistor T0 and the second switching part (eg Figure 6 Z2) is set on the same layer.

[0090] The embodiment of the present disclosure arranges the first transfer portion, the gate of the driving transistor and the second transfer portion on the same layer, which can greatly improve the utilization rate of the layer, thereby reducing the number of patterning processes, thereby reducing process costs and improving production efficiency.

[0091] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projections of the first transition portion Z1 , the first electrode plate C1 - 1 of the first capacitor, and the second electrode plate C1 - 2 of the first capacitor on the base substrate 100 overlap with each other.

[0092] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projections of the second transition portion Z2 , the first electrode plate C1 - 1 of the first capacitor, and the second electrode plate C1 - 2 of the first capacitor C1 on the base substrate 100 overlap with each other.

[0093] In some embodiments of the present disclosure, Figure 6As shown, the orthographic projection of the second transition portion Z2 on the base substrate 100 does not overlap with the orthographic projection of the first transition portion Z1 and the gate of the driving transistor T0 on the base substrate 100 .

[0094] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the pixel circuit 200 further includes: a second capacitor C2;

[0095] The first electrode plate (eg Figure 6 C2-1) is electrically connected to the first power signal line VDD, and the second plate of the second capacitor C2 (e.g. Figure 6 C2-2) through the second adapter (eg Figure 6 Z2) and the second plate of the first capacitor C1 (eg Figure 6 C1-2) electrical connection;

[0096] The second adapter (for example Figure 6 Z2) and the first adapter (eg Figure 6 Z1) is located on the same layer.

[0097] In some embodiments of the present disclosure, Figure 6 As shown, the first plate C2-1 of the second capacitor, the first plate C1-1 of the first capacitor and the first power signal line VDD are located in the same layer;

[0098] The second plate C2 - 2 of the second capacitor and the second plate C1 - 2 of the first capacitor are located in the same layer.

[0099] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projection of the second transition portion Z2 on the base substrate 100 overlaps with the orthographic projections of the first electrode plate C2 - 1 of the second capacitor and the second electrode plate C2 - 2 of the second capacitor on the base substrate 100 .

[0100] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projections of the first plate C2 - 1 of the second capacitor, the second plate C2 - 2 of the second capacitor, and the gate of the driving transistor T0 on the base substrate 100 overlap with each other.

[0101] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the pixel circuit 200 further includes: a first transistor T1;

[0102] The gate of the first transistor T1 is electrically connected to the first reset signal line Reset1, and the first electrode of the first transistor T1 is connected to the first reset signal line Reset1 through the third switching part (for example Figure 6Z3) is electrically connected to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is connected to the first switching part (eg Figure 6 Z1) is electrically connected to the gate of the driving transistor T0;

[0103] The third adapter (for example Figure 6 Z3), a first reset signal line Reset1, and a first switching portion (eg Figure 6 Z1) is located on the same layer.

[0104] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projection of the third transfer portion Z3 on the base substrate 100 overlaps with the orthographic projection of the first initialization signal line Vinit1 on the base substrate 100 .

[0105] In some embodiments of the present disclosure, Figure 6 As shown, the first initialization signal line Vinit1 and the first power signal line VDD are located in the same layer.

[0106] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the first capacitor C1 also includes a third plate (eg Figure 6 The second electrode of the first transistor T1 is reused as the third electrode plate of the first capacitor C1 (for example Figure 6 C1-3), the third plate (e.g. Figure 6 C1-3) through the first adapter (eg Figure 6 Z1) and the first plate of the first capacitor C1 (eg Figure 6 C1-1) electrical connection.

[0107] In the actual example of the present disclosure, the second electrode of the first transistor is reused as the third electrode plate of the first capacitor. Such a configuration can increase the capacitance of the first capacitor while saving the space occupied by the first capacitor, thereby improving space utilization.

[0108] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the pixel circuit 200 further includes: a second transistor T2;

[0109] The gate of the second transistor T2 is electrically connected to the first scanning signal line Gate1, and the first electrode of the second transistor T2 is electrically connected to the first scanning signal line Gate1 through the first switching portion (eg Figure 6 The Z1 of the second transistor is electrically connected to the gate of the driving transistor T0, and the second electrode of the second transistor T2 is electrically connected to the data signal line DA;

[0110] The first scanning signal line Gate1 and the first switching portion (eg Figure 6Z1) are located in the same layer, and the first scanning signal line Gate1 and the data signal line DA are located in different layers.

[0111] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the pixel circuit 200 further includes: a third transistor T3;

[0112] The gate of the third transistor T3 is electrically connected to the first light emitting control signal line EM1, and the first electrode of the third transistor T3 is electrically connected to the first light emitting control signal line EM1 through the fourth switching part (for example Figure 6 Z4) is electrically connected to the first power signal line VDD, and the second electrode of the third transistor T3 is electrically connected to the first node N1;

[0113] The first transition portion (eg Figure 6 Z1), the fourth adapter (for example Figure 6 Z4) and the first light emitting control signal line EM1 are located in the same layer.

[0114] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projection of the fourth transfer portion Z4 on the base substrate 100 overlaps with the orthographic projection of the first power signal line VDD on the base substrate 100 .

[0115] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the pixel circuit 200 further includes: a fourth transistor T4;

[0116] The gate of the fourth transistor T4 is electrically connected to the second light emitting control signal line EM2, and the first electrode of the fourth transistor T4 is connected to the second light emitting control signal line EM2 through the fifth switching part (for example Figure 6 Z5) and the second plate of the first capacitor C1 (eg Figure 6 The second electrode of the fourth transistor T4 is electrically connected to the second node N2;

[0117] The first transition portion (eg Figure 6 Z1), the fifth adapter (for example Figure 6 Z5) and the second light emitting control signal line EM2 are located on the same layer.

[0118] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projection of the fifth transfer portion Z5 on the base substrate 100 is located between the orthographic projections of the first reset signal line Reset1 and the first initialization signal line Vinit1 on the base substrate 100 .

[0119] In some embodiments of the present disclosure, Figure 5 and Figure 6 As shown, the pixel circuit 200 further includes: a fifth transistor T5;

[0120] The gate of the fifth transistor T5 is electrically connected to the second reset signal line Reset2, the first electrode of the fifth transistor T5 is electrically connected to the second node N2, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2 through the sixth switching part (for example Figure 6 Z6) is electrically connected to the second initialization signal line Vinit2;

[0121] The fifth adapter (eg Figure 6 Z5), the sixth adapter (eg Figure 6 Z6) and the second reset signal line Reset2 are located on the same layer.

[0122] In some embodiments of the present disclosure, Figure 6 As shown, the orthographic projection of the sixth transition portion Z6 on the base substrate 100 overlaps with the orthographic projection of the second initialization signal line Vinit2 on the base substrate 100 .

[0123] In some embodiments of the present disclosure, Figure 6 As shown, the second initialization signal line Vinit2 and the second electrode plate C1 - 2 of the first capacitor are located in the same layer.

[0124] In some embodiments of the present disclosure, Figure 5 As shown, the array substrate also includes a light-emitting device L, the first electrode of the light-emitting device L is electrically connected to the second node N2, and the second electrode of the light-emitting device L is electrically connected to the second power signal line VSS; illustratively, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L can include: at least one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), and a mini light-emitting diode (Mini LED). Exemplarily, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application, and is not limited here.

[0125] In some embodiments of the present disclosure, Figure 6As shown, the first power signal line VDD, the first light emitting control signal line EM1, the first scanning signal line Gate1, the first reset signal line Reset1, the first initialization signal line Vinit1, the second light emitting control signal line EM2, the second reset signal line Reset2 and the second initialization signal line Vinit2 all extend along the first direction F1;

[0126] The first power signal line VDD, the first light emitting control signal line EM1, the first scanning signal line Gate1, the first reset signal line Reset1, the first initialization signal line Vinit1, the second light emitting control signal line EM2, the second reset signal line Reset2 and the second initialization signal line Vinit2 are sequentially arranged in sequence along the second direction F2;

[0127] The first direction F1 and the second direction F2 are arranged to intersect each other.

[0128] For example, Figure 7 As shown, the first conductive layer 102 may include: a first power signal line VDD, a first plate C2 - 1 of a second capacitor, a first plate C1 - 1 of a first capacitor, and a first initialization signal line Vinit1 .

[0129] For example, Figure 7 As shown, the first power signal line VDD and the first plate C2-1 of the second capacitor are integrated; the first plate C1-1 of the first capacitor and the first plate C2-1 of the second capacitor are spaced apart along the second direction F2; the first plate C1-1 of the first capacitor and the first initialization signal line Vinit1 are spaced apart along the second direction F2.

[0130] For example, Figure 8 As shown, the second conductive layer 104 may include: a second plate C2 - 2 of the second capacitor, a second plate C1 - 2 of the first capacitor, and a second initialization signal line Vinit2 .

[0131] For example, Figure 8 As shown, the second electrode plate C2 - 2 of the second capacitor, the second electrode plate C1 - 2 of the first capacitor and the second initialization signal line Vinit2 are sequentially arranged at intervals along the second direction F2 .

[0132] For example, Fig. 9 As shown, the semiconductor layer 106 may include: an active layer T0-O of a driving transistor, an active layer T1-O of a first transistor, an active layer T2-O of a second transistor, an active layer T3-O of a third transistor, an active layer T4-O of a fourth transistor, an active layer T5-O of a fifth transistor, and a third plate C1-3 of a first capacitor.

[0133] Exemplarily, the active layer T0-O of the driving transistor and the active layer T3-O of the third transistor are integrated; the active layer T4-O of the fourth transistor and the active layer T5-O of the fifth transistor are integrated.

[0134] In the actual example of the present disclosure, the source region or the drain region in the active layer of the first transistor can be reused as the third plate of the first capacitor. This arrangement can increase the capacitance of the first capacitor while saving the space occupied by the first capacitor, thereby improving space utilization.

[0135] For example, Fig.10 As shown, the third conductive layer 108 may include: a gate T0-G of a driving transistor, a gate T1-G of a first transistor, a gate T2-G of a second transistor, a gate T3-G of a third transistor, a gate T4-G of a fourth transistor, a gate T5-G of a fifth transistor, a first light-emitting control signal line EM1, a first scanning signal line Gate1, a first reset signal line Reset1, a second light-emitting control signal line EM2, a second reset signal line Reset2, a first transfer part Z1, a second transfer part Z2, a third transfer part Z3, a fourth transfer part Z4, a fifth transfer part Z5 and a sixth transfer part Z6.

[0136] Among them, it should be noted that the first light-emitting control signal line EM1 is multiplexed as the gate T3-G of the third transistor, the first scanning signal line Gate1 is multiplexed as the gate T2-G of the second transistor, the first reset signal line Reset1 is multiplexed as the gate T1-G of the first transistor, the second light-emitting control signal line EM2 is multiplexed as the gate T4-G of the fourth transistor, and the second reset signal line Reset2 is multiplexed as the gate T5-G of the fifth transistor.

[0137] In the embodiment of the present disclosure, multiple transfer parts, gates of multiple transistors, a first light-emitting control signal line, a first scanning signal line, a first reset signal line, a second light-emitting control signal line and a second reset signal line are all arranged on the third conductive layer, which greatly improves the utilization rate of the third conductive layer, thereby saving space, reducing the number of film layers, reducing process complexity and process costs, and improving production efficiency.

[0138] Furthermore, the resistance of the conductive material used in the third conductive layer in the actual example of the present disclosure is lower than the resistance of the conductive material used in the second conductive layer, which can reduce the switching resistance of the switching part, avoid signal loss, improve signal transmission efficiency, and thus improve the display effect.

[0139] For example, Fig.11 As shown, the fourth conductive layer 110 may include: a data signal line DA, a first initialization signal line Vinit1, a second power signal line VSS, and a second initialization signal line Vinit2.

[0140] For example, Fig.11 As shown, the data signal line DA, the first initialization signal line Vinit1, the second power signal line VSS and the second initialization signal line Vinit2 all extend along the second direction F2 and are arranged at intervals from each other along the first direction F1.

[0141] It should be noted that the first initialization signal line Vinit1 in the fourth conductive layer 110 can be electrically connected to the first initialization signal line Vinit1 in the first conductive layer 102 through the third adapter Z3, so that the orthographic projection of the first initialization signal line Vinit1 on the substrate is arranged in a grid shape, which is conducive to the stability of signal transmission. The second initialization signal line Vinit2 in the fourth conductive layer 110 can be electrically connected to the second initialization signal line Vinit2 in the second conductive layer 104 through the sixth adapter Z6, so that the orthographic projection of the second initialization signal line Vinit2 on the substrate is arranged in a grid shape, which is conducive to the stability of signal transmission.

[0142] For example, the layout diagram of the first conductive layer 102 and the second conductive layer 104 overlapping each other is as shown in FIG. Fig.12 shown.

[0143] For example, the schematic diagram of the layout of the first conductive layer 102, the second conductive layer 104 and the semiconductor layer 106 superimposed on each other is shown in FIG. Fig.13 shown.

[0144] For example, the schematic diagram of the layout of the first conductive layer 102, the second conductive layer 104, the semiconductor layer 106 and the third conductive layer 108 stacked on each other is shown in FIG. Fig.14 shown.

[0145] The structural diagrams of other pixel circuits provided by the embodiments of the present disclosure are as follows: Fig.15 As shown, the implementation of the above embodiment is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0146] In some embodiments of the present disclosure, the gate of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first power signal line VDD, and the second electrode of the first transistor T1 is electrically connected to the gate of the driving transistor T0. This arrangement can save signals, reduce wiring complexity, and facilitate design.

[0147] The method for manufacturing an array substrate provided by an embodiment of the present disclosure includes: sequentially forming a first conductive layer, a second conductive layer, a semiconductor layer, and a third conductive layer on a base substrate to form a pixel circuit located on the base substrate;

[0148] The first conductive layer includes a first plate of the first capacitor; the second conductive layer includes a second plate of the first capacitor; the semiconductor layer includes an active layer of the driving transistor; and the third conductive layer includes a gate of the driving transistor, a first switching portion and a second switching portion.

[0149] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided by the embodiment of the present invention. The principle of solving the problem by the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0150] An embodiment of the present disclosure provides a display device, which includes: an array substrate, the array substrate includes a plurality of pixel units arranged in an array, and the pixel unit may include a plurality of sub-pixels. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that a color display can be achieved by mixing red, green, and blue. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that a color display can be achieved by mixing red, green, blue, and white. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0151] In the embodiment of the present disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, so that the display panel can realize the function of displaying a picture.

[0152] In specific implementation, in the embodiment of the present invention, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations on the present invention.

[0153] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0154] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein: include: A substrate substrate, comprising a plurality of pixel circuits; The pixel circuit comprises: a driving transistor and a first capacitor; the gate of the driving transistor is electrically connected to the first plate of the first capacitor through a first switching portion, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second plate of the first capacitor through a second switching portion; The first transfer portion, the gate of the driving transistor and the second transfer portion are arranged on the same layer.

2. The array substrate according to claim 1, wherein: The first transfer portion, the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor overlap with each other in their orthographic projections on the base substrate.

3. The array substrate according to claim 1, wherein: The second transfer portion, the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor overlap with each other in orthographic projection on the base substrate.

4. The array substrate according to claim 1, wherein: The orthographic projection of the second transfer portion on the base substrate does not overlap with the orthographic projections of the first transfer portion and the gate of the driving transistor on the base substrate.

5. The array substrate according to any one of claims 1 to 4, wherein: The pixel circuit further includes: a second capacitor; The first electrode plate of the second capacitor is electrically connected to the first power signal line, and the second electrode plate of the second capacitor is electrically connected to the second electrode plate of the first capacitor through the second adapter; The second transition portion and the first transition portion are located at the same layer.

6. The array substrate according to claim 5, wherein: The first electrode plate of the second capacitor, the first electrode plate of the first capacitor and the first power signal line are located in the same layer; The second plate of the second capacitor and the second plate of the first capacitor are located in the same layer.

7. The array substrate according to claim 5, wherein: The orthographic projection of the second transition portion on the base substrate overlaps with the orthographic projection of the first electrode plate of the second capacitor and the orthographic projection of the second electrode plate of the second capacitor on the base substrate.

8. The array substrate according to claim 5, wherein: The first plate of the second capacitor, the second plate of the second capacitor, and the gate of the driving transistor overlap each other in orthographic projection on the base substrate.

9. The array substrate according to any one of claims 6 to 8, wherein: The pixel circuit further includes: a first transistor; The gate of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initialization signal line through the third switching portion, and the second electrode of the first transistor is electrically connected to the gate of the driving transistor through the first switching portion; The third transfer portion, the first reset signal line, and the first transfer portion are located in the same layer.

10. The array substrate according to claim 9, wherein: An orthographic projection of the third transfer portion on the base substrate overlaps with an orthographic projection of the first initialization signal line on the base substrate.

11. The array substrate according to claim 9, wherein: The first initialization signal line and the first power signal line are located in the same layer.

12. The array substrate according to claim 9, wherein: The first capacitor also includes a third plate; the second electrode of the first transistor is reused as the third plate of the first capacitor, and the third plate is electrically connected to the first plate of the first capacitor through the first switching portion.

13. The array substrate according to any one of claims 6 to 8, wherein: The pixel circuit further includes: a second transistor; The gate of the second transistor is electrically connected to the first scanning signal line, the first electrode of the second transistor is electrically connected to the gate of the driving transistor through the first switching portion, and the second electrode of the second transistor is electrically connected to the data signal line; The first scanning signal line and the first switching portion are located in the same layer, and the first scanning signal line and the data signal line are located in different layers.

14. The array substrate according to any one of claims 6 to 8, wherein: The pixel circuit further includes: a third transistor; The gate of the third transistor is electrically connected to the first light emitting control signal line, the first electrode of the third transistor is electrically connected to the first power signal line through the fourth switching portion, and the second electrode of the third transistor is electrically connected to the first node; The first transfer portion, the fourth transfer portion and the first light-emitting control signal line are located in the same layer.

15. The array substrate according to claim 14, wherein: The orthographic projection of the fourth transition portion on the base substrate overlaps with the orthographic projection of the first power signal line on the base substrate.

16. The array substrate according to any one of claims 6 to 8, wherein: The pixel circuit further includes: a fourth transistor; The gate of the fourth transistor is electrically connected to the second light emitting control signal line, the first electrode of the fourth transistor is electrically connected to the second electrode plate of the first capacitor through the fifth adapter, and the second electrode of the fourth transistor is electrically connected to the second node; The first transfer portion, the fifth transfer portion and the second light-emitting control signal line are located in the same layer.

17. The array substrate according to claim 16, wherein: The orthographic projection of the fifth transfer portion on the base substrate is located between the orthographic projections of the first reset signal line and the first initialization signal line on the base substrate.

18. The array substrate according to claim 16, wherein: The pixel circuit further includes: a fifth transistor; The gate of the fifth transistor is electrically connected to the second reset signal line, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the second initialization signal line through the sixth switching portion; The fifth transfer portion, the sixth transfer portion and the second reset signal line are located in the same layer.

19. The array substrate according to claim 18, wherein: An orthographic projection of the sixth transfer portion on the base substrate overlaps with an orthographic projection of the second initialization signal line on the base substrate.

20. The array substrate according to claim 18, wherein: The second initialization signal line and the second electrode plate of the first capacitor are located in the same layer.

21. The array substrate according to any one of claims 17 to 20, wherein: The first power signal line, the first light emission control signal line, the first scan signal line, the first reset signal line, the first initialization signal line, the second light emission control signal line, the second reset signal line and the second initialization signal line all extend along a first direction; The first power signal line, the first light emitting control signal line, the first scanning signal line, the first reset signal line, the first initialization signal line, the second light emitting control signal line, the second reset signal line and the second initialization signal line are sequentially arranged in a spaced relationship along a second direction; The first direction and the second direction are arranged to intersect each other.

22. A display device, wherein: Comprising the array substrate as described in any one of claims 1-21.

23. A method for manufacturing an array substrate according to any one of claims 1 to 21, wherein: include: Sequentially forming a first conductive layer, a second conductive layer, a semiconductor layer and a third conductive layer on the base substrate to form a pixel circuit on the base substrate; Among them, the first conductive layer includes the first plate of the first capacitor; the second conductive layer includes the second plate of the first capacitor; the semiconductor layer includes the active layer of the driving transistor; and the third conductive layer includes the gate of the driving transistor, the first transition portion and the second transition portion.

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