ESD protection device
By designing an ESD protection device that eliminates the P-type well region, and using the first doped type substrate and unit structure to form the first thyristor structure, the problem of resistance-affecting the triggering process of the thyristor structure in the prior art is solved, and a stronger ESD capability and a more easily adjustable maintenance voltage are achieved.
Patent Information
- Application Number
- CN202411959302.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-18
AI Technical Summary
The triggering process of the thyristor structure of the existing ESD protection devices is affected by the resistance of the NW1 region, the resistance of the pt region and the resistance of the PW region below N2, and the P-type well region PW has an amplification effect that will affect the transistor, resulting in poor maintenance current regulation.
An ESD protection device is designed, including a first doped type substrate and a cell structure located in the substrate, the cell structure includes a first well region of the second doped type, a first doped type of first doped type, a second doped type of second doped type adjacent to the first doped region, and a fourth doped region of the second doped type in the substrate to form a first thyristor structure. This structure eliminates the P-type well region PW, reduces the lithography step, increases the amplification effect of the thyristor structure, and makes the maintenance voltage easier to adjust.
By removing the P-type well region, the concentration of current is reduced, the trigger voltage of the device is reduced, the ESD capability is improved, and the process steps are simplified.
Smart Images
Figure CN119855244A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to an ESD protection device. Background Art
[0002] The electrostatic discharge (ESD) phenomenon of integrated circuits is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside when the chip is floating. Since the internal resistance of the integrated circuit chip is very low, when the ESD phenomenon occurs, an instantaneous, high peak current will be generated, and a large amount of Joule heat will be generated, which will cause the integrated circuit chip to be invalid. Therefore, it is very important to use high-performance ESD protection devices to discharge electrostatic charges. Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an ESD protection device to solve the problems existing in the prior art.
[0004] According to a first aspect of the present invention, an ESD protection device is provided, comprising: a substrate of a first doping type; and at least one unit structure located in the substrate, the unit structure comprising: a first well region of a second doping type located in the substrate; a first doping region of the first doping type located in the first well region, a second doping region of the second doping type at least partially located in the first well region and adjacent to the first doping region, and a fourth doping region of the second doping type located in the substrate, the first doping region, the first well region, the substrate, and the fourth doping region forming a first thyristor structure, wherein the side surface and the bottom surface of the fourth doping region are surrounded by the substrate
[0005] Preferably, the unit structure also includes: a third doping region of the first doping type located in the substrate and adjacent to the fourth doping region, a second well region of the second doping type located in the substrate; and a fifth doping region of the second doping type at least partially located in the second well region, wherein the side and bottom surfaces of the third doping region are surrounded by the substrate, and the third doping region and the fifth doping region form a first diode structure.
[0006] Preferably, the unit structure further includes: a sixth doping region of the first doping type located in the second well region and adjacent to the fifth doping region.
[0007] Preferably, it further includes a seventh doping region of the first doping type located between the first well region and the fourth doping region.
[0008] Preferably, the first well region completely surrounds the lower surface of the second doped region.
[0009] Preferably, the first well region partially surrounds a lower surface of the second doped region.
[0010] Preferably, the method further comprises a third well region of the first doping type located between the seventh doping region and the fourth doping region to prevent the first well region and the fourth doping region from penetrating.
[0011] Preferably, the depth of the third well region is greater than the depth of the fourth doping region.
[0012] Preferably, the depth of the seventh doping region is less than the depth of the first doping region.
[0013] Preferably, the doping concentration of the third well region is greater than the doping concentration of the seventh doping region.
[0014] Preferably, the second well region completely or partially surrounds the lower surface of the fifth doping region.
[0015] Preferably, when the at least one unit structure includes one unit structure, the first doping region, the second doping region, the sixth doping region and the fifth doping region are electrically connected to the first input / output terminal, and the third doping region and the fourth doping region are electrically connected to the second input / output terminal.
[0016] Preferably, the at least one unit structure includes a first unit structure and a second unit structure, wherein the first doping region, the second doping region, the sixth doping region and the fifth doping region in the first unit structure are electrically connected to the first input / output terminal, the first doping region, the second doping region, the sixth doping region and the fifth doping region in the second unit structure are electrically connected to the second input / output terminal, and the third doping region and the fourth doping region in the first unit structure are electrically connected to the third doping region and the fourth doping region in the second unit structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 Shown is a cross-sectional view of an ESD protection device in the prior art;
[0018] Figure 2 Shown is a cross-sectional view of an ESD protection device according to Embodiment 1 of the present invention;
[0019] Figure 3 Shown is a cross-sectional view of an ESD protection device according to a second embodiment of the present invention;
[0020] Figure 4 Shown is a cross-sectional view of an ESD protection device according to a third embodiment of the present invention;
[0021] Figure 5 Shown is a cross-sectional view of an ESD protection device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION
[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0023] Please refer to Figure 1 , Figure 1 The figure is a cross-sectional view of a bidirectional ESD protection device of the prior art. In the figure, the first input / output terminal I / O-1 to the second input / output terminal I / O-2 is a first thyristor structure SCR1 connected in series with a second diode D2, and the second input / output terminal I / O-2 to the first input / output terminal I / O-1 is a second thyristor structure SCR2 connected in series with a first diode D1. Figure 1 As shown in the figure, the triggering process of the thyristor includes three parts. First, the NW1 / Pt&PW&P2 diodes are broken down. Second, the PW resistance area below the N2 area reaches 0.7V, and the triode composed of NW1 / PW / N2 is turned on. Finally, the voltage of the NW1 area below the P1 area reaches 0.7V, and the triode composed of P1 / NW1 / PW is turned on, resulting in the final thyristor SCR turning on. The main disadvantage of the existing thyristor structure is that its triggering is affected by the resistance of the NW1 area, the resistance of the pt area, and the resistance of the PW area below N2. At the same time, the existence of PW will affect the amplification effect of the triode composed of NW1 / PW / N2, which is not conducive to the regulation of the holding current of the thyristor structure.
[0024] Please refer to Figure 2 , Figure 2It is a cross-sectional view of the ESD protection device of the first embodiment of the present invention. In this embodiment, the ESD protection device is a unidirectional structure. The ESD protection device includes a substrate 101 of a first doping type and a unit structure located in the substrate 101. The unit structure includes a first well region 102 of a second doping type located in the substrate 101, a first doping region 105 of a first doping type located in the first well region 102; a second doping region 104 of a second doping type located in the first well region 102 and adjacent to the first doping region 105; a third doping region 108 of the first doping type and a fourth doping region 107 of the second doping type located adjacent to each other in the substrate 101; wherein the first doping region 105, the first well region 102, the substrate 101, and the fourth doping region 107 form a first thyristor structure. In this embodiment, the third doping region 108 is in contact with the fourth doping region 107, and the third doping region 108 and the fourth doping region 107 are surrounded by the substrate 101, that is, the side surfaces and the bottom surfaces of the third doping region 108 and the fourth doping region 107 are in contact with the substrate 101. In this embodiment, the first well region 102 extends from the upper surface of the substrate 101 to the inside thereof; the first doping region 105 and the second doping region 104 extend from the upper surface of the first well region 102 to the inside thereof, and the third doping region 108 and the fourth doping region 107 extend from the upper surface of the substrate 101 to the inside thereof.
[0025] Optionally, the substrate 101 is composed of silicon, for example. In this embodiment, the substrate 101 is preferably a high-resistance substrate. If the doping concentration of the substrate 101 is too low, leakage may occur. If the doping concentration of the substrate 101 is too high, the capacitance of the device will be affected. Therefore, the doping concentration of the substrate 101 is preferably 1×10 13 cm -3 ~1×10 14 cm -3 .
[0026] Optionally, the junction depth of the first well region 102 is relatively shallow, for example, less than 1 um, so as to reduce the area of the first well region and further reduce the capacitance of the first well region.
[0027] Since the first well region 102 and the fourth doping region 107 are too close, there is a risk of punch-through, which leads to increased leakage, and if the first well region 102 and the fourth doping region 107 are too far apart, the clamping voltage will increase. Therefore, in this embodiment, the distance between the first well region 102 and the fourth doping region 107 is set to be greater than or equal to 4um and less than or equal to 5um.
[0028] The unit structure further includes a second well region 103 of a second doping type, and a fifth doping region 109 of a second doping type located in the second well region 103, wherein the third doping region 108 and the fifth doping region 109 form a first diode. Further, the unit structure further includes a sixth doping region 110 of a first doping type located in the second well region 103 and adjacent to the fifth doping region 109, wherein the fifth doping region 109 and the sixth doping region 110 may be symmetrically arranged with the first doping region 105 and the second doping region 104. The second well region 103 extends from the upper surface of the substrate 101 to the interior thereof, and the sixth doping region 110 and the fifth doping region 109 extend from the upper surface of the second well region 103 to the interior thereof.
[0029] The unit structure further includes a seventh doping region 106 located between the first well region 102 and the fourth doping region 107. The seventh doping region 106 extends from the upper surface of the substrate 101 to the interior of the substrate. The seventh doping region 106 is of the first doping type. The seventh doping region 106 is used to turn on the first thyristor structure, that is, the breakdown voltage of the seventh doping region 106 and the adjacent first well region 102 is the turn-on voltage of the first thyristor. Preferably, the distance between the first well region 102 and the adjacent seventh doping region 106 is set to be greater than 0um and less than or equal to 1um. Such a setting can not only ensure the turn-on voltage of the first well region 102 and the seventh doping region 106, but also effectively reduce the junction capacitance between the first well region 102 and the seventh doping region 106. Preferably, the depth of the seventh doping region 106 in the substrate 101 is less than the depth of the first well region 102, and further, the depth of the seventh doping region 106 in the substrate 101 is less than the depth of the first doping region 105.
[0030] Among them, the first doping region 105, the second doping region 104, the sixth doping region 110 and the fifth doping region 109 are electrically connected to the first input / output terminal I / O-1, and the third doping region 108 and the fourth doping region 107 are electrically connected to the second input / output terminal I / O-2.
[0031] The first doping type is one of N-type and P-type, and the second doping type is the other of the N-type and P-type.
[0032] Please refer to Figure 3 , Figure 3 The ESD protection device in the embodiment has a bidirectional symmetrical structure. Figure 3 ESD protection devices and Figure 1 The difference between the ESD protection devices in Figure 3The ESD protection device includes two identical unit structures, and the other structures are basically the same and will not be described in detail. Specifically, the ESD protection device includes a substrate 101, and a Figure 2 The first unit structure 140 and the second unit structure 150 have the same unit structure. The first doping region 105, the first well region 102, the substrate 101, and the fourth doping region 107 in the first unit structure 140 form a first thyristor structure, and the third doping region 108 and the fifth doping region 109 form a first diode; the first doping region 105, the first well region 102, the substrate 101, and the fourth doping region 107 in the second unit structure 150 form a second thyristor structure, and the third doping region 108 and the fifth doping region 109 form a second diode. In this embodiment, the first doping region 105, the second doping region 104, the sixth doping region 110 and the fifth doping region 109 in the first unit structure 140 are electrically connected to the first input / output terminal I / O-1, the first doping region 105, the second doping region 104, the sixth doping region 110 and the fifth doping region 109 in the second unit structure 150 are electrically connected to the second input / output terminal I / O-2, and the third doping region 108 and the fourth doping region 107 in the first unit structure 140 are electrically connected to the third doping region 108 and the fourth doping region 107 in the second unit structure 150. Therefore, from the first input / output terminal I / O-1 to the second input / output terminal I / O-2, the first thyristor structure is connected in series with the second diode, and from the second input / output terminal I / O-2 to the first input / output terminal I / O-1, the second thyristor structure is connected in series with the first diode.
[0033] The ESD protection device further includes an isolation structure 215 located between the first unit structure 140 and the second unit structure 150 , and further includes an isolation structure located at an edge of the device. The isolation structure may include a trench and an insulating material filled in the trench.
[0034] Compared with the prior art, the P-type well region PW is omitted in the present embodiment, thereby reducing the photolithography steps for forming the P-type well region PW, thereby simplifying the process steps; further, for the first transistor in the thyristor structure (the first well region 102 / the seventh doping region 106 & the substrate 101 / the fourth doping region 107), there is no consumption of electron holes by the P-type well region, that is, the doping concentration of the base region of the first transistor is reduced, thereby increasing the amplification effect of the first transistor; further, because the P-type well region is omitted, the amplification effect of the thyristor structure is increased, and the maintenance voltage of the thyristor structure is more susceptible to changes in the doping concentration or area of the first well region, that is, the maintenance voltage of the thyristor structure is easier to adjust.
[0035] In addition, due to Figure 1 The prior art includes a P-type well region PW, and the doping concentration of the P-type well region PW is high, and the current of the device basically flows along the surface of the device ( Figure 1 The red dotted line in the figure is the current flow path); in this embodiment, after the P-type well region PW is removed, the electrons flow from the first doping region 105 / first well region 102 not only through the seventh doping region 106 to the fourth doping region 107, but also through the substrate 101 to the fourth doping region 107. In this process, the current flow area becomes larger ( Figure 3 The red dotted line in the middle is the current flow path. The corresponding resistance becomes smaller, so the trigger voltage of the device becomes smaller, and the area of current flow becomes larger, the current is not easy to concentrate, and the ESD capability of the device becomes stronger.
[0036] Please refer to Figure 4 , Figure 4 It is a cross-sectional view of the ESD protection device according to the third embodiment of the present invention. Figure 4 ESD protection devices and Figure 3 The difference between the ESD protection devices in Figure 4 In the ESD protection device, the first well region 102 half surrounds the second doping region 104, the second well region 103 half surrounds the sixth doping region 109, and the other structures are basically the same and will not be repeated here. Specifically, a part of the lower surface of the second doping region 104 contacts the substrate 101, and a part contacts the first well region 102; a part of the lower surface of the fifth doping region 109 contacts the substrate 101, and a part contacts the second well region 103. That is, the area of the first well region 102 and the second well region 103 is reduced, thereby reducing the junction capacitance between the first well region 102 and the substrate 201 and the second well region 103 and the substrate 201, and at the same time reducing the resistance under the second doping region 104 and the fifth doping region 109, further reducing the clamping voltage of the device.
[0037] Please refer to Figure 5 , Figure 5 It is a cross-sectional view of the ESD protection device according to the fourth embodiment of the present invention. Figure 5 ESD protection devices and Figure 4 The difference between the ESD protection devices in Figure 5The ESD protection device also includes a third well region 111, and the other structures are basically the same and are not described here. Specifically, the third well region 111 is located between the seventh doping region 106 and the fourth doping region 107, and is set to the first doping type to prevent the first well region 102 and the fourth doping region 107 from penetrating. The depth of the third well region 111 is set to be greater than the depth of the fourth doping region 107, and the doping concentration of the third well region 111 is greater than the doping concentration of the seventh doping region 106. Preferably, the third well region 111 is in contact with the fourth doping region 107.
[0038] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. An ESD protection device, characterized in that: include: a substrate of a first doping type; as well as at least one unit structure located in the substrate, the unit structure comprising: a first well region of a second doping type located in the substrate; a first doping region of the first doping type located in the first well region, a second doping region of the second doping type at least partially located in the first well region and disposed adjacent to the first doping region, and a A fourth doping region of the second doping type, the first doping region, the first well region, the substrate, and the fourth doping region form a first thyristor structure, Wherein, the side surfaces and the bottom surface of the fourth doping region are surrounded by the substrate.
2. The ESD protection device according to claim 1, characterized in that: The unit structure also includes: a third doping region of the first doping type located in the substrate and adjacent to the fourth doping region, a second well region of a second doping type located in the substrate; and a fifth doping region of the second doping type at least partially located in the second well region, The side surfaces and the bottom surface of the third doping region are surrounded by the substrate, and the third doping region and the fifth doping region form a first diode structure.
3. The ESD protection device according to claim 2, characterized in that: The unit structure further includes: a sixth doping region of the first doping type located in the second well region and adjacent to the fifth doping region.
4. The ESD protection device according to claim 1, characterized in that: It also includes a seventh doping region of the first doping type located between the first well region and the fourth doping region.
5. The ESD protection device according to claim 1, characterized in that: The first well region completely surrounds a lower surface of the second doped region.
6. The ESD protection device according to claim 1, characterized in that: The first well region partially surrounds a lower surface of the second doping region.
7. The ESD protection device according to claim 4, characterized in that: It also includes a third well region of the first doping type located between the seventh doping region and the fourth doping region to prevent the first well region and the fourth doping region from penetrating.
8. The ESD protection device according to claim 7, characterized in that: The depth of the third well region is greater than the depth of the fourth doping region.
9. The ESD protection device according to claim 4, characterized in that: The depth of the seventh doping region is less than the depth of the first doping region.
10. The ESD protection device according to claim 7, characterized in that: The doping concentration of the third well region is greater than the doping concentration of the seventh doping region.
11. The ESD protection device according to claim 2, characterized in that: The second well region completely or partially surrounds a lower surface of the fifth doping region.
12. The ESD protection device according to claim 3, characterized in that: When the at least one unit structure includes one unit structure, the first doping region, the second doping region, the sixth doping region and the fifth doping region are electrically connected to the first input / output terminal, and the third doping region and the fourth doping region are electrically connected to the second input / output terminal.
13. The ESD protection device according to claim 3, characterized in that: The at least one unit structure includes a first unit structure and a second unit structure, wherein the first doping region, the second doping region, the sixth doping region and the fifth doping region in the first unit structure are electrically connected to a first input / output terminal, the first doping region, the second doping region, the sixth doping region and the fifth doping region in the second unit structure are electrically connected to a second input / output terminal, and the third doping region and the fourth doping region in the first unit structure are electrically connected to the third doping region and the fourth doping region in the second unit structure.