Solar cell, preparation method thereof and photovoltaic module
By forming a mask layer and doped semiconductor layer on the substrate surface of the HBC battery and removing it using height difference, the pattern design of the film layer is achieved, solving the problem of complex pattern design on the back of the HBC battery, reducing the production cost and process difficulty, and promoting mass production and efficient conversion of solar cells.
Patent Information
- Application Number
- CN202510069179.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2025-04-18
AI Technical Summary
During the preparation of HBC battery, since the positive and negative electrodes of the battery are both set on the back of the battery, the patterning design on the back is complicated, which increases the difficulty and cost of production process, and limits the mass production of HBC batteries.
By sequentially forming the first intrinsic amorphous silicon layer and the mask layer on the first surface of the substrate, and forming a plurality of grooves arranged at intervals on the mask layer, then forming a first doped semiconductor thin film layer and a first protective film layer on the side where the mask layer is away from the substrate, removing it by using the height difference between the mask layer and the protective sub-part to obtain a spaced distribution first doped semiconductor layer and an alternately distributed second doped semiconductor layer to realize the pattern design of the film layer.
The difficulty and cost of the preparation process of solar cells are reduced, the preparation efficiency is improved, and the mass production of solar cells is conducive to the mass production of solar cells. By controlling the ratio of the grooved area and the untouched area of the mask layer, the high conversion efficiency of the solar cells is maintained.
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Figure CN119855285A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of photovoltaic technology, and in particular to solar cells and methods for preparing the same, and photovoltaic modules. Background Art
[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that convert sunlight directly into electrical energy. As they are green and environmentally friendly products that do not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.
[0003] The electrodes of interdigitated back contact (IBC) cells are located on the back of the cell, which can reduce the shading of the light-receiving surface of the cell, thereby improving the conversion efficiency of the cell, and gradually become the main research and development direction of industrial high-efficiency cells. The amorphous silicon film in HJT (Heterojunction with Intrinsic Thin-film) cells can effectively passivate the surface of the silicon wafer and effectively reduce the recombination of the silicon wafer surface. The HBC cell, which combines HJT cell and IBC cell technology, has a high efficiency and has gradually become a research hotspot.
[0004] In the related art, during the preparation of HBC batteries, since the positive and negative electrodes of the battery are both arranged on the back of the battery, the patterning design of the back of the battery is relatively complex and difficult, which increases the difficulty and cost of the manufacturing process of the HBC battery and limits the mass production of the HBC battery. Summary of the invention
[0005] Based on this, the present application provides a solar cell and a preparation method thereof, and a photovoltaic module to reduce the difficulty and cost of the preparation process of the solar cell, which is conducive to the mass production of solar cells.
[0006] An embodiment of the first aspect of the present application provides a method for preparing a solar cell, comprising:
[0007] Providing a substrate, and sequentially forming a first intrinsic amorphous silicon layer and a mask layer on a first surface of the substrate, and forming a plurality of grooves on the mask layer that are spaced apart and expose the first intrinsic amorphous silicon layer;
[0008] forming a first doped semiconductor thin film layer and a first protective film layer in sequence on a side of the mask layer away from the substrate, so that the first doped semiconductor thin film layer covers the mask layer and the first intrinsic amorphous silicon layer exposed by the groove, and the first protective film layer covers the first doped semiconductor thin film layer;
[0009] The mask layer and the first protective film layer and the first doped semiconductor film layer located on the side of the mask layer away from the substrate are removed to obtain a plurality of first doped semiconductor layers distributed at intervals and a plurality of protective sub-portions correspondingly arranged on the side of the plurality of first doped semiconductor layers away from the substrate;
[0010] A second doped semiconductor thin film layer is formed on a side of the protection sub-portion away from the substrate, so that the second doped semiconductor thin film layer covers the protection sub-portion and the first intrinsic amorphous silicon layer not covered by the first doped semiconductor layer, and the protection sub-portion and the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate are removed to obtain a second doped semiconductor layer alternately distributed with the first doped semiconductor layer.
[0011] In one embodiment, the step of sequentially forming a first doped semiconductor thin film layer and a first protective film layer on a side of the mask layer away from the substrate, so that the first doped semiconductor thin film layer covers the mask layer and the first intrinsic amorphous silicon layer exposed by the groove, and so that the first protective film layer covers the first doped semiconductor thin film layer, comprises:
[0012] The sum of the thickness of the first doped semiconductor thin film layer and the thickness of the first protective film layer is made smaller than the thickness of the mask layer.
[0013] In one embodiment, the step of removing the mask layer and the first protective film layer and the first doped semiconductor thin film layer located on a side of the mask layer away from the substrate comprises:
[0014] removing the first protective film layer and the first doped semiconductor thin film layer located on a side of the mask layer away from the substrate;
[0015] The mask layer is then removed to obtain a plurality of first doped semiconductor layers that are spaced apart and a plurality of protection sub-portions that are arranged one by one on a side of the plurality of first doped semiconductor layers away from the substrate.
[0016] In one embodiment, the step of removing the first protective film layer and the first doped semiconductor thin film layer located on a side of the mask layer away from the substrate comprises:
[0017] Keeping a first preset distance between the first surface of the substrate and the liquid surface of the first etching solution, so that the first protective film layer located on the side of the mask layer away from the substrate is immersed in the first etching solution and removed by the first etching solution;
[0018] The first surface of the substrate is maintained at a second preset distance from the liquid surface of the second etching solution, so that the first doped semiconductor thin film layer located on the side of the mask layer away from the substrate is immersed in the second etching solution and removed by the second etching solution.
[0019] In one embodiment, the step of removing the mask layer to obtain a plurality of first doped semiconductor layers arranged at intervals and a plurality of protection sub-portions arranged one by one on a side of the plurality of first doped semiconductor layers away from the substrate includes:
[0020] The substrate is placed in a third etching solution, the third etching solution reacts with the mask layer, and the third etching solution does not react with the first doped semiconductor thin film layer, the first protective film layer and the first intrinsic amorphous silicon layer, so as to remove the mask layer and obtain a plurality of first doped semiconductor layers arranged at intervals and a plurality of protective sub-portions correspondingly arranged on the side of the plurality of first doped semiconductor layers away from the substrate.
[0021] In one embodiment, the step of forming a second doped semiconductor thin film layer on a side of the protection sub-portion away from the substrate, making the second doped semiconductor thin film layer cover the protection sub-portion and the first intrinsic amorphous silicon layer not covered by the first doped semiconductor layer, and removing the protection sub-portion and the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate to obtain a second doped semiconductor layer alternately distributed with the first doped semiconductor layer, comprises:
[0022] forming a second doped semiconductor thin film layer on a side of the protection sub-portion away from the substrate, so that the second doped semiconductor thin film layer covers the protection sub-portion and the first intrinsic amorphous silicon layer not covered by the first doped semiconductor layer, and the sum of the thickness of the first doped semiconductor layer and the thickness of the protection sub-portion is greater than the thickness of the second doped semiconductor thin film layer;
[0023] removing the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate;
[0024] The protection sub-portion is removed to obtain a second doped semiconductor layer that is alternately distributed with the first doped semiconductor layer, and an end surface of the second doped semiconductor layer close to the first doped semiconductor layer is in contact with an end surface of the first doped semiconductor layer close to the second doped semiconductor layer.
[0025] In one embodiment, the step of removing the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate comprises:
[0026] The first surface of the substrate is kept at a third preset distance from the liquid surface of the fourth etching solution, so that the second doped semiconductor film layer located on the side of the protection sub-portion away from the substrate is immersed in the fourth etching solution and removed by the fourth etching solution.
[0027] In one embodiment, the step of removing the protection sub-portion to obtain a second doped semiconductor layer alternately distributed with the first doped semiconductor layer comprises:
[0028] The substrate is placed in a fifth etching solution, the fifth etching solution reacts with the protective sub-portion, and the fifth etching solution does not react with the second doped semiconductor thin film layer and the first doped semiconductor layer, so as to remove the protective sub-portion and obtain a second doped semiconductor layer that is alternately distributed with the first doped semiconductor layer, and the end surface of the second doped semiconductor layer close to the first doped semiconductor layer is in contact with the end surface of the first doped semiconductor layer close to the second doped semiconductor layer.
[0029] In one embodiment, the method for preparing the solar cell further comprises:
[0030] A second intrinsic amorphous silicon layer, a third doped semiconductor layer and an anti-reflection layer are sequentially formed on the second surface of the substrate; the doping type of the third doped semiconductor layer is the same as the doping type of the substrate; and the second surface is arranged opposite to the first surface.
[0031] In one embodiment, the method for preparing the solar cell further comprises:
[0032] A transparent conductive layer covering the first doped semiconductor layer and the second doped semiconductor layer is formed, and an isolation groove is formed on the transparent conductive layer, so that the isolation groove penetrates the transparent conductive layer along the thickness direction of the substrate, and the orthographic projection of the isolation groove on the substrate partially overlaps with the orthographic projections of the adjacent first doped semiconductor layer and the second doped semiconductor layer on the substrate.
[0033] An embodiment of the second aspect of the present application provides a solar cell, comprising:
[0034] substrate;
[0035] A first intrinsic amorphous silicon layer, disposed on a first surface of the substrate;
[0036] A first doped semiconductor layer, disposed on a side of the first intrinsic amorphous silicon layer away from the substrate;
[0037] A second doped semiconductor layer is disposed on a side of the first intrinsic amorphous silicon layer away from the substrate, and the second doped semiconductor layer and the first doped semiconductor layer are alternately distributed;
[0038] An end surface of the first doped semiconductor layer close to the second doped semiconductor layer contacts an end surface of the second doped semiconductor layer close to the first doped semiconductor layer.
[0039] An embodiment of a third aspect of the present application provides a photovoltaic assembly, comprising the solar cell described in any of the above embodiments.
[0040] The above-mentioned method for preparing a solar cell, by utilizing a mask layer having a certain thickness, so that there is a height difference between the first doped semiconductor thin film layer and the first protective film layer located in the area where the mask layer is located and the first doped semiconductor thin film layer and the first protective film layer located in the area where the groove is located, utilizing the height difference to remove the first protective film layer and the first doped semiconductor thin film layer located on the side of the mask layer away from the substrate, while retaining the first protective film layer and the first doped semiconductor thin film layer located in the area where the groove is located, removing the mask layer, and obtaining a plurality of first doped semiconductor layers distributed at intervals and a plurality of protective sub-parts correspondingly arranged on the sides of the plurality of first doped semiconductor layers away from the substrate; utilizing the certain thickness of the protective sub-parts, so that the second doped semiconductor thin film layer located in the area where the first doped semiconductor layer is located and the first doped semiconductor thin film layer located in the area where the first doped semiconductor layer is located are There is a height difference in the second doped semiconductor thin film layer outside the region where the doped semiconductor layer is located. The height difference is used to remove the second doped semiconductor thin film layer located on the side of the protective sub-portion away from the substrate, so that the second doped semiconductor thin film layer located outside the region where the first doped semiconductor layer is located is retained, and the protective sub-portion is removed, thereby obtaining the second doped semiconductor layer alternately distributed with the first doped semiconductor layer, that is, realizing the graphic design of the film layer on the side of the first intrinsic amorphous silicon layer away from the substrate. In this way, the difficulty and cost of graphic design of the film layer on the side of the first intrinsic amorphous silicon layer away from the substrate can be reduced, and the efficiency of graphic design of the film layer on the side of the first intrinsic amorphous silicon layer away from the substrate can be improved, thereby reducing the difficulty and cost of the preparation process of solar cells, improving the preparation efficiency of solar cells, and facilitating the mass production of solar cells;
[0041] In addition, by controlling the ratio of the grooved area to the ungrooved area of the mask layer, the area ratio of the first doped semiconductor layer to the second doped semiconductor layer can be within a reasonable range, so that the solar cell maintains a high conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 A flow chart of a method for preparing a solar cell provided in some embodiments of the present application.
[0043] Figure 2 Another flow chart of a method for preparing a solar cell provided in some embodiments of the present application.
[0044] Figure 3 Another flow chart of a method for preparing a solar cell provided in some embodiments of the present application.
[0045] Figure 4 Still another flow chart of a method for preparing a solar cell provided in some embodiments of the present application.
[0046] Figure 5 A process flow chart of a method for preparing a solar cell provided in some embodiments of the present application.
[0047] Figure 6 A schematic diagram of the structure of a solar cell provided in some embodiments of the present application.
[0048] Description of reference numerals:
[0049] 10. Solar cell; 11. Substrate; 111. First surface; 112. Second surface; 13. First intrinsic amorphous silicon layer; 14a. First doped semiconductor thin film layer; 14. First doped semiconductor layer; 15a. Second doped semiconductor thin film layer; 15. Second doped semiconductor layer; 16. Mask layer; 16a. Groove; 17. First protective film layer; 17a. Protective sub-portion; 18. Second intrinsic amorphous silicon layer; 19. Third doped semiconductor layer; 20. Anti-reflection layer; 21. Transparent conductive layer; 22. Isolation groove. DETAILED DESCRIPTION
[0050] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.
[0051] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
[0052] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0053] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.
[0054] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0055] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.
[0056] First, see Figure 1 and Figure 5 , the present application embodiment provides a method for preparing a solar cell, comprising:
[0057] S10, providing a substrate 11, and sequentially forming a first intrinsic amorphous silicon layer 13 and a mask layer 16 on a first surface 111 of the substrate 11, and forming a plurality of grooves 16a which are spaced apart and expose the first intrinsic amorphous silicon layer 13 on the mask layer 16;
[0058] S20, forming a first doped semiconductor thin film layer 14a and a first protective film layer 17 in sequence on a side of the mask layer 16 away from the substrate 11, so that the first doped semiconductor thin film layer 14a covers the mask layer 16 and the first intrinsic amorphous silicon layer 13 exposed by the groove 16a, and the first protective film layer 17 covers the first doped semiconductor thin film layer 14a;
[0059] S30, removing the mask layer 16 and the first protective film layer 17 and the first doped semiconductor thin film layer 14a located on the side of the mask layer 16 away from the substrate 11, to obtain a plurality of first doped semiconductor layers 14 distributed at intervals and a plurality of protective sub-portions 17a correspondingly arranged on the side of the plurality of first doped semiconductor layers 14 away from the substrate 11;
[0060] S40, forming a second doped semiconductor thin film layer 15a on the side of the protection sub-portion 17a away from the substrate 11, so that the second doped semiconductor thin film layer 15a covers the protection sub-portion 17a and the first intrinsic amorphous silicon layer 13 that is not blocked by the first doped semiconductor layer 14, and removing the protection sub-portion 17a and the second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11, to obtain the second doped semiconductor layer 15 alternately distributed with the first doped semiconductor layer 14.
[0061] It should be noted that the substrate 11 can be a P-type silicon wafer or an N-type silicon wafer; the doping type of the first doped semiconductor film layer 14a is opposite to the doping type of the substrate 11, and the doping type of the first doped semiconductor layer 14 is opposite to the doping type of the substrate 11; the doping type of the second doped semiconductor film layer 15a is the same as the doping type of the substrate 11, and the doping type of the second doped semiconductor layer 15 is the same as the doping type of the substrate 11; the first surface can be the backlight surface.
[0062] The method for preparing the solar cell 10 provided in the embodiment of the present application is to sequentially form a first intrinsic amorphous silicon layer 13 and a mask layer 16 on the first surface 111 of the substrate 11, and form a plurality of grooves 16a which are spaced apart and expose the first intrinsic amorphous silicon layer 13 on the mask layer 16, so that the first doped semiconductor thin film layer 14a covers the mask layer 16 and the first intrinsic amorphous silicon layer 13 exposed by the grooves 16a, and the first protective film layer 17 covers the first doped semiconductor thin film layer 14a. Since the mask layer 16 has a certain thickness, there is a height difference between the first doped semiconductor thin film layer 14a and the first protective film layer 17 located in the area where the mask layer 16 is located and the first doped semiconductor thin film layer 14a and the first protective film layer 17 located in the area where the grooves 16a are located. The first protective film layer 17 and the first doped semiconductor thin film layer 14a located in the area where the grooves 16a are located are removed by utilizing the height difference. The film layer 14a is retained, and the mask layer 16 is removed, so as to obtain a plurality of first doped semiconductor layers 14 that are distributed at intervals and a plurality of protection sub-portions 17a that are arranged one by one on the side of the plurality of first doped semiconductor layers 14 away from the substrate 11; the second doped semiconductor thin film layer 15a is made to cover the protection sub-portion 17a and the first intrinsic amorphous silicon layer 13 that is not covered by the first doped semiconductor layer 14. Since the protection sub-portion 17a has a certain thickness, there is a height difference between the second doped semiconductor thin film layer 15a located in the area where the first doped semiconductor layer 14 is located and the second doped semiconductor thin film layer 15a located outside the area where the first doped semiconductor layer 14 is located. The second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11 is removed by utilizing the height difference, so that the second doped semiconductor thin film layer 15a located outside the area where the first doped semiconductor layer 14 is located is retained, and the protection sub-portion 17a is removed, thereby obtaining the second doped semiconductor layers 15 that are alternately distributed with the first doped semiconductor layers 14. That is to say, the present application utilizes the height difference brought by the mask layer 16 to pattern the first doped semiconductor thin film layer 14a and the first protective film layer 17 to obtain the first doped semiconductor layer 14 and the protective sub-portion 17a, and utilizes the height difference brought by the protective sub-portion 17a to pattern the second doped semiconductor thin film layer 15a to obtain the second doped semiconductor layer 15, thereby realizing the graphic design of the film layer on the side of the first intrinsic amorphous silicon layer 13 away from the substrate 11. In this way, the difficulty and cost of graphic design of the film layer on the side of the first intrinsic amorphous silicon layer 13 away from the substrate 11 can be reduced, and the efficiency of graphic design of the film layer on the side of the first intrinsic amorphous silicon layer 13 away from the substrate 11 can be improved, thereby reducing the difficulty and cost of the preparation process of the solar cell 10, improving the preparation efficiency of the solar cell 10, and facilitating the mass production of the solar cell 10.
[0063] In some of these embodiments, see Figure 2 and Figure 5In S20, a first doped semiconductor thin film layer 14a and a first protective film layer 17 are sequentially formed on a side of the mask layer 16 away from the substrate 11, so that the first doped semiconductor thin film layer 14a covers the mask layer 16 and the first intrinsic amorphous silicon layer 13 exposed by the groove 16a, and the first protective film layer 17 covers the first doped semiconductor thin film layer 14a, specifically including:
[0064] The sum of the thickness of the first doped semiconductor thin film layer 14 a and the thickness of the first protective film layer 17 is smaller than the thickness of the mask layer 16 .
[0065] Specifically, the thickness of the mask layer 16 may be 5 um to 20 um; the thickness of the first doped semiconductor thin film layer 14 a may be 5 nm to 30 nm; and the thickness of the first protective film layer 17 may be 1 um to 10 um.
[0066] In this embodiment, by making the sum of the thickness of the first doped semiconductor thin film layer 14a and the thickness of the first protective film layer 17 smaller than the thickness of the mask layer 16, when the first doped semiconductor thin film layer 14a and the first protective film layer 17 located on the side of the mask layer 16 away from the substrate 11 are subsequently removed, it can be ensured that the first doped semiconductor thin film layer 14a and the first protective film layer 17 located in the area where the groove 16a is located are not affected, so as to realize the patterning of the first doped semiconductor thin film layer 14a and the first protective film layer 17, simplify the patterning process of the first doped semiconductor thin film layer 14a and the first protective film layer 17, and improve the patterning efficiency.
[0067] In some of these embodiments, see Figure 2 and Figure 5 In S30, the mask layer 16 and the first protective film layer 17 and the first doped semiconductor film layer 14a located on the side of the mask layer 16 away from the substrate 11 are removed, specifically including:
[0068] S310, removing the first protective film layer 17 and the first doped semiconductor thin film layer 14a located on the side of the mask layer 16 away from the substrate 11;
[0069] Specifically, a wet process can be used to remove the first protective film layer 17 and the first doped semiconductor thin film layer 14a located on the side of the mask layer 16 away from the substrate. Since the sum of the thickness of the first doped semiconductor thin film layer 14a and the thickness of the first protective film layer 17 is less than the thickness of the mask layer 16, the first protective film layer 17 and the first doped semiconductor thin film layer 14a located outside the mask layer 16 are not affected by the wet process.
[0070] S320, removing the mask layer 16 to obtain a plurality of first doped semiconductor layers 14 arranged at intervals and a plurality of protection sub-portions 17a arranged one by one on a side of the plurality of first doped semiconductor layers 14 away from the substrate 11;
[0071] Specifically, the mask layer 16 can be removed by a wet process, and the etching solution can be selected according to the material properties of the mask layer 16, the first protective film layer 17, the first doped semiconductor thin film layer 14a and the first intrinsic amorphous silicon layer 13 to ensure that the mask layer 16 is removed while the first protective film layer 17, the first doped semiconductor thin film layer 14a and the first intrinsic amorphous silicon layer 13 are not damaged.
[0072] In this embodiment, by removing the first protective film layer 17 and the first doped semiconductor thin film layer 14a located on the side of the mask layer 16 away from the substrate 11, the first doped semiconductor thin film layer 14a and the first protective film layer 17 can be patterned. Moreover, due to the height difference brought by the mask layer 16, the first doped semiconductor thin film layer 14a and the first protective film layer 17 located in the area where the groove 16a is located can be kept intact; by removing the mask layer 16, the first doped semiconductor thin film layer 14a and the first protective film layer 17 attached to the side wall of the mask layer 16 can be peeled off and removed together with the mask layer 16, thereby improving the patterning accuracy of the first doped semiconductor thin film layer 14a and the first protective film layer 17, and obtaining a plurality of first doped semiconductor layers 14 arranged at intervals and a plurality of protective sub-portions 17a correspondingly arranged on the side of the plurality of first doped semiconductor layers 14 away from the substrate 11.
[0073] In some embodiments, in S310, removing the first protection film layer 17 and the first doped semiconductor film layer 14a located on the side of the mask layer 16 away from the substrate 11 includes:
[0074] Keeping the first surface 111 of the substrate 11 at a first preset distance from the liquid surface of the first etching solution, so that the first protective film layer 17 located on the side of the mask layer 16 away from the substrate 11 is immersed in the first etching solution and is removed by the first etching solution;
[0075] Specifically, the first protective film layer 17 may be one of silicon oxide, silicon nitride, and silicon oxynitride, and the first etching solution may be a hydrofluoric acid solution, which may be used to remove the first protective film layer 17 located on the side of the mask layer 16 away from the substrate 11 .
[0076] The first surface of the substrate 11 is kept at a second preset distance from the liquid surface of the second etching solution, so that the first doped semiconductor thin film layer 14a located on the side of the mask layer 16 away from the substrate 11 is immersed in the second etching solution and removed by the second etching solution.
[0077] Specifically, the second etching solution may be an alkaline solution, such as ammonia water or potassium hydroxide solution, and the alkaline solution may be used to remove the first doped semiconductor thin film layer 14 a located on the side of the mask layer 16 away from the substrate 11 .
[0078] In this embodiment, the first surface of the substrate 11 is maintained at a first preset distance from the liquid surface of the first etching solution, so that the first protective film layer 17 located on the side of the mask layer 16 away from the substrate 11 is immersed in the first etching solution, and due to the height difference caused by the mask layer 16, the first protective film layer 17 located outside the area where the mask layer 16 is located will not contact the first etching solution, thereby achieving patterning of the first protective film layer 17; the first surface of the substrate 11 is maintained at a second preset distance from the liquid surface of the second etching solution, so that the first doped semiconductor thin film layer 14a located on the side of the mask layer 16 away from the substrate 11 is immersed in the second etching solution, and due to the height difference caused by the mask layer 16, the first doped semiconductor thin film layer 14a located outside the area where the mask layer 16 is located will not contact the second etching solution, thereby achieving patterning of the first doped semiconductor thin film layer 14a. That is to say, the height difference brought by the mask layer 16 is combined with the wet etching process to achieve patterning of the first doped semiconductor thin film layer 14a and the first protective film layer 17, thereby reducing the cost of patterning and improving the efficiency of patterning.
[0079] In some embodiments, in S320, the mask layer 16 is removed to obtain a plurality of first doped semiconductor layers 14 arranged at intervals and a plurality of protection sub-portions 17a arranged one by one on a side of the plurality of first doped semiconductor layers 14 away from the substrate 11, specifically including:
[0080] The substrate 11 is placed in a third etching solution, the third etching solution reacts with the mask layer 16, and the third etching solution does not react with the first doped semiconductor thin film layer 14a, the first protective film layer 17 and the first intrinsic amorphous silicon layer 13, so as to remove the mask layer 16 and obtain a plurality of first doped semiconductor layers 14 arranged at intervals and a plurality of protective sub-portions 17a arranged one by one on the side of the plurality of first doped semiconductor layers 14 away from the substrate 11.
[0081] In this embodiment, by placing the substrate 11 in the third etching solution, the third etching solution reacts with the mask layer 16, and the third etching solution does not react with the first doped semiconductor thin film layer 14a, the first protective film layer 17 and the first intrinsic amorphous silicon layer 13, so that the mask layer 16 can be removed without damaging the first protective film layer 17, the first doped semiconductor thin film layer 14a and the first intrinsic amorphous silicon layer 13, thereby obtaining a plurality of first doped semiconductor layers 14 arranged at intervals and a plurality of protective sub-portions 17a correspondingly arranged on the side of the plurality of first doped semiconductor layers 14 away from the substrate 11, and at the same time, the passivation effect of the first intrinsic amorphous silicon layer 13 can be guaranteed.
[0082] In a specific example, the mask layer 16 can be a wet film that is resistant to alkali corrosion, for example, it can resist etching by alkaline solutions such as ammonia water, potassium hydroxide, and sodium hydroxide, and can be easily etched by acid solutions such as hydrochloric acid and sulfuric acid. In this way, the mask layer 16 can be removed by an acid solution without causing damage to the first protective film layer 17, the first doped semiconductor thin film layer 14a, and the first intrinsic amorphous silicon layer 13.
[0083] In some of these embodiments, see Figure 3 and Figure 5 In S40, a second doped semiconductor thin film layer 15a is formed on a side of the protection sub-portion 17a away from the substrate 11, so that the second doped semiconductor thin film layer 15a covers the protection sub-portion 17a and the first intrinsic amorphous silicon layer 13 not covered by the first doped semiconductor layer 14, and the protection sub-portion 17a and the second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11 are removed to obtain a second doped semiconductor layer 15 alternately distributed with the first doped semiconductor layer 14, specifically including:
[0084] S410, forming a second doped semiconductor thin film layer 15a on a side of the protection sub-portion 17a away from the substrate 11, so that the second doped semiconductor thin film layer 15a covers the protection sub-portion 17a and the first intrinsic amorphous silicon layer 13 not covered by the first doped semiconductor layer 14, and the sum of the thickness of the first doped semiconductor layer 14 and the thickness of the protection sub-portion 17a is greater than the thickness of the second doped semiconductor thin film layer 15a;
[0085] Specifically, the thickness of the second doped semiconductor thin film layer 15 a is 5 nm to 30 nm.
[0086] S420, removing the second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11;
[0087] Specifically, a wet process can be used to remove the second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11. Since the sum of the thickness of the first doped semiconductor layer 14 and the thickness of the protection sub-portion 17a is greater than the thickness of the second doped semiconductor thin film layer 15a, the second doped semiconductor thin film layer 15a located outside the area where the first doped semiconductor layer 14 is located will not be affected by the wet process.
[0088] S430, removing the protection sub-portion 17a to obtain the second doped semiconductor layer 15 that is alternately distributed with the first doped semiconductor layer 14, wherein the end surface of the second doped semiconductor layer 15 close to the first doped semiconductor layer 14 is in contact with the end surface of the first doped semiconductor layer 14 close to the second doped semiconductor layer 15;
[0089] Specifically, the protection sub-portion 17a can be removed by a wet process, and the etching solution can be selected according to the material properties of the protection sub-portion 17a, the first doped semiconductor layer 14 and the second doped semiconductor thin film layer 15a to ensure that the first doped semiconductor layer 14 and the second doped semiconductor thin film layer 15a are not damaged while the protection sub-portion 17a is removed.
[0090] In this embodiment, by making the sum of the thickness of the first doped semiconductor layer 14 and the thickness of the protective sub-portion 17a greater than the thickness of the second doped semiconductor thin film layer 15a, when the second doped semiconductor thin film layer 15a located on the side of the protective sub-portion 17a away from the substrate 11 is removed, the second doped semiconductor thin film layer 15a located outside the area where the first doped semiconductor layer 14 is located can be ensured not to be damaged, thereby achieving the patterning of the second doped semiconductor thin film layer 15a; by removing the protective sub-portion 17a, the second doped semiconductor thin film layer 15a attached to the side wall of the protective sub-portion 17a can be removed. The thin film layer 15a is peeled off and removed together with the protective sub-portion 17a, thereby improving the patterning accuracy of the second doped semiconductor thin film layer 15a, and obtaining the second doped semiconductor layer 15 that is alternately distributed with the first doped semiconductor layer 14; in addition, the end face of the second doped semiconductor layer 15 close to the first doped semiconductor layer 14 is in contact with the end face of the first doped semiconductor layer 14 close to the second doped semiconductor layer 15, which can increase the area of the first doped semiconductor layer 14 and the second doped semiconductor layer 15, increase the effective power generation area of the solar cell 10, and improve the conversion efficiency of the solar cell 10.
[0091] In some embodiments, in S420, removing the second doped semiconductor thin film layer 15a located on a side of the protection sub-portion 17a away from the substrate 11 includes:
[0092] Keeping the first surface of the substrate 11 at a third preset distance from the liquid surface of the fourth etching solution, so that the second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11 is immersed in the fourth etching solution and removed by the fourth etching solution;
[0093] Specifically, the fourth etching solution may be an alkaline solution, such as ammonia water or potassium hydroxide solution.
[0094] In this embodiment, the first surface of the substrate 11 is maintained at a third preset distance from the liquid surface of the fourth etching solution, so that the second doped semiconductor thin film layer 15a located on the side of the protection sub-portion 17a away from the substrate 11 is immersed in the fourth etching solution. Since the sum of the thicknesses of the first doped semiconductor layer 14 and the protection sub-portion 17a is greater than the thickness of the second doped semiconductor thin film layer 15a, the second doped semiconductor thin film layer 15a located outside the area where the first doped semiconductor layer 14 is located is not in contact with the fourth etching solution, thereby achieving patterning of the second doped semiconductor thin film layer 15a using a wet process, which can reduce the cost of patterning the second doped semiconductor thin film layer 15a, and further reduce the preparation cost of the solar cell 10.
[0095] In some embodiments, in S430, the protection sub-portion 17a is removed to obtain the second doped semiconductor layer 15 that is alternately distributed with the first doped semiconductor layer 14, including:
[0096] The substrate 11 is placed in a fifth etching solution, the fifth etching solution reacts with the protective sub-portion 17a, and the fifth etching solution does not react with the second doped semiconductor thin film layer 15a and the first doped semiconductor layer 14, so as to remove the protective sub-portion 17a, and obtain the second doped semiconductor layer 15 that is alternately distributed with the first doped semiconductor layer 14, and the end surface of the second doped semiconductor layer 15 close to the first doped semiconductor layer 14 is in contact with the end surface of the first doped semiconductor layer 14 close to the second doped semiconductor layer 15;
[0097] Specifically, the fifth etching solution may be a hydrofluoric acid solution.
[0098] In this embodiment, by placing the substrate 11 in the fifth etching solution, the fifth etching solution reacts with the protective sub-portion 17a, and the fifth etching solution does not react with the second doped semiconductor thin film layer 15a and the first doped semiconductor layer 14, so that the protective sub-portion 17a can be removed without damaging the second doped semiconductor thin film layer 15a and the first doped semiconductor layer 14, thereby obtaining the second doped semiconductor layer 15 that is alternately distributed with the first doped semiconductor layer 14, and the end surface of the second doped semiconductor layer 15 close to the first doped semiconductor layer 14 is in contact with the end surface of the first doped semiconductor layer 14 close to the second doped semiconductor layer 15.
[0099] In some of these embodiments, see Figure 4 and Figure 5 , the method for preparing a solar cell further comprises:
[0100] S50, forming a second intrinsic amorphous silicon layer 18, a third doped semiconductor layer 19 and an anti-reflection layer 20 in sequence on the second surface 112 of the substrate 11; the doping type of the third doped semiconductor layer 19 is the same as that of the substrate 11; the second surface 112 is arranged opposite to the first surface 111.
[0101] It is understandable that the first surface 111 may be a backlight surface, and the second surface 112 may be a light-receiving surface.
[0102] In the present embodiment, a second intrinsic amorphous silicon layer 18, a third doped semiconductor layer 19 and an anti-reflection layer 20 are sequentially formed on the second surface 112 of the substrate 11; the doping type of the third doped semiconductor layer 19 is the same as the doping type of the substrate 11; the second intrinsic amorphous silicon layer 18 can provide a chemical passivation effect, which can passivate the dangling bonds of the second surface 112 and reduce the defect state density of the second surface 112; the third doped semiconductor layer 19 can provide a field passivation effect, which can reduce the recombination of the second surface 112; the anti-reflection layer 20 can improve the light utilization rate of the solar cell 10, thereby effectively improving the conversion efficiency of the solar cell 10.
[0103] It should be noted that S50 may be located before S40. In this case, a mask protection layer needs to be formed on the side of the anti-reflection layer 20 away from the substrate 11, and the mask protection layer may be removed after S40. Preferably, S50 is located after S40, so that the second intrinsic amorphous silicon layer 18, the third doped semiconductor layer 19 and the anti-reflection layer 20 may be directly formed in sequence on the second surface 112 of the substrate 11, without the need to deposit a mask protection layer and remove the mask protection layer, thereby simplifying the preparation process of the solar cell 10, improving the preparation efficiency of the solar cell 10, and reducing the preparation cost of the solar cell 10.
[0104] In some of these embodiments, see Figure 4 and Figure 5 , the method for preparing a solar cell further comprises:
[0105] S60, forming a transparent conductive layer 21 covering the first doped semiconductor layer 14 and the second doped semiconductor layer 15, and forming an isolation groove 22 on the transparent conductive layer 21, so that the isolation groove 22 penetrates the transparent conductive layer 21 along the thickness direction of the substrate 11, and the orthographic projection of the isolation groove 22 on the substrate 11 partially overlaps with the orthographic projection of the adjacent first doped semiconductor layer 14 and the second doped semiconductor layer 15 on the substrate 11;
[0106] Specifically, the transparent conductive layer 21 can be isolated and scribed by laser to form an isolation groove 22 on the transparent conductive layer 21. The width of the isolation groove 22 can be 1um to 25um. The laser wavelength is selected to be 200nm to 500nm, the type is nanosecond laser, femtosecond laser or picosecond laser, and the laser frequency range is 10 12 Hz~10 19 Hz.
[0107] In this embodiment, a transparent conductive layer 21 covering the first doped semiconductor layer 14 and the second doped semiconductor layer 15 is formed, and an isolation groove 22 is formed on the transparent conductive layer 21, so that the isolation groove 22 penetrates the transparent conductive layer 21 along the thickness direction of the substrate 11, and the orthographic projection of the isolation groove 22 on the substrate 11 and the orthographic projection of the adjacent first doped semiconductor layer 14 and the second doped semiconductor layer 15 on the substrate 11 are partially overlapped. In this way, the isolation groove 22 can block the lateral conduction between the adjacent first doped semiconductor layer 14 and the second doped semiconductor layer 15, thereby reducing the probability of leakage. In addition, the transparent conductive layer 21 has good conductivity, which can improve the carrier transmission efficiency, thereby facilitating the improvement of the conversion efficiency of the solar cell 10.
[0108] In some of these embodiments, see Figure 5 In S10, a substrate 11 is provided, and a first intrinsic amorphous silicon layer 13 and a mask layer 16 are sequentially formed on a first surface of the substrate 11, and a plurality of grooves 16a which are spaced apart and expose the first intrinsic amorphous silicon layer 13 are formed on the mask layer 16, specifically comprising:
[0109] Pre-treating the substrate 11 so that the first surface of the substrate 11 is a polished surface and the second surface 112 of the substrate 11 is a suede structure;
[0110] A first intrinsic amorphous silicon layer 13 and a patterned mask layer 16 are sequentially formed on the first surface of the substrate 11 . The patterned mask layer 16 includes a plurality of grooves 16 a which are spaced apart and expose the first intrinsic amorphous silicon layer 13 .
[0111] In some embodiments, the substrate 11 is pre-treated so that the first surface of the substrate 11 is a polished surface and the second surface 112 of the substrate 11 is a suede structure, specifically including:
[0112] Cleaning the substrate 11 to remove organic matter, metal ions and a damaged layer on the substrate 11;
[0113] A second protective film layer is formed on the first surface of the substrate 11; specifically, the material of the second protective film layer may be silicon oxynitride;
[0114] A suede structure is formed on the second surface 112 of the substrate 11;
[0115] The second protective film layer is removed.
[0116] Second, see Figure 6The embodiment of the present application provides a solar cell 10, comprising a substrate 11, a first intrinsic amorphous silicon layer 13, a first doped semiconductor layer 14 and a second doped semiconductor layer 15; the first intrinsic amorphous silicon layer 13 is arranged on the first surface of the substrate 11; the first doped semiconductor layer 14 is arranged on a side of the first intrinsic amorphous silicon layer 13 away from the substrate 11; the second doped semiconductor layer 15 is arranged on a side of the first intrinsic amorphous silicon layer 13 away from the substrate 11, and the second doped semiconductor layer 15 and the first doped semiconductor layer 14 are alternately distributed; the end surface of the first doped semiconductor layer 14 close to the second doped semiconductor layer 15 is in contact with the end surface of the second doped semiconductor layer 15 close to the first doped semiconductor layer 14.
[0117] The solar cell 10 in the embodiment of the present application can be prepared by the preparation method in the first aspect, so that the difficulty and cost of the preparation process of the solar cell 10 can be reduced, the preparation efficiency of the solar cell 10 can be improved, and it is beneficial to the mass production of the solar cell 10; in addition, the area ratio of the first doped semiconductor layer 14 and the second doped semiconductor layer 15 can be maintained within a reasonable range, and the first doped semiconductor layer 14 and the second doped semiconductor layer 15 have a larger area, thereby increasing the effective power generation area of the solar cell 10 and improving the conversion efficiency of the solar cell 10.
[0118] In a third aspect, the embodiments of the present application provide a photovoltaic module, comprising the solar cell 10 in any of the above embodiments, so as to improve the efficiency of the photovoltaic module.
[0119] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0120] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a solar cell, characterized in that: include: Providing a substrate, and sequentially forming a first intrinsic amorphous silicon layer and a mask layer on a first surface of the substrate, and forming a plurality of grooves on the mask layer that are spaced apart and expose the first intrinsic amorphous silicon layer; forming a first doped semiconductor thin film layer and a first protective film layer in sequence on a side of the mask layer away from the substrate, so that the first doped semiconductor thin film layer covers the mask layer and the first intrinsic amorphous silicon layer exposed by the groove, and the first protective film layer covers the first doped semiconductor thin film layer; The mask layer and the first protective film layer and the first doped semiconductor film layer located on the side of the mask layer away from the substrate are removed to obtain a plurality of first doped semiconductor layers distributed at intervals and a plurality of protective sub-portions correspondingly arranged on the side of the plurality of first doped semiconductor layers away from the substrate; A second doped semiconductor thin film layer is formed on a side of the protection sub-portion away from the substrate, so that the second doped semiconductor thin film layer covers the protection sub-portion and the first intrinsic amorphous silicon layer not covered by the first doped semiconductor layer, and the protection sub-portion and the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate are removed to obtain a second doped semiconductor layer alternately distributed with the first doped semiconductor layer.
2. The method for preparing a solar cell according to claim 1, characterized in that: The step of sequentially forming a first doped semiconductor thin film layer and a first protective film layer on a side of the mask layer away from the substrate, so that the first doped semiconductor thin film layer covers the mask layer and the first intrinsic amorphous silicon layer exposed by the groove, and the first protective film layer covers the first doped semiconductor thin film layer, comprises: The sum of the thickness of the first doped semiconductor thin film layer and the thickness of the first protective film layer is made smaller than the thickness of the mask layer.
3. The method for preparing a solar cell according to claim 2, characterized in that: The step of removing the mask layer, the first protective film layer and the first doped semiconductor film layer located on a side of the mask layer away from the substrate comprises: removing the first protective film layer and the first doped semiconductor thin film layer located on a side of the mask layer away from the substrate; The mask layer is then removed to obtain a plurality of first doped semiconductor layers that are spaced apart and a plurality of protection sub-portions that are arranged one by one on a side of the plurality of first doped semiconductor layers away from the substrate.
4. The method for preparing a solar cell according to claim 3, characterized in that: The step of removing the first protective film layer and the first doped semiconductor thin film layer located on a side of the mask layer away from the substrate comprises: Keeping a first preset distance between the first surface of the substrate and the liquid surface of the first etching solution, so that the first protective film layer located on the side of the mask layer away from the substrate is immersed in the first etching solution and removed by the first etching solution; The first surface of the substrate is maintained at a second preset distance from the liquid surface of the second etching solution, so that the first doped semiconductor thin film layer located on the side of the mask layer away from the substrate is immersed in the second etching solution and removed by the second etching solution.
5. The method for preparing a solar cell according to claim 3, characterized in that: The step of removing the mask layer to obtain a plurality of first doped semiconductor layers arranged at intervals and a plurality of protection sub-portions arranged one by one on a side of the plurality of first doped semiconductor layers away from the substrate includes: The substrate is placed in a third etching solution, the third etching solution reacts with the mask layer, and the third etching solution does not react with the first doped semiconductor thin film layer, the first protective film layer and the first intrinsic amorphous silicon layer, so as to remove the mask layer and obtain a plurality of first doped semiconductor layers arranged at intervals and a plurality of protective sub-portions correspondingly arranged on the side of the plurality of first doped semiconductor layers away from the substrate.
6. The method for preparing a solar cell according to claim 1, characterized in that: The step of forming a second doped semiconductor thin film layer on a side of the protection sub-portion away from the substrate, making the second doped semiconductor thin film layer cover the protection sub-portion and the first intrinsic amorphous silicon layer not covered by the first doped semiconductor layer, and removing the protection sub-portion and the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate to obtain a second doped semiconductor layer alternately distributed with the first doped semiconductor layer, comprises: forming a second doped semiconductor thin film layer on a side of the protection sub-portion away from the substrate, so that the second doped semiconductor thin film layer covers the protection sub-portion and the first intrinsic amorphous silicon layer not covered by the first doped semiconductor layer, and the sum of the thickness of the first doped semiconductor layer and the thickness of the protection sub-portion is greater than the thickness of the second doped semiconductor thin film layer; removing the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate; The protection sub-portion is removed to obtain a second doped semiconductor layer that is alternately distributed with the first doped semiconductor layer, and an end surface of the second doped semiconductor layer close to the first doped semiconductor layer is in contact with an end surface of the first doped semiconductor layer close to the second doped semiconductor layer.
7. The method for preparing a solar cell according to claim 6, characterized in that: The step of removing the second doped semiconductor thin film layer located on a side of the protection sub-portion away from the substrate comprises: The first surface of the substrate is kept at a third preset distance from the liquid surface of the fourth etching solution, so that the second doped semiconductor film layer located on the side of the protection sub-portion away from the substrate is immersed in the fourth etching solution and removed by the fourth etching solution.
8. The method for preparing a solar cell according to claim 6, characterized in that: The step of removing the protection sub-portion to obtain a second doped semiconductor layer alternately distributed with the first doped semiconductor layer comprises: The substrate is placed in a fifth etching solution, the fifth etching solution reacts with the protective sub-portion, and the fifth etching solution does not react with the second doped semiconductor thin film layer and the first doped semiconductor layer, so as to remove the protective sub-portion and obtain a second doped semiconductor layer that is alternately distributed with the first doped semiconductor layer, and the end surface of the second doped semiconductor layer close to the first doped semiconductor layer is in contact with the end surface of the first doped semiconductor layer close to the second doped semiconductor layer.
9. The method for preparing a solar cell according to claim 1, characterized in that: The method for preparing the solar cell further comprises: A second intrinsic amorphous silicon layer, a third doped semiconductor layer and an anti-reflection layer are sequentially formed on the second surface of the substrate; the doping type of the third doped semiconductor layer is the same as the doping type of the substrate; and the second surface is arranged opposite to the first surface.
10. The method for preparing a solar cell according to claim 1, characterized in that: The method for preparing the solar cell further comprises: A transparent conductive layer covering the first doped semiconductor layer and the second doped semiconductor layer is formed, and an isolation groove is formed on the transparent conductive layer, so that the isolation groove penetrates the transparent conductive layer along the thickness direction of the substrate, and the orthographic projection of the isolation groove on the substrate partially overlaps with the orthographic projections of the adjacent first doped semiconductor layer and the second doped semiconductor layer on the substrate.
11. A solar cell, characterized in that: include: substrate; A first intrinsic amorphous silicon layer, disposed on a first surface of the substrate; A first doped semiconductor layer, disposed on a side of the first intrinsic amorphous silicon layer away from the substrate; A second doped semiconductor layer is disposed on a side of the first intrinsic amorphous silicon layer away from the substrate, and the second doped semiconductor layer and the first doped semiconductor layer are alternately distributed; An end surface of the first doped semiconductor layer close to the second doped semiconductor layer contacts an end surface of the second doped semiconductor layer close to the first doped semiconductor layer.
12. A photovoltaic module, characterized in that: Comprising the solar cell according to claim 11.