Silicon wafer, battery piece and photovoltaic module

Abstract

The invention discloses a silicon wafer, a battery piece and a photovoltaic module, and relates to the technical field of silicon wafer manufacturing. The silicon wafer is provided with two opposite first edges and two opposite second edges, one first edge is connected with the two adjacent second edges through first chamfers, and the other first edge is connected with the two adjacent second edges through second chamfers; the ratio of the length of the first side to the length of the second side is 1.2-6; and the length of the first chamfer is greater than that of the second chamfer. After the silicon wafer is prepared into a battery piece, because the battery piece is provided with the first chamfer and the second chamfer which can assist in distinguishing the positive electrode and the negative electrode, marks do not need to be additionally arranged on the silicon wafer, and the processing efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon wafers, and in particular to a silicon wafer, a battery wafer and a photovoltaic module. Background Art

[0002] Currently, most solar cells use single crystal silicon wafers as their raw materials. The cost and photoelectric conversion efficiency of single crystal silicon wafers directly affect the development of solar cells. In order to further increase the photoelectric conversion efficiency of the battery, the existing back-contact battery cells have both positive and negative electrodes set on the back of the battery. Since the P / N area is on the same side of the battery cell, the positive and negative electrodes of the battery cell cannot be identified when the battery cells are connected in series. Usually, it is necessary to set separate marks on the battery cell. However, this method increases the battery process steps and affects the efficiency of battery component processing. Summary of the invention

[0003] The object of the present invention is to provide a silicon wafer, a battery wafer and a photovoltaic module, so as to save the need for a separate marking process and improve processing efficiency.

[0004] In a first aspect, the present invention provides a silicon wafer, the silicon wafer having two opposite first sides and two opposite second sides, wherein one first side is connected to two adjacent second sides via a first chamfer, and the other first side is connected to two adjacent second sides via a second chamfer; the ratio of the length of the first side to the length of the second side is 1.2 to 6;

[0005] The length of the first chamfer is greater than the length of the second chamfer.

[0006] When the above technical solution is adopted, the silicon wafer has two first chamfers located on a first side of the silicon wafer, and a second chamfer located on another first side, the ratio of the first side to the second side is 1.2-6, and the length of the second chamfer is less than the length of the first chamfer. When such a silicon wafer is used to prepare a battery cell, since the length of the first side and the second side of the silicon wafer is 1.2-6, the utilization rate of the silicon rod can be effectively improved during the manufacturing process of the silicon wafer; when the component version is determined, the space of the container can be fully utilized; at the same time, since the opposite sides of the back contact battery cell have the first chamfer and the second chamfer respectively, the length of the first chamfer is greater than the length of the second chamfer, which can easily identify the placement direction of the battery cell, so as to assist in the alignment of the PN zones between multiple battery cells and distinguish the positive and negative poles of the battery cells. Therefore, there is no need to set additional marks on the silicon wafer or the battery cell, which eliminates the marking process, saves labor time, and improves processing efficiency.

[0007] In some possible implementations, a projection length of the first chamfer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

[0008] When the above technical solution is adopted, due to excessive thermal stress at the chamfer, when the projection length of the first chamfer is less than 0.05mm, the projection length of the first chamfer is too small, which will lead to an increase in the area of ​​the original silicon rod removed during the silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the silicon wafer processing cost; when the projection length of the first chamfer is greater than 9mm, due to the excessive chamfer of the silicon wafer, using such silicon wafers to prepare solar cells will result in a large blank area between the solar cells, affecting the power generation of the photovoltaic module.

[0009] In some possible implementations, the projection length of the second chamfer is greater than 0 and less than or equal to 8.5 mm.

[0010] When adopting the above technical solution, the projection length of the second chamfer is greater than 0 to prevent the chamfer from being too sharp, which may cause the stress at the edge of the silicon wafer to not be released in time, and increase the fragmentation rate of the silicon wafer during transportation or transfer; the projection length of the second chamfer is less than or equal to 8.5 mm to prevent the chamfer of the silicon wafer from being too large, resulting in a large blank area between the battery cells, which affects the power generation of the photovoltaic module.

[0011] In some possible implementations, a difference between a projection length of the first chamfer on the first side and a projection length of the first chamfer on the second side is 0 mm to 2 mm;

[0012] And / or, a difference between a projection length of the second chamfer on the first side and a projection length of the second chamfer on the second side is 0 mm to 1 mm.

[0013] When the above technical solution is adopted, the projections of the first chamfer on the first side and the second side are different. In view of the different concentration levels of stress on different sides of the silicon wafer, the projection difference of the first chamfer on different sides is set within 0 to 2 mm, which can reasonably alleviate the stress at the edge of the silicon wafer, prevent the projection difference of the first chamfer on the first side and the second side from being large, and reduce the utilization rate of the silicon rods used for processing silicon.

[0014] In some possible implementations, a projection length of the first chamfer on the first side is 0.05 mm to 9 mm, and a projection length of the first chamfer on the second side is 0.05 mm to 7 mm;

[0015] And / or, the projection length of the second chamfer on the first side is 0.05 mm to 5 mm, and the projection length of the second chamfer on the second side is 0.05 mm to 5 mm.

[0016] When the above technical solution is adopted, the projection length of the first chamfer on the first side can be greater than the projection length of the first chamfer on the second side, and the projection length of the second chamfer on the first side can be less than / equal to the projection length of the second chamfer on the second side. Since the projection of the first chamfer on the long side is longer, the problem of edge stress concentration corresponding to the long side is effectively alleviated; the projection on the second side is shorter, which can alleviate the stress concentration degree of the second edge. Since the stress dispersion degree of each chamfer is similar and the stress of the silicon wafer as a whole is relatively uniform, warping and uneven strength distribution can be effectively avoided, and at the same time, too much blank space at the component end is prevented, which affects the power generation of the photovoltaic component.

[0017] In some possible implementations, a difference between a projection length of the first chamfer on the first side and a projection length of the second chamfer on the first side is 0.05 mm to 8 mm;

[0018] And / or, a difference between a projection length of the first chamfer on the second side and a projection length of the second chamfer on the second side is 0.05 mm to 8 mm.

[0019] When the above technical solution is adopted, the difference is within this range, which can facilitate the naked eye to observe the size relationship between the first chamfer and the second chamfer, and prevent the difference from being less than 0.05mm, which makes it difficult to identify the positive and negative arrangement order of the subsequently prepared battery cell. The difference is greater than 8mm, resulting in a projected length of the first chamfer that is too large. During the silicon wafer preparation process, more silicon rods are removed, the utilization rate of the silicon rods is low, and the cost of silicon wafer preparation is increased.

[0020] In some possible implementations, the first chamfer is an arc chamfer or a linear chamfer; and / or, the second chamfer is an arc chamfer or a linear chamfer. When the first chamfer and the second chamfer are arc chamfers, less of the silicon rod is removed, thereby improving the utilization rate of silicon wafer cutting, and the arc chamfer allows a smooth transition between the first edge and the second edge, preventing the problem of excessive edge stress and excessive silicon wafer fragmentation during transportation or processing of the silicon wafer; when the first chamfer and the second chamfer are linear chamfers, compared with the arc chamfer, the processing is simple, the processing efficiency is improved, and the processing cost is reduced; in addition, when the projection length is the same, the battery cells prepared from the linear chamfered silicon wafers have a small blank space between the battery cells when they are processed into components, and the power generation of the components is increased.

[0021] In some possible implementations, the length of the first side is 182 mm to 300 mm, and the length of the second side is 83 mm to 150 mm. When preparing cells, silicon wafers of this size do not need to be laser-sliced, which improves the passivation effect of the cell edge and improves the photoelectric conversion efficiency of the cell. It is suitable for cells of various sizes and different types of photovoltaic modules.

[0022] In some possible implementations, the surface of the silicon wafer has a plurality of first lines arranged at intervals, the spacing between two adjacent first lines is 1 mm to 4 mm, and the distance between the highest point and the lowest point on the first lines is 0.5 mm to 4 mm. The first lines are cutting lines formed on the surface of the silicon wafer when the silicon wafer is cut. When the spacing between adjacent first lines is less than this range, the first lines are relatively dense, which reduces the mechanical strength of the silicon wafer. If the spacing between the first lines is greater than this range, the surface of the silicon wafer is smooth, which makes it easy for the conductive interconnect to slip. When the distance between the highest point and the lowest point of the first lines is less than 0.5 mm, the processing efficiency of the silicon wafer is affected and the manufacturing cost of the silicon wafer is increased. When the distance between the highest point and the lowest point of the first lines is greater than 4 mm, the flatness of the surface of the silicon wafer is affected.

[0023] In some possible implementations, the spacing between two adjacent first lines at the first chamfer is 0.05 mm to 3 mm, and / or the spacing between two adjacent first lines at the second chamfer is 0.1 mm to 4 mm. If the spacing between two adjacent first lines at the chamfer is less than 0.05 mm, the first lines at the chamfer are denser, reducing the mechanical strength of the chamfer; if the spacing between two adjacent first lines at the chamfer is greater than 4 mm, the surface flatness of the silicon wafer will be affected.

[0024] In a second aspect, the present invention further provides a battery cell, which is prepared from the silicon wafer described in any one of the above items, and the surface of the battery cell has a first electrode, and the first electrode extends along a first side of the silicon wafer.

[0025] In some possible implementations, the first electrode is a secondary gate line.

[0026] Since the battery cell is prepared from the silicon wafer of the first aspect, it has the same beneficial effects as the first aspect and will not be described in detail.

[0027] In some possible implementations, the surface of the battery cell has a first texture, and the first texture and the first electrode extend in the same direction, thereby reducing the risk of gate breakage of the first electrode caused by the first texture.

[0028] In a third aspect, the present invention further provides a photovoltaic module, comprising at least two cells and at least one conductive interconnection member, wherein the conductive interconnection member is connected between two adjacent cells, and the cell is the cell described above. Since the photovoltaic module comprises the cell of the second aspect, it has the same beneficial effects as the first and second aspects, which will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1 A schematic diagram of the structure of a silicon wafer provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of a structure in which a silicon wafer surface has a first texture provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of a process of a silicon wafer preparation method provided by an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of another process of preparing a silicon wafer provided in an embodiment of the present invention.

[0034] Figure numerals: 1 is a round silicon rod, 2 is a rectangular silicon rod, 21 is a first surface, 22 is a second surface, 23 is a cutting plane, 3 is a half rod, 4 is a silicon wafer, 10 is a first edge, 20 is a second edge, 30 is a first chamfer, 40 is a second chamfer, and 50 is a first texture. DETAILED DESCRIPTION

[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0038] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0039] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] At present, most solar cells use single crystal silicon wafers as their raw materials. The cost and photoelectric conversion efficiency of single crystal silicon wafers directly affect the development of solar cells. Solar cells usually cut single crystal silicon rods into square rods, cut the square rods to prepare a whole silicon wafer, prepare multiple film layers on the whole silicon wafer, and cut the whole cell wafer to cut the whole solar cell into at least two sliced ​​solar cell wafers, such as two half-pieces. Afterwards, the sliced ​​solar cells are used to make photovoltaic modules.

[0041] Currently, solar cells are usually cut by using laser technology to slice the entire cell into small pieces. The small silicon wafers formed in this way will form laser damage and defects on the edge of the cell due to the action of the laser, affecting the passivation performance of the cell, and further affecting the photoelectric conversion efficiency of the solar cell. Therefore, a cell with good edge consistency is urgently needed.

[0042] In order to prepare solar cells with good edge consistency, one method is to prepare silicon wafers into small pieces. Since the silicon wafer ends are cut using diamond wire to obtain small silicon wafers, the edge passivation effect of such silicon wafers is good, which can improve the photoelectric conversion efficiency of solar cells.

[0043] like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a silicon wafer 4, which has two opposite first sides 10 and two opposite second sides 20, wherein one of the first sides 10 is connected to the two second sides 20 by a first chamfer 30, and the other first side 10 is connected to the two second sides 20 by a second chamfer 40; the ratio of the length of the first side 10 to the length of the second side 20 is 1.2 to 6, and the ratio can be specifically 1.2, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, etc. The length of the first chamfer is greater than the length of the second chamfer. When the first chamfer and / or the second chamfer is an arc chamfer, the length of the arc chamfer refers to the distance of the line between the two end points of the arc chamfer, and when the first chamfer and / or the second chamfer is a linear chamfer, the length of the linear chamfer refers to the length of the straight line between the two end points of the linear chamfer.

[0044] The projection length of the first chamfer refers to the projection of the first chamfer on the first side and / or the second side, the projection length of the second chamfer refers to the projection of the second chamfer on the first side and / or the second side, and the projection length of the first chamfer is greater than the projection length of the second chamfer, which means that the projection length of the first chamfer 30 on the first side 10 is greater than the projection length of the second chamfer 40 on the first side 10, and the projection length of the first chamfer 30 on the second side 20 is greater than or equal to the projection length of the second chamfer 40 on the second side 20; or, the projection length of the first chamfer 30 on the first side 10 is greater than or equal to the projection length of the second chamfer 40 on the first side 10, and the projection length of the first chamfer 30 on the second side 20 is greater than the projection length of the second chamfer 40 on the second side 20. That is, when the projection length of the first chamfer 30 on the first side 10 is greater than the projection length of the second chamfer 40 on the first side 10, the projection length of the first chamfer 30 on the second side 20 cannot be less than the projection length of the second chamfer 40 on the second side 20, so that the projection length of the first chamfer 30 is greater than the projection length of the second chamfer 40. Alternatively, that is, when the projection length of the first chamfer 30 on the second edge 20 is greater than the projection length of the second chamfer 40 on the second edge 20, the projection length of the first chamfer 30 on the first edge 10 cannot be less than the projection length of the second chamfer 40 on the first edge 10, so that the projection length of the first chamfer 30 is greater than the projection length of the second chamfer 40.

[0045] It should be noted that the projection length of the silicon wafer chamfer refers to the projection length on the first side or the second side of the silicon wafer after the edge or corner of the silicon wafer is chamfered. The shape of the silicon wafer chamfer can be an arc chamfer or a linear chamfer, wherein the linear chamfer includes a right angle, an oblique angle, etc.; the arc chamfer includes a circular chamfer, an arc-shaped chamfer, etc. When the chamfer shape is a linear chamfer, the projection length described in this application refers to the projection length of the linear chamfer on the first side or the second side.

[0046] The projection length of the chamfer can be measured by optical measurement, scanning microscope or other measurement methods to evaluate the size of the chamfer.

[0047] In the case of adopting the above technical solution, the silicon wafer has two first chamfers 30 located on one first side 10 of the silicon wafer 4, and two second chamfers 40 located on the other first side 10. Comparing the lengths of the first chamfers 30 and the second chamfers 40, the length of the first chamfer 30 is greater than the length of the second chamfer 40, that is, compared with the first chamfer 30 and the second chamfer 40, the first chamfer 30 is a larger chamfer and the second chamfer 40 is a smaller chamfer. When such a silicon wafer is used to prepare a cell, since the two opposite sides of the cell have the first chamfer 30 and the second chamfer 40 respectively, and the length of the first chamfer 30 is greater than the length of the second chamfer 40, the placement direction of the cell can be easily identified, so as to assist in the alignment of the PN regions between multiple cells and distinguish the positive and negative electrodes. For example, when multiple cells are arranged to form a battery string of a component, each cell is placed in the same direction, and the cells are aligned in the order of the first chamfer 30, the second chamfer 40, the first chamfer 30, and the second chamfer 40 in a row, the P region of the previous cell is automatically aligned with the P region or N region of the next cell, and the appropriate conductive interconnection parts and string welding process can be conveniently selected to obtain a battery component. Therefore, there is no need to set additional marks on the silicon wafer or cell, which eliminates the marking process, saves labor time, and improves processing efficiency. At the same time, the ratio of the length of the first side 10 of the silicon wafer to the length of the second side 20 is 1.2 to 6, which can effectively improve the utilization rate of the silicon rod in the preparation process of the silicon wafer; when the component version is determined, the space of the container can be fully utilized.

[0048] In some embodiments, the projection length of the first chamfer 30 is greater than or equal to 0.05 mm and less than or equal to 9 mm, that is, the projection length of the first chamfer 30 on the first side 10 and / or the second side 20 is greater than or equal to 0.5 mm and less than or equal to 9 mm. Specifically, the projection length of the first chamfer 30 can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, etc.

[0049] When the above technical solution is adopted, due to excessive thermal stress at the chamfer, when the projection length of the first chamfer 30 is less than 0.05mm, the projection length of the first chamfer 30 is too small, which will lead to an increase in the area of ​​the original silicon rod removed during the silicon wafer processing, affecting the utilization rate of the silicon rod and increasing the silicon wafer processing cost; when the projection length of the first chamfer 30 is greater than 9mm, due to the excessive chamfer of the silicon wafer, using such a silicon wafer to prepare a solar cell will result in a large blank area between the solar cells, affecting the power generation of the photovoltaic module.

[0050] In some embodiments, the projection length of the second chamfer 40 is greater than 0 and less than or equal to 8.5 mm. That is, the projection length of the second chamfer 40 on the first side 10 and / or the second side 20 is greater than 0 and less than or equal to 8.5 mm. Specifically, the projection length of the second chamfer 40 can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 8.5 mm, etc.

[0051] When adopting the above technical solution, the projection length of the second chamfer 40 is greater than 0, which prevents the chamfer from being too sharp, resulting in the stress at the edge of the silicon wafer cannot be released in time, and increases the fragmentation rate of the silicon wafer during transportation or transfer; the projection length of the second chamfer is less than or equal to 8.5mm, which prevents the chamfer of the silicon wafer from being too large, resulting in a large blank area between the battery cells, affecting the power generation of the photovoltaic module.

[0052] Further, in the present embodiment, the difference between the projection length of the first chamfer 30 on the first side 10 and the projection length on the second side 20 is 0 mm to 2 mm, specifically, the difference may be 0, 0.2 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.5 mm, 1.7 mm, 2 mm, etc. That is, the projection length of the first chamfer 30 on the first side 10 and the projection length on the second side 20 may be the same or different. And / or, the difference between the projection length of the second chamfer 40 on the first side 10 and the projection length on the second side 20 is 0 mm to 1 mm, specifically, the difference may be 0, 0.2 mm, 0.5 mm, 0.8 mm, 1 mm, etc. That is, the projection length of the second chamfer 40 on the first side 10 and the projection length on the second side 20 may be the same or different. When the projection lengths of the chamfer on the first side and the second side are the same, they can be referred to as the projection length of the first chamfer 30 or the projection length of the second chamfer 40, and the processing technology of the first chamfer 30 and the second chamfer 40 is simplified. When the projection lengths of the chamfer on the first side and the second side are different, the projection length of the first chamfer 30 on the first side 10 can be greater than the projection length of the first chamfer 30 on the second side 20, and the projection length of the second chamfer 40 on the first side 10 can be greater than / equal to the projection length of the second chamfer 40 on the second side 20. Since the first side 10 is the long side of the silicon wafer and the second side 20 is the short side of the silicon wafer, that is, the projection of the chamfer on the long side is longer and the projection on the short side is shorter, so that the projection of the first chamfer on the first side and the second side is different, combined with the different concentration of stress on different sides of the silicon wafer, the projection difference of the first chamfer on different sides is set within 0-2mm, which can reasonably relieve the stress on the edge of the silicon wafer, prevent the large difference in the projection of the first chamfer on the first side and the second side, and reduce the utilization rate of the silicon rod used for processing silicon.

[0053] Exemplarily, the projection length of the first chamfer 30 on the first side 10 is 0.05 mm to 9 mm, and specifically can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, 5.5 mm, 6 mm, 6.5 mm, 7 mm, 7.5 mm, 8 mm, 8.5 mm, 9 mm, etc. The projection length of the first chamfer 30 on the second side 20 is 0.05 mm to 7 mm, and specifically can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, etc. As long as the projection length of the first chamfer 30 on the first side 10 is greater than the projection length on the second side 20.

[0054] Exemplarily, the projection length of the second chamfer 40 on the first side 10 is 0.05 mm to 5 mm, and specifically can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, etc. The projection length of the second chamfer on the second side is 0.05 mm to 5 mm, and specifically can be 0.05 mm, 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, etc. As long as the projection length of the second chamfer 40 on the first side 10 is greater than the projection length on the second side 20.

[0055] When the above technical solution is adopted, the projection length of the first chamfer on the first side can be greater than the projection length of the first chamfer on the second side, and the projection length of the second chamfer on the first side can be less than / equal to the projection length of the second chamfer on the second side. Since the projection of the first chamfer on the long side is longer, the problem of edge stress concentration corresponding to the long side is effectively alleviated; the projection on the short side is shorter, which can alleviate the stress concentration on the short edge while preventing the projection on the short side from being too long, resulting in too much blank space at the component end, affecting the power generation of the photovoltaic component.

[0056] In some embodiments, the difference between the projection length of the first chamfer 30 on the first side 10 and the projection length of the second chamfer 40 on the first side 10 is 0.05mm to 8mm, and the difference can specifically be 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 8mm, etc.; indicating that the projection length of the first chamfer 30 on the first side 10 is greater than the projection length of the second chamfer 40 on the first side 10.

[0057] And / or, the difference between the projection length of the first chamfer 30 on the second side 20 and the projection length of the second chamfer 40 on the second side 20 is 0.05mm~8mm, and the difference can specifically be 0.05mm, 0.1mm, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 6mm, 7mm, 8mm, etc.; indicating that the projection length of the first chamfer 30 on the second side 20 is greater than the projection length of the second chamfer 40 on the second side 20.

[0058] The above difference is within this range, which can facilitate the naked eye to observe the size relationship between the first chamfer 30 and the second chamfer 40. If the difference is less than 0.05mm, it is not easy to identify the positive and negative arrangement order of the battery sheet prepared by the silicon wafer. If the difference is greater than 8mm, the projection length of the first chamfer 30 is too large, and in the process of silicon wafer preparation, more silicon rods are removed, the utilization rate of silicon rods is low, and the cost of silicon wafer preparation is increased. Or because the difference is too large, the second chamfer 40 is too small, which causes the stress concentration of the corners of the silicon wafer 4 and increases the risk of fragmentation. Therefore, the projection lengths of the first chamfer and the second chamfer on the first side and the second side of the silicon wafer are respectively within the above range, which can identify the size relationship of the chamfers, improve material utilization, and reduce the risk of fragmentation.

[0059] like Figure 1 and Figure 2 As shown, in some embodiments, the first chamfer 30 is an arc chamfer or a linear chamfer; and / or, the second chamfer 40 is an arc chamfer or a linear chamfer. That is, the first chamfer 30 and the second chamfer 40 can both be arc chamfers or both be linear chamfers, or the first chamfer 30 is one of the arc chamfers or the linear chamfers, and the second chamfer 40 is the other of the arc chamfers or the linear chamfers. When the first chamfer 30 and the second chamfer 40 are both the same type of chamfers, it is convenient to use the same grinding process to grind the first chamfer 30 and the second chamfer 40. Of course, when the first chamfer 30 and the second chamfer 40 are different types of chamfers, the method of processing the chamfers can be selected according to needs.

[0060] When the first chamfer 30 and the second chamfer 40 are arc-shaped chamfers, the projection length of the arc-shaped chamfers on the first side 10 and the second side 20 is the projection length.

[0061] When the chamfer is set to an arc chamfer, less part of the silicon rod is removed, thereby improving the utilization rate of silicon wafer cutting. Since the first edge 10 and the second edge 20 adopt an arc chamfer for a smooth transition, it can prevent the silicon wafer from having excessive edge stress and excessive silicon wafer fragmentation rate during transportation or processing.

[0062] When the first chamfer 30 and the second chamfer 40 are linear chamfers, the size of the linear chamfer can be expressed by the bevel length of the linear chamfer, that is, the projection length of the chamfer. Compared with the arc chamfer, the linear chamfer is simple to process, which improves the processing efficiency and reduces the processing cost. In addition, when the projection length is the same, the solar cells prepared from the silicon wafers with linear chamfers have small blank areas between the solar cells when they are processed into components, and the power generation of the components is high.

[0063] In some embodiments, the length of the first side 10 is 182 mm to 300 mm. Due to the presence of the chamfer, the length of the first side 10 can be represented by the distance between the two opposite second sides 20, that is, the sum of the length of the first side 10 and the projection length of the two first chamfers 30 on the first side 10 is 182 mm to 300 mm, which is defined as the long side distance. The long side distance can be 182 mm, 185 mm, 190 mm, 195 mm, 200 mm, 205 mm, 210 mm, 220 mm, 230 mm, 240 mm, 250 mm, 270 mm, 290 mm, 300 mm, etc.; the second side 20 The length of the second side 20 is 83mm~150mm. Due to the existence of the chamfer, the length of the second side 20 can be obtained by the spacing between the two opposite first sides 10 is 83mm~150mm, that is, the sum of the length of the second side 20, the projection length of the first chamfer 30 on the second side 20 and the projection length of the second chamfer 40 on the second side 20 is 83mm~150mm, which is defined as the short margin. The short margin can be specifically 83mm, 85mm, 90mm, 91mm, 96mm, 100mm, 105mm, 110mm, 115mm, 120mm, 125mm, 135mm, 145mm, 150mm, etc.

[0064] The technicians in this field select the first side 10 and the second side 20 within the above-mentioned length range. Compared with other side lengths, the utilization rate of the silicon rod is higher. At the same time, when such silicon wafers are used to prepare components, the blank area between the battery cells is small, and the size of the container can be maximized, thereby improving the utilization rate of the component-end container.

[0065] The silicon rod utilization data corresponding to silicon wafers with different margins and first chamfers 30 and second chamfers 40 of different sizes are shown in Table 1 below, wherein the silicon rod utilization is the ratio of the area of ​​one side of the silicon wafer 4 prepared after slicing to the area of ​​the circular end face of the circular silicon rod 1 parallel to the slicing direction.

[0066] Table 1. Silicon rod utilization rate corresponding to the projection length of different chamfers on silicon wafers with different margins

[0067]

[0068] According to the size of the silicon wafer 4 in the above embodiment and the data in Table 1, it can be seen from Example 1 and Comparative Example 1, as well as from Example 2 and Comparative Example 2 that, for the same silicon wafer size, when the projection length of the chamfer is different, the utilization rate of the silicon rod is relatively high. From Example 2 and Example 3, when the projection length of the chamfer is the same, the larger the size of the silicon wafer, the higher the utilization rate of the silicon rod; from Example 4 and Comparative Example 3, when the projection length of the chamfer is the same, as the silicon wafer size exceeds the range of the present application, the utilization rate of the silicon rod decreases; thus, it can be concluded that within the silicon wafer size range of the present application, when the projection length of the chamfer is different, the utilization rate of the silicon rod is relatively high.

[0069] like Figure 2 As shown, in some embodiments, the surface of the silicon wafer has a plurality of first lines 50 arranged at intervals, and the spacing between two adjacent first lines 50 is 1mm to 4mm. Specifically, the spacing between two adjacent first lines 50 is 1mm, 2mm, 3mm, 4mm, etc. The distance between the highest point and the lowest point on the first line 50 is 0.5mm to 4mm. Specifically, the distance between the highest point and the lowest point on the first line 50 can be 0.5mm, 1mm, 2mm, 3mm, 4mm, etc. It should be noted that the first lines 50 are formed on the surface of the silicon wafer by grinding between the cutting line and the silicon wafer surface during the slicing process. Since the silicon rod is fed relative to the cutting wire net, the cutting line is subjected to pressure from the silicon rod, and the cutting line is bent to a certain extent in the feeding direction while reciprocating, and each first line 50 formed accordingly appears as an arc visible to the naked eye on the surface of the silicon wafer. Since the first lines 50 are arc-shaped, they have the highest point and the lowest point. Figure 2 In order to show the state of the first lines 50 on the silicon wafer 4, part of the first lines 50 are schematically drawn to show their contours and curvatures, etc., which does not represent the actual structure of the first lines 50. It can be seen in the figure that a plurality of first lines 50 are densely arranged along the cutting direction.

[0070] When the spacing between two adjacent first lines 50 is smaller than this range, the first lines 50 are denser, reducing the mechanical strength of the silicon wafer and reducing the efficiency of slicing by the cutting line. If the spacing between the first lines 50 is larger than this range, the spacing between the first lines 50 is too large, affecting the appearance of the silicon wafer and easily causing the conductive interconnect to slip when the battery at the module end is connected in series.

[0071] The spacing between two adjacent first lines 50 refers to the distance between the lowest points or the distance between the highest points on the first lines 50, which can be measured by a measuring tool such as a sorting machine or a vernier caliper, or can be obtained by collecting data from a displacement sensor. This application does not make any specific restrictions on this.

[0072] Usually, the extension direction of the first electrode on the battery cell made of the silicon wafer 4 is the same as the extension direction of the first side of the battery cell, so that the extension direction of the first pattern 50 on the battery cell is the same as the extension direction of the first electrode, reducing the risk of the first electrode being broken due to the first pattern 50. Therefore, when the silicon wafer 4 is manufactured, the extension direction of the first pattern 50 on the silicon wafer 4 is the same as the extension direction of the first side 10 of the silicon wafer 4.

[0073] In some embodiments, the spacing between two adjacent first lines 50 at the first chamfer 30 is 0.05 mm to 3 mm, specifically 0.05 mm, 1 mm, 2 mm, 3 mm; and / or, the spacing between two adjacent first lines 50 at the second chamfer 40 is 0.1 mm to 4 mm, specifically 0.1 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm. If the spacing between two adjacent first lines 50 at the chamfer is less than this range, the first lines 50 at the chamfer are denser, reducing the mechanical strength of the chamfer. If the spacing between two adjacent first lines 50 is greater than this range, it means that the arrangement density of the first lines 50 on the surface of the silicon wafer 4 is smaller, and the surface of the silicon wafer 4 is smoother, which is not conducive to the positioning between the conductive interconnect (such as the solder strip) and the silicon wafer 4, and may cause slippage and dislocation, which is prone to short circuit or poor conductivity. In addition, since the second chamfer 40 is smaller than the first chamfer 30, the stress is more concentrated at the second chamfer 40. Therefore, the spacing between adjacent first lines 50 at the second chamfer 40 is greater than the spacing between two adjacent first lines 50 at the first chamfer 30, so as to reduce the stress concentration at the second chamfer 40 and further reduce the risk of fragmentation and hidden cracks.

[0074] The spacing between two adjacent first lines at the first chamfer refers to the spacing between the lowest points on two adjacent first lines in the area where the chamfer is located. It can usually be detected using detection tools such as a sorting machine or a vernier caliper. For those skilled in the art, the distance between the highest points on the first lines can also be detected. This distance, as the spacing between two adjacent first lines, is also within the protection scope of this application. This application does not limit the method for detecting the distance.

[0075] It should be noted that the first line at the first chamfer refers to the line formed on the surface of the silicon wafer in the area where the first chamfer of the silicon wafer is located when the cutting line is ground against the surface of the silicon wafer as it goes back and forth during the silicon wafer cutting process. That is, the first line is on the surface of the silicon wafer, and the surface is in the area where the chamfer of the silicon wafer is located.

[0076] Based on the silicon wafer 4 described in any of the above embodiments, an embodiment of the present invention further provides a battery cell, which is prepared from the silicon wafer described in any of the above embodiments. The surface of the battery cell has a first electrode, and the first electrode extends along the first edge of the silicon wafer. The battery cell can be a back-contact battery cell, and the positive and negative electrodes are both arranged on the back of the battery cell.

[0077] Since the battery cell is prepared from the silicon wafer described in any of the above embodiments, it has the same beneficial effects as the silicon wafer in the above embodiments, which will not be described in detail here.

[0078] In some embodiments, the surface of the cell has a first pattern, and the first pattern and the first electrode extend in the same direction, that is, the first electrode extends along the first edge of the silicon wafer, so that the risk of the first electrode being broken due to the first pattern can be reduced.

[0079] It should be noted that the first lines of the present application and the first electrode extending in the same direction specifically means that the directions of the first lines and the first electrode are substantially the same or consistent. Since the first lines have a certain curvature, their extending direction is approximately parallel to the first electrode.

[0080] In some embodiments, the first electrode may include a main grid line and / or a secondary grid line. For a battery cell without a main grid, since the secondary grid line is relatively small, the extension direction of the secondary grid line on the half-cell battery cell made of the silicon wafer in the present application is parallel to the length direction of the battery cell, which can reduce the risk of the first pattern causing the secondary grid line to break.

[0081] The embodiment of the present invention also provides a photovoltaic module, including at least two cells and at least one conductive interconnection, wherein the conductive interconnection is connected between two adjacent cells, and the cell is a cell as described in any of the above embodiments. The conductive interconnection extends along the first side of the silicon wafer, and the conductive interconnection can be a welding strip, one end of the conductive interconnection is connected to the positive electrode on the back of the previous cell, and the other end of the conductive interconnection is connected to the negative electrode on the back of the next cell, so as to achieve the connection of the positive and negative electrodes of adjacent cells. The positive and negative electrodes of the cell are identified and arranged according to the first chamfer and the second chamfer on the battery to prevent the positive and negative electrodes from being connected incorrectly.

[0082] Since the photovoltaic module includes a cell, it has the same beneficial effects as the silicon wafer and the cell described in any of the above embodiments, which will not be described in detail here.

[0083] like Figure 3 As shown, based on the silicon wafer described in any of the above embodiments, an embodiment of the present invention further provides a method for preparing a silicon wafer, comprising the following steps:

[0084] Step S101, providing a round silicon rod 1. The round silicon rod 1 can be a silicon rod manufactured by a Czochralski method.

[0085] Step S102 , cutting the round silicon rod 1 to obtain a rectangular silicon rod 2 , wherein the rectangular silicon rod 2 has two opposite first surfaces 21 and two opposite second surfaces 22 .

[0086] In practical applications, the round silicon rod 1 can be cut using a diamond wire cutting device, where four diamond wires are used to form a rectangle to cut the round silicon rod 1 simultaneously, or one diamond wire is used to cut one surface of the rectangular silicon rod 2 each time.

[0087] Step S103 , grinding the rectangular silicon rod 2 to obtain a rectangular silicon rod 2 having four first chamfers 30 , wherein the first surface 21 and the second surface 22 are connected via the first chamfers 30 .

[0088] In practical applications, the four surfaces of the rectangular silicon rod 2 and the intersections of the four surfaces are ground and polished by grinding equipment to obtain four smooth surfaces and four first chamfers 30. The surface of the rectangular silicon rod 2 and the first chamfer 30 can be formed by multiple grindings or by simultaneous grinding. The grinding process is selected according to the grinding equipment.

[0089] Step S104, the rectangular silicon rod 2 is evenly cut into two halves along the cutting plane 23 parallel to the first surface 21 to obtain two half rods 3. Similarly, the rectangular silicon rod 2 can be gradually cut along the length direction of the rectangular silicon rod 2 using a diamond wire to obtain two identical half rods 3, the cutting plane 23 obtained by the new cutting is arranged opposite to and parallel to the first surface 21, wherein the first surface 21 of each half rod 3 has two first chamfers 30.

[0090] Step S105, grinding the half rod 3 so that two second chamfers 40 are formed at the connection between the cutting plane 23 and the two second surfaces 22 of the half rod 3. In practical applications, the same grinding equipment and process as in step S300 can be used to grind and polish the cutting plane 23 and the connection between the cutting plane 23 and the two second surfaces 22 to obtain a flat cutting plane and second chamfers 40. At this time, the projection length of the second chamfer 40 is smaller than the projection length of the first chamfer 30. The size of the chamfer can be expressed by referring to the description of the chamfer size in the silicon wafer 4, which will not be repeated here.

[0091] Step S106, slicing the half-rod 3 to obtain a silicon wafer 4 having two first chamfers 30 and two second chamfers 40, the silicon wafer 4 having two opposite first edges 10 and two opposite second edges 20, the first edge 10 being obtained by slicing the first surface 21 and the cutting plane 23 of the half-rod 3, the second edge 20 being obtained by slicing the second surface 22 of the half-rod 3, the first chamfer 30 and the second chamfer 40 of the silicon wafer 4 corresponding to the first chamfer 30 and the second chamfer 40 of the half-rod 3 respectively. One of the first edges 10 is connected to two adjacent second edges 20 via the first chamfer 30, and the other first edge 10 is connected to two adjacent second edges 20 via the second chamfer 40; the projection length of the first chamfer 30 is greater than the projection length of the second chamfer, and the ratio of the length of the first edge to the length of the second edge is 1.2 to 6.

[0092] The dimensions of the first chamfer 30 and the second chamfer 40 of the obtained silicon wafer 4 can be found in the relevant description in the silicon wafer embodiment, which will not be repeated here.

[0093] In the case of adopting the above technical solution, the round silicon rod 1 is cut to obtain a rectangular silicon rod 2, and then the rectangular silicon rod 2 is ground to obtain four first chamfers 30, and then the rectangular silicon rod 2 is evenly cut into two half rods 3, each half rod 3 has two first chamfers 30, and then the half rod 3 is ground to obtain two new second chamfers 40, and finally sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. Compared with the existing method of using laser to slice the large silicon wafer obtained by slicing to obtain half-wafers, laser slicing will cause damage and defect states in the cross section of the silicon wafer, affecting the photoelectric conversion efficiency of the cell. However, the present application directly obtains half-wafers in the silicon rod processing link and after slicing. Since the rectangular silicon rod and the half rod are both ground, the morphology of the silicon rod surface and chamfer is relatively flat, and the morphology of the side and chamfer of the half-wafer directly obtained after slicing is better. After preparing the cell, the passivation effect of the cell can be improved, thereby improving the quality of the cell and improving the photoelectric conversion efficiency. In addition, the projection length of the second chamfer 40 of the prepared silicon wafer 4 is smaller than the projection length of the first chamfer 30. After the silicon wafer 4 is prepared into a back-contact cell, since the two opposite sides of the back-contact cell have two groups of first chamfers 30 and second chamfers 40 of different sizes, the cell itself already has chamfer structures of different sizes that can assist in distinguishing the positive and negative pole directions. Chamfer structures of different sizes can be formed in the existing silicon wafer grinding process and chamfering process. Therefore, there is no need to set additional marks on the silicon wafer or cell, which eliminates the marking process, saves labor time, and improves processing efficiency.

[0094] like Figure 4 As shown, based on the silicon wafer described in any of the above embodiments, the embodiment of the present invention also provides another method for preparing a silicon wafer, including the following steps:

[0095] Step S201, providing a round silicon rod 1. The round silicon rod 1 can be a silicon rod manufactured by a Czochralski method.

[0096] Step S202 , cutting the round silicon rod 1 to obtain a rectangular silicon rod 2 , wherein the rectangular silicon rod 2 has two opposite first surfaces 21 and two opposite second surfaces 22 .

[0097] In practical applications, the round silicon rod 1 can be cut using a diamond wire cutting device, where four diamond wires are used to form a rectangle to cut the round silicon rod 1 simultaneously, or one diamond wire is used to cut one surface of the rectangular silicon rod 2 each time.

[0098] Step S203, the rectangular silicon rod 2 is evenly cut into two halves along the cutting plane 23 parallel to the first surface 21 to obtain two half rods 3. Similarly, the rectangular silicon rod 2 can be gradually cut along the length direction of the rectangular silicon rod 2 using a diamond wire to obtain two identical half rods 3, and the newly cut cutting plane 23 is arranged opposite to and parallel to the first surface 21, and at this time, the half rod 3 does not have a ground chamfer.

[0099] Step S204 , grinding the half rod 3 so that two first chamfers 30 are formed at the connection between the first surface 21 of the half rod 3 and the two second surfaces 22 , and two second chamfers 40 are formed at the connection between the cutting plane 23 of the half rod 3 and the two second surfaces 22 .

[0100] In practical applications, the four surfaces of the half rod 3 and the intersections of the four surfaces are ground and polished by a grinding device to obtain four flat surfaces and two first chamfers 30 and two second chamfers 40. The surface of the rectangular silicon rod 2 can be formed by multiple grindings or by simultaneous grinding. The grinding process is selected according to the grinding equipment. The sizes of the first chamfer 30 and the second chamfer 40 are different, and the first chamfer 30 and the second chamfer 40 can be ground separately. The size representation of the chamfer can refer to the description of the chamfer size in the above-mentioned silicon wafer, which will not be repeated here.

[0101] Step S205, slicing the half-rod 3 to obtain a silicon wafer 4 having two first chamfers 30 and two second chamfers 40, the silicon wafer 4 having two opposite first edges 10 and two opposite second edges 20, the first edge 10 being obtained by slicing the first surface 21 and the cutting plane 23 of the half-rod 3, the second edge 20 being obtained by slicing the second surface 22 of the half-rod 3, the first chamfer 30 and the second chamfer 40 of the silicon wafer 4 corresponding to the first chamfer 30 and the second chamfer 40 of the half-rod 3 respectively. One of the first edges 10 is connected to two adjacent second edges 20 via the first chamfer 30, and the other first edge 10 is connected to two adjacent second edges 20 via the second chamfer 40; the projection length of the first chamfer 30 is greater than the projection length of the second chamfer.

[0102] The dimensions of the first chamfer 30 and the second chamfer 40 of the obtained silicon wafer 4 can be found in the relevant description in the silicon wafer embodiment, which will not be repeated here.

[0103] In the case of adopting the above technical solution, the round silicon rod 1 is cut to obtain a rectangular silicon rod 2, and then the rectangular silicon rod 2 is evenly cut into two half rods 3, and then the half rod 3 is ground to obtain two first chamfers 30 and two second chamfers 40, and finally the half rod 3 is sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. Compared with the existing method of using laser to slice the large silicon wafer obtained by slicing to obtain half-wafers, laser slicing will cause damage and defect states in the cross section of the silicon wafer, affecting the photoelectric conversion efficiency of the cell. However, the present application directly obtains half-wafers in the silicon rod processing link and after slicing. Since the rectangular silicon rod and the half rod are both ground, the morphology of the silicon rod surface and chamfer is relatively flat, and the side and chamfer of the half-wafer directly obtained after slicing are better. After preparing the cell, the passivation effect of the cell can be improved, thereby improving the quality of the cell and improving the photoelectric conversion efficiency. In addition, the size of the second chamfer 40 of the prepared silicon wafer 4 is smaller than the size of the first chamfer 30. After the silicon wafer is prepared into a back-contact half-cell battery cell, since the two opposite sides of the back-contact half-cell battery cell are two groups of first chamfers and second chamfers of different sizes, it itself already has chamfer structures of different sizes that can assist in distinguishing the positive and negative pole directions. Chamfer structures of different sizes can be formed in the existing silicon wafer grinding process and chamfering processing process. Therefore, there is no need to set additional marks on the silicon wafer or battery cell, which eliminates the marking process, saves labor time, and improves processing efficiency.

[0104] In addition, the difference between the second silicon wafer preparation method and the first silicon wafer preparation method is that the first chamfer 30 and the second chamfer 40 are obtained by grinding after cutting in half. In this way, the grinding and cutting processes can be further simplified, the number of conversions between grinding equipment and cutting equipment can be reduced, and the processing efficiency can be further improved.

[0105] In the above two silicon wafer preparation methods, the first chamfer 30 is the chamfer formed when the round silicon rod 1 is processed into a silicon wafer. That is, when the round silicon rod 1 is cut to obtain the rectangular silicon rod 2, part of the arc surface of the round silicon rod 1 is retained on the rectangular silicon rod 2, and is directly used as the first chamfer 30 after grinding, so that the slicing utilization rate of the round silicon rod 1 can be improved, the waste of silicon rod materials can be reduced, and the cost can be reduced.

[0106] In the above two silicon wafer preparation methods, slicing the half rod 3 in step S106 and step S205 specifically includes the following steps:

[0107] The first surface 21 or the cutting plane 23 of the half rod 3 is bonded to the carrier, and the distance between the two second surfaces 22 is greater than the distance between the first surface 21 and the cutting plane 23. The carrier can be a resin plate or a plastic plate, and the half rod 3 is bonded and fixed to the wafer support through the carrier.

[0108] The carrier plate and the cutting wire net are moved close to each other in a direction perpendicular to the first surface 21, and the half-rod 3 is sliced ​​by the moving cutting wire net. In specific applications, the crystal holder is driven to move, and the carrier plate and the half-rod 3 are driven to move close to the cutting wire net. At the same time, the cutting wire net performs wire cutting, and the half-rod 3 is cut by the cutting wire net until it is cut into the carrier plate, and the slicing is completed.

[0109] Afterwards, the wafer support is driven to drive the cut silicon wafer away from the cutting wire net, and the slicing is completed, so that the adjacent attached silicon wafers 4 are separated, and finally the silicon wafer 4 is separated from the carrier to obtain the silicon wafer 4.

[0110] When the above technical solution is adopted, the slicing direction of the half rod 3 is such that the first line 50 on the obtained silicon wafer 4 is parallel to the long side direction of the silicon wafer 4, that is, the first side 10, and the first electrode on the half-cell battery cell made of the silicon wafer extends along the long side direction of the half-cell battery cell, so that the extension direction of the first electrode is the same as the extension direction of the first line on the battery cell, thereby reducing the risk of the first electrode being broken due to the first line.

[0111] When adopting the above technical solution, the first electrode may include a main grid line and / or a secondary grid line. For a battery cell without a main grid, since the secondary grid line is relatively small, the extension direction of the secondary grid line on the half-cell battery cell made of the silicon wafer in this application is parallel to the long side direction of the battery cell, which can reduce the risk of the first pattern causing the grid to break at the secondary grid line.

[0112] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0113] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A silicon wafer, characterized in that: The silicon wafer has two opposite first edges and two opposite second edges, wherein one of the first edges is connected to two adjacent second edges via a first chamfer, and the other first edge is connected to two adjacent second edges via a second chamfer; the ratio of the length of the first edge to the length of the second edge is 1.2 to 6; and the length of the first chamfer is greater than the length of the second chamfer.

2. The silicon wafer according to claim 1, characterized in that: The projection length of the first chamfer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

3. The silicon wafer according to claim 1, characterized in that: The projection length of the second chamfer is greater than 0 mm and less than or equal to 8.5 mm.

4. The silicon wafer according to claim 1, characterized in that: A difference between a projection length of the first chamfer on the first side and a projection length of the first chamfer on the second side is 0 mm to 2 mm; And / or, a difference between a projection length of the second chamfer on the first side and a projection length of the second chamfer on the second side is 0 mm to 1 mm.

5. The silicon wafer according to claim 1, characterized in that: The projection length of the first chamfer on the first side is 0.05 mm to 9 mm, and the projection length of the first chamfer on the second side is 0.05 mm to 7 mm; And / or, a projection length of the second chamfer on the first side is 0.05 mm to 5 mm, and a projection length of the second chamfer on the second side is 0.05 mm to 5 mm.

6. The silicon wafer according to claim 1, characterized in that: The difference between the projection length of the first chamfer on the first side and the projection length of the second chamfer on the first side is 0.05 mm to 8 mm; And / or, a difference between a projection length of the first chamfer on the second side and a projection length of the second chamfer on the second side is 0.05 mm to 8 mm.

7. The silicon wafer according to claim 1, characterized in that: The first chamfer is an arc-shaped chamfer or a linear chamfer; and / or the second chamfer is an arc-shaped chamfer or a linear chamfer.

8. The silicon wafer according to claim 1, characterized in that: The distance between two opposite second sides is 182 mm to 300 mm, and the distance between two opposite first sides is 83 mm to 150 mm.

9. The silicon wafer according to any one of claims 1 to 8, characterized in that: The surface of the silicon wafer has a plurality of first lines arranged at intervals, the distance between two adjacent first lines is 1 mm to 4 mm, and the distance between the highest point and the lowest point on the first lines is 0.5 mm to 4 mm.

10. The silicon wafer according to claim 9, characterized in that: The spacing between two adjacent first lines at the first chamfer is 0.05 mm to 3 mm, and / or the spacing between two adjacent first lines at the second chamfer is 0.1 mm to 4 mm.

11. A battery cell, characterized in that: The cell is prepared from the silicon wafer according to any one of claims 1 to 10, wherein the surface of the cell has a first electrode, and the first electrode extends along a first edge of the silicon wafer.

12. The battery cell according to claim 11, characterized in that: The surface of the battery cell has a first pattern, and the first pattern and the first electrode extend in the same direction.

13. The battery cell according to claim 11, characterized in that: The first electrode is a secondary gate line.

14. A photovoltaic module, comprising at least two solar cells and at least one conductive interconnector, wherein the conductive interconnector is connected between two adjacent solar cells, characterized in that: The battery cell is a battery cell as described in any one of claims 11 to 13.

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