Silicon wafer, battery piece and photovoltaic module

Abstract

The invention discloses a silicon wafer, a battery piece and a photovoltaic module. The silicon wafer is provided with a first surface, a second surface and a side face located between the first surface and the second surface, the first surface and the second surface are each provided with two opposite first edges and two opposite second edges, and one first edge is connected with the two adjacent second edges through a first chamfer on the side face. The other first edge is connected with the two adjacent second edges through second chamfers on the side surface of the silicon wafer; the projection length of the first chamfer is smaller than 5 mm, and the projection length of the first chamfer is larger than or equal to the projection length of the second chamfer. The side surface where the second chamfer is located is provided with a plurality of first grooves, and the included angle between the extension direction of the first grooves and the first surface of the silicon wafer is 0-10 degrees. The first groove of the second chamfer on the silicon wafer can effectively reduce the risk of edge breakage and fragment, when a film layer on a battery piece is removed through floating on water, the cleaning dead angle of the second chamfer can be reduced, water flow in front of the second chamfer is guided to the side through the first groove, and flooding is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon wafers, and in particular to a silicon wafer, a battery wafer and a photovoltaic module. Background Art

[0002] At present, most solar cells use single crystal silicon wafers as their raw materials. The cost and photoelectric conversion efficiency of single crystal silicon wafers directly affect the development of solar cells. Photovoltaic cells usually cut single crystal silicon rods into silicon wafers. In order to increase the power generation of components, the existing silicon wafers require the chamfers of silicon wafers to be smaller and smaller, resulting in a serious fragmentation rate during the processing of silicon wafer ends, which affects the cost of silicon wafer processing. Summary of the invention

[0003] The object of the present invention is to provide a silicon wafer, a battery wafer and a photovoltaic module to reduce the fragmentation rate of the silicon wafer.

[0004] In a first aspect, the present invention provides a silicon wafer, the silicon wafer having a first surface, a second surface, and a side surface between the first surface and the second surface, the first surface and the second surface each having two opposite first edges and two opposite second edges, one of the first edges being connected to two adjacent second edges via a first chamfer on the side surface of the silicon wafer, and the other first edge being connected to two adjacent second edges via a second chamfer on the side surface of the silicon wafer;

[0005] The projection length of the first chamfer is less than 5 mm, and the projection length of the first chamfer is greater than or equal to the projection length of the second chamfer;

[0006] The side surface where the second chamfer is located has a plurality of first grooves, and the angle between the extension direction of the first grooves and the first surface and / or the second surface of the silicon wafer is 0° to 10°.

[0007] When the above technical solution is adopted, the projection length of the first chamfer on the silicon wafer is less than 5 mm, and the projection length of the first chamfer is greater than or equal to the projection length of the second chamfer, and the angle between the extension direction of the first groove of the second chamfer and the surface of the silicon wafer is 0° to 10°. In this way, when the projection length of the silicon wafer is too small, the stress distribution at the edge of the silicon wafer can be improved by arranging the first groove at the chamfer; at the same time, since the diamond wire contacts the first surface and / or the second surface during cutting to form the first texture on the first surface and / or the second surface, the extension direction of the first groove on the second chamfer is different from the first texture on the first surface and / or the second surface of the silicon wafer, and no superimposed stress is generated at the second chamfer of the silicon wafer, which solves the probability of superimposed stress being formed at the chamfer during silicon wafer processing, and does not cause the problems of weakened strength, fragmentation and edge collapse of the silicon wafer. As the size of silicon wafers increases, the chamfer of silicon wafers tends to decrease. In the process of preparing solar cells using the above silicon wafers, when the phosphorus-silicate glass or the coating on the solar cell is removed by the "floating on water" method, that is, the silicon wafer floats on the cleaning liquid and moves, and the side of the silicon wafer and the phosphorus-silicate glass or the coating on the side in contact with the cleaning liquid are cleaned by the cleaning liquid, when the angle between the first groove of the second chamfer and the first surface and / or the second surface of the silicon wafer is 0° to 10°, that is, when it is substantially parallel to the first surface and / or the second surface of the silicon wafer, the silicon wafer When floating on the liquid surface, the direction of water flow is the same as the extension direction of the first groove. Therefore, the cleaning dead corner of the phosphosilicate glass or the coating on the second chamfer can be reduced, and the water flow in front of the second chamfer is diverted to the side by the first groove. Compared with the existing chamfer where the first groove is inclined to the first surface and / or the second surface of the silicon wafer, the water flow will be directed to the upper surface of the silicon wafer. The direction of the first groove in the present application reduces the occurrence of liquid overflow, is beneficial to the cleaning of the coating, and reduces the damage to the film layer on the first surface and / or the second surface of the silicon wafer.

[0008] In some possible implementations, the spacing between two adjacent first grooves is less than or equal to 3 um. When the spacing between the first grooves is within this range, the stress distribution at the chamfer can be improved and the risk of fragmentation can be reduced. If the spacing is greater than this range, the strength uniformity and flatness of the second chamfer are reduced, affecting the photoelectric conversion efficiency of the battery.

[0009] In some possible implementations, the width of the first groove is 1um to 20um. When the width of the first groove is greater than 1um, the width of the first groove is too large, and during the chamfering process, the grain size of the diamond sand used for grinding is larger, the grinding resistance increases, which is not conducive to grinding, and increases the edge collapse rate and fragmentation rate during the silicon wafer processing process; when the width of the first groove is less than 20um, it cannot effectively solve the problem of high fragmentation rate caused by stress at the edge of the silicon wafer.

[0010] In some possible implementations, the thickness of the silicon wafer is 70 to 130 um. When the thickness of the silicon wafer is greater than 130 um, the stress on the silicon wafer is more concentrated, and the stress at the edge of the silicon wafer is significantly reduced. During the cleaning process of the silicon wafer processing, the fragmentation rate of the silicon wafer is less than 0.2%; when the thickness of the silicon wafer is less than 70 um, the difficulty of processing and manufacturing is increased, and the problem of cracking will also occur due to the small thickness.

[0011] In some possible implementations, the length of the first side is 182 mm to 300 mm, the length of the second side is 182 mm to 300 mm, and the length of the first side is different from the length of the second side. The larger the silicon wafer size, the larger the surface area of ​​the battery, and the higher the power generation of the photovoltaic module. When the size of the silicon wafer is within the above range, the utilization rate of the silicon rod in the silicon wafer processing process can be effectively improved, and the silicon wafer manufacturing cost can be reduced.

[0012] In some possible implementations, the length of the first side is 182 mm to 300 mm, and the length of the second side is 91 mm to 150 mm. The cell prepared from the silicon wafer does not need to be laser scribed, and laser damage or defects will not be formed on the edge of the cell, thereby ensuring the passivation effect of the cell and improving the photoelectric conversion efficiency of the solar cell. It is suitable for cells of various specifications and sizes and photovoltaic modules of different formats.

[0013] In some possible implementations, the second chamfer is an arc-shaped chamfer, and a first angle between a tangent line at one end of the arc-shaped chamfer connected to the first side and the first side is 30° to 60°.

[0014] When the technical solution of the present application is adopted, when the first angle is less than 30°, the chamfer is too sharp, resulting in an increase in the fragmentation rate of the edge of the silicon wafer. When the first angle between the tangent of one end of the arc chamfer connected to the first edge and the first edge is greater than 60°, the projection length of the arc chamfer is large, resulting in a large amount of blank space at the component end, affecting the power generation of the component.

[0015] And / or, a second angle between a tangent line at one end of the arc-shaped chamfer connected to the second side and the second side is 30° to 50°.

[0016] By adopting the above technical solution, since the second side is smaller than the first side, the stress on the second side is more concentrated. By setting the tangent of one end of the arc chamfer connected to the second side and the second angle of the second side within the above range, the stress distribution on the second side and the chamfer can be effectively dispersed, thereby reducing the fragmentation rate.

[0017] In some possible implementations, the second chamfer is a linear chamfer, and the angle between the linear chamfer and the first side is 35° to 85°. The angle is an acute angle, so that the angle formed by the linear chamfer and the first side is greater than 35° to prevent the silicon wafer chamfer from being too sharp, resulting in a fragmentation rate during transportation; when the angle formed by the linear chamfer and the first side is less than 85°, the angle between the linear chamfer and the adjacent second side is prevented from being too large, resulting in a large blank area at the component end, affecting the power generation at the component end.

[0018] In some possible implementations, the first chamfer has a plurality of second grooves, and the extension direction of the second grooves intersects with the surface of the silicon wafer. After the silicon wafer is used to prepare a cell, an angle is formed between the extension direction of the conductive interconnection on the cell and the second grooves, so that during the soldering process of the conductive interconnection passing through the first chamfer, the second grooves on the first chamfer have a certain limiting effect on the conductive interconnection, which can reduce the slippage of the conductive interconnection on the first surface and / or the second surface of the silicon wafer.

[0019] In some possible implementations, the first surface and / or the second surface of the silicon wafer has a plurality of first lines arranged at intervals, and the extension direction of the first lines is the same as that of the first edge. The first lines are cutting lines formed on the first surface and / or the second surface of the silicon wafer when the silicon wafer is cut by diamond wire. When the extension direction of the first lines is the same as that of the first edge, the distribution of the edge stress of the silicon wafer in the direction of extension of the first edge of such a silicon wafer is improved due to the arrangement of the first lines, and the strength of the silicon wafer will not be reduced.

[0020] In the second aspect, the present invention further provides a battery cell, which is prepared from the silicon wafer described in any of the above items, and the surface of the battery cell has a first electrode, and the first electrode extends along the first edge of the silicon wafer. Since the battery cell is prepared from the silicon wafer of the first aspect, it has the same beneficial effects as the first aspect and will not be repeated.

[0021] In some possible implementations, the surface of the battery cell has a first pattern, and the first pattern and the first electrode extend in the same direction. This arrangement reduces the risk of the first electrode being disconnected due to the first pattern.

[0022] In a third aspect, the present invention further provides a photovoltaic module, comprising at least two cells and at least one conductive interconnection, wherein the conductive interconnection is connected between two adjacent cells, and the conductive interconnection extends along a first side of the silicon chip. The cell of the present invention is a cell as described in any one of the above items. Since the photovoltaic module comprises the cell of the second aspect, it has the same beneficial effects as the first and second aspects, which will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 A schematic diagram of the structure of a silicon wafer provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a structure in which a first surface of a silicon wafer provided by an embodiment of the present invention has a first texture;

[0026] Figure 3 A partial schematic diagram of the side surface of the silicon wafer provided by an embodiment of the present invention where the second chamfer is located;

[0027] Figure 4 A partial schematic diagram of the side surface of a silicon wafer provided by an embodiment of the present invention where a first chamfer is located;

[0028] Figure 5 A schematic diagram of a process of a silicon wafer preparation method provided by an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of another process of preparing a silicon wafer provided in an embodiment of the present invention.

[0030] Figure numerals: 1 is a round silicon rod, 2 is a rectangular silicon rod, 21 is a first surface, 22 is a second surface, 23 is a cutting plane, 3 is a half rod, 4 is a silicon wafer, 10 is a first edge, 20 is a second edge, 30 is a first chamfer, 301 is a second groove, 40 is a second chamfer, 401 is a first groove, and 50 is a first texture. DETAILED DESCRIPTION

[0031] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0034] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0035] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] Most solar cells use single crystal silicon wafers as their raw materials. The cost and photoelectric conversion efficiency of single crystal silicon wafers directly affect the development of solar cells. Solar cells usually start by cutting single crystal silicon rods into square rods, which are then cut into silicon wafers to prepare photovoltaic cells.

[0037] At present, with the industry's extreme pursuit of silicon wafer cost and photoelectric conversion efficiency, the size of silicon wafers has become larger and the chamfer size has gradually become smaller. However, the smaller chamfer size is not conducive to the dispersion of silicon wafer edge stress, resulting in a high fragmentation rate in the silicon wafer manufacturing process. To this end, the inventor of this application provides a new silicon wafer.

[0038] like Figure 1-Figure 4As shown, an embodiment of the present invention provides a silicon wafer 4, which has a first surface, a second surface, and a side surface located between the first surface and the second surface, and the first surface and the second surface both have two opposite first edges 10 and two opposite second edges 20, wherein one first edge 10 is connected to two adjacent second edges 20 through a first chamfer 30 on the side surface of the silicon wafer, and the other first edge 10 is connected to two adjacent second edges 20 through a second chamfer 40 on the side surface of the silicon wafer; the projection length of the first chamfer 30 is less than 5 mm, and the projection length of the first chamfer 30 is greater than or equal to the projection length of the second chamfer 40; the side surface where the second chamfer 40 is located has a plurality of first grooves 401, and the angle between the extension direction of the first groove 401 and the surface of the silicon wafer is 0° to 10°, and specifically can be 0°, 1°, 3°, 5°, 7°, 9°, 10°.

[0039] It should be noted that the projection length of the silicon wafer chamfer refers to the projection length on the first side or the second side of the silicon wafer after the edge or corner of the silicon wafer is chamfered. The shape of the silicon wafer chamfer can be an arc chamfer or a linear chamfer, wherein the linear chamfer includes a right angle, an oblique angle, etc.; the arc chamfer includes a circular chamfer, an arc-shaped chamfer, etc. When the chamfer shape is a linear chamfer, the projection length described in this application refers to the projection length of the linear chamfer on the first side or the second side.

[0040] The projection length of the chamfer can be measured by optical measurement, scanning microscope or other measurement methods to evaluate the size of the chamfer.

[0041] In the present application, the projection length of the first chamfer 30 and the second chamfer 40 refers to the projection of the first chamfer 30 and the second chamfer 40 on the first edge 10 and / or the second edge 20. The projection length of the first chamfer 30 is greater than or equal to the projection length of the second chamfer 40, which means that the projection length of the first chamfer 30 on the first edge 10 is greater than or equal to the projection length of the second chamfer 40 on the first edge 10, and the projection length of the first chamfer 30 on the second edge 20 is greater than or equal to the projection length of the second chamfer 40 on the second edge 20.

[0042] When the above technical solution is adopted, since the current method of preparing silicon wafers by diamond wire cutting will cause the angle between the first groove on the chamfer of the silicon wafer and the first surface and / or the second surface of the silicon wafer to be too large, causing the risk of edge collapse at the chamfer on the silicon wafer, based on this, the angle between the extension direction of the first groove 401 of the second chamfer 40 of the silicon wafer of the present application and the surface of the silicon wafer 4 is reduced to 0° to 10°, and the first groove 401 substantially parallel to the first surface and / or the second surface of the silicon wafer is obtained by adjusting the direction of the first groove of the chamfer, and the direction in which the first groove 401 on the second chamfer 40 extends is equal to the angle between the first groove 401 and the second surface of the silicon wafer. The first lines 50 on the first surface and / or the second surface of the silicon wafer are different, and no superimposed stress will be generated at the second chamfer 40 of the silicon wafer, which solves the probability of superimposed stress being formed at the chamfer during the processing of the silicon wafer, and will not cause the problem of weakening the strength of the silicon wafer, fragmentation and edge collapse. In addition, since the preparation of the silicon rod requires high-temperature crystal pulling, the thermal stress at the edge position is large. Since the silicon wafer is a product cut from a square-like rod taken out of a silicon round rod, the chamfer on the silicon wafer is closest to the edge of the original round rod. Due to the large thermal shock during the crystal pulling process, the thermal stress formed at the chamfer of the silicon wafer is large. The first groove 401 at the second chamfer can improve the stress distribution at the edge of the silicon wafer and reduce the fragmentation rate. When the angle is 0°, that is, the extension direction of the first groove 401 is parallel to the first surface and / or the second surface of the silicon wafer, in the process of using such a silicon wafer to make a solar cell, when the phosphorus silicon glass or the coating layer on the solar cell is removed by the "floating on water" method, that is, the silicon wafer 4 floats on the cleaning liquid, and the side of the silicon wafer 4 and the phosphorus silicon glass or the coating layer on the side facing the liquid surface are cleaned by the cleaning liquid. Since the first groove 401 of the second chamfer 40 is parallel to the surface of the silicon wafer 4, when the silicon wafer 4 floats on the liquid surface, the water flow direction is parallel to the surface of the silicon wafer 4. The first groove 401 extends in the same direction, and therefore, can reduce the cleaning dead angle of the phosphosilicate glass or the coating on the second chamfer 40, and the water flow in front of the second chamfer 40 is diverted to the side by the first groove 401. Compared with the existing chamfer where the wear marks are inclined to the first surface and / or the second surface of the silicon wafer, the water flow will be directed to the upper surface of the silicon wafer. The direction of the first groove 401 in the present application reduces the occurrence of overflow, is beneficial to the cleaning of the coating, reduces the damage to the film layer on the upper surface of the silicon wafer, and helps to improve the photoelectric conversion efficiency of the battery.

[0043] In some embodiments, the spacing between two adjacent first grooves 401 is less than or equal to 3um. Specifically, the spacing between adjacent first grooves 401 can be 0.1μm, 0.5μm, 0.8μm, 1μm, 1.2μm, 1.5μm, 1.7μm, 2μm, 2.3μm, 2.6μm, 2.8μm, 3μm, etc. The first grooves 401 within this spacing range can improve the stress distribution at the chamfer of the silicon wafer and reduce the risk of fragments. If the spacing between two adjacent first grooves 401 is greater than this spacing range, the strength uniformity of the second chamfer 40 and the flatness of the first surface and / or second surface of the silicon wafer are reduced, affecting the photoelectric conversion efficiency of the battery.

[0044] In some embodiments, the width of the first groove 401 is 1um to 20um. Specifically, the width of the first groove 401 can be 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 12um, 14um, 15um, 16um, 17um, 19um, 20um, etc. When the width of the first groove 401 is greater than 20um, the width of the first groove 401 is too large. During the processing of the second chamfer 40, the grain size of the diamond sand used in grinding is large, the grinding resistance increases, which is not conducive to grinding, and increases the edge collapse rate and fragmentation rate during the processing of the silicon wafer; when the width of the first groove 401 is less than 1um, the problem of high fragmentation rate caused by stress at the edge of the silicon wafer cannot be solved.

[0045] In some possible implementations, the thickness of the silicon wafer 4 is less than or equal to 130 μm. When the thickness of the silicon wafer is greater than 130 μm, the stress on the silicon wafer 4 is more concentrated. When the thickness is less than or equal to 130 μm, the stress at the edge of the silicon wafer 4 is significantly reduced. During the cleaning process of the silicon wafer 4, the fragmentation rate of the silicon wafer 4 is less than 0.2%.

[0046] In some embodiments, the margin of the first side 10 is 182 mm to 300 mm, the margin of the second side 20 is 182 mm to 300 mm, and the margin of the first side 10 is different from the margin of the second side 20. Due to the presence of the chamfer, the length of the first side 10 can be represented by the spacing between the two opposite second sides 20, that is, the sum of the length of the first side 10 and the projection length of the two first chamfers 30 on the first side 10 is 182 mm to 300 mm. The length of the first side 10 can be 182 mm, 185 mm, 190 mm, 195 mm, 200 mm, 205 mm, 210 mm, 220 mm, 230 mm, 240 mm, 250 mm, 270 mm, 290 mm, 300 mm, etc.; the length of the second side 20 The length of can be represented by the spacing between two opposite first sides 10, that is, the sum of the length of the second side 20 and the projection length of the first chamfer 30 on the second side 20 and the projection length of the second chamfer 40 on the second side 20 is 182mm-300mm, and the length of the second side 20 can be specifically 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc. The length of the first side 10 can be greater than the length of the second side 20. The larger the size of the silicon wafer, the larger the surface area of ​​the battery and the higher the photoelectric conversion efficiency. When the size of the silicon wafer is within the above range, the utilization rate of the silicon rod in the silicon wafer processing process can be effectively improved, and the silicon wafer manufacturing cost can be reduced.

[0047] In other embodiments, the length of the first side 10 is 182 mm to 300 mm, and the length of the first side 10 can be specifically 182 mm, 185 mm, 190 mm, 195 mm, 200 mm, 205 mm, 210 mm, 220 mm, 230 mm, 240 mm, 250 mm, 270 mm, 290 mm, 300 mm, etc.; the length of the second side 20 is 91 mm to 150 mm, and the length of the second side 20 can be specifically 91 mm, 95 mm, 98 mm, 100 mm, 105 mm, 110 mm, 115 mm, 120 mm, 125 mm, 130 mm, 135 mm, 140 mm, 145 mm, 150 mm, etc. The cell prepared from the silicon wafer does not need to be laser scribed, and the silicon wafer of this size can be directly manufactured to obtain a cell, and laser damage or defects will not be formed on the edge of the cell, thereby ensuring the passivation effect of the cell and improving the photoelectric conversion efficiency of the solar cell. It is suitable for cells of various sizes and specifications and photovoltaic modules of different formats.

[0048] The corresponding fragmentation rate data of silicon wafers with different side lengths and different chamfer projection lengths with the first groove direction on the second chamfer 40 changed or unchanged are shown in Table 1 below, where the fragmentation rate is the fragmentation rate caused by the cleaning process in the silicon wafer preparation process.

[0049] In this embodiment, the direction of the first groove remains unchanged, which means that the angle between the direction of the first groove formed at the second chamfer by using the existing chamfering process and the first surface and / or the second surface of the silicon wafer is greater than 80°, and the change in the direction of the first groove is the direction of the first groove of this application.

[0050] Table 1. Fragmentation rate of silicon wafers with different side lengths and projection lengths

[0051]

[0052] It can be seen from the size of the silicon wafer 4 in the above embodiments and the data in Table 1, for example, by comparing Example 1 with Comparative Example 1, comparing Example 2 with Comparative Example 2, comparing Example 3 with Comparative Example 3, comparing Example 4 with Comparative Example 4, comparing Example 5 with Comparative Example 5, and comparing Example 6 with Comparative Example 6 that when the size of the silicon wafer is within 182 mm to 300 mm and under the same conditions, when the projection length is below 5 mm, the fragmentation rate is reduced; by comparing Example 7 with Comparative Example 7, when the size of the silicon wafer is too large, such as when one side is greater than 300 mm, and the projection length is below 5 mm, the fragmentation rate remains basically unchanged by changing the direction of the groove at the chamfer.

[0053] Through the comparison of Examples 1 to 6, and the unchanged direction of the first groove at the chamfer and the changed direction of the first groove at the chamfer in Comparative Examples 1 to 6, it can be seen that when the angle between the extension direction of the first groove in the present application and the first surface and / or the second surface of the silicon wafer is 0° to 10°, the corresponding silicon wafer fragmentation rate is significantly reduced.

[0054] In some embodiments, the second chamfer 40 is an arc chamfer, which can reduce the edge stress of the silicon wafer 4; the first angle between the tangent of the end connected to the first edge 10 on the arc chamfer and the first edge 10 is 30° to 60°, and can be specifically 30°, 35°, 40°, 45°, 50°, 55°, 60°, etc. When the first angle is less than 30°, the chamfer is too sharp, resulting in an increase in the fragmentation rate of the silicon wafer edge; when the first angle between the tangent of the end connected to the first edge 10 on the arc chamfer and the first edge 10 is greater than 60°, the projection length of the arc chamfer is large, resulting in more blank space at the component end, affecting the power generation of the component.

[0055] And / or, a second angle between a tangent line at the other end of the arc chamfer connected to the second side 20 and the second side 20 is 30° to 50°, specifically 30°, 35°, 40°, 45°, 50°, etc.

[0056] By adopting the above technical solution, since the second edge 20 is smaller than the first edge 10, the stress on the second edge 20 is more concentrated. By setting the tangent of one end of the arc chamfer connected to the second edge 20 and the second angle of the second edge 20 within the above range, the stress distribution at the second edge 20 and the second chamfer 40 can be effectively dispersed, thereby reducing the fragmentation rate.

[0057] In other embodiments, the second chamfer 40 is a linear chamfer, which can improve the utilization rate of silicon rods for large-sized silicon wafers. The angle between the linear chamfer and the first edge 10 is 35° to 85°, and can be specifically 35°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, etc. The angle is an acute angle, so that the angle formed by the linear chamfer and the first edge 10 is greater than 35° to prevent the silicon wafer chamfer from being too sharp, resulting in a fragmentation rate during transportation; when the angle formed by the linear chamfer and the first edge 10 is less than 85°, it is prevented that the angle between the linear chamfer and the adjacent second edge 20 is too large, resulting in a large blank area at the component end, affecting the effective utilization area of ​​the battery cell.

[0058] It should be noted that the linear chamfers of the present application may specifically include straight line, oblique line or multi-segment line, etc., and chamfer shapes that are generally straight lines or linear structures are all within the protection scope of the present application.

[0059] In some embodiments, the first chamfer 30 is an arc chamfer or a linear chamfer. When the first chamfer 30 is an arc chamfer, it can reduce the edge stress of the silicon wafer 4. When the first chamfer 30 is a linear chamfer, the linear chamfer can improve the utilization rate of silicon rods for large-sized silicon wafers.

[0060] like Figure 4 As shown, in some possible implementations, the first chamfer 30 has a plurality of second grooves 301, and the extension direction of the second grooves 301 intersects with the surface of the silicon wafer 4, that is, there is an angle between the second grooves 301 and the surface of the silicon wafer 4, and the angle is less than 90°, and can be 10°, 20°, 30°, 45°, 60°, 80°, 85°, etc. The second grooves 301 are wear marks formed when the first chamfer 30 is ground. After the silicon wafer is prepared into a battery cell, there is an angle between the extension direction of the conductive interconnection on the battery cell and the second grooves 301. Therefore, during the string soldering process of the conductive interconnection passing through the first chamfer 30, the second grooves 301 on the first chamfer 30 further have a certain limiting effect on the conductive interconnection, which can reduce the slippage of the conductive interconnection on the first surface and / or the second surface of the silicon wafer.

[0061] like Figure 2As shown, in some embodiments, the surface of the silicon wafer 4 has a plurality of first lines 50 arranged at intervals, and the extension direction of the first lines 50 is the same as the extension direction of the first edge 10. It should be noted that the first lines 50 are friction textures formed on the first surface and / or the second surface of the silicon wafer when the cutting line rubs against the first surface and / or the second surface of the silicon wafer during the silicon wafer preparation process. Since the silicon rod is fed relative to the cutting wire mesh, the cutting line is subjected to pressure from the silicon rod, and the cutting line forms a certain degree of bending in the feeding direction while reciprocating, and each first line 50 formed accordingly appears as an arc visible to the naked eye on the first surface and / or the second surface of the silicon wafer. Figure 2 In order to show the state of the first lines 50 on the silicon wafer 4, part of the first lines 50 are schematically drawn to show their contours and curvatures, etc., which does not represent the actual structure of the first lines 50. It can be seen in the figure that a plurality of first lines 50 are densely arranged along the cutting direction.

[0062] When the extension direction of the first lines 50 is the same as the extension direction of the first edge 10, the extension direction of the first electrode on the cell made of the silicon wafer is the same as the long side direction of the cell, reducing the risk of the first electrode being broken due to the first lines. Therefore, when the silicon wafer is manufactured, the extension direction of the first lines 50 on the silicon wafer is the same as the long side of the silicon wafer 4, that is, the same as the extension direction of the first edge 10. In addition, the arrangement of the first lines improves the distribution of the edge stress of the silicon wafer in the direction of the first side extension, and does not cause a decrease in the strength of the silicon wafer.

[0063] It is worth noting that, during the silicon wafer preparation process, the silicon rods are fed relative to the cutting wire mesh, the cutting wires are subjected to pressure from the silicon rods, and the cutting wires form a certain degree of bending in the feeding direction while reciprocating. Each corresponding first line 50 is presented as an arc visible to the naked eye on the first surface and / or the second surface of the silicon wafer, and the extension direction of the first line is the same as the long side of the silicon wafer, which means it is substantially the same or consistent.

[0064] In some embodiments, the spacing between two adjacent first lines 50 is 1 mm to 4 mm, specifically, the spacing between two adjacent first lines 50 is 1 mm, 2 mm, 3 mm, 4 mm, etc. Since the first lines 50 are slightly curved, with a highest point and a lowest point, the distance between the highest point and the lowest point on the first lines 50 is 0.5 mm to 4 mm, specifically, the distance between the highest point and the lowest point on the first lines 50 can be 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, etc. .

[0065] The spacing between two adjacent first lines 50 refers to the distance between the lowest points or the distance between the highest points on the first lines, which can be measured by a measuring tool such as a sorter or a vernier caliper, or can be obtained by collecting data from a displacement sensor. This application does not make any specific limitation on this.

[0066] When the spacing between two adjacent first lines 50 is smaller than this range, the first lines 50 are denser, reducing the mechanical strength of the silicon wafer, and the efficiency of slicing by the cutting line is low. If the spacing between the first lines 50 is larger than this range, the spacing between the first lines 50 is too large, the flatness of the first surface and / or the second surface of the silicon wafer is uneven, affecting the overall appearance, and the local surface roughness of the silicon wafer is too small, which easily causes the conductive interconnect to slip. When the distance between the highest point and the lowest point of the first line 50 is less than 0.5mm, it means that the cutting speed of the cutting line is slow, the cutting line is subjected to less force, and the slicing efficiency is reduced. The first surface and / or the second surface of the silicon wafer are smooth, which can easily cause the conductive interconnect to slip. When the distance between the highest point and the lowest point of the first line 50 is greater than 4mm, the cutting line is subjected to greater force, which can easily cause excessive pressure on the silicon wafer to cause fragments during the cutting process, affecting the life of the cutting line. The cutting speed is too fast, resulting in excessive spacing between the first lines, uneven flatness of the first surface and / or the second surface of the silicon wafer, affecting the overall appearance, and too small a local surface roughness of the silicon wafer, which can easily cause the conductive interconnect to slip.

[0067] Based on the silicon wafer 4 described in any of the above embodiments, an embodiment of the present invention further provides a battery cell, which is prepared from the silicon wafer described in any of the above embodiments. The surface of the battery cell has a first electrode, and the first electrode extends along the first edge of the silicon wafer. The battery cell can be a back-contact battery cell, and the positive and negative electrodes are both arranged on the back of the battery cell.

[0068] Since the battery cell is prepared from the silicon wafer described in any of the above embodiments, it has the same beneficial effects as the silicon wafer in the above embodiments, which will not be described in detail here.

[0069] In some embodiments, the surface of the battery cell has a plurality of first lines arranged at intervals, and the extension direction of the first lines is the same as the extension direction of the first electrode, so that the risk of disconnection of the first electrode caused by the first lines can be reduced.

[0070] It should be noted that the first lines of the present application and the first electrode extending in the same direction specifically means that the directions of the first lines and the first electrode are substantially the same or consistent. Since the first lines have a certain curvature, their extending direction is approximately parallel to the first electrode.

[0071] In some embodiments, the first electrode may include a main grid line and / or a secondary grid line. For a battery cell without a main grid, since the secondary grid line is relatively small, the extension direction of the secondary grid line on the half-cell battery cell made of the silicon wafer in the present application is parallel to the length direction of the battery cell, which can reduce the risk of the first pattern causing the secondary grid line to break.

[0072] The embodiment of the present invention further provides a photovoltaic module, comprising at least two cells and at least one conductive interconnection, wherein the conductive interconnection is connected between two adjacent cells, and the cell is a cell as described in any of the above embodiments. The conductive interconnection may be a welding strip, wherein one end of the conductive interconnection is connected to the positive electrode on the back of the previous cell, and the other end of the conductive interconnection is connected to the negative electrode on the back of the next cell, so as to achieve the connection between the positive and negative electrodes of adjacent cells.

[0073] Since the photovoltaic module includes a cell, it has the same beneficial effects as the silicon wafer and the cell described in any of the above embodiments, which will not be described in detail here.

[0074] Based on the silicon wafer described in any of the above embodiments, an embodiment of the present invention further provides a method for preparing a silicon wafer, comprising the following steps:

[0075] Step S101, providing a round silicon rod 1. The round silicon rod 1 can be a silicon rod manufactured by a Czochralski method.

[0076] Step S102 , cutting the round silicon rod 1 to obtain a rectangular silicon rod 2 , wherein the rectangular silicon rod 2 has two opposite first surfaces 21 and two opposite second surfaces 22 .

[0077] In practical applications, the round silicon rod 1 can be cut using a diamond wire cutting device, where four diamond wires are used to form a rectangle to cut the round silicon rod 1 simultaneously, or one diamond wire is used to cut one surface of the rectangular silicon rod 2 each time.

[0078] Step S103, grinding the rectangular silicon rod 2 to obtain a rectangular silicon rod 2 with four first chamfers 30 or four second chamfers 40, or a rectangular silicon rod 2 with two first chamfers 30 and two second chamfers 40, and slicing the rectangular silicon rod 2 to obtain a silicon wafer in which the first surface 21 and the second surface 22 are connected by the first chamfers 30 and / or the second chamfers 40.

[0079] It should be noted that when the chamfer shapes of the silicon wafers are the same, when the projection length of the first chamfer 30 is equal to the projection length of the second chamfer 40, that is, the first chamfer 30 and the second chamfer 40 are equal, the rectangular silicon rod can be ground to form a rectangular silicon rod with four first chamfers 30 or four second chamfers 40, and the silicon rod can be sliced ​​to obtain a silicon wafer with four identical chamfers; when the projection length of the first chamfer 30 is greater than the projection length of the second chamfer 40, that is, the first chamfer 30 and the second chamfer 40 are of different sizes, the rectangular silicon rod is ground to form a rectangular silicon rod with two first chamfers 30 and two second chamfers 40, and such a silicon rod can be sliced ​​to obtain a silicon wafer with two first chamfers 30 and two second chamfers 40.

[0080] In practical applications, the four surfaces of the rectangular silicon rod 2 and the intersections of the four surfaces are ground and polished by a grinding device to obtain four flat surfaces and four first chamfers 30. The surface of the rectangular silicon rod 2 and the first chamfers 30 can be formed by multiple grindings or by simultaneous grinding. The grinding process is selected according to the grinding device. In this process, the diamond on the grinding wheel grinds the first chamfer 30 to obtain a plurality of second grooves 301. The extension direction of the second grooves 301 intersects with the two end surfaces of the silicon rod.

[0081] For those skilled in the art, the four surfaces of the rectangular silicon rod 2 and the intersections of the four surfaces can also be ground and polished by a grinding device to obtain four flat surfaces and four second chamfers 40. The surface of the rectangular silicon rod 2 and the second chamfers 40 can be formed by multiple grindings or by simultaneous grinding. The grinding process is selected according to the grinding device. In this process, the diamond on the grinding wheel grinds the second chamfer 40 to obtain a plurality of first grooves 401. The angle between the extension direction of the first groove 401 and the surface of the silicon wafer is 0° to 10°.

[0082] like Figure 5 As shown, the present application also includes, when preparing silicon wafers, adding a step of cutting the rectangular silicon rod in half before slicing the rectangular silicon rod 2, so as to prepare silicon wafers directly used for preparing battery cells. There is no need to laser scribing the silicon wafers before preparing the battery, thus avoiding poor passivation of the silicon wafer edges caused by laser scribing, which affects the photoelectric conversion efficiency of the battery cells.

[0083] Step S104, the rectangular silicon rod 2 is evenly cut into two halves along the cutting plane 23 parallel to the first surface 21 to obtain two rectangular silicon rods, namely half rods 3. Similarly, the rectangular silicon rod 2 can be gradually cut along the length direction of the rectangular silicon rod 2 by using a diamond wire to obtain two identical half rods 3, and the newly cut cutting plane 23 is arranged opposite to and parallel to the first surface 21, wherein the first surface 21 of each half rod 3 has two first chamfers 30.

[0084] Step S105, grinding the half rod 3 so that two second chamfers 40 are formed at the connection between the cutting plane 23 and the two second faces 22 of the half rod 3. In practical applications, the same grinding equipment and process as in step S300 can be used to grind and polish the cutting plane 23 and the connection between the cutting plane 23 and the two second faces 22 to obtain a flat cutting plane and a second chamfer 40. At this time, the projection length of the second chamfer 40 is less than the projection length of the first chamfer 30, and in this process, the diamond on the grinding wheel grinds the second chamfer 40 to obtain a plurality of first grooves 401, and the extension direction of the first grooves 401 is parallel to the two end faces of the silicon rod. The size of the chamfer can refer to the description of the chamfer size in the above silicon wafer 4, which will not be repeated here.

[0085] Step S106, slicing the half-rod 3 to obtain a silicon wafer 4 having two first chamfers 30 and two second chamfers 40, the silicon wafer 4 having two opposite first edges 10 and two opposite second edges 20, the first edge 10 being obtained by slicing the first surface 21 of the half-rod 3 and the cutting plane 23, the second edge 20 being obtained by slicing the second surface 22 of the half-rod 3, the first chamfer 30 and the second chamfer 40 of the silicon wafer 4 corresponding to the first chamfer 30 and the second chamfer 40 of the half-rod 3 respectively. One of the first edges 10 is connected to the two adjacent second edges 20 via the first chamfer 30, and the other first edge 10 is connected to the two adjacent second edges 20 via the second chamfer 40.

[0086] The dimensions of the first chamfer 30 and the second chamfer 40 of the obtained silicon wafer 4 can be found in the relevant description in the silicon wafer embodiment, which will not be repeated here.

[0087] In the case of adopting the above technical solution, the round silicon rod 1 is cut to obtain a rectangular silicon rod 2, and then the rectangular silicon rod 2 is ground to obtain four first chamfers 30, and then the rectangular silicon rod 2 is evenly cut into two half rods 3, each half rod 3 has two first chamfers 30, and then the half rod 3 is ground to obtain two new second chamfers 40, and finally sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. Compared with the existing method of using laser to slice the large silicon wafer obtained by slicing to obtain half-wafers, laser slicing will cause damage and defect states in the cross section of the silicon wafer, affecting the photoelectric conversion efficiency of the cell. However, the present application directly obtains half-wafers in the silicon rod processing link and after slicing. Since the rectangular silicon rod and the half rod are both ground, the morphology of the silicon rod surface and chamfer is relatively flat, and the morphology of the side and chamfer of the half-wafer directly obtained after slicing is better. After preparing the cell, the passivation effect of the cell can be improved, thereby improving the quality of the cell and improving the photoelectric conversion efficiency. In addition, the projection length of the second chamfer 40 of the prepared silicon wafer 4 is smaller than the projection length of the first chamfer 30. After the silicon wafer 4 is prepared into a back-contact half-cell battery cell, since the two opposite sides of the back-contact half-cell battery cell have two groups of first chamfers 30 and second chamfers 40 of different sizes, it already has chamfer structures of different sizes and shapes that can distinguish the positive and negative directions. Therefore, there is no need to set additional marks on the silicon wafer or battery cell, which eliminates the marking process, saves labor time, and improves processing efficiency.

[0088] like Figure 6 As shown, based on the silicon wafer described in any of the above embodiments, the embodiment of the present invention also provides another method for preparing a silicon wafer, including the following steps:

[0089] Step S201, providing a round silicon rod 1. The round silicon rod 1 can be a silicon rod manufactured by a Czochralski method.

[0090] Step S202 , cutting the round silicon rod 1 to obtain a rectangular silicon rod 2 , wherein the rectangular silicon rod 2 has two opposite first surfaces 21 and two opposite second surfaces 22 .

[0091] In practical applications, the round silicon rod 1 can be cut using a diamond wire cutting device, where four diamond wires are used to form a rectangle to cut the round silicon rod 1 simultaneously, or one diamond wire is used to cut one surface of the rectangular silicon rod 2 each time.

[0092] Step S203, the rectangular silicon rod 2 is evenly cut into two halves along the cutting plane 23 parallel to the first surface 21 to obtain two half rods 3. Similarly, the rectangular silicon rod 2 can be gradually cut along the length direction of the rectangular silicon rod 2 using a diamond wire to obtain two identical half rods 3, and the newly cut cutting plane 23 is arranged opposite to and parallel to the first surface 21, and at this time, the half rod 3 does not have a ground chamfer.

[0093] Step S204, grinding the half rod 3, so that two first chamfers 30 are formed at the connection between the first surface 21 of the half rod 3 and the two second surfaces 22, and two second chamfers 40 are formed at the connection between the cutting plane 23 of the half rod 3 and the two second surfaces 22. In this process, the diamond grains of the grinding wheel grind the second chamfers 40 to obtain a plurality of first grooves, and the extension direction of the first grooves is parallel to the two end surfaces of the silicon rod. The diamond grains of the grinding wheel grind the first chamfers 30 to obtain a plurality of second grooves, and the extension direction of the second grooves intersects with the two end surfaces of the silicon rod.

[0094] In practical applications, the four surfaces of the half rod 3 and the intersections of the four surfaces are ground and polished by a grinding device to obtain four flat surfaces and two first chamfers 30 and two second chamfers 40. The surface of the rectangular silicon rod 2 can be formed by multiple grindings or by simultaneous grinding. The grinding process is selected according to the grinding device to grind the first chamfer 30 and the second chamfer 40 respectively. The size of the chamfer can refer to the description of the chamfer size in the above silicon wafer, which will not be repeated here.

[0095] Step S205, slicing the half-rod 3 to obtain a silicon wafer 4 having two first chamfers 30 and two second chamfers 40, the silicon wafer 4 having two opposite first edges 10 and two opposite second edges 20, the first edge 10 being obtained by slicing the first surface 21 and the cutting plane 23 of the half-rod 3, the second edge 20 being obtained by slicing the second surface 22 of the half-rod 3, the first chamfer 30 and the second chamfer 40 of the silicon wafer 4 corresponding to the first chamfer 30 and the second chamfer 40 of the half-rod 3 respectively. One of the first edges 10 is connected to the two adjacent second edges 20 via the first chamfer 30, and the other first edge 10 is connected to the two adjacent second edges 20 via the second chamfer 40.

[0096] The dimensions of the first chamfer 30 and the second chamfer 40 of the obtained silicon wafer 4 can be found in the relevant description in the silicon wafer embodiment, which will not be repeated here.

[0097] In the case of adopting the above technical solution, the round silicon rod 1 is cut to obtain a rectangular silicon rod 2, and then the rectangular silicon rod 2 is evenly cut into two half rods 3, and then the half rod 3 is ground to obtain two first chamfers 30 and two second chamfers 40, and finally the half rod 3 is sliced ​​to obtain a silicon wafer 4 with two first chamfers 30 and two second chamfers 40. Compared with the existing method of using laser to slice the large silicon wafer obtained by slicing to obtain half-wafers, laser slicing will cause damage and defect states in the cross section of the silicon wafer, affecting the photoelectric conversion efficiency of the cell. However, the present application directly obtains half-wafers in the silicon rod processing link and after slicing. Since the rectangular silicon rod and the half rod are both ground, the morphology of the silicon rod surface and chamfer is relatively flat, and the side and chamfer of the half-wafer directly obtained after slicing are better. After preparing the cell, the passivation effect of the cell can be improved, thereby improving the quality of the cell and improving the photoelectric conversion efficiency. In addition, the size of the second chamfer 40 of the prepared silicon wafer 4 is smaller than the size of the first chamfer 30. After the silicon wafer is prepared into a back-contact half-cell cell, since the two opposite sides of the back-contact half-cell cell are respectively two groups of first chamfers and second chamfers of different sizes, the placement direction of the cell can be easily identified to assist in the alignment of the PN regions between multiple cells and distinguish the positive and negative electrodes. For example, when multiple cells are arranged to form a battery string of a component, each cell is placed in the same direction, and when the cells are aligned in the order of the first chamfer 30, the second chamfer 40, the first chamfer 30 and the second chamfer 40 in a column, the P region of the previous cell automatically aligns with the P region or N region of the next cell, and the appropriate conductive interconnection parts and string welding process can be conveniently selected to obtain a battery component. Therefore, there is no need to set additional marks on the silicon wafer or cell, which saves the marking process, saves labor time, and improves processing efficiency.

[0098] In addition, the difference between the second silicon wafer preparation method and the first silicon wafer preparation method is that the first chamfer 30 and the second chamfer 40 are obtained by grinding after cutting in half. In this way, the grinding and cutting processes can be further simplified, the number of conversions between grinding equipment and cutting equipment can be reduced, and the processing efficiency can be further improved.

[0099] In the above two silicon wafer preparation methods, the first chamfer 30 can be a partial arc surface of the round silicon rod 1. That is, when the round silicon rod 1 is cut to obtain the rectangular silicon rod 2, a partial arc surface of the round silicon rod 1 is retained on the rectangular silicon rod 2, and is directly used as the first chamfer 30 after grinding, so that the slicing utilization rate of the round silicon rod 1 can be improved, the waste of silicon rod materials can be reduced, and the cost can be reduced.

[0100] In the above two silicon wafer preparation methods, slicing the half rod 3 in step S106 and step S205 specifically includes the following steps:

[0101] The first surface 21 or the cutting plane 23 of the half rod 3 is bonded to the carrier, and the distance between the two second surfaces 22 is greater than the distance between the first surface 21 and the cutting plane 23. The carrier can be a resin plate or a plastic plate, and the half rod 3 is bonded and fixed to the wafer support through the carrier.

[0102] The carrier plate and the cutting wire net are moved close to each other in a direction perpendicular to the first surface 21, and the half-rod 3 is sliced ​​by the moving cutting wire net. In specific applications, the crystal holder is driven to move, and the carrier plate and the half-rod 3 are driven to move close to the cutting wire net. At the same time, the cutting wire net performs wire cutting, and the half-rod 3 is cut by the cutting wire net until it is cut into the carrier plate, and the slicing is completed.

[0103] Afterwards, the wafer support is driven to drive the cut silicon wafer away from the cutting wire net, and the slicing is completed, so that the adjacent attached silicon wafers 4 are separated, and finally the silicon wafer 4 is separated from the carrier to obtain the silicon wafer 4.

[0104] When the above technical solution is adopted, the slicing direction of the half rod 3 is such that the first line 50 on the obtained silicon wafer 4 is parallel to the long side direction of the silicon wafer 4, that is, the first side 10, and the extension direction of the first electrode on the half-cell battery cell made of the silicon wafer is parallel to the long side direction of the half-cell battery cell, so that the first electrode is parallel to the first line on the battery cell, reducing the risk of gate breakage of the first electrode caused by the first line.

[0105] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0106] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A silicon wafer, characterized in that: The silicon wafer has a first surface and a second surface, and a side surface between the first surface and the second surface, and the first surface and the second surface each have two opposite first edges and two opposite second edges, wherein one of the first edges is connected to two adjacent second edges via a first chamfer on the side surface of the silicon wafer, and the other of the first edges is connected to two adjacent second edges via a second chamfer on the side surface of the silicon wafer; The projection length of the first chamfer is less than 5 mm, and the projection length of the first chamfer is greater than or equal to the projection length of the second chamfer; The side surface where the second chamfer is located has a plurality of first grooves, and the angle between the extension direction of the first grooves and the first surface and / or the second surface of the silicon wafer is 0° to 10°.

2. The silicon wafer according to claim 1, characterized in that: The distance between two adjacent first grooves is less than or equal to 3 um.

3. The silicon wafer according to claim 1, characterized in that: The width of the first groove is 1 um to 20 um.

4. The silicon wafer according to claim 1, characterized in that: The thickness of the silicon wafer is 70um to 130um.

5. The silicon wafer according to claim 1, characterized in that: The length of the first side is 182 mm to 300 mm, the length of the second side is 182 mm to 300 mm, and the length of the first side is different from the length of the second side.

6. The silicon wafer according to claim 1, characterized in that: The length of the first side is 182 mm to 300 mm, and the length of the second side is 91 mm to 150 mm.

7. The silicon wafer according to claim 6, characterized in that: The second chamfer is an arc chamfer, and a first angle between a tangent line at one end of the arc chamfer connected to the first side and the first side is 30° to 60°; And / or, a second angle between a tangent line at one end of the arc-shaped chamfer connected to the second side and the second side is 30° to 50°.

8. The silicon wafer according to claim 6, characterized in that: The second chamfer is a linear chamfer, and the included angle between the linear chamfer and the first side is 35° to 85°.

9. The silicon wafer according to claim 8, characterized in that: The side surface where the first chamfer is located has a plurality of second grooves, and the extension direction of the second grooves intersects with the first surface and / or the second surface of the silicon wafer.

10. The silicon wafer according to any one of claims 1 to 9, characterized in that: The first surface and / or the second surface of the silicon wafer has a plurality of first lines arranged at intervals, and the extension direction of the first lines is the same as the extension direction of the first edge.

11. A battery cell, characterized in that: The cell is prepared from the silicon wafer according to any one of claims 1 to 10, wherein the surface of the cell has a first electrode, and the first electrode extends along a first edge of the silicon wafer.

12. The battery cell according to claim 11, characterized in that: The surface of the battery cell has a first pattern, and the first pattern and the first electrode extend in the same direction.

13. A photovoltaic module, comprising at least two solar cells and at least one conductive interconnector, wherein the conductive interconnector is connected between two adjacent solar cells, characterized in that: The battery cell is the battery cell as claimed in claim 11 or 12.

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