Solar cell and preparation method thereof, photovoltaic module and electric equipment

Abstract

The invention discloses a solar cell and a preparation method thereof, a photovoltaic module and electric equipment, and belongs to the technical field of cells. The solar cell includes: a substrate; the conducting layer is located on at least one side of the two opposite sides of the substrate in the thickness direction, and the side, away from the substrate, of the conducting layer is provided with a groove structure; the passivation contact layer is located on at least part of the inner surface of the groove structure; and the electrode structure is positioned on one side, deviating from the substrate, of the conductive layer and is filled in the groove structure. The electrode contact performance can be improved, the electrode tension is increased, the battery reliability is improved, and the battery efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of solar cells, and in particular relates to a solar cell and a preparation method thereof, a photovoltaic module, and electrical equipment. Background Art

[0002] Since the amorphous silicon film in the solar cell has poor conductivity, it is necessary to form a transparent conductive film on the amorphous silicon film to enhance the charge transport capability, and then use the low-temperature silver paste screen printing process to form electrodes on the conductive film. However, the curing and sintering temperature of the low-temperature silver paste is low, resulting in low welding tension and poor weldability after the silver paste is cured into an electrode, which affects the reliability of the electrode. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a solar cell and a preparation method, a photovoltaic module, and an electrical device, which can improve the electrode contact performance, increase the electrode tension, improve the reliability of the solar cell, and improve the efficiency of the solar cell.

[0004] In a first aspect, the present application provides a solar cell, comprising:

[0005] substrate;

[0006] A conductive layer, located on at least one of two opposite sides of the substrate along the thickness direction, wherein a side of the conductive layer facing away from the substrate has a groove structure;

[0007] A passivation contact layer, located on at least a portion of the inner surface of the groove structure;

[0008] The electrode structure is located on a side of the conductive layer away from the substrate and is filled in the groove structure.

[0009] According to the solar cell of the present application, a groove structure is provided on the side of the conductive layer facing away from the substrate, and the electrode is filled in the groove structure, thereby increasing the contact area between the electrode and the conductive layer, improving the electrode contact performance, and increasing the electrode tension, thereby improving the reliability of the solar cell. In addition, a passivation contact layer is provided on the inner surface of the groove structure to effectively passivate the recombination center formed after etching the groove structure, thereby improving the efficiency of the solar cell.

[0010] According to one embodiment of the present application, the conductive layer includes a first conductive sublayer, and the first conductive sublayer is located on one side of the substrate along the thickness direction;

[0011] The groove structure comprises a first groove, and the first groove is located on a side of the first conductive sublayer away from the substrate;

[0012] The passivation contact layer includes a first passivation layer, and the first passivation layer is located on at least a portion of the inner surface of the first groove;

[0013] The electrode structure includes a first electrode, which is located on a side of the first conductive sublayer away from the substrate and fills the first groove.

[0014] According to one embodiment of the present application, the conductive layer further includes a second conductive sublayer, and the second conductive sublayer is located on a side of the substrate away from the first conductive sublayer;

[0015] The electrode structure further includes a second electrode, and the second electrode is located on a side of the second conductive sublayer away from the substrate.

[0016] According to an embodiment of the present application, the groove structure further includes a second groove, and the second groove is located on a side of the second conductive sublayer away from the substrate;

[0017] The second electrode also fills the second groove.

[0018] According to an embodiment of the present application, the passivation contact layer further includes a second passivation layer, and the second passivation layer is located on at least a portion of the inner surface of the second groove.

[0019] According to one embodiment of the present application, the substrate includes a hole transport layer disposed near the first conductive sublayer, and an electron transport layer disposed near the second conductive sublayer; the work function of the first passivation layer is not less than the work function of the second passivation layer.

[0020] According to one embodiment of the present application, a work function difference between the first passivation layer and the second passivation layer is greater than or equal to 0 and less than or equal to 2.6 eV.

[0021] According to one embodiment of the present application, the work function of the first passivation layer is 5.0-6.2 eV, and the work function of the second passivation layer is 3.6-5.0 eV; and / or,

[0022] The first passivation layer includes MoO x 、NiO x , WO x and VO x and MoN x One or more combinations thereof, wherein the second passivation layer comprises TiO x , LiF x 、ZnO x SnO x and MgO x One or more combinations of .

[0023] According to one embodiment of the present application, the base further includes a silicon substrate, a first intrinsic amorphous silicon layer located between the silicon substrate and the hole transport layer, and a second intrinsic amorphous silicon layer located between the silicon substrate and the electron transport layer;

[0024] The hole transport layer includes a P-type doped amorphous silicon layer, and the electron transport layer includes an N-type doped amorphous silicon layer.

[0025] According to one embodiment of the present application, the thickness of the passivation contact layer is 1-3 nm; and / or,

[0026] The depth of the groove structure is 10-20 nm; and / or,

[0027] The groove structure extends along the first direction, and the size of the groove structure along the second direction is 60-90 μm.

[0028] The first direction, the second direction and the thickness direction are perpendicular to each other; and / or,

[0029] The thickness of the conductive layer is 100-140 nm.

[0030] According to one embodiment of the present application, the electrode structure includes a main gate electrode.

[0031] In a second aspect, the present application provides a method for preparing a solar cell, comprising:

[0032] Providing a substrate and a conductive layer, wherein the conductive layer is located on at least one of two opposite sides of the substrate in a thickness direction;

[0033] forming a groove structure on a side of the conductive layer away from the substrate;

[0034] forming a passivation contact layer on at least a portion of the inner surface of the groove structure;

[0035] An electrode structure is formed on a side of the conductive layer away from the substrate, and the electrode structure fills the groove structure.

[0036] In a third aspect, the present application provides a photovoltaic module, comprising the solar cell described in the first aspect.

[0037] In a fourth aspect, the present application provides an electrical device, comprising the photovoltaic module described in the third aspect above.

[0038] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0039] A groove structure is provided on the side of the conductive layer facing away from the substrate, and the electrode is filled in the groove structure, thereby increasing the contact area between the electrode and the conductive layer, improving the electrode contact performance, and increasing the electrode tension, thereby improving the reliability of the solar cell. In addition, a passivation contact layer is provided on the inner surface of the groove structure to effectively passivate the recombination center formed after etching the groove structure, thereby improving the efficiency of the solar cell.

[0040] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0042] Figure 1 This is one of the structural schematic diagrams of the solar cell provided in the embodiment of the present application;

[0043] Figure 2 This is the second structural schematic diagram of the solar cell provided in the embodiment of the present application;

[0044] Figure 3 It is a schematic diagram of the process of the method for preparing a solar cell provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0046] The solar cell and preparation method, photovoltaic module, and electrical equipment provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0047] Figure 1 and Figure 2 The schematic diagram of the structure of the solar cell provided in the embodiment of the present application. The solar cell may be a heterojunction cell (HJT) or other types of solar cells, which are not specifically limited here.

[0048] like Figure 1 and Figure 2 As shown, the solar cell provided in the embodiment of the present application includes a substrate 1, a conductive layer 2, a passivation contact layer 3 and an electrode structure 4.

[0049] The substrate 1 is used to separate and transfer charges. The substrate 1 may include a plurality of film layers stacked along the thickness direction of the substrate 1. For example, the substrate 1 may include a silicon substrate and an amorphous silicon film layer stacked along the thickness direction. The film layers in the substrate 1 may be different depending on the type of solar cell.

[0050] The conductive layer 2 is located on at least one of the two opposite sides of the substrate 1 in the thickness direction, that is, the conductive layer 2 can be located on any side of the substrate 1 in the thickness direction, or can be located on both opposite sides of the substrate 1 in the thickness direction. The conductive layer 2 is used to collect and transmit photogenerated carriers. The conductive layer 2 can be a transparent conductive film, such as TCO (indium tin oxide), IWO (indium doped tungsten oxide) or ICO (indium doped cerium oxide).

[0051] The conductive layer 2 has a groove structure 5 on one side away from the substrate 1. The groove structure 5 does not penetrate the conductive layer 2 along the thickness direction, that is, the bottom of the groove structure 5 is located inside the conductive layer 2, and the sidewall and bottom of the groove structure 5 are both conductive layer 2.

[0052] The groove structure 5 may be located on at least one of the two opposite sides of the substrate 1 in the thickness direction. In the case where the conductive layer 2 is located on either side of the substrate 1 in the thickness direction, the groove structure 5 is located on one side of the substrate 1 in the thickness direction, that is, the groove structure 5 is located in the conductive layer 2 on one side of the substrate 1 in the thickness direction. In the case where the conductive layer 2 is located on the opposite sides of the substrate 1 in the thickness direction, the groove structure 5 may be located on either side of the substrate 1 in the thickness direction, that is, the groove structure 5 may be located in the conductive layer 2 on either side of the substrate 1 in the thickness direction; the groove structure 5 may be located on the opposite sides of the substrate 1 in the thickness direction, that is, the groove structure 5 may be located in the conductive layer 2 on the opposite sides of the substrate 1 in the thickness direction.

[0053] The passivation contact layer 3 is located on at least part of the inner surface of the groove structure 5. The thickness of the passivation contact layer 3 is relatively thin, and the passivation contact layer 3 can cover part of the inner surface of the groove structure 5, or can cover the entire inner surface of the groove structure 5, such as the passivation contact layer 3 can cover the sidewall and bottom of the groove structure 5. The passivation contact layer 3 is used to effectively passivate the recombination center formed after etching the groove structure. The passivation contact layer 3 can be made of a work function material with good thermal stability.

[0054] The electrode structure 4 is located on the side of the conductive layer 2 facing away from the substrate 1, and is filled in the groove structure 5. The height of the electrode structure 4 along the thickness direction is greater than the depth of the groove structure 5 along the thickness direction, so that part of the electrode structure 4 is filled in the groove structure 5, and the other part is located outside the groove structure 5. The passivation contact layer 3 is located between the electrode structure 4 and the conductive layer 2. The electrode structure 4 is used to collect and conduct photocurrent. The electrode structure 4 can be connected to an external circuit to conduct current to the external circuit. The electrode structure 4 can include metals such as silver.

[0055] The electrode structure 4 may be located on at least one of the two opposite sides of the substrate 1 in the thickness direction. In the case where the conductive layer 2 is located on any side of the substrate 1 in the thickness direction, the electrode structure 4 and the conductive layer 2 are located on the same side of the substrate 1, that is, the substrate 1 has the conductive layer 2 and the electrode structure 4 in sequence on any side in the thickness direction. In the case where the conductive layer 2 is located on the opposite sides of the substrate 1 in the thickness direction, the electrode structure 4 is located on the opposite sides of the substrate 1 in the thickness direction, that is, the opposite sides of the substrate 1 in the thickness direction respectively have the conductive layer 2 and the electrode structure 4 in sequence.

[0056] It should be noted that, when the conductive layer 2 on one side or two opposite sides of the substrate 1 along the thickness direction has a groove structure 5, the electrode structure 4 is located on the side of the conductive layer 2 away from the substrate 1 and is filled in the groove structure 5; when the conductive layer 2 on one side of the substrate 1 along the thickness direction does not have a groove structure 5, the electrode structure 4 is located on the side of the conductive layer 2 away from the substrate 1.

[0057] In the process of preparing solar cells (such as heterojunction cells), the conductivity of the amorphous silicon film in the substrate is poor, and it is necessary to first form a transparent conductive film (such as TCO) on the amorphous silicon film, and then use screen printing technology to form electrodes on the transparent conductive film. Due to the unique properties of amorphous silicon film such as high hydrogen content, the temperature in the electrode manufacturing process must not be too high (generally the electrode curing temperature is 180-200°C), so a low-temperature silver paste screen printing process is used to form electrodes on the transparent conductive film. However, the curing and sintering temperature of low-temperature silver paste is low, resulting in low welding tension and poor solderability after the silver paste is cured into an electrode, which affects the reliability of the electrode.

[0058] Based on this, in this embodiment, a groove structure 5 is formed by etching on the side of the conductive layer 2 away from the substrate 1, a passivation contact layer 3 is formed on the inner surface of the groove structure 5, and then a low-temperature slurry is printed at the groove structure 5, and the electrode structure 4 is formed after curing and sintering. By filling the electrode structure 4 in the groove structure 5 of the conductive layer 2, the contact area between the electrode structure 4 and the conductive layer 2 is increased, the electrode contact performance is improved, and the electrode tension is increased, thereby improving the battery reliability.

[0059] In addition, the etching of the groove structure 5 will introduce impurities and defects, introduce localized energy levels in the forbidden band, and become recombination centers, which will promote the recombination of electrons and holes, resulting in a shortened carrier lifetime, thereby affecting the battery efficiency. In this embodiment, a passivation contact layer 3 is formed on the inner surface of the groove structure 5, and the passivation contact layer 3 covers the recombination center to make it inactive, thereby reducing the recombination rate, increasing the carrier lifetime, and further improving the battery efficiency.

[0060] In some embodiments, the electrode structure 4 may include a main gate electrode, which is located on the side of the conductive layer 2 away from the substrate 1 and fills the groove structure 5. This embodiment can increase the contact area between the main gate electrode and the conductive layer 2, improve the contact performance of the main gate electrode, and increase the tension of the main gate electrode.

[0061] The electrode structure 4 may further include a secondary gate electrode. The secondary gate electrode is located on a side of the conductive layer 2 away from the substrate 1 , or the secondary gate electrode is located on a side of the conductive layer 2 away from the substrate 1 and fills the groove structure 5 .

[0062] In some embodiments, the conductive layer 2 includes a first conductive sublayer 21, which is located on one side of the substrate 1 along the thickness direction. The first conductive sublayer 21 can be located on any side of the substrate 1 along the thickness direction, for example, the first conductive sublayer 21 is located on the back side of the substrate 1.

[0063] The groove structure 5 includes a first groove 51, which is located on the side of the first conductive sublayer 21 away from the substrate 1. The passivation contact layer 3 includes a first passivation layer 31, which is located on at least part of the inner surface of the first groove 51, that is, the first passivation layer 31 covers the sidewall and bottom of the first groove 51. The electrode structure 4 includes a first electrode 41, which is located on the side of the first conductive sublayer 21 away from the substrate 1 and fills the first groove 51. The first electrode 41 can be a main gate electrode.

[0064] The groove structure 5 may include one or more first grooves 51. The first groove 51 may extend along a first direction, and a plurality of first grooves 51 may be spaced apart along a second direction, and the thickness direction, the first direction, and the second direction are perpendicular to each other.

[0065] The passivation contact layer 3 may include one or more first passivation layers 31. The number of the first passivation layers 31 may be less than or equal to the number of the first grooves 51. Each first passivation layer 31 corresponds to at least a portion of the inner surface of a first groove 51. In the case where the number of the first passivation layers 31 is less than the number of the first grooves 51, the inner surfaces of some of the first grooves 51 are provided with the first passivation layer 31, and the inner surfaces of another portion of the first grooves 51 do not have the first passivation layer 31. In the case where the number of the first passivation layers 31 is the same as the number of the first grooves 51, the inner surface of each first groove 51 is provided with a first passivation layer 31 to effectively passivate the recombination center formed after etching each first groove 51, thereby effectively improving the battery efficiency.

[0066] The electrode structure 4 may include one or more first electrodes 41. The first electrode 41 may extend along the first direction, and the plurality of first electrodes 41 may be arranged at intervals along the second direction. The number of the first electrodes 41 may be greater than or equal to the number of the first grooves 51. Each first groove 51 corresponds to a first electrode 41. When the number of the first electrodes 41 is greater than the number of the first grooves 51, part of the first electrodes 41 are filled in the first grooves 51, and another part of the first electrodes 41 are located on the side of the first conductive sublayer 21 away from the substrate 1 and are not filled in the first grooves 51. When the number of the first electrodes 41 is the same as the number of the first grooves 51, each first electrode 41 is filled in a first groove 51 to increase the contact area between each first electrode 41 and the first conductive sublayer 21, improve the contact performance of each first electrode 41, and increase the tension of each first electrode 41.

[0067] In some embodiments, Figure 2 As shown, the conductive layer 2 further includes a second conductive sublayer 22, that is, the conductive layer 2 includes a first conductive sublayer 21 and a second conductive sublayer 22. The second conductive sublayer 22 is located on the side of the substrate 1 away from the first conductive sublayer 21, that is, the first conductive sublayer 21 and the second conductive sublayer 22 are respectively located on opposite sides of the substrate 1 along the thickness direction. The first conductive sublayer 21 has a first groove 51, and the second conductive sublayer 22 may have a groove or may not have a groove.

[0068] The electrode structure 4 further includes a second electrode 42, that is, the electrode structure 4 includes a first electrode 41 and a second electrode 42. The first electrode 41 is located on the side of the first conductive sublayer 21 away from the substrate 1 and fills the first groove 51. The second electrode 42 is located on the side of the second conductive sublayer 22 away from the substrate 1.

[0069] The electrode structure 4 may include one or more second electrodes 42. The second electrode 42 may extend along the first direction, and a plurality of second electrodes 42 may be arranged at intervals along the second direction. The second electrode 42 may be a main gate electrode.

[0070] When the second conductive sublayer 22 has no groove, the second electrode 42 is located on the side of the second conductive sublayer 22 away from the substrate 1. When the second conductive sublayer 22 has a groove, the second electrode 42 is located on the side of the second conductive sublayer 22 away from the substrate 1 and fills the groove.

[0071] In some embodiments, the groove structure 5 further includes a second groove 52 , which is located on a side of the second conductive sublayer 22 away from the substrate 1 . The second electrode 42 is located on a side of the second conductive sublayer 22 away from the substrate 1 and fills the second groove 52 .

[0072] The groove structure 5 may include one or more second grooves 52. The second grooves 52 may extend along the first direction, and the plurality of second grooves 52 may be arranged at intervals along the second direction. The number of the second grooves 52 may be less than or equal to the number of the second electrodes 42. Each second groove 52 corresponds to a second electrode 42. When the number of the second grooves 52 is less than the number of the second electrodes 42, part of the second electrodes 42 are filled in the second grooves 52, and another part of the second electrodes 42 are located on the side of the second conductive sublayer 22 away from the substrate 1 and are not filled in the second grooves 52. When the number of the second electrodes 42 is the same as the number of the second grooves 52, each second electrode 42 is filled in a second groove 52 to increase the contact area between each second electrode 42 and the second conductive sublayer 22, improve the contact performance of each second electrode 42, and increase the tension of each second electrode 42.

[0073] The inner surface of the second groove 52 may or may not have a passivation contact layer. When the inner surface of the second groove 52 does not have a passivation contact layer, the second electrode 42 is in direct contact with the second conductive sublayer 22. When the inner surface of the second groove 52 has a passivation contact layer 3, the second electrode 42 is in contact with the second conductive sublayer 22 through the passivation contact layer 3.

[0074] In some embodiments, the passivation contact layer 3 further includes a second passivation layer 32, that is, the passivation contact layer 3 includes a first passivation layer 31 and a second passivation layer 32. The first passivation layer 31 is located on at least a portion of the inner surface of the first groove 51, and the second passivation layer 32 is located on at least a portion of the inner surface of the second groove 52.

[0075] The passivation contact layer 3 may include one or more second passivation layers 32. The number of the second passivation layers 32 may be less than or equal to the number of the second grooves 52. Each second passivation layer 32 is located on the inner surface of a corresponding second groove 52. In the case where the number of the second passivation layers 32 is less than the number of the second grooves 52, the inner surfaces of some of the second grooves 52 are provided with the second passivation layer 32, and the inner surfaces of another part of the second grooves 52 do not have the second passivation layer 32. In the case where the number of the second passivation layers 32 is the same as the number of the second grooves 52, the inner surface of each second groove 52 is provided with a second passivation layer 32 to effectively passivate the recombination center formed after etching each second groove 52, thereby effectively improving the battery efficiency.

[0076] In some embodiments, the substrate 1 includes a hole transport layer disposed near the first conductive sublayer 21, and an electron transport layer disposed near the second conductive sublayer 22. The work function of the first passivation layer 31 is not less than the work function of the second passivation layer 32. The side of the substrate 1 close to the second passivation layer 32 (such as the front side of the substrate 1) is an electron transport layer, which needs to promote electron transport. The first passivation layer 31 uses a low work function material with good thermal stability, which is conducive to electron transport and reduces the energy loss of electrons during the transmission process, thereby improving the transmission efficiency of electrons. The side of the substrate 1 close to the first passivation layer 31 (such as the back side of the substrate 1) is a hole transport layer, which needs to suppress electron transport and promote hole transport. The first passivation layer 31 uses a high work function material with good thermal stability to hinder electron transport, reduce the transmission efficiency of electrons, and further improve the efficiency of the battery.

[0077] In some embodiments, the work function difference between the first passivation layer 31 and the second passivation layer 32 is greater than or equal to 0 and less than or equal to 2.6 eV.

[0078] In some embodiments, the work function of the first passivation layer 31 is 5.0-6.2 eV, and the work function of the second passivation layer 32 is 3.6-5.0 eV.

[0079] In some embodiments, the material of the first passivation layer 31 is a high work function material with good thermal stability, such as the first passivation layer 31 includes MoO x 、NiO x , WO x and VO x and MoN x The material of the second passivation layer 32 is a high work function material with good thermal stability, such as the second passivation layer 32 includes TiO x , LiF x 、ZnO x SnO x and MgO x One or more combinations of the above.

[0080] In some embodiments, the thickness of the passivation contact layer 3 is 1-3 nm, that is, the thickness of the first passivation layer 31 is 1-3 nm, and the thickness of the second passivation layer 32 is 1-3 nm. The thickness of the first passivation layer 31 and the second passivation layer 32 may be the same or different.

[0081] In some embodiments, the depth of the groove structure 5 (i.e., the dimension of the groove structure 5 along the thickness direction) is 10-20 nm, i.e., the depth of the first groove 51 is 10-20 nm, and the depth of the second groove 52 is 10-20 nm. The depths of the first groove 51 and the second groove 52 can be the same or different.

[0082] In some embodiments, the size of the groove structure 5 along the second direction is 60-90 μm, that is, the size of the first groove 51 along the second direction is 60-90 μm, and the size of the second groove 52 along the second direction is 60-90 μm. The sizes of the first groove 51 and the second groove 52 along the second direction can be the same or different. Among them, the size of the groove structure 5 along the second direction is the width of the groove structure 5.

[0083] When the inner surface of the groove structure 5 does not have a passivation contact layer 3, the width of the groove structure 5 along the second direction is the same as the width of the electrode structure 4 along the second direction; when the inner surface of the groove structure 5 has a passivation contact layer 3, the width of the groove structure 5 along the second direction is slightly larger than the width of the electrode structure 4 along the second direction.

[0084] In some embodiments, Figure 1 As shown, the base 1 includes a silicon substrate 11 , an intrinsic amorphous silicon layer 12 located between the silicon substrate 11 and the conductive layer 2 , and a doped amorphous silicon layer 13 located between the intrinsic amorphous silicon layer 12 and the conductive layer 2 .

[0085] The intrinsic amorphous silicon layer 12 may be located on at least one of the two opposite sides of the silicon substrate 11 in the thickness direction, and the doped amorphous silicon layer 13 may be located on at least one of the two opposite sides of the silicon substrate 11 in the thickness direction. In the case where the conductive layer 2 and the electrode structure 4 are located on any side of the substrate 1 in the thickness direction (i.e., any side of the silicon substrate 1 in the thickness direction), the intrinsic amorphous silicon layer 12 and the doped amorphous silicon layer 13 are located on one side of the silicon substrate 11 in the thickness direction, and the intrinsic amorphous silicon layer 12, the doped amorphous silicon layer 13, the conductive layer 2 and the electrode structure 4 are sequentially stacked on any side of the silicon substrate 11 in the thickness direction. In the case where the conductive layer 2 and the electrode structure 4 are located on the two opposite sides of the substrate 1 in the thickness direction (i.e., the two opposite sides of the silicon substrate 1 in the thickness direction), the intrinsic amorphous silicon layer 12 and the doped amorphous silicon layer 13 are located on the two opposite sides of the silicon substrate 11 in the thickness direction, and the intrinsic amorphous silicon layer 12, the doped amorphous silicon layer 13, the conductive layer 2 and the electrode structure 4 are sequentially stacked on the two opposite sides of the silicon substrate 11 in the thickness direction.

[0086] In some embodiments, the solar cell is a heterojunction cell, such as Figure 2As shown, the base includes a silicon substrate 11, a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a hole transport layer and an electron transport layer. The first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are respectively located on opposite sides of the silicon substrate 11 along the thickness direction, the hole transport layer is located on the side of the first intrinsic amorphous silicon layer away from the silicon substrate 11, and the electron transport layer is located on the side of the second intrinsic amorphous silicon layer away from the silicon substrate 11. Among them, the hole transport layer includes a P-type amorphous silicon film 131, the electron transport layer includes an N-type amorphous silicon film 132, the first intrinsic amorphous silicon layer may include a first intrinsic hydrogenated amorphous silicon film 121, and the second intrinsic amorphous silicon layer may include a second intrinsic hydrogenated amorphous silicon film 122. The first intrinsic hydrogenated amorphous silicon film 121 is located on the back side of the silicon substrate 11, and the second intrinsic hydrogenated amorphous silicon film 122 is located on the front side of the silicon substrate 11. The P-type amorphous silicon film 131 is located on a side of the first intrinsic hydrogenated amorphous silicon film 121 away from the silicon substrate 11 , and the N-type amorphous silicon film 132 is located on a side of the second intrinsic hydrogenated amorphous silicon film 122 away from the silicon substrate 11 .

[0087] The silicon substrate 11 may be an N-type single crystal silicon substrate, and a second intrinsic hydrogenated amorphous silicon film 122 and an N-type amorphous silicon film 132 are sequentially disposed on the front side of the silicon substrate 11 to form a PN junction. A first intrinsic hydrogenated amorphous silicon film 121 and a P-type amorphous silicon film 131 are sequentially disposed on the back side of the silicon substrate 11 to form a back surface field.

[0088] The first conductive sublayer 21 is located on the side of the P-type amorphous silicon film 131 away from the silicon substrate 11, the first groove 51 is located on the side of the first conductive sublayer 21 away from the silicon substrate 11, the first passivation layer 31 is located on at least part of the inner surface of the first groove 51, and the first electrode 41 is located on the side of the first conductive sublayer 21 away from the silicon substrate 11 and fills the first groove 51. The second conductive sublayer 22 is located on the side of the N-type amorphous silicon film 132 away from the silicon substrate 11, the second groove 52 is located on the side of the second conductive sublayer 22 away from the silicon substrate 11, the second passivation layer 32 is located on at least part of the inner surface of the second groove 52, and the second electrode 42 is located on the side of the second conductive sublayer 22 away from the silicon substrate 11 and fills the second groove 52.

[0089] The first conductive sublayer 21 and the second conductive sublayer 22 may both include TCO. The thickness of the first conductive sublayer 21 and the second conductive sublayer 22 may both be 100-140 nm. In some embodiments, the thickness of the first conductive sublayer 21 and the second conductive sublayer 22 may both be 100-120 nm.

[0090] The first electrode 41 and the second electrode 42 can both be main gate electrodes. The number of the first electrodes 41 can be 20-25, and the number of the second electrodes 42 can be 20-30. The widths of the first electrode 41 and the second electrode 42 can both be 70-90 μm, and the aspect ratios of the first electrode 41 and the second electrode 42 can both be 15%-25%. In some embodiments, the number of the first electrodes 41 is 20-25, the width of the first electrode 41 is 70-80 μm, and the aspect ratio of the first electrode 41 is 20%-25%. The number of the second electrodes 42 is 20-25, the width of the second electrode 42 is 70-80 μm, and the aspect ratio of the second electrode 42 is 20%-25%. Among them, the aspect ratio of the first electrode 41 and the second electrode 42 can also be set larger to improve the photoelectric conversion efficiency of the battery and increase the short-circuit current.

[0091] According to the solar cell provided in the embodiment of the present application, a groove structure 5 is provided on the side of the conductive layer 2 facing away from the substrate 1, and the electrode structure 4 is filled in the groove structure 5, so as to increase the contact area between the electrode and the conductive layer, improve the electrode contact performance, and increase the electrode tension, thereby improving the reliability of the solar cell, and a passivation contact layer 3 is provided on the inner surface of the groove structure 5, so as to effectively passivate the recombination center formed after etching the groove structure 5, thereby improving the cell efficiency.

[0092] Correspondingly, an embodiment of the present application further provides a photovoltaic assembly, comprising the solar cell in the above embodiment.

[0093] The photovoltaic module provided in the embodiment of the present application can improve the reliability of solar cells and improve the efficiency of solar cells.

[0094] Correspondingly, an embodiment of the present application further provides an electrical device, comprising the photovoltaic module in the above embodiment.

[0095] The electrical equipment provided in the embodiments of the present application can improve the reliability of solar cells and improve the efficiency of solar cells.

[0096] Correspondingly, an embodiment of the present application also provides a method for preparing a solar cell, which can manufacture the solar cell in the above embodiment.

[0097] like Figure 3 As shown, the method for preparing a solar cell provided in the embodiment of the present application includes steps 110 to 140.

[0098] Step 110: Provide a substrate and a conductive layer, wherein the conductive layer is located on at least one of two opposite sides of the substrate along a thickness direction.

[0099] In some embodiments, in combination Figure 1 and Figure 2As shown, the base 1 includes a silicon substrate 11 , an intrinsic amorphous silicon layer 12 and a doped amorphous silicon layer 13 .

[0100] First, a silicon substrate 11 is provided, and the silicon substrate 11 is cleaned and textured to form a special pyramid texture surface to reduce light reflection and trap light. Then, a thin film deposition process is used to form an intrinsic amorphous silicon layer 12 on at least one of the two opposite sides of the silicon substrate 11 along the thickness direction. Then, a thin film deposition process is used to form an impurity-doped amorphous silicon layer 13 on the side of the intrinsic amorphous silicon layer 12 away from the silicon substrate 11. Then, a thin film deposition process is used to form a conductive layer 2 on the side of the impurity-doped amorphous silicon layer 13 away from the silicon substrate 11.

[0101] In some embodiments, Figure 2 As shown, the intrinsic amorphous silicon layer 12 may include a first intrinsic hydrogenated amorphous silicon film 121 and a second intrinsic hydrogenated amorphous silicon film 122. The doped amorphous silicon layer 13 may include a P-type amorphous silicon film 131 and an N-type amorphous silicon film 132.

[0102] First, a silicon substrate 11 is provided, and the silicon substrate 11 is cleaned and textured to form a special pyramid texture surface to reduce light reflection and trap light. Then, a first intrinsic hydrogenated amorphous silicon film 121 is formed on the back of the silicon substrate 11, and a second intrinsic hydrogenated amorphous silicon film 122 is formed on the front of the silicon substrate 11 by a thin film deposition process. Then, an N-type amorphous silicon film 132 is formed on the surface of the second intrinsic hydrogenated amorphous silicon film 122, and a P-type amorphous silicon film 131 is formed on the surface of the first intrinsic hydrogenated amorphous silicon film 121. Among them, the N-type amorphous silicon film can be used as an electron transport layer, and the P-type amorphous silicon film can be used as a hole transport layer.

[0103] In some embodiments, in combination Figure 2 As shown, the conductive layer 2 includes a first conductive sublayer 21 and a second conductive sublayer 22. The first conductive sublayer 21 and the second conductive sublayer 22 can both be TCO.

[0104] The first conductive sublayer 21 is formed on the surface of the P-type amorphous silicon film 131 , and the second conductive sublayer 22 is formed on the surface of the N-type amorphous silicon film 132 by using a magnetron sputtering (PVD) or reactive plasma deposition (RPD) process.

[0105] The conductive layer 2 can be prepared using a target material of indium tin oxide (In2O3 / SnO2 mass ratio of 99:1). The thickness of the conductive layer 2 can be 100-140nm, that is, the thickness of the first conductive sublayer 21 and the second conductive sublayer 22 can both be 100-140nm. In some embodiments, the thickness of the first conductive sublayer 21 and the second conductive sublayer 22 can both be 100-120nm.

[0106] Step 120 : forming a groove structure on a side of the conductive layer facing away from the substrate.

[0107] A laser etching or chemical etching process is used to form a groove structure 5 on the side of the conductive layer 2 facing away from the silicon substrate 11 .

[0108] In some embodiments, in combination Figure 2 As shown, the groove structure 5 includes a first groove 51 and a second groove 52 .

[0109] By using laser etching or chemical etching process, a first groove 51 is etched on the surface of the first conductive sub-layer 21 , and a second groove 52 is etched on the surface of the second conductive sub-layer 22 .

[0110] In some embodiments, the depth of the groove structure 5 (i.e., the dimension of the groove structure 5 along the thickness direction) is 10-20 nm, i.e., the depth of the first groove 51 is 10-20 nm, and the depth of the second groove 52 is 10-20 nm. The depths of the first groove 51 and the second groove 52 can be the same or different.

[0111] In some embodiments, the size of the groove structure 5 along the second direction is 60-90 μm, that is, the size of the first groove 51 along the second direction is 60-90 μm, and the size of the second groove 52 along the second direction is 60-90 μm. The widths of the first groove 51 and the second groove 52 along the second direction may be the same or different. Among them, the size of the groove structure 5 along the second direction is the width of the groove structure 5.

[0112] Step 130 : forming a passivation contact layer on at least a portion of the inner surface of the recess structure.

[0113] A thin film deposition process is used to form a passivation contact layer 3 on at least a portion of the inner surface of the groove structure 5. The passivation contact layer 3 needs to be annealed at a temperature of 180-200°C.

[0114] In some embodiments, in combination Figure 2 As shown, the passivation contact layer 3 includes a first passivation layer 31 and a second passivation layer 32 .

[0115] By adopting the PECVD process, a first passivation layer 31 is formed on the inner surface of the first groove 51 , and a second passivation layer 32 is formed on the inner surface of the second groove 52 .

[0116] In some embodiments, the work function of the first passivation layer 31 is higher than the work function of the second passivation layer 32. The side of the substrate 1 close to the second passivation layer 32 (such as the front side of the substrate 1) is an electron transport layer, which needs to promote electron transport. The first passivation layer 31 uses a low work function material with good thermal stability, which is conducive to electron transport and reduces the energy loss of electrons during the transport process, thereby improving the transmission efficiency of electrons. The side of the substrate 1 close to the first passivation layer 31 (such as the back side of the substrate 1) is a hole transport layer, which needs to inhibit electron transport and promote hole transport. The first passivation layer 31 uses a high work function material with good thermal stability to hinder electron transport, reduce the transmission efficiency of electrons, and further improve the battery efficiency.

[0117] In some embodiments, the work function difference between the first passivation layer 31 and the second passivation layer 32 is greater than 0 and less than or equal to 2.6 eV.

[0118] In some embodiments, the work function of the first passivation layer 31 is 5.0-6.2 eV, and the work function of the second passivation layer 32 is 3.6-5.0 eV.

[0119] In some embodiments, the material of the first passivation layer 31 is a high work function material with good thermal stability, such as the first passivation layer 31 includes MoO x 、NiO x , WO x and VO x and MoN x The material of the second passivation layer 32 is a high work function material with good thermal stability, such as the second passivation layer 32 includes TiO x , LiF x 、ZnO x SnO x and MgO x One or more combinations of the above.

[0120] In some embodiments, the thickness of the passivation contact layer 3 is 1-3 nm, that is, the thickness of the first passivation layer 31 is 1-3 nm, and the thickness of the second passivation layer 32 is 1-3 nm. The thickness of the first passivation layer 31 and the second passivation layer 32 may be the same or different.

[0121] Step 140: forming an electrode structure on a side of the conductive layer facing away from the substrate, and the electrode structure fills the groove structure.

[0122] The low-temperature slurry is printed by screen printing, laser transfer or inkjet printing technology, and the electrode structure is formed after solidification and sintering.

[0123] In some embodiments, in combination Figure 2As shown, the electrode structure 4 includes a first electrode 41 and a second electrode 42. The first electrode 41 and the second electrode 42 can both be metal electrodes.

[0124] A low-temperature main grid paste is printed at the first groove 51 by screen printing, laser transfer or inkjet printing technology, and the first electrode 41 is formed after sintering and curing. A low-temperature main grid paste is printed at the second groove 52, and the second electrode 42 is formed after sintering and curing. The first electrode 41 and the second electrode 42 can both be main grid electrodes. While forming the first electrode 41 and the second electrode 42, the secondary grid paste can be printed in the secondary grid contact area of ​​the conductive layer 2, and the secondary grid electrode is formed after sintering and curing.

[0125] The number of the first electrodes 41 may be 20-25, and the number of the second electrodes 42 may be 20-30. The width of the first electrode 41 and the second electrode 42 may both be 70-90 μm, and the aspect ratio of the first electrode 41 and the second electrode 42 may both be 15%-25%. In some embodiments, the number of the first electrodes 41 is 20-25, the width of the first electrode 41 is 70-80 μm, and the aspect ratio of the first electrode 41 is 20%-25%. The number of the second electrodes 42 is 20-25, the width of the second electrode 42 is 70-80 μm, and the aspect ratio of the second electrode 42 is 20%-25%.

[0126] The present application is further described in detail below in conjunction with specific implementation methods, but the implementation methods of the present application are not limited thereto.

[0127] Example 1

[0128] (1) The silicon substrate 11 (N-type single crystal silicon substrate) is cleaned and textured to form a special pyramid texture surface to reduce light reflection and trap light.

[0129] (2) A first intrinsic hydrogenated amorphous silicon film 121 is deposited on the back side of the silicon substrate 11, and a second intrinsic hydrogenated amorphous silicon film 122 is deposited on the front side of the silicon substrate 11. Then, an N-type amorphous silicon film 132 is deposited on the surface of the second intrinsic hydrogenated amorphous silicon film 122, and a P-type amorphous silicon film 131 is formed on the surface of the first intrinsic hydrogenated amorphous silicon film 121.

[0130] (3) Using magnetron sputtering or reactive plasma deposition technology, a first conductive sublayer 21 is formed on the surface of the P-type amorphous silicon film 131, and a second conductive sublayer 22 is formed on the surface of the N-type amorphous silicon film 132. The first conductive sublayer 21 and the second conductive sublayer 22 are TCO layers with a thickness of 100 nm.

[0131] (4) Using laser etching technology, a first groove 51 is etched on the surface of the first conductive sublayer 21, and a second groove 52 is etched on the surface of the second conductive sublayer 22. The first groove 51 and the second groove 52 have a depth of 20 nm and a width of 70 μm.

[0132] (5) Using the PECVD process, a first passivation layer 31 is formed on the inner surface of the first groove 51, and a second passivation layer 32 is formed on the inner surface of the second groove 52. The target material of the first passivation layer 31 can be MoO x , with a thickness of 3 nm. The target material of the second passivation layer 32 can be TiO x , thickness is 3nm.

[0133] (6) A low-temperature main grid paste is printed on the main grid contact area (including the first groove 51) of the first conductive sublayer 21 by screen printing, laser transfer or inkjet printing, and the first electrode 41 is formed after sintering and curing. A low-temperature main grid paste is printed on the main grid contact area (including the second groove 52) of the second conductive sublayer 22, and the second electrode 42 is formed after sintering and curing. At the same time, the secondary grid paste is printed on the secondary grid contact area of ​​the first conductive sublayer 21 and the second conductive sublayer 22, and the secondary grid electrode is formed after sintering and curing. The number of the first electrodes 41 is 20, the width is 70 μm, and the aspect ratio is 20%. The number of the second electrodes 42 is 20, the width is 70 μm, and the aspect ratio is 20%.

[0134] After testing, the conversion efficiency Eta of the battery in Example 1 is 25.38%, the open circuit voltage UOC is 0.749V, the short circuit current ISC is 8.773A, the fill factor FF is 85.160%, and the main grid tension average is 2.41N.

[0135] Example 2

[0136] It is basically the same as Example 1, except that in step (5) of Example 2, the thickness of the first passivation layer 31 and the second passivation layer 32 are both 2 nm.

[0137] After testing, the conversion efficiency Eta of the battery in Example 2 is 25.42%, the open circuit voltage UOC is 0.749V, the short circuit current ISC is 8.784A, the fill factor FF is 85.20%, and the main grid tension average is 2.43N.

[0138] Example 3

[0139] It is basically the same as Example 1, except that in step (5) of Example 3, the thickness of the first passivation layer 31 and the second passivation layer 32 are both 1 nm.

[0140] After testing, the conversion efficiency Eta of the battery in Example 2 is 25.48%, the open circuit voltage UOC is 0.750V, the short circuit current ISC is 8.789A, the fill factor FF is 85.240%, and the main grid tension average is 2.42N.

[0141] Comparative Example 1

[0142] (1) The silicon substrate (N-type single crystal silicon substrate) is cleaned and textured to form a special pyramid texture surface to reduce light reflection and trap light.

[0143] (2) A first intrinsic hydrogenated amorphous silicon film is deposited on the back side of the silicon substrate, and a second intrinsic hydrogenated amorphous silicon film is deposited on the front side of the silicon substrate. Then, an N-type amorphous silicon film is deposited on the surface of the second intrinsic hydrogenated amorphous silicon film, and a P-type amorphous silicon film is formed on the surface of the first intrinsic hydrogenated amorphous silicon film.

[0144] (3) Using magnetron sputtering or reactive plasma deposition technology, a first conductive sublayer is formed on the surface of the P-type amorphous silicon film, and a second conductive sublayer is formed on the surface of the N-type amorphous silicon film. The first conductive sublayer and the second conductive sublayer are TCO layers with a thickness of 100 nm.

[0145] (4) Based on the busbar-free technology and using a screen printing process, a low-temperature silver paste is printed on the surface of the first conductive sublayer and the second conductive sublayer, and the low-temperature silver paste is dried in a drying furnace (the temperature does not exceed 200° C.) to form a metal electrode. The number of metal electrodes on the surface of the first conductive sublayer is 110, the width is 30 um, and the aspect ratio is 30%. The number of metal electrodes on the surface of the second conductive sublayer is 65, the width is 30 um, and the aspect ratio is 30%.

[0146] After testing, the conversion efficiency Eta of the battery in Comparative Example 1 is 25.32%, the open circuit voltage UOC is 0.748V, the short circuit current ISC is 8.766A, the fill factor FF is 85.130%, and the average electrode tension is 1.93N.

[0147] The test results of Example 1, Example 2, Example 3 and Comparative Example 1 are shown in Table 1.

[0148]

[0149] Table 1

[0150] It can be seen from Table 1 that, compared with Comparative Example 1, Examples 1 to 3 have improved battery conversion efficiency, open circuit voltage, short circuit current, fill factor, main grid tension and other performance.

[0151] According to the method for preparing a solar cell provided in an embodiment of the present application, a groove structure 5 is provided on the side of the conductive layer 2 facing away from the substrate, and the electrode structure 4 is filled in the groove structure 5, so as to increase the contact area between the electrode and the conductive layer 2, improve the electrode contact performance, and increase the electrode tension, thereby improving the battery reliability. In addition, a passivation contact layer 3 is provided on the inner surface of the groove structure 5 to effectively passivate the recombination center formed after etching the groove structure 5, thereby improving the battery efficiency.

[0152] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0153] In the description of the present application, “plurality” means two or more.

[0154] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0155] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A solar cell, characterized in that: include: substrate; A conductive layer, located on at least one of two opposite sides of the substrate along the thickness direction, wherein a side of the conductive layer facing away from the substrate has a groove structure; A passivation contact layer, located on at least a portion of the inner surface of the groove structure; The electrode structure is located on a side of the conductive layer away from the substrate and is filled in the groove structure.

2. The solar cell according to claim 1, characterized in that The conductive layer includes a first conductive sublayer, and the first conductive sublayer is located on one side of the substrate along the thickness direction; The groove structure comprises a first groove, and the first groove is located on a side of the first conductive sublayer away from the substrate; The passivation contact layer includes a first passivation layer, and the first passivation layer is located on at least a portion of the inner surface of the first groove; The electrode structure includes a first electrode, which is located on a side of the first conductive sublayer away from the substrate and fills the first groove.

3. The solar cell according to claim 2, characterized in that: The conductive layer further includes a second conductive sublayer, and the second conductive sublayer is located on a side of the substrate away from the first conductive sublayer; The electrode structure further includes a second electrode, and the second electrode is located on a side of the second conductive sublayer away from the substrate.

4. The solar cell according to claim 3, characterized in that: The groove structure further includes a second groove, and the second groove is located on a side of the second conductive sublayer away from the substrate; The second electrode also fills the second groove.

5. The solar cell according to claim 4, characterized in that: The passivation contact layer further includes a second passivation layer, and the second passivation layer is located on at least a portion of an inner surface of the second groove.

6. The solar cell according to claim 5, characterized in that: The substrate includes a hole transport layer disposed near the first conductive sublayer, and an electron transport layer disposed near the second conductive sublayer; A work function of the first passivation layer is not less than a work function of the second passivation layer.

7. The solar cell according to claim 6, characterized in that: A work function difference between the first passivation layer and the second passivation layer is greater than or equal to 0 and less than or equal to 2.6 eV.

8. The solar cell according to claim 7, characterized in that: The work function of the first passivation layer is 5.0-6.2 eV, and the work function of the second passivation layer is 3.6-5.0 eV; and / or, The first passivation layer includes MoO x 、NiO x , WO x and VO x and MoN x One or more combinations thereof, wherein the second passivation layer comprises TiO x , LiF x 、ZnO x SnO x and MgO x One or more combinations of .

9. The solar cell according to claim 6, characterized in that: The base also includes a silicon substrate, a first intrinsic amorphous silicon layer between the silicon substrate and the hole transport layer, and a second intrinsic amorphous silicon layer between the silicon substrate and the electron transport layer; The hole transport layer includes a P-type amorphous silicon thin film, and the electron transport layer includes an N-type amorphous silicon thin film.

10. The solar cell according to any one of claims 1 to 9, characterized in that: The thickness of the passivation contact layer is 1-3 nm; and / or, The depth of the groove structure is 10-20 nm; and / or, The groove structure extends along a first direction, a size of the groove structure along a second direction is 60-90 μm, and the first direction, the second direction and the thickness direction are perpendicular to each other; and / or, The thickness of the conductive layer is 100-140 nm.

11. The solar cell according to any one of claims 1 to 9, characterized in that: The electrode structure includes a main gate electrode.

12. A method for preparing a solar cell according to any one of claims 1 to 11, characterized in that: include: Providing a substrate and a conductive layer, wherein the conductive layer is located on at least one of two opposite sides of the substrate in a thickness direction; forming a groove structure on a side of the conductive layer away from the substrate; forming a passivation contact layer on at least a portion of the inner surface of the groove structure; An electrode structure is formed on a side of the conductive layer away from the substrate, and the electrode structure fills the groove structure.

13. A photovoltaic module, characterized in that: Comprising the solar cell according to any one of claims 1 to 11.

14. An electrical device, characterized in that: Comprising the photovoltaic module as claimed in claim 13.

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