Solar cell and photovoltaic module

Abstract

The invention relates to a solar cell and a photovoltaic module. The solar cell comprises a substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, and the second surface is provided with a first edge extending along a first direction; the second surface comprises doped conductive layers arranged in or on the second surface, the doped conductive layers extend along a second direction, and the first direction intersects with the second direction; in the first direction, the second surface comprises a first area and a second area, and the first area comprises at least one first edge grid line which is close to the first edge and extends in the first direction; the distance between the doped conductive layer with the polarity opposite to that of the first edge grid line in the first area and the adjacent first edge in the second direction is D, and the distance D is larger than the distance between the doped conductive layer with at least one polarity in the second area and the adjacent first edge in the second direction. A photovoltaic module includes a cell string having electrical connections and solar cells. According to the invention, the arrangement of the edge grid lines is optimized, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular, to solar cells and photovoltaic modules. Background Art

[0002] As the demand for clean energy increases, the importance of solar cells as devices that convert sunlight energy into electrical energy is becoming increasingly prominent. Back-contact solar cells (BC cells) have attracted much attention due to their unique structural design. The positive and negative electrodes of back-contact solar cells are both set on the backlight side of the cell, and there is no grid line blocking the light side, which reduces shading losses, increases short-circuit current (Jsc), and thus improves energy conversion efficiency. In addition, the backlight side can accommodate wider metal grid lines, reducing series resistance (Rs) and increasing fill factor (FF). At the same time, the appearance is more beautiful and the assembly of components is more convenient.

[0003] However, existing back-contact solar cells have technical bottlenecks. The backlight emitter and field area lack optimized design, and the electrodes overlap in space, which increases the risk of short circuits and requires high process precision. The P-type doped conductive area and N-type doped conductive area under the positive and negative pole grid lines lack reasonable design, which limits the further improvement of battery performance. How to reasonably design the structure and production process of the P-type doped conductive area and the N-type doped conductive area, further improve the photoelectric conversion efficiency while ensuring the reliability of the components, reduce production costs, and improve the component yield, is still a problem that needs to be solved urgently.

[0004] Therefore, there is a need to provide improved solar cells and photovoltaic modules to overcome or at least reduce at least some of the disadvantages existing in the above-mentioned prior art. Summary of the invention

[0005] To solve the above technical problems, according to the first aspect of the present application, a solar cell is provided, the solar cell comprising a substrate, the substrate having a first surface and a second surface arranged opposite to each other, the second surface having a first edge extending along a first direction; the second surface comprising a doped conductive layer arranged in or on the second surface, the doped conductive layers all extending along the second direction, the first direction intersecting with the second direction; along the first direction, the second surface comprises a first region and a second region, the first region comprising at least one first edge grid line close to the first edge and extending along the first direction; the doped conductive layer in the first region having a polarity opposite to that of the first edge grid line and an adjacent first edge in the second direction are spaced apart by D, the spacing D being greater than the spacing between the doped conductive layer of at least one polarity in the second region and an adjacent first edge in the second direction.

[0006] Optionally, the distance D is greater than a distance between the doped conductive layer in the second region having a polarity opposite to that of the first edge gate line and an adjacent first edge in the second direction.

[0007] Optionally, a length of the first region in the first direction accounts for 2% to 20% of a total length of the first edge of the substrate.

[0008] Optionally, the doped conductive layer includes a first doped conductive layer and a second doped conductive layer, the first doped conductive layer and the second doped conductive layer have opposite polarities, and the first doped conductive layer and the second doped conductive layer are alternately arranged in or on the second plane; in the second region, the distance between the first doped conductive layer and the first edge in the second direction is L2, and the distance between the second doped conductive layer and the first edge in the second direction is L1, wherein 0≤L1≤300 μm; and / or 0≤L2≤300 μm.

[0009] Optionally, a doping type of the second doped conductive layer is opposite to a conductive type of the substrate, and in the second region, L1<L2.

[0010] Optionally, the second surface includes a second edge, the second edge extends along the first direction and is arranged opposite to the first edge, and the first region includes at least one second edge gate line close to the second edge and extending along the first direction; the doped conductive layer in the first region with opposite polarity to the second edge gate line is spaced B from the second edge in the second direction, and B is different from D.

[0011] Optionally, the second surface includes a second edge, the second edge extends along the first direction and is arranged opposite to the first edge, and the first region includes at least one second edge gate line close to the second edge and extending along the first direction; in the first region, a second edge doped conductive layer is arranged adjacent to the first edge, and a first edge doped conductive layer is arranged adjacent to the second edge, and the first edge doped conductive layer and the second edge doped conductive layer extend along the first direction; the projection of the second edge doped conductive layer on the second surface at least partially overlaps with the projection of the first edge gate line close to the first edge and extending along the first direction on the second surface, and / or the projection of the first edge doped conductive layer on the second surface at least partially overlaps with the projection of the second edge gate line close to the second edge and extending along the first direction on the second surface.

[0012] Optionally, the second surface includes a second edge, which extends along the first direction and is arranged opposite to the first edge; in the first region, a second edge doped conductive layer is arranged adjacent to the first edge, and a first edge doped conductive layer is arranged adjacent to the second edge, and the first edge doped conductive layer and the second edge doped conductive layer extend along the first direction; the doping type of the first edge doped conductive layer is opposite to the doping type of the substrate; the distance between the second edge doped conductive layer and the first edge in the second direction is N, and the distance between the first edge doped conductive layer and the second edge in the second direction is N′, wherein N>N′.

[0013] Optionally, the second surface includes a second edge, which extends along the first direction and is arranged opposite to the first edge; in the first region, a second edge doped conductive layer is arranged adjacent to the first edge, and a first edge doped conductive layer is arranged adjacent to the second edge, and the first edge doped conductive layer and the second edge doped conductive layer extend along the first direction; the doping type of the first edge doped conductive layer is opposite to the doping type of the substrate; the second edge doped conductive layer has a first width C in the second direction, and the first edge doped conductive layer has a second width A in the second direction, wherein C≤A.

[0014] Optionally, a collector gate line is arranged on the doped conductive layer, and in the first region, a distance between part of the collector gate line and the first edge in the second direction is d1, and in the second region, a distance between the collector gate line and the first edge in the second direction is d2, wherein d1>d2>0.

[0015] According to a second aspect of the present application, a photovoltaic assembly is provided. The photovoltaic assembly includes a cell string. The cell string includes an electrical connector and at least two of the above-mentioned solar cells. The electrical connector is electrically connected to the solar cells.

[0016] The present application optimizes the arrangement of edge grid lines to prevent short circuits caused by contact between edge grid lines and oppositely doped conductive layers; in addition, by reasonably regulating the spacing distribution between the doped conductive layer and the corresponding edge, the utilization rate of the power generation area on the substrate surface is improved, thereby improving the photoelectric conversion efficiency of the battery.

[0017] Based on the detailed description of the specific embodiments of the present application in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Features, advantages and exemplary embodiments of the present application will be described below with reference to the accompanying drawings, in which like reference numerals indicate like elements, and in which: Figure 1 A schematic diagram of a partial structure of a solar cell provided in one embodiment of the present application; Figure 2 Shows Figure 1 Schematic diagram of a first modified embodiment of a partial structure of a solar cell shown in FIG. Figure 3 Shows Figure 1 Schematic diagram of a second modified embodiment of the partial structure of a solar cell shown in ; Figure 4 Shows Figure 1 Schematic diagram of a third modified embodiment of the partial structure of a solar cell shown in ; Figure 5 Shows Figure 1 Schematic diagram of a fourth modified embodiment of the partial structure of a solar cell shown in ; Figure 6 Another partial structural schematic diagram of a solar cell provided in one embodiment of the present application; Figure 7 Shows Figure 6 A schematic diagram of a first modified embodiment of another partial structure of a solar cell shown in FIG. Figure 8 Shows Figure 6 A schematic diagram of a second modified embodiment of another partial structure of a solar cell shown in FIG. Fig. 9 Shows Figure 6 A schematic diagram of a third modified embodiment of another partial structure of a solar cell shown in FIG. Fig.10 Shows Figure 6 A schematic diagram of a fourth modified embodiment of another partial structure of a solar cell shown in FIG. Fig.11 A schematic diagram of another partial structure of a solar cell provided in one embodiment of the present application; Fig.12 A schematic diagram of another partial structure of a solar cell provided in one embodiment of the present application. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0020] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0021] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0023] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] The present application provides a solar cell. Figure 1 This is a schematic diagram of a partial structure of a solar cell 100 provided in an embodiment of the present application, wherein for the sake of simplicity, only the first edge E11 of the solar cell 100 is shown. Figure 2 Shows Figure 1 FIG. 2 is a schematic diagram of a first variant embodiment 200 of a partial structure of a solar cell shown in FIG. Figure 3 Shows Figure 1 FIG. 3 is a schematic diagram of a second modified embodiment 300 of a partial structure of a solar cell. Figure 4 Shows Figure 1 FIG. 4 is a schematic diagram of a third modified embodiment 400 of a local structure of a solar cell. Figure 5 Shows Figure 1 FIG. 5 is a schematic diagram of a fourth modified embodiment 500 of a local structure of a solar cell. Figure 6 This is another partial structural schematic diagram of a solar cell 100 provided in an embodiment of the present application, wherein for the sake of simplicity, only the second edge E12 of the solar cell 100 is shown. Figure 7 Shows Figure 6 FIG. 1 is a schematic diagram of another modified embodiment 110 of a partial structure of a solar cell. Figure 8 Shows Figure 6 FIG. 1 is a schematic diagram of a second modified embodiment 120 of another partial structure of a solar cell. Fig. 9 Shows Figure 6 FIG. 1 is a schematic diagram of a third modified embodiment 130 of another partial structure of a solar cell. Fig.10 Shows Figure 6 FIG. 1 is a schematic diagram of another modified embodiment 140 of a partial structure of a solar cell. Fig.11 A schematic diagram of another partial structure of a solar cell provided in an embodiment of the present application. Fig.12 A schematic diagram of another partial structure of a solar cell provided in one embodiment of the present application.

[0025] like Figures 1 to 12 As shown, the solar cell 100 includes a substrate 10, the substrate 10 has a first surface (not shown) and a second surface arranged opposite to each other, the second surface having a first edge E11 extending along a first direction D1. In this embodiment, the solar cell 100 may be a back contact solar cell, more specifically an interdigitated back contact solar cell (IBC cell), wherein the first surface is the light-facing surface of the solar cell 100, and the second surface is the backlight surface of the solar cell 100.

[0026] The substrate 10 may be a semiconductor substrate, and the material of the substrate 10 may be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the substrate 10 may be an intrinsic conductive substrate, an N-type conductive substrate or a P-type conductive substrate. Preferably, the substrate 10 is a P-type conductive substrate or an N-type conductive substrate. Compared with an intrinsic conductive substrate, a P-type conductive substrate or an N-type conductive substrate has better conductivity, so that the finally manufactured solar cell 100 has a lower body resistivity, thereby improving the efficiency of the solar cell 100.

[0027] Exemplarily, the substrate 10 is an N-type silicon substrate. Compared with a P-type conductive substrate, an N-type silicon substrate has the advantages of a long minority carrier lifetime, no light decay, and good weak light performance.

[0028] like Figures 1 to 12 As shown, the second surface includes a doped conductive layer arranged in or on the second surface, and the doped conductive layer extends along the second direction D2, wherein the first direction D1 intersects with the second direction D2. Specifically, in this embodiment, the first direction D1 is perpendicular to the second direction D2. The function of the doped conductive layer is to passivate the substrate surface to reduce recombination and improve the contact performance between the electrode and the substrate surface. The doped conductive layer includes a first doped conductive layer 101 and a second doped conductive layer 102, the first doped conductive layer 101 and the second doped conductive layer 102 have opposite polarities, and the first doped conductive layer 101 and the second doped conductive layer 102 are alternately arranged in or on the second surface. Specifically, in this embodiment, the first doped conductive layer 101 and the second doped conductive layer 102 are alternately arranged or alternately arranged on the second surface to achieve effective isolation between the first doped conductive layer 101 and the second doped conductive layer 102. Among them, the doping types of the first doped conductive layer 101 and the second doped conductive layer 102 are opposite to each other, so as to collect and guide electrons and holes respectively to form a photocurrent.

[0029] The first doped conductive layer 101 and the second doped conductive layer 102 may also both be semiconductor doped conductive layers. In terms of the internal arrangement of the material, the first doped conductive layer 101 and the second doped conductive layer 102 may be amorphous, microcrystalline, single crystal, nanocrystalline or polycrystalline, etc., which may be additionally formed on the substrate 10 by deposition technology, or may be formed in the substrate 10 by in-situ doping methods such as ion implantation. In terms of specific materials, the materials of the first doped conductive layer 101 and the second doped conductive layer 102 may be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs), etc. In terms of conductivity type, the first doped conductive layer 101 may be one of an N-type doped conductive layer and a P-type doped conductive layer, and the second doped conductive layer 102 may be the other of an N-type doped conductive layer and a P-type doped conductive layer.

[0030] In some examples, the first doped conductive layer 101 may be a P-type doped conductive layer, and the second doped conductive layer 102 may be an N-type doped conductive layer; or, the first doped conductive layer 101 may be an N-type doped conductive layer, and the second doped conductive layer 102 may be a P-type doped conductive layer.

[0031] Exemplarily, the substrate 10 is an N-type silicon substrate, the first doped conductive layer 101 is a boron-doped P-type doped conductive layer, and the second doped conductive layer 102 is a phosphorus-doped N-type doped conductive layer. At this time, since the heavily phosphorus-doped region has a greater solubility for metal impurities, the phosphorus in the second doped conductive layer 102 can provide phosphorus gettering passivation for the first doped conductive layer 101, thereby improving the efficiency of the solar cell 100.

[0032] In this embodiment, along the first direction D1, the second surface includes a first region 10A and a second region 10B. Specifically, the first doped conductive layer 101 and the second doped conductive layer 102 both extend along the second direction D2, and the first doped conductive layer 101 and the second doped conductive layer 102 form a first region 10A and a second region 10B on the second surface, wherein the first region 10A includes at least one first edge gate line 210 close to the first edge E11 and extending along the first direction D1. Specifically, as Figures 1 to 12 As shown, the first doped conductive layer 101 and the second doped conductive layer 102 both extend substantially along the second direction D2. It should be noted that, in order to make the illustration clearer, the first region 10A and the second region 10B are distinguished by a single-point dashed line in the figure, that is, the region composed of the first doped conductive layer 101 and the second doped conductive layer 102 shown on the left side of the single-point dashed line is the first region 10A, and the region composed of the first doped conductive layer 101 and the second doped conductive layer 102 shown on the right side of the single-point dashed line is the second region 10B.

[0033] In this embodiment, the distance between the doped conductive layer with opposite polarity to the first edge gate line 210 in the first region 10A and the adjacent first edge E11 in the second direction D2 is D, and the distance D is greater than the distance between the doped conductive layer with at least one polarity in the second region 10B and the adjacent first edge E11 in the second direction D2.

[0034] Optionally, in the second region 10B, the distance between the first doped conductive layer 101 and the first edge E11 in the second direction D2 is L2, and the distance between the second doped conductive layer 102 and the first edge E11 in the second direction D2 is L1, wherein D>L1, or D>L2, or D>L1 and D>L2. This arrangement, on the one hand, provides a structural basis for the optimized arrangement of edge gate lines, preventing the edge gate lines from contacting with the oppositely doped conductive layer and causing a short circuit; on the other hand, by reasonably regulating the distribution of the distance between the doped conductive layer and the first edge E11, the utilization rate of the power generation area on the substrate surface is improved, thereby improving the photoelectric conversion efficiency of the battery.

[0035] In some embodiments, the distance D is greater than the distance between the doped conductive layer with opposite polarity to the first edge gate line 210 in the second region 10B and the adjacent first edge E11 in the second direction D2. Figure 1 In the embodiment shown, D>L2. Specifically, such arrangement increases the area of ​​the doped conductive layer with opposite polarity to the edge gate line in the second region 10B, compensates for the reduced area of ​​the doped conductive layer with opposite polarity to the edge gate line in the first region 10A, and improves current adaptability.

[0036] In this embodiment, the spacing D satisfies 600 μm≤D≤1100 μm. For example, the spacing D may be 600 μm, or 650 μm, or 700 μm, or 750 μm, or 800 μm, or 850 μm, or 900 μm, or 950 μm, or 1000 μm, or 1050 μm, or 1100 μm, or any value between any two of the above.

[0037] In some embodiments, the length of the first region 10A in the first direction D1 accounts for 2% to 20% of the total length of the first edge E11 of the substrate 10. If the length of the first region 10A in the first direction D1 accounts for 2% or more, sufficient space can be provided for the edge grid line setting, reducing the process difficulty; if the length of the first region 10A in the first direction D1 accounts for 20% or less, it can prevent excessive loss of power generation area on the basis of ensuring the processing accuracy of the edge grid line, thereby ensuring the power generation efficiency of the solar cell. Fig.11 For example, the “length of the first region 10A in the first direction D1” defined herein may refer to Fig.11 The distance between the dashed line shown in FIG. 1 and the first point P1 in the first direction D1, or Fig.11 The distance between the single-point dashed line shown in and the second point P2 in the first direction D1, wherein the first point P1 is the intersection of the chamfer of the substrate 10 and the first edge E11, the second point P2 is the point on the third edge E13 of the substrate 10 that is farthest from the single-point dashed line in the first direction D1, and the chamfer is arranged between the first edge E11 and the third edge E13.

[0038] Specifically, the length of the first region 10A in the first direction D1 may account for 2%, 5%, 8%, 11%, 15%, 18%, 20% of the total length of the first edge E11 of the substrate 10, or any value therebetween.

[0039] like Figures 1 to 5As shown, the spacings L1 and L2 satisfy the following conditions: 0≤L1≤300 μm; and / or, 0≤L2≤300 μm. In the second region 10B, the spacing L2 between the first doped conductive layer 101 and the first edge E11 in the second direction D2 and the spacing L1 between the second doped conductive layer 102 and the first edge E11 in the second direction D2 may be the same or different. Specifically, in the second region 10B, there are three typical structural configuration modes: In the first structural configuration mode, L1=L2≠0, that is, the lengths of the first doped conductive layer 101 and the second doped conductive layer 102 in the second direction D2 are the same, and the spacing L1 is equal to the spacing L2, see Figure 1 and Figures 3 to 5 , this design is conducive to achieving uniform carrier distribution; in the second structural configuration mode, the first doped conductive layer 101 and the second doped conductive layer 102 have different lengths in the second direction D2, and one of L1 and L2 is 0, specifically, the second doped conductive layer 102 extends along the second direction D2 to the first edge E11, and the first doped conductive layer 101 is spaced apart from the first edge E11 in the second direction D2 (not shown), or the first doped conductive layer 101 extends along the second direction D2 to the first edge E11, and the second doped conductive layer 102 is spaced apart from the first edge E11 in the second direction D2 (see Figure 2 ), this design can optimize the electric field distribution; in the third configuration mode, L1=L2=0, that is, the first doped conductive layer 101 and the second doped conductive layer 102 both extend along the second direction D2 to the first edge E11. Among them, the first doped conductive layer 101 and / or the second doped conductive layer 102 extend along the second direction D2 to the first edge E11. Such an increased area of ​​the doped conductive layer is conducive to reducing the electrode transmission resistance and improving the carrier collection efficiency. In addition, the graphical design simplifies the production process, which not only improves the process controllability, but also can achieve production capacity improvement.

[0040] In some embodiments, when the doping type of the second doped conductive layer 102 is opposite to the conductivity type of the substrate, in the second region 10B, the distance L1 between the second doped conductive layer 102 and the first edge E11 in the second direction D2 is smaller than the distance L2 between the first doped conductive layer 101 and the first edge E11 in the second direction D2, that is, L1<L2. In other words, in the second region 10B, the area of ​​the second doped conductive layer 102 is larger than the area of ​​the first doped conductive layer 101. When the doping type of the second doped conductive layer 102 is opposite to the conductivity type of the substrate, increasing the area of ​​the second doped conductive layer as a junction region can facilitate the separation and extraction of carriers, thereby improving the photoelectric conversion efficiency.

[0041] For example, the spacing L1 can be 10 μm, or 20 μm, or 30 μm, or 40 μm, or 50 μm, or 60 μm, or 70 μm, or 80 μm, or 90 μm, or 100 μm, or 110 μm, or 120 μm, or 130 μm, or 140 μm, or 150 μm, or 160 μm, or 170 μm, or 180 μm, or 190 μm, or 200 μm, or 210 μm, or 220 μm, or 230 μm, or 240 μm, or 250 μm, or 260 μm, or 270 μm, or 280 μm, or 290 μm, or 300 μm, or any value in between any two of the above.

[0042] For example, the spacing L2 can be 10 μm, or 20 μm, or 30 μm, or 40 μm, or 50 μm, or 60 μm, or 70 μm, or 80 μm, or 90 μm, or 100 μm, or 110 μm, or 120 μm, or 130 μm, or 140 μm, or 150 μm, or 160 μm, or 170 μm, or 180 μm, or 190 μm, or 200 μm, or 210 μm, or 220 μm, or 230 μm, or 240 μm, or 250 μm, or 260 μm, or 270 μm, or 280 μm, or 290 μm, or 300 μm, or any value in between any two of the above.

[0043] In some embodiments, Figures 6 to 10 as well as Fig.12 As shown, the second surface includes a second edge E12, the second edge E12 extends along the first direction D1 and is arranged opposite to the first edge E11, the first region 10A includes at least one second edge grid line 210' close to the second edge E12 and extending along the first direction D1, and the distance between the doped conductive layer with the opposite polarity to the second edge grid line 210' in the first region 10A and the second edge E12 in the second direction D2 is B, and B is different from D. In this way, by reasonably regulating the distribution of the distances between the doped conductive layer and the first edge E11 and the second edge E12, the junction area of ​​the solar cell is increased, thereby improving the photoelectric conversion efficiency of the cell.

[0044] In this embodiment, the spacing B satisfies 680 μm≤B≤1020 μm. For example, the spacing B may be 680 μm, or 700 μm, or 720 μm, or 750 μm, or 780 μm, or 800 μm, or 820 μm, or 850 μm, or 880 μm, or 900 μm, or 920 μm, or 950 μm, or 980 μm, or 1000 μm, or 1020 μm, or any value between any two of the above.

[0045] In some embodiments, the second surface includes a second edge E12, the second edge E12 extends along the first direction D1 and is arranged opposite to the first edge E11, the first region 10A includes at least one second edge gate line 210′ ​​close to the second edge E12 and extending along the first direction D1; in the first region 10A, a second edge doped conductive layer 102A is arranged close to the first edge E11, and a first edge doped conductive layer 101A is arranged close to the second edge E12, and the first edge doped conductive layer 101A and the second edge doped conductive layer 102A extend along the first direction D1. The projection of the second edge doped conductive layer 102A on the second surface at least partially overlaps with the projection of the first edge gate line 210 close to the first edge E11 and extending along the first direction D1 on the second surface, and / or the projection of the first edge doped conductive layer 101A on the second surface at least partially overlaps with the projection of the second edge gate line 210′ ​​close to the second edge E12 and extending along the first direction D1 on the second surface. The projection areas of the edge doped conductive layer and the corresponding edge gate line on the second surface at least partially overlap, which can further improve the contact performance between the edge gate line and the substrate and is beneficial to the collection and extraction of carriers.

[0046] Optionally, a distance B between the doped conductive layer with opposite polarity to the second edge gate line 210′ ​​in the first region 10A and the second edge E12 in the second direction D2 is greater than a distance D between the doped conductive layer with opposite polarity to the first edge gate line 210 in the first region 10A and the adjacent first edge E11 in the second direction D2, that is, B>D. When the doping type of the first edge doped conductive layer 101A is the same as the conductive type of the substrate 10, in the case of B>D, the area of ​​the doped conductive layer in the junction region near the second edge E12 in the first region 10A can be increased, the junction area can be increased, and the efficiency of carrier separation and extraction can be improved, thereby improving the battery efficiency.

[0047] The shapes of the first edge doped conductive layer 101A and the second edge doped conductive layer 102A can be optimized according to structural elements such as pads and edge gate lines. This design not only improves the current collection efficiency, but also avoids welding operations in the edge area, thereby reducing the risk of stress concentration and cracking, and further improving the yield and reliability of the component. For example, see Figures 1 to 5 , the widening conductive layer is located at the right end of the second edge doped conductive layer 102A and has a widening width M, and the rest of the second edge doped conductive layer 102A remains as a non-widening conductive layer. Figures 6 to 10 In the local area shown, the widened conductive layer is located at the right end of the first edge doped conductive layer 101A and has a widened width M′, while the rest of the first edge doped conductive layer 101A remains as a non-widened conductive layer. Figures 4 to 5 , the boundary of the second edge-doped conductive layer 102A adjacent to the second region 10B may have at least one second protrusion T102. Figure 6 to Figure 7 , the boundary of the first edge doped conductive layer 101A adjacent to the second region 10B may have at least one first protrusion T101. Figures 1 to 12 In the local area shown, a hollow area X can be set in the widened conductive layer, and the hollow area X does not contain a doped conductive layer. This setting can form a velvet surface in the hollow area to increase the light trapping effect of the solar cell and increase the bifaciality. On the other hand, it can balance the current adaptability on the basis of ensuring welding, and avoid the current imbalance caused by the excessive area of ​​the doped conductive layer of a local doping type. It should be noted that the size of the hollow area can be designed according to the actual situation and is not limited to the illustrated situation.

[0048] In some embodiments, Fig.11 In the first region 10A, the length of the second edge doped conductive layer 102A in the first direction D1 accounts for 3% to 17% of the total length of the first edge E11 of the substrate 10, and / or the length of the second edge doped conductive layer 102A in the first direction D1 is greater than or equal to 7 mm and less than or equal to 8.50 mm. For example, the length of the second edge doped conductive layer 102A in the first direction D1 can be 7.mm, or 7.26 mm, or 7.36 mm, or 7.46 mm, or 7.56 mm, or 7.66 mm, or 7.76 mm, or 7.86 mm, or 7.96 mm, or 8.02 mm, or 8.22 mm, or 8.50 mm, or any value between any two of the above. It should be noted that Figures 1 to 5 Only a portion of the second edge doped conductive layer 102A is schematically shown, rather than the entire second edge doped conductive layer 102A being completely shown. Fig.11The entire second edge doped conductive layer 102A is shown in full, wherein the length of the second edge doped conductive layer 102A in the first direction D1 refers to the distance from the edge of the second edge doped conductive layer 102A adjacent to the second region 10B to the edge of the second edge doped conductive layer 102A away from the second region 10B.

[0049] In some embodiments, Fig.12 , in the first region 10A, the length of the first edge doped conductive layer 101A in the first direction D1 accounts for 4% to 20% of the total length of the first edge E11 of the substrate 10, and / or the length of the first edge doped conductive layer 101A in the first direction D1 is greater than or equal to 8 mm and less than or equal to 9.5 mm. For example, the length of the first edge doped conductive layer 101A in the first direction D1 can be 8 mm, 8.21 mm, or 8.31 mm, or 8.41 mm, or 8.51 mm, or 8.61 mm, or 8.71 mm, or 8.81 mm, or 8.91 mm, or 9.01 mm, or 9.15 mm, or 9.35 mm, or 9.5 mm, or any value between any two of the above. Similarly, Figures 6 to 10 Only a portion of the first edge doped conductive layer 101A is schematically shown, rather than the entire first edge doped conductive layer 101A being completely shown. Fig.12 The entire first edge doped conductive layer 101A is shown in full, wherein the length of the first edge doped conductive layer 101A in the first direction D1 refers to the distance from the edge of the first edge doped conductive layer 101A adjacent to the second region 10B to the edge of the first edge doped conductive layer 101A away from the second region 10B.

[0050] In some embodiments, in the first region 10A, a second edge doped conductive layer 102A is disposed adjacent to the first edge E11, and a first edge doped conductive layer 101A is disposed adjacent to the second edge E12, and the first edge doped conductive layer 101A and the second edge doped conductive layer 102A extend along a first direction D1; the doping type of the first edge doped conductive layer 101A is opposite to the doping type of the substrate; Figure 1 and Figure 6As shown, the spacing between the second edge doped conductive layer 102A and the first edge E11 in the second direction D2 is N, and the spacing between the first edge doped conductive layer 101A and the second edge E12 in the second direction D2 is N′, wherein N>N′. Designed in this way, it is possible to flexibly adjust whether there is a blank area between the edge doped conductive layer and the corresponding edge (i.e., no doped conductive layer exists in the blank area) according to actual needs. This design flexibility enables the solar cell to better adapt to different process conditions and performance requirements during the manufacturing process, while taking into account the reliability and efficiency of the solar cell. Reducing the blank area or even not setting the blank area at the edge of the first edge doped conductive layer 101A with the opposite doping type to the substrate can increase the area of ​​the PN junction region and improve the carrier separation and extraction efficiency. In addition, by setting the blank area between the edge doped conductive layer and the corresponding edge, the direct contact between the opposite doped conductive layers can be effectively isolated, avoiding the leakage problem caused by the short circuit between the opposite doped conductive layers, thereby improving the electrical performance and reliability of the solar cell.

[0051] Optionally, N′=0; and / or, the spacing N satisfies 50 μm≤N≤300 μm. For example, the spacing N may be 50 μm, or 60 μm, or 70 μm, or 80 μm, or 90 μm, or 100 μm, or 110 μm, or 120 μm, or 130 μm, or 140 μm, or 150 μm, or 160 μm, or 170 μm, or 180 μm, or 190 μm, or 200 μm, or 210 μm, or 220 μm, or 230 μm, or 240 μm, or 250 μm, or 260 μm, or 270 μm, or 280 μm, or 290 μm, or 300 μm, or any value therebetween.

[0052] In some embodiments, in the first region 10B, a second edge doped conductive layer 102A is disposed adjacent to the first edge E11, and a first edge doped conductive layer 101A is disposed adjacent to the second edge E12, and the first edge doped conductive layer 101A and the second edge doped conductive layer 102A extend along a first direction D1; the doping type of the first edge doped conductive layer 101A is opposite to the doping type of the substrate; The second edge doped conductive layer 102A has a first width C in the second direction D2, and the first edge doped conductive layer 101A has a second width A in the second direction D2, wherein C≤A. The width of the second edge doped conductive layer 102A is set to be relatively small, thereby avoiding leakage problems caused by short circuits between heterogeneous doped conductive layers, thereby improving the electrical performance and reliability of the solar cell.

[0053] like Figure 1 As shown, 200 μm≤C≤500 μm. Specifically, the first width C is the width of the second edge doped conductive layer 102A between the first edge E11 and the first doped conductive layer 101 in the second direction D2. This design optimizes the structural layout of the solar cell by rationalizing the local partitioning of the backlight surface, thereby improving the overall performance of the solar cell.

[0054] For example, the first width C may be 200 μm, or 210 μm, or 220 μm, or 230 μm, or 240 μm, or 250 μm, or 260 μm, or 270 μm, or 280 μm, or 290 μm, or 300 μm, or 310 μm, or 320 μm, or 330 μm, or 340 μm, or 350 μm, or 360 μm, or 370 μm, or 380 μm, or 390 μm, or 400 μm, or 410 μm, or 420 μm, or 430 μm, or 440 μm, or 450 μm, or 460 μm, or 470 μm, or 480 μm, or 490 μm, or 500 μm, or any value in between any two of the above.

[0055] Optionally, 630 μm≤A≤970 μm. Specifically, the second width A is the width of the portion of the first edge doped conductive layer 101A between the second edge E12 and the second doped conductive layer 102 in the second direction D2. This design optimizes the structural layout of the solar cell by rationalizing the local partitioning of the backlight surface, thereby improving the overall performance of the solar cell.

[0056] For example, the second width A may be 630 μm, or 640 μm, or 650 μm, or 660 μm, or 670 μm, or 680 μm, or 690 μm, or 700 μm, or 710 μm, or 720 μm, or 730 μm, or 740 μm, or 750 μm, or 760 μm, or 770 μm, or 780 μm, or 790 μm, or 800 μm, or 810 μm, or 820 μm, or 830 μm, or 840 μm, or 850 μm, or 860 μm, or 870 μm, or 880 μm, or 890 μm, or 900 μm, or 910 μm, or 920 μm, or 930 μm, or 940 μm, or 950 μm, or 960 μm. μm, or 970 μm, or any value therebetween.

[0057] In some embodiments, Fig.11 and Fig.12 As shown, a collector grid line is arranged on the doped conductive layer, and in the first region 10A, the distance between part of the collector grid line and the first edge E11 in the second direction D2 is d1, and in the second region 10B, the distance between the collector grid line and the first edge E11 in the second direction D2 is d2, wherein d1>d2>0. The distance between part of the collector grid line and the first edge E11 in the first region 10A in the second direction D2 is greater than the distance between the collector grid line and the first edge E11 in the second region 10B in the second direction D2, so as to avoid leakage caused by the collector grid line exceeding the range of the doped conductive layer. In addition, the distance between the collector grid line and the first edge in the first region and the second region needs to be greater than or equal to 0, that is, the collector grid line cannot directly contact the edge of the substrate, so as to reduce the occurrence of leakage and reduce the cost of electrode raw materials.

[0058] The method for preparing the solar cell in the embodiment of the present application is roughly as follows.

[0059] S1: Select a single crystal silicon wafer, and perform double-sided polishing on the single crystal silicon wafer to remove a damaged layer to obtain a silicon substrate, wherein the silicon substrate has a first surface and a second surface opposite to the first surface.

[0060] S2: The second surface of the silicon substrate is subjected to tunneling oxide layer and polysilicon layer preparation.

[0061] S3: depositing and diffusing doping elements on the polysilicon layer to form a first doped conductive layer.

[0062] S4: Design a barrier layer or laser film opening, and then use alkaline etching to perform interval etching to etch and remove the first doped conductive layer until the silicon substrate is reached, so that the high layer and the middle layer are arranged adjacently and spaced apart.

[0063] S5: preparing a tunneling oxide layer and a polysilicon layer on the second surface of the silicon substrate and the second surface of the remaining first doped conductive layer.

[0064] S6: performing phosphorus deposition diffusion on the polysilicon layer after step S5 to form a second doped conductive layer.

[0065] S7: After step S6, the first doped conductive layer remaining after step S4 is subjected to printing etching or laser film opening, wherein the etching width or the film opening width is larger than the first doped conductive layer.

[0066] S8: After step S7, the first surface of the silicon substrate is acid-etched and then alkaline-textured, so that a velvet structure with light-trapping function is formed on the light-facing surface. The velvet structure may include a pyramid structure, and the back-to-light surface forms high-level areas, low-level areas, and middle-level areas that are staggered, thereby isolating the first doped conductive layer from the second doped conductive layer.

[0067] S9: passivating the structure after step S8, so that the light-facing surface is covered with multiple passivation anti-reflection film layers, and the backlight surface is covered with multiple passivation films, thereby forming a composite passivation film layer on the backlight surface.

[0068] S10: Electrodes are printed at intervals on the composite passivation film layer, electrodes are formed on the first doped conductive layer and the second doped conductive layer respectively, and a low-layer gap area is set on the backlight surface and between the high layer and the middle layer, wherein the ratio of the width of the first doped conductive layer to the width of the second doped conductive layer is approximately between 0.85 and 1.75 (the optimal ratio for different line spacings is different).

[0069] The embodiment of the present application also provides a photovoltaic module. The photovoltaic module includes a battery string, and the battery string includes an electrical connector (such as a welding strip) and at least two of the above-mentioned solar cells 100, and the electrical connector is electrically connected to the solar cell. That is, at least two solar cells 100 in the photovoltaic module can be connected in series and / or in parallel through the electrical connector to form a battery string.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "an example", "some embodiments", or "preferred embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0071] The embodiments of the present application are described in detail above. However, aspects of the present application are not limited to the above embodiments. Various modifications and substitutions may be applied to the above embodiments without departing from the scope of the present application.

Claims

1. A solar cell, characterized in that: include A substrate, the substrate having a first surface and a second surface arranged opposite to each other, the second surface having a first edge extending along a first direction; The second surface includes a doped conductive layer arranged in or on the second surface, the doped conductive layers all extend along a second direction, and the first direction intersects the second direction; Along the first direction, the second surface includes a first area and a second area, and the first area includes at least one first edge grid line close to the first edge and extending along the first direction; The distance between the doped conductive layer with opposite polarity to the first edge gate line in the first region and the adjacent first edge in the second direction is D, and the distance D is greater than the distance between the doped conductive layer with at least one polarity in the second region and the adjacent first edge in the second direction.

2. The solar cell according to claim 1, characterized in that The distance D is greater than a distance between the doped conductive layer in the second region having a polarity opposite to that of the first edge gate line and an adjacent first edge in the second direction.

3. The solar cell according to claim 1, characterized in that A length of the first region in the first direction accounts for 2% to 20% of a total length of the first edge of the substrate.

4. The solar cell according to claim 1, characterized in that The doped conductive layer comprises a first doped conductive layer and a second doped conductive layer, the first doped conductive layer and the second doped conductive layer have opposite polarities, and the first doped conductive layer and the second doped conductive layer are alternately arranged in or on the second plane; In the second region, a distance between the first doped conductive layer and the first edge in the second direction is L2, and a distance between the second doped conductive layer and the first edge in the second direction is L1, wherein 0≤L1≤300 μm; and / or 0≤L2≤300 μm.

5. The solar cell according to claim 4, characterized in that: The doping type of the second doped conductive layer is opposite to the conductivity type of the substrate, and in the second region, L1<L2.

6. The solar cell according to claim 1, characterized in that The second surface includes a second edge, the second edge extends along the first direction and is arranged opposite to the first edge, and the first region includes at least one second edge grid line close to the second edge and extending along the first direction; The distance between the doped conductive layer in the first region having a polarity opposite to that of the second edge gate line and the second edge in the second direction is B, and B is different from D.

7. The solar cell according to claim 1, characterized in that The second surface includes a second edge, the second edge extends along the first direction and is arranged opposite to the first edge, and the first region includes at least one second edge grid line close to the second edge and extending along the first direction; In the first region, a second edge doped conductive layer is disposed adjacent to the first edge, and a first edge doped conductive layer is disposed adjacent to the second edge, and the first edge doped conductive layer and the second edge doped conductive layer extend along the first direction; The projection of the second edge doped conductive layer on the second surface at least partially overlaps with the projection of the first edge gate line on the second surface close to the first edge and extending along the first direction, and / or the projection of the first edge doped conductive layer on the second surface at least partially overlaps with the projection of the second edge gate line on the second surface close to the second edge and extending along the first direction.

8. The solar cell according to claim 1, characterized in that The second surface includes a second edge, the second edge extends along the first direction and is arranged opposite to the first edge; In the first region, a second edge doped conductive layer is disposed adjacent to the first edge, and a first edge doped conductive layer is disposed adjacent to the second edge, the first edge doped conductive layer and the second edge doped conductive layer extend along the first direction; the doping type of the first edge doped conductive layer is opposite to the doping type of the substrate; The distance between the second edge doped conductive layer and the first edge in the second direction is N, and the distance between the first edge doped conductive layer and the second edge in the second direction is N′, wherein N>N′.

9. The solar cell according to claim 1, characterized in that: The second surface includes a second edge, the second edge extends along the first direction and is arranged opposite to the first edge; In the first region, a second edge doped conductive layer is disposed adjacent to the first edge, and a first edge doped conductive layer is disposed adjacent to the second edge, the first edge doped conductive layer and the second edge doped conductive layer extend along the first direction; the doping type of the first edge doped conductive layer is opposite to the doping type of the substrate; The second edge doped conductive layer has a first width C in the second direction, and the first edge doped conductive layer has a second width A in the second direction, wherein C≤A.

10. The solar cell according to claim 1, characterized in that: A collector grid line is arranged on the doped conductive layer. In the first region, the distance between some of the collector grid lines and the first edge in the second direction is d1, In the second region, the distance between the collector grid line and the first edge in the second direction is d2, Among them, d1>d2>0.

11. A photovoltaic module, characterized in that: The invention comprises a battery string, wherein the battery string comprises an electrical connector and at least two solar cells according to any one of claims 1 to 10, wherein the electrical connector is electrically connected to the solar cells.

Images