Solar cell and preparation method thereof, solar cell module and power utilization device

Abstract

The invention relates to the technical field of solar cells, in particular to a solar cell and a preparation method thereof, a solar cell module and a power utilization device, and the solar cell comprises a crystalline silicon light absorption layer, a charge transmission layer comprising a doped polycrystalline silicon layer, a first passivation layer and a first metal electrode, the first metal electrode penetrates through the first passivation layer and is in contact with the doped polycrystalline silicon layer; the surface, close to the first metal electrode, of the crystalline silicon light absorption layer comprises a suede area and a polishing area, the orthographic projection of the first metal electrode on the crystalline silicon light absorption layer is located in the suede area, and the surface, making contact with the first metal electrode, of the doped polycrystalline silicon layer is provided with a cambered surface contact site. The solar cell not only can ensure passivation contact, but also is relatively low in contact resistance and relatively high in photoelectric conversion efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to solar cells and methods for preparing the same, solar cell modules and electrical devices. Background Art

[0002] Metallization plays a vital role in the manufacturing process of crystalline silicon solar cells. Its main function is to form metal electrodes on the front and back of the cell. These electrodes are responsible for collecting and transmitting current, which directly affects the performance of the cell. The metallization process usually uses screen printing technology to print metal paste (silver paste, silver aluminum paste, etc.) onto the surface of the cell, and then solidifies it through a sintering process to form an ohmic contact. The key challenge of metallization technology is how to optimize the design and materials of metal electrodes to reduce the shading effect, reduce contact resistance, reduce metal recombination, and improve the overall efficiency of the cell. Although various studies have been carried out, large contact resistance and metal recombination are still challenges facing solar cells. Summary of the invention

[0003] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the present invention provides a solar cell having both passivation performance and contact resistance and a preparation method thereof, a solar cell module and an electric device.

[0004] In the first aspect of the present application, a solar cell is provided. According to an embodiment of the present application, the solar cell includes: a crystalline silicon light absorption layer having a first side and a second side opposite to each other; a charge transfer layer located on the first side of the crystalline silicon light absorption layer and including a doped polycrystalline silicon layer; a first passivation layer located on the side of the charge transfer layer away from the crystalline silicon light absorption layer; a first metal electrode, the first metal electrode penetrates the first passivation layer and contacts the doped polycrystalline silicon layer; wherein the crystalline silicon light absorption layer includes a velvet area and a polished area on the surface close to the first metal electrode, and the orthographic projection of the first metal electrode on the crystalline silicon light absorption layer is located in the velvet area; the surface of the doped polycrystalline silicon layer in contact with the first metal electrode has a curved surface pit that is concave toward the doped polycrystalline silicon layer, and the surface of the first metal electrode in contact with the doped polycrystalline silicon layer has a curved surface convex portion that is convex toward the doped polycrystalline silicon layer, and the curved surface convex portion is cooperatively arranged in the curved surface pit.

[0005] In the solar cell, the contact interface structure between the first metal electrode and the doped polysilicon layer can not only increase the specific surface area of ​​the contact between the first metal electrode and the doped polysilicon layer and ensure the contact performance of the first metal electrode, but also ensure the passivation performance of the non-contact area, minimize metal recombination, and improve the photoelectric conversion efficiency of the solar cell.

[0006] According to an embodiment of the present application, the surface of the doped polysilicon layer in contact with the first metal electrode includes a plurality of protruding structures protruding toward the first metal electrode, and the arc-surface pits are located on the surfaces of the protruding structures.

[0007] According to an embodiment of the present application, the size of the protruding structure base is 0.5 μm to 2 μm.

[0008] According to an embodiment of the present application, the arc surface pit includes a hemispherical pit.

[0009] According to an embodiment of the present application, the radius of the hemispherical pit is 10 nm to 180 nm.

[0010] According to an embodiment of the present application, a surface of the crystalline silicon light absorption layer close to the first metal electrode satisfies at least one of the following conditions:

[0011] The area of ​​the suede area accounts for 0.5% to 7%;

[0012] The reflectivity of the suede area is 5% to 35%;

[0013] The reflectivity of the polished area is 40% to 70%.

[0014] According to an embodiment of the present application, the velvet area includes a plurality of spaced-apart sub-velvet areas, the first metal electrode includes a plurality of spaced-apart first sub-electrodes, the orthographic projection of each of the first sub-electrodes on the crystalline silicon light absorption layer is located in one of the sub-velvet areas, the width of each of the sub-velvet areas is greater than or equal to the width of each of the first sub-electrodes, and / or the width of each of the sub-velvet areas is 40μm to 100μm; and / or the width of each of the first sub-electrodes is 10μm to 50μm.

[0015] According to an embodiment of the present application, the solar cell further includes: a tunneling layer located between the crystalline silicon light absorption layer and the charge transport layer.

[0016] According to an embodiment of the present application, the solar cell also includes: an emitter layer, located on the second side of the crystalline silicon light absorption layer; a second passivation layer, located on the side of the emitter away from the crystalline silicon light absorption layer; an anti-reflection layer, located on the side of the second passivation layer away from the crystalline silicon light absorption layer; and a second metal electrode, wherein the second metal electrode penetrates the anti-reflection layer, the second passivation layer and the emitter layer, and contacts the crystalline silicon light absorption layer.

[0017] According to an embodiment of the present application, the second passivation layer includes a plurality of stacked second sub-passivation layers, and the hydrogen content in the plurality of second sub-passivation layers gradually increases in a direction away from the crystalline silicon light absorption layer.

[0018] In a second aspect of the present application, a method for preparing the aforementioned solar cell is provided. According to an embodiment of the present application, the method comprises: performing laser oxidation treatment on a predetermined area on the first side surface of the crystalline silicon light absorption layer to form an oxidation protection layer in the predetermined area; performing polishing treatment on the first side surface of the crystalline silicon light absorption layer and removing the oxidation protection layer to form a velvet area and a polished area; sequentially forming a charge transfer layer and a first passivation layer on the first side surface of the polished crystalline silicon light absorption layer; printing a first conductive paste on the surface of the first passivation layer away from the crystalline silicon light absorption layer, and then sequentially performing high temperature sintering, light injection treatment and laser enhancement treatment to form a first metal electrode.

[0019] According to an embodiment of the present application, based on the total mass of the first conductive paste, the first conductive paste includes 83% to 90% silver powder; 0.5% to 3% glass powder; and 7% to 12% organic phase.

[0020] According to an embodiment of the present application, the wavelength of the laser used in the laser oxidation treatment step and the wavelength of the laser used in the laser enhancement treatment step are independently 300nm to 600nm; and / or the spot diameter of the laser is 40μm to 100μm.

[0021] According to an embodiment of the present application, the method satisfies at least one of the following conditions: forming the charge transport layer includes: depositing an intrinsic polycrystalline silicon layer by chemical vapor deposition, and then doping the polycrystalline silicon layer by ion diffusion or ion implantation to obtain a doped polycrystalline silicon layer; forming the charge transport layer includes: obtaining a prefabricated polycrystalline silicon layer by plasma enhanced chemical vapor deposition, and annealing the prefabricated polycrystalline silicon layer to obtain the doped polycrystalline silicon layer; forming the first passivation layer includes: forming the first passivation layer by plasma enhanced chemical vapor deposition.

[0022] According to an embodiment of the present application, before forming the charge transport layer, the method further includes: forming a tunneling layer on the first side surface of the crystalline silicon light absorption layer by a plasma enhanced chemical vapor deposition method.

[0023] According to an embodiment of the present application, the method also includes: forming an emitter layer on the second side surface of the crystalline silicon light absorption layer by an ion diffusion method; forming a second passivation layer on the surface of the emitter layer away from the crystalline silicon light absorption layer by an atomic layer deposition method; forming an anti-reflection layer on the surface of the second passivation layer away from the crystalline silicon light absorption layer by a plasma enhanced chemical vapor deposition method; and forming a second metal electrode on the surface of the anti-reflection layer away from the crystalline silicon light absorption layer by sequential printing and sintering.

[0024] In a third aspect of the present application, a solar cell assembly is provided. According to an embodiment of the present application, the solar cell assembly comprises the solar cell described above or the solar cell prepared by the method described above. The solar cell assembly has a higher open circuit voltage and photoelectric conversion effect.

[0025] In a fourth aspect of the present application, an electric device is provided. According to an embodiment of the present application, the electric device includes the solar cell assembly described above. The electric device has all the features and advantages of the solar cell assembly described above, which will not be described one by one here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the partial cross-sectional structure of a solar cell according to an embodiment of the present application.

[0027] Figure 2 It is a schematic diagram of a partial cross-sectional structure of a solar cell according to another embodiment of the present application.

[0028] Figure 3 It is a schematic diagram of a partial cross-sectional structure of a solar cell according to another embodiment of the present application.

[0029] Figure 4 It is a schematic diagram of a partial cross-sectional structure of a solar cell according to another embodiment of the present application.

[0030] Figure 5 It is a schematic diagram of a process of forming a velvet area and a polished area on the surface of a crystalline silicon light absorbing layer according to an embodiment of the present application.

[0031] Reference numerals:

[0032] 1: Crystalline silicon light absorption layer 11: First side 12: Second side 111: Textured area 1111: Sub-textured area 112: Polished area 2: Charge transfer layer 21: Doped polysilicon layer 211: Curved pits 212: Protruding structure 3: First passivation layer 4: First metal electrode 41: Curved protrusion 42: First sub-electrode 5: Tunneling layer 6: Emitter layer 7: Second passivation layer 8: Anti-reflection layer 9: Second metal electrode 10: Crystalline silicon substrate 101: Oxidation protection layer DETAILED DESCRIPTION

[0033] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to be used to explain the present invention, but should not be understood as limiting the present invention.

[0034] In a first aspect of the present application, a solar cell is provided. According to an embodiment of the present application, referring to Figure 1The solar cell comprises: a crystalline silicon light absorption layer 1, having a first side 11 and a second side 12 opposite to each other; a charge transfer layer 2, located on the first side of the crystalline silicon light absorption layer 1, and comprising a doped polycrystalline silicon layer 21; a first passivation layer 3, located on a side of the charge transfer layer 2 away from the crystalline silicon light absorption layer 1; a first metal electrode 4, wherein the first metal electrode 4 penetrates the first passivation layer 3 and contacts the doped polycrystalline silicon layer 21; wherein the surface of the crystalline silicon light absorption layer 1 close to the first metal electrode 4 comprises a velvet area 111 and a polished area 112, and the orthographic projection of the first metal electrode 4 on the crystalline silicon light absorption layer 1 is located in the velvet area 111; the surface of the doped polycrystalline silicon layer 21 in contact with the first metal electrode 4 has a curved surface pit 211 sunken toward the doped polycrystalline silicon layer, and the surface of the first metal electrode 4 in contact with the doped polycrystalline silicon layer 21 has a curved surface protrusion 41 protruding toward the doped polycrystalline silicon layer, and the curved surface protrusion 41 is cooperatively arranged in the curved surface pit 211.

[0035] In the solar cell, the contact interface structure between the first metal electrode and the doped polysilicon layer can not only increase the contact area between the first metal electrode and the doped polysilicon layer and ensure the contact performance of the first metal electrode, but also ensure the passivation performance of the non-contact area, thereby reducing metal recombination as much as possible and improving the photoelectric conversion efficiency of the solar cell.

[0036] It can be understood that the "arc surface pit" mentioned in this article refers to a pit with at least a portion of the surface being an arc surface, and correspondingly, the "arc surface protrusion" refers to a protrusion with at least a portion of the surface being an arc surface.

[0037] According to an embodiment of the present application, the arc surface pit includes a hemispherical pit. It is understandable that there are usually some errors in the preparation process. Therefore, the "hemispherical pit" described in this article can be an ideal hemispherical pit or a pit that is approximately hemispherical. In this way, the first metal electrode and the doped polysilicon layer have a larger contact area and a smaller contact resistance.

[0038] According to an embodiment of the present application, the radius of the hemispherical pit may be 10 nm to 180 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, etc. With the above size, the contact resistance between the first metal electrode and the doped polysilicon layer can be further reduced.

[0039] According to an embodiment of the present application, the crystalline silicon light absorption layer may be a single crystal silicon layer or a polycrystalline silicon layer, and its conductivity type may be n-type or p-type. As an example, it may be n-type single crystal silicon or n-type polycrystalline silicon.

[0040] It can be understood that in order to avoid shading as much as possible, the first metal electrode can be set in the form of a metal grid line, that is, it can include a plurality of metal traces arranged at intervals, including a metal grid, etc., that is, the first metal electrode only covers a small part of the area of ​​the first passivation layer. It can also be understood that the first metal electrode is arranged corresponding to the velvet area on the surface of the crystalline silicon light absorption layer. Therefore, according to the embodiment of the present application, on the surface of the crystalline silicon light absorption layer close to the first metal electrode, the area ratio of the velvet area is 0.5% to 7%, specifically 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, etc. With the above area ratio, the setting requirements of the first metal electrode can be met, and the light transmittance is high, which is conducive to improving the light absorption effect of the solar cell.

[0041] According to an embodiment of the present application, on the surface of the crystalline silicon light absorbing layer close to the first metal electrode, the reflectivity of the velvet area can be 5% to 35%, specifically 5%, 10%, 15%, 20%, 25%, 30%, 35%, etc. With the above reflectivity, it is beneficial for the subsequent doped polysilicon layer and the first metal electrode to have a suitable contact area and a small contact resistance, while maintaining a good passivation contact, thereby facilitating the improvement of the open circuit voltage and photoelectric conversion efficiency of the solar cell.

[0042] According to an embodiment of the present application, on the surface of the crystalline silicon light absorbing layer close to the first metal electrode, the reflectivity of the polished area is 40% to 70%, specifically 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc. The polished area has the above reflectivity, which is beneficial to reduce reflection loss, reduce charge recombination, improve the internal quantum efficiency of the battery, improve contact performance, improve surface defects, improve passivation quality, etc.

[0043] According to an embodiment of the present application, the doping element in the doped polysilicon layer may include at least one of phosphorus, boron, carbon, nitrogen, and oxygen. In some embodiments, the doping concentration in the doped polysilicon layer is 10 15 -10 21 atoms·cm -3 Specific examples include 10 15 atoms·cm -3 , 10 16 atoms·cm -3 , 10 17 atoms·cm -3 , 10 18 atoms·cm -3 , 10 19 atoms·cm -3 , 10 20atoms·cm -3 , 10 21 atoms·cm -3 Etc. Thus, it is beneficial to pass charges. For example, when the conductivity type of the crystalline silicon light-absorbing layer is n-type, it can allow electrons to pass through, but prevent holes from passing through; thus, it is beneficial to improve the passivation effect, reduce recombination, and improve the photoelectric conversion efficiency of solar cells.

[0044] According to the embodiments of the present application, referring to Figure 1 The surface of the doped polysilicon layer 21 in contact with the first metal electrode 4 includes a plurality of protruding structures 212 protruding toward the first metal electrode 4, and the arc surface pits 211 are located on the surface of the protruding structures 212. Thus, the contact area between the first metal electrode and the doped polysilicon layer can be further increased, the contact resistance can be reduced, and at the same time, a good passivation contact can be maintained, metal recombination can be reduced, and the photoelectric conversion efficiency of the solar cell can be improved.

[0045] According to an embodiment of the present application, the size of the base of the protrusion structure 212 is 0.5 μm to 2 μm, specifically 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2.0 μm, etc. Within this size range, the doped polysilicon and the first metal electrode have a suitable contact area, a small contact resistance, a good passivation contact effect, less metal recombination, and the solar cell can achieve a higher open circuit voltage and a greater photoelectric conversion efficiency.

[0046] It can be understood that the raised structure on the doped polysilicon layer is inherited from the velvet area on the crystalline silicon light absorption layer. Specifically, the velvet area of ​​the crystalline silicon light absorption layer has a pyramid structure. After the doped polysilicon layer is formed on the velvet area of ​​the crystalline silicon light absorption layer, such as by a deposition method, the surface of the doped polysilicon layer has a morphology corresponding to the surface of the crystalline silicon light absorption layer, that is, a raised structure is formed on the doped polysilicon layer at a position corresponding to the pyramid structure on the velvet area. Due to the material characteristics of the crystalline silicon light absorption layer, its pyramid has a shape similar to a quadrangular pyramid, and the base (i.e., the bottom) of the pyramid is generally square. Correspondingly, the raised structure on the doped polysilicon layer also has a shape similar to a quadrangular pyramid, and the bottom (or base) of the raised structure is also square. The size of the base of the raised structure refers to the side length of the bottom square of the raised structure.

[0047] According to the embodiments of the present application, the doped polysilicon layer can be a single layer or multiple layers, which can be selected according to actual needs. The thickness of the doped polysilicon layer can be 20nm to 200nm, such as 20nm, 50nm, 100nm, 150nm, 200nm, etc.

[0048] In some embodiments, in addition to the doped polysilicon layer, the charge transfer layer may also include at least one of a silicon oxide layer and an amorphous silicon layer stacked with the doped polysilicon layer, and the specific stacking order of each layer is not particularly limited in this application. As an example, the charge transfer layer may include a doped polysilicon layer, a silicon oxide layer, and another doped polysilicon layer stacked in sequence. It should be noted that when the charge transfer layer includes more than two doped polysilicon layers, the polysilicon layer closest to the first metal electrode is in contact with the first metal electrode.

[0049] According to an embodiment of the present application, the material of the first passivation layer may include silicon nitride, and the thickness of the first passivation layer may be 60 nm to 100 nm (specifically 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.), thereby achieving a better passivation effect.

[0050] As mentioned above, the first metal electrode can be set in the form of a metal grid line, that is, it can include a plurality of metal traces arranged at intervals, including a metal grid, etc. Therefore, according to the embodiment of the present application, referring to Figure 2 The velvet region 111 includes a plurality of spaced-apart sub-velvet regions 1111, the first metal electrode 4 includes a plurality of spaced-apart first sub-electrodes 42, the orthographic projection of each of the first sub-electrodes 42 on the crystalline silicon light absorption layer 1 is located within one of the sub-velvet regions 1111, the width W1 of each of the sub-velvet regions 1111 is greater than or equal to the width W2 of each of the first sub-electrodes 42, and the width W1 of each of the sub-velvet regions is 40 μm~100μm (specifically 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, etc.); the width W2 of each of the first sub-electrodes is 10μm~50μm (specifically 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, etc.).

[0051] In the text, viewed from a top-down perspective, the first sub-electrode and the sub-velvet area are basically in the shape of an elongated rectangle. The width W1 of the sub-velvet area and the width W2 of the first sub-electrode 42 both refer to the length of the short side of the elongated rectangle. They can be measured through 3D microscope observation. For example, the width of 5 locations can be measured and the average value can be taken.

[0052] According to an embodiment of the present application, the material of the first metal electrode may include at least one of silver, aluminum and alloys thereof, such as silver, silver-aluminum alloy, etc. Thus, the first metal electrode has better conductivity and lower corrosion performance to the passivation layer, which is beneficial to ensure the passivation effect while reducing the contact resistance between the first metal electrode and the doped polysilicon layer.

[0053] According to the embodiments of the present application, referring to Figure 3 The solar cell further comprises: a tunneling layer 5, which is located between the crystalline silicon light absorption layer 1 and the charge transport layer 2. Thus, the surface of the crystalline silicon light absorption layer can be effectively passivated, the surface dangling bonds can be reduced, and the surface recombination rate can be reduced; the charge can be transported, which is helpful to improve the current collection efficiency; a low-resistance ohmic contact can be provided; the electric field strength on the surface of the battery can be reduced, thereby reducing the direct influence of the electric field on the charge, which is helpful to improve the stability and life of the battery; and further, it is beneficial to improve the fill factor, open circuit voltage and photoelectric conversion efficiency of the solar cell.

[0054] According to an embodiment of the present application, the material of the tunneling layer may include silicon oxide; the thickness of the tunneling layer is 0.5-2nm, such as 0.5nm, 0.6nm, 0.7nm, 0.8nm, 0.9nm, 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2nm, etc.

[0055] According to the embodiments of the present application, referring to Figure 4 The solar cell further includes: an emitter layer 6, located on the second side of the crystalline silicon light absorption layer 1; a second passivation layer 7, located on the side of the emitter layer 6 away from the crystalline silicon light absorption layer 1; an anti-reflection layer 8, located on the side of the second passivation layer 7 away from the crystalline silicon light absorption layer 1; a second metal electrode 9, the second metal electrode 9 penetrates the anti-reflection layer 6, the second passivation layer 7 and the emitter layer 8, and contacts the crystalline silicon light absorption layer 1.

[0056] According to an embodiment of the present application, the material of the emitter layer includes a boron-diffused emitter layer, that is, boron atoms diffuse into a portion of the crystalline silicon substrate to form a boron-diffused emitter layer.

[0057] According to an embodiment of the present application, the second passivation layer may be a single-layer structure or a multi-layer structure. As an example, the second passivation layer may include a plurality of stacked second sub-passivation layers, and the hydrogen content in the plurality of second sub-passivation layers gradually increases along the direction away from the crystalline silicon light absorbing layer. Specifically, the hydrogen content in the outer layer (i.e., away from the light absorbing layer) is high, which can effectively passivate defects and reduce recombination, and the hydrogen content in the inner layer is low, which can facilitate the sintering of the conductive paste during the preparation of the second metal electrode.

[0058] According to an embodiment of the present application, the material of the second passivation layer may include at least one of silicon oxide and aluminum oxide; the thickness of the second passivation layer is 1nm to 10nm, such as 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc.

[0059] According to an embodiment of the present application, the second metal electrode may also be provided in the form of a metal grid line or a metal mesh, etc. In some embodiments, the material of the second metal electrode may include at least one of silver, aluminum and alloys thereof, such as silver, silver-aluminum alloy, etc. Thus, the second metal electrode has better conductivity and better effect of collecting and conducting current.

[0060] In a second aspect of the present application, a method for preparing the aforementioned solar cell is provided. According to an embodiment of the present application, the method comprises the following steps:

[0061] S1: Perform laser oxidation treatment on a predetermined area on the first side surface of the crystalline silicon light absorbing layer to form an oxidation protection layer in the predetermined area. The schematic diagram of the process is shown in FIG. Figure 5 .

[0062] According to the embodiment of the present application, the crystalline silicon light absorption layer used in this step can be a crystalline silicon light absorption layer obtained by performing necessary pretreatment on the crystalline silicon substrate, and the specific pretreatment can be selected according to actual needs. For example, the crystalline silicon substrate can be subjected to texturing treatment to obtain the crystalline silicon light absorption layer.

[0063] According to an embodiment of the present application, in this step, the laser oxidation treatment refers to laser irradiation of a predetermined area to convert a partial thickness of the velvet structure into an oxide layer, thereby protecting the velvet structure from being destroyed in subsequent steps.

[0064] Specifically, in this step, the laser oxidation treatment can use a nanosecond laser or a picosecond laser, and the laser wavelength can be 300nm to 600nm. As a specific example, a 355nm purple laser can be selected. The diameter of the laser spot can be 40μm to 100μm, such as 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, etc. As needed, high-purity oxygen can be introduced during laser oxidation treatment to increase the density of the oxide layer and the protectiveness of the oxide protective layer.

[0065] It can be understood that in this step, the diameter of the laser spot determines the width of the sub-texture area. Try to choose a laser with a smaller spot diameter to obtain a sub-texture area with a smaller width, which is beneficial to reduce the width of the first sub-electrode and reduce the shading area of ​​the first metal electrode. As mentioned above, due to the size of the laser spot diameter, the width of the sub-texture area is greater than the width of the first sub-electrode. However, this setting is beneficial to the preparation of the first sub-electrode, can provide a larger processing margin, and reduce the difficulty of preparation.

[0066] S2: Polishing the first side surface of the crystalline silicon light absorbing layer and removing the oxide protection layer to form a velvet area and a polishing area. The schematic diagram of the process is shown in FIG. Figure 5 .

[0067] In this step, the first side surface of the crystalline silicon light absorbing layer can be polished by conventional methods, for example, by using alkaline solution, and the surface velvet structure not protected by the oxidation protection layer is removed to form a polished surface, while the surface of the oxidized protection layer does not react with the alkaline solution, and the velvet structure is retained.

[0068] In this step, the oxide protective layer can be removed by pickling or other steps. After the oxide protective layer is removed, a crystalline silicon light absorption layer having both a polished area and a velvet area can be obtained.

[0069] S3: forming a charge transport layer and a first passivation layer in sequence on the first side surface of the polished crystalline silicon light absorption layer.

[0070] Specifically, the charge transport layer can be prepared by chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0071] In some embodiments, forming the charge transport layer includes: depositing an intrinsic polysilicon layer by chemical vapor deposition, and then doping the polysilicon layer by ion diffusion or ion implantation to obtain a doped polysilicon layer.

[0072] In some embodiments, forming the charge transport layer includes: obtaining a prefabricated polysilicon layer by a plasma enhanced chemical vapor deposition method, and annealing the prefabricated polysilicon layer to obtain the doped polysilicon layer.

[0073] In some embodiments, forming the first passivation layer may include: forming the first passivation layer by a plasma enhanced chemical vapor deposition method.

[0074] S4: printing a first conductive paste on a surface of the first passivation layer away from the crystalline silicon light absorption layer, and then sequentially performing high temperature sintering, light injection treatment and laser enhancement treatment to form a first metal electrode.

[0075] In this step, the first conductive paste may be printed by screen printing or other methods, and then subjected to high temperature sintering and light injection treatments. The first conductive paste may then be subjected to laser enhancement treatment to form arc surface contact sites.

[0076] Specifically, in this step, high-temperature sintering and light injection treatment can be performed in accordance with conventional operations in the art. For example, high-temperature sintering can be performed by sintering the intermediate product after coating the first conductive paste at a temperature of 700°C to 800°C, and then placing the sintered intermediate product under a light source to allow the intermediate product to work under certain lighting conditions, usually for a few minutes to a few hours.

[0077] Specifically, the laser enhancement treatment can be to use a laser to irradiate the first conductive paste after the light injection treatment. In this step, a nanosecond laser or a picosecond laser can be used, and the laser wavelength can be 300nm to 600nm. As a specific example, a 355nm purple laser can be selected. The diameter of the laser spot can be 40μm to 100μm, such as 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, etc.

[0078] In this step, a first conductive paste with low corrosion can be used, so as to reduce the contact resistance while ensuring the passivation contact effect.

[0079] In some embodiments, based on the total mass of the first conductive paste, the first conductive paste includes 83% to 90% silver powder, 0.5% to 3% glass powder, and 7% to 12% organic phase. Specifically, based on the total mass of the first conductive paste, the mass percentage of silver powder in the first conductive paste can be 83%, 84%, 85%, 86%, 87%, 88%, 89%, 90%, etc.; the mass percentage of glass powder in the first conductive paste can be 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, etc.; the mass percentage of organic phase in the first conductive paste can be 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, 10%, 10.5%, 11%, 11.5%, 12%, 12.5%, 13%, etc.

[0080] It can be understood that the role of the organic phase in the first conductive paste includes adjusting the rheological properties, printing properties and drying properties of the paste to meet different processing requirements. In some embodiments, the organic phase in the first conductive paste may include a solvent and a binder, and may also include a plasticizer, a curing agent, a leveling agent, a stabilizer, a thixotropic agent and a filler, etc., depending on the use requirements.

[0081] As an example, the binder may include acrylic resins, epoxy resins, phenolic resins, etc., for improving the adhesion and stability of the silver paste.

[0082] As an example, the solvent may include alcohols (such as ethanol and isopropanol), ketones (such as acetone and methyl ethyl ketone) and esters (such as ethyl acetate and butyl butyrate), etc., which are used to adjust the viscosity and fluidity of the silver paste.

[0083] According to an embodiment of the present application, before forming the charge transport layer, the method further includes: S5: forming a tunneling layer on the first side surface of the crystalline silicon light absorption layer by a plasma enhanced chemical vapor deposition method.

[0084] According to an embodiment of the present application, the method also includes: S6: forming an emitter layer on the second side surface of the crystalline silicon light absorption layer by an ion diffusion method; S7: forming a second passivation layer on the surface of the emitter layer away from the crystalline silicon light absorption layer by an atomic layer deposition method; S8: forming an anti-reflection layer on the surface of the second passivation layer away from the crystalline silicon light absorption layer by a plasma enhanced chemical vapor deposition method; S9: forming a second metal electrode on the surface of the anti-reflection layer away from the crystalline silicon light absorption layer by sequential printing and sintering.

[0085] In a third aspect of the present application, a solar cell assembly is provided. According to an embodiment of the present application, the solar cell assembly comprises the solar cell described above or the solar cell prepared by the method described above. The solar cell assembly has a higher open circuit voltage and photoelectric conversion effect.

[0086] In a fourth aspect of the present application, an electric device is provided. According to an embodiment of the present application, the electric device includes the solar cell assembly described above. The electric device has all the features and advantages of the solar cell assembly described above, which will not be described one by one here.

[0087] It is understood that there is no particular limitation on the specific type of the electrical device, including but not limited to vehicles, wearable devices, game consoles, detection equipment, lighting equipment, energy storage equipment, etc. It is also understood that in addition to the solar cell assembly described above, the electrical device may also include necessary structures and components, which may be specifically carried out with reference to conventional technology and are not particularly limited in this application.

[0088] The embodiments of the present application are described in detail below.

[0089] Example 1

[0090] (1) Select an N-type silicon substrate with a thickness of 130 μm, and use a groove-type alkali texturing process to obtain a reflectivity of 10% and a pyramid base size of 1 μm;

[0091] (2) The silicon substrate after texturing is subjected to high-temperature boron diffusion, and BCl3 and O2 are introduced. The junction temperature is 1050°C and the junction time is 4600s to form a boron diffusion layer with a square resistance of 400Ω / □, which is the emitter layer;

[0092] (3) The boron-expanded silicon substrate is etched with chain HF to form BSG (borosilicate glass) on the back side (i.e., the first side), and then the gate line area designed on the back side is laser-oxidized with a laser, wherein the laser uses a 355nm purple laser with a laser spot diameter of 50μm. High-purity oxygen can be introduced during the laser oxidation process to increase the density of the oxide layer and the protectiveness of the mask (i.e., the oxide protection layer);

[0093] (4) After forming the patterned mask, the silicon substrate is etched cleanly in the non-laser area using an alkali using a groove etching machine to form a polished area. The silicon oxide mask has a certain corrosion resistance to alkali, and the velvet structure under the mask is retained to form a velvet area, which accounts for 5% of the area. After that, the groove etching is concentrated through acid washing, alkali washing, acid washing, and water washing, and the back velvet area is modified for the second time, with a reflectivity of 30%, while the reflectivity of the back polished area is 53%;

[0094] (5) Prepare the back charge transfer layer and tunneling layer, that is, deposit the back tunneling layer and phosphorus-doped polysilicon layer (i.e., doped polysilicon layer). Using plasma enhanced chemical vapor deposition (PECVD), the back tunneling layer and phosphorus-doped polysilicon can be deposited in the same tube. The tunneling layer needs to be passed through N2O for in-situ oxidation deposition, and the thickness of silicon oxide is 1.2nm. Phosphorus-doped polysilicon needs to be passed through SiH4, phosphine, and H2 for deposition, with a total thickness of 110nm. Then SiH4 and N2O are passed through to form a 10nm oxide layer as a protective layer (MASK). After that, high temperature annealing is used to activate the phosphorus atoms. The annealing temperature is 895℃. The square resistance after annealing is 45Ω / □, and the doping concentration is 5×10 20 atoms·cm -3 ;

[0095] (6) After the annealed silicon substrate is etched using chain HF to etch the mask formed on the front side, the silicon substrate is subjected to a de-plating process to remove the phosphorus-doped polysilicon and tunneling layer plated on the front side, remove the BSG on the front side, and remove the mask on the back side. The purpose of this step is to prevent battery leakage;

[0096] (7) The silicon wafer is sequentially coated with aluminum oxide (i.e., the second passivation layer) on the front side (the second side) + silicon nitride (i.e., the anti-reflection layer) on the front side + silicon nitride (i.e., the first passivation layer) on the back side.

[0097] (8) The aluminum oxide second passivation layer can be formed by atomic layer deposition (ALD) with a thickness of 5 nm. The aluminum oxide passivation layer is an aluminum oxide stack, including an aluminum oxide layer 1 + an aluminum oxide layer 2, the hydrogen content of the aluminum oxide layer 2 is higher than that of the aluminum oxide layer 1, and the hydrogen content is controlled by the flow rate of H2O introduced;

[0098] (9) The front silicon nitride anti-reflection layer comprises silicon nitride, silicon oxynitride and silicon oxide, and is formed by PECVD. The specific structure from the inside to the outside (i.e., the direction away from the silicon substrate) is silicon nitride, silicon oxynitride and silicon oxide, respectively, and the total thickness is 75 nm;

[0099] (10) The first back silicon nitride passivation layer comprises silicon nitride and silicon oxynitride, and is formed by PECVD. The specific structure is silicon nitride and silicon oxynitride from the inside to the outside, and the total thickness is 85 nm. The first passivation layer also plays an anti-reflection role.

[0100] (11) Low-corrosion silver paste is screen-printed on both the front and back sides of the silicon substrate. After high-temperature sintering (peak temperature of 760°C), light injection treatment is performed and then the conductive paste is laser enhanced to form the first metal electrode on the back and the second metal electrode on the front, completing the preparation of the complete battery.

[0101] The second metal electrode is connected to the boron diffused emitter layer, and the first metal electrode is connected to the phosphorus-doped polysilicon layer to form an ohmic contact. The silver paste used to form the second metal electrode is manufactured by HiSilicon, and the model is SSP-995PF-BFB-TL. The silver paste used to form the first metal electrode uses low-corrosion pure silver paste (88% silver powder; 2% glass powder; 10% organic phase), and is laser enhanced and optimized for contact treatment. The paste in the first metal electrode contacts the doped polysilicon layer to form a hemispherical contact with a radius of 50 μm.

[0102] Comparative Example 1

[0103] (1) Select an N-type silicon substrate with a thickness of 130 μm, which is textured by trough alkali, with a reflectivity of 10% and a pyramid base size of 1 μm;

[0104] (2) The silicon substrate after texturing is subjected to high-temperature boron diffusion, and BCl3 and O2 are introduced. The junction temperature is 1040°C and the junction time is 5600s to form a boron diffusion layer with a square resistance of 130Ω / □, which is the emitter layer;

[0105] (3) The BSG formed on the back of the silicon substrate after boron diffusion is etched using chain HF, and then the back velvet surface is etched cleanly using alkali using a slot etching machine to form a polished surface with a reflectivity of 53%;

[0106] (4) The cleaned silicon substrate is used for deposition of the back tunneling layer and phosphorus-doped polysilicon layer. Using plasma enhanced chemical vapor deposition (PECVD), the back tunneling layer and the phosphorus-doped polysilicon layer can be deposited in the same tube. The tunneling layer needs to be passed through N2O for in-situ oxidation deposition, and the thickness of silicon oxide is 1.2nm. The phosphorus-doped polysilicon layer needs to be passed through SiH4, phosphine, and H2 for deposition, with a total thickness of 110nm. Then SiH4 and N2O are passed through to form a 10nm oxide layer as a protective layer (MASK). After that, high temperature annealing is used to activate the phosphorus atoms. The annealing temperature is 895℃. After annealing, the square resistance is 45Ω / □, and the doping concentration is 5×10 20 atoms·cm -3 ;

[0107] (5) After the annealed silicon substrate is etched using chain HF to etch the mask formed on the front side, the silicon substrate is subjected to a de-plating process to remove the phosphorus-doped polysilicon layer and tunneling layer plated on the front side, remove the BSG on the front side, and remove the mask on the back side. The purpose of this step is to prevent battery leakage;

[0108] (6) After the emitter layer and the back charge transfer layer are prepared, the silicon substrate is coated with aluminum oxide on the front side, silicon nitride on the front side, and silicon nitride on the back side in sequence.

[0109] (7) The aluminum oxide second passivation layer can be formed by atomic layer deposition (ALD) with a thickness of 5 nm. The aluminum oxide passivation layer is an aluminum oxide stack, including an aluminum oxide layer 1 + an aluminum oxide layer 2, the hydrogen content of the aluminum oxide layer 2 is higher than that of the aluminum oxide layer 1, and the hydrogen content is controlled by the flow rate of H2O introduced;

[0110] (8) The front silicon nitride anti-reflection layer comprises silicon nitride, silicon oxynitride and silicon oxide, and is formed by PECVD. The specific structure from inside to outside is silicon nitride, silicon oxynitride and silicon oxide, and the total thickness is 75 nm;

[0111] (9) The first back silicon nitride passivation layer comprises silicon nitride and silicon oxynitride, which are formed by PECVD. The specific structure is silicon nitride and silicon oxynitride from the inside to the outside, and the total thickness is 85 nm. The first passivation layer also plays an anti-reflection role.

[0112] (10) Conductive paste is screen-printed on both the front and back sides. The front side uses silver-aluminum paste produced by HiSilver and model number SSP-995PF, and the back side uses pure silver paste produced by HiSilver and model number SSP-995PF-BF. After high-temperature sintering and light injection treatment, a first metal electrode and a second metal electrode are formed, thereby completing the preparation of a complete battery.

[0113] The second metal electrode is connected to the boron-diffused emitter layer, and the first metal electrode is connected to the phosphorus-doped polysilicon layer to form an ohmic contact.

[0114] Performance testing: The battery efficiency Eta, open circuit voltage Uoc, short circuit current Jsc and fill factor FF of the solar cells prepared in the above embodiments and comparative examples were tested using a German halm electrical performance tester. The test results are shown in Table 1.

[0115] Table 1

[0116] Eta / % Uoc / V Jsc / (mA / cm2) FF / % Comparative Example 1 24.88 0.7263 41.08 83.40 Example 1 25.30 0.7362 41.13 83.54

[0117] It can be clearly seen from the data in Table 1 that the solar cell in the embodiment forms a hemispherical contact site, which reduces the contact resistance and reduces the recombination. The cell efficiency Eta, open circuit voltage Uoc, short circuit current Jsc and fill factor FF of the solar cell are significantly improved.

[0118] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0119] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0120] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0121] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0122] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0123] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A crystalline silicon light absorbing layer having a first side and a second side opposite to each other; A charge transport layer, located on a first side of the crystalline silicon light absorption layer, and comprising a doped polysilicon layer; A first passivation layer is located on a side of the charge transport layer away from the crystalline silicon light absorption layer; a first metal electrode, the first metal electrode penetrates the first passivation layer and contacts the doped polysilicon layer; The surface of the crystalline silicon light absorption layer close to the first metal electrode includes a suede area and a polished area, and the orthographic projection of the first metal electrode on the crystalline silicon light absorption layer is located in the suede area; At least a portion of the surface of the doped polysilicon layer in contact with the first metal electrode has a curved surface pit recessed toward the doped polysilicon layer, and at least a portion of the surface of the first metal electrode in contact with the doped polysilicon layer has a curved surface protrusion protruding toward the doped polysilicon layer, and the curved surface protrusion is cooperatively arranged in the curved surface pit.

2. The solar cell according to claim 1, characterized in that The surface of the doped polysilicon layer in contact with the first metal electrode includes a plurality of protruding structures protruding toward the first metal electrode, and the arc-surface pits are located on the surfaces of the protruding structures.

3. The solar cell according to claim 2, characterized in that: The size of the protruding structure base is 0.5 μm to 2 μm.

4. The solar cell according to claim 1, characterized in that The arc surface pit includes a hemispherical pit.

5. The solar cell according to claim 4, characterized in that: The radius of the hemispherical pit is 10nm to 180nm.

6. The solar cell according to claim 1, characterized in that The surface of the crystalline silicon light absorption layer close to the first metal electrode satisfies at least one of the following conditions: The area of ​​the suede area accounts for 0.5% to 7%; The reflectivity of the suede area is 5% to 35%; The reflectivity of the polished area is 40% to 70%.

7. The solar cell according to claim 1, characterized in that The velvet area includes a plurality of spaced-apart sub-velvet areas, the first metal electrode includes a plurality of spaced-apart first sub-electrodes, the orthographic projection of each of the first sub-electrodes on the crystalline silicon light absorption layer is located in one of the sub-velvet areas, the width of each of the sub-velvet areas is greater than or equal to the width of each of the first sub-electrodes, and / or the width of each of the sub-velvet areas is 40μm to 100μm; and / or the width of each of the first sub-electrodes is 10μm to 50μm.

8. The solar cell according to claim 1, characterized in that Also includes: The tunneling layer is located between the crystalline silicon light absorption layer and the charge transport layer.

9. The solar cell according to any one of claims 1 to 8, characterized in that Also includes: An emitter layer, located on the second side of the crystalline silicon light absorbing layer; A second passivation layer is located on a side of the emitter away from the crystalline silicon light absorbing layer; an anti-reflection layer, located on a side of the second passivation layer away from the crystalline silicon light absorbing layer; A second metal electrode, wherein the second metal electrode penetrates the anti-reflection layer, the second passivation layer and the emitter layer, and contacts the crystalline silicon light absorption layer.

10. The solar cell according to claim 9, characterized in that: The second passivation layer includes a plurality of stacked second sub-passivation layers, and the hydrogen content in the plurality of second sub-passivation layers gradually increases along a direction away from the crystalline silicon light absorption layer.

11. A method for preparing a solar cell according to any one of claims 1 to 10, characterized in that: include: Performing laser oxidation treatment on a predetermined area on the first side surface of the crystalline silicon light absorbing layer to form an oxidation protection layer in the predetermined area; Polishing the first side surface of the crystalline silicon light absorption layer, and then removing the oxidation protection layer to form a suede area and a polished area; forming a charge transport layer and a first passivation layer in sequence on the first side surface of the polished crystalline silicon light absorption layer; A first conductive paste is printed on a surface of the first passivation layer away from the crystalline silicon light absorption layer, and then high-temperature sintering, light injection treatment and laser enhancement treatment are performed in sequence to form a first metal electrode.

12. The method according to claim 11, characterized in that Based on the total mass of the first conductive paste, the first conductive paste includes 83% to 90% silver powder, 0.5% to 3% glass powder, and 7% to 12% organic phase.

13. The method according to claim 11, characterized in that The wavelength of the laser used in the laser oxidation treatment step and the wavelength of the laser used in the laser enhancement treatment step are independently 300nm to 600nm; and / or the spot diameter of the laser is 40μm to 100μm.

14. The method according to claim 11, characterized in that Satisfy at least one of the following conditions: Forming the charge transport layer comprises: depositing an intrinsic polysilicon layer by chemical vapor deposition, and then doping the polysilicon layer by ion diffusion or ion implantation to obtain a doped polysilicon layer; Forming the charge transport layer includes: obtaining a prefabricated polysilicon layer by a plasma enhanced chemical vapor deposition method, and annealing the prefabricated polysilicon layer to obtain the doped polysilicon layer; Forming the first passivation layer includes forming the first passivation layer by a plasma enhanced chemical vapor deposition method.

15. The method according to claim 11, characterized in that Before forming the charge transport layer, the method further comprises: A tunneling layer is formed on the first side surface of the crystalline silicon light absorption layer by a plasma enhanced chemical vapor deposition method.

16. The method according to claim 11, characterized in that Also includes: forming an emitter layer on the second side surface of the crystalline silicon light absorbing layer by an ion diffusion method; forming a second passivation layer on the surface of the emitter layer away from the crystalline silicon light absorbing layer by atomic layer deposition; forming an anti-reflection layer on a surface of the second passivation layer away from the crystalline silicon light absorbing layer by a plasma enhanced chemical vapor deposition method; By sequentially performing printing, sintering and light injection processes, a second metal electrode is formed on the surface of the anti-reflection layer away from the crystalline silicon light absorption layer.

17. A solar cell module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 10 or a solar cell prepared by the method according to any one of claims 11 to 16.

18. An electrical device, characterized in that: A solar cell module comprising the solar cell module according to claim 17.

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