TBC solar cell and preparation method thereof

Abstract

The invention discloses a TBC solar cell and a preparation method thereof. The preparation method of the TBC solar cell comprises the following steps: cleaning and polishing an N-type silicon substrate; depositing a first tunneling oxide layer and a first intrinsic polycrystalline silicon layer on the back surface; boron diffusion; performing laser grooving, etching and cleaning; depositing a second tunneling layer and a second intrinsic polycrystalline silicon layer on the back surface; phosphorus diffusion; performing laser grooving, etching and cleaning; depositing an aluminum oxide film and an anti-reflection film on two sides; and preparing a metal electrode. According to the invention, the phosphorus-doped polycrystalline silicon layer is added on the boron-doped polycrystalline silicon layer, the second tunneling layer of the interlayer can form a secondary gettering effect, and the passivation level of the boron-doped polycrystalline silicon layer is improved. A built-in electric field formed by the two PN junctions generates more carriers, more holes are forced to be gathered and transversely transmitted at the boron-doped polycrystalline silicon layer and more easily collected by a metal electrode, and a back suede structure and a carrier collection optimization structure are added on the basis of not increasing the process flow.

Description

Technical Field

[0001] The invention relates to the field of photovoltaic manufacturing, and in particular to a TBC solar cell and a preparation method thereof. Background Art

[0002] The existing TBC (Top-Contact Back-Contact) battery back passivation contact structure can significantly improve the carrier collection efficiency of the back grid line. The key is to reduce carrier recombination by setting a suitable passivation layer on the back, thereby improving the efficiency of the battery. However, the implementation of this structure usually requires the use of a polysilicon (Poly-Silicon) layer with a higher doping concentration on the back, while ensuring a high passivation level. This is because a higher doping concentration helps to improve the contact performance between the back grid line and the carriers, thereby improving the carrier collection ability.

[0003] However, the back P region usually uses boron-doped polysilicon (Poly-Si:B) material, which brings high doping concentration while also introducing a problem that cannot be ignored. The boron doping process causes boron atoms to generate recombination centers in the silicon lattice, which accelerate the recombination of electrons and holes, thereby reducing the passivation effect of the battery. This phenomenon not only affects the passivation level of the back region, but also leads to a decrease in battery efficiency. Summary of the invention

[0004] In order to solve the technical problems mentioned in the prior art, the present disclosure proposes a TBC solar cell and a preparation method thereof.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A TBC solar cell, characterized in that the TBC solar cell comprises a silicon substrate, the silicon substrate has a front side and a back side opposite to each other, the back side of the silicon substrate has first areas and second areas alternately arranged along a first direction, there is a spacing area between the first areas and the second areas, and the first direction is perpendicular to a thickness direction of the silicon substrate;

[0007] The first region includes a first PN junction, a first tunneling layer, and a first doped polysilicon layer arranged in sequence in a direction away from the back side of the substrate;

[0008] The surface of the first doped polysilicon layer has a first sub-region and a second sub-region arranged at two ends of the first sub-region along a first direction, the first sub-region includes a suede structure and a passivation layer arranged in sequence in a direction away from the back side of the substrate; the second sub-region includes a dielectric layer, a second doped polysilicon layer, and a passivation layer arranged in sequence in a direction away from the back side of the substrate;

[0009] The spacer region includes a suede structure and a passivation layer arranged in sequence in a direction away from the back side of the substrate;

[0010] The second region includes a second PN junction, a second tunneling layer, a second doped polysilicon layer, and a passivation layer which are sequentially arranged in a direction away from the back side of the substrate;

[0011] The front side of the silicon substrate comprises a suede structure and a passivation layer arranged in sequence in a direction away from the front side of the substrate;

[0012] The TBC solar cell further includes a first electrode and a second electrode. The first electrode is located in the first sub-region and passes through the passivation layer to contact the first doped polysilicon layer. The second electrode is located in the second region and passes through the passivation layer to contact the second doped polysilicon layer.

[0013] Preferably, the doping element of the first doped polysilicon or the second doped silicon is a Group III or Group V element, wherein the doping element of the second doped polysilicon layer has opposite conductivity to that of the first doped polysilicon layer.

[0014] Preferably, the passivation layer is a stack of aluminum oxide and silicon nitride, wherein the thickness of the aluminum oxide film is 3 nm to 5 nm.

[0015] Preferably, the first tunneling layer is a tunneling oxide layer, the thickness of the first tunneling layer is 1 nm to 2.5 nm, the thickness of the first doped polysilicon layer is 320 nm to 340 nm,

[0016] Preferably, the thickness of the second tunneling layer is 1 nm to 1.5 nm, and the thickness of the second doped polysilicon layer is 300 nm to 320 nm.

[0017] Preferably, the dielectric layer is a silicon oxide layer containing a first doping element and a second doping element.

[0018] The present invention also claims protection for a method for preparing a TBC solar cell, comprising the following steps:

[0019] Step S1: cleaning and polishing the N-type silicon substrate;

[0020] Step S2: depositing a first tunneling layer and a first intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0021] Step S3: performing boron diffusion on the first intrinsic polysilicon layer to form a boron-doped polysilicon layer and a BSG layer, and diffusing toward the N-type silicon substrate to form a first PN junction;

[0022] Step S4: using laser to remove the BSG layer in the N region and the Gap region on the back side of the N-type silicon substrate; etching and cleaning the BSG layer on the front side of the N-type silicon substrate, etching and cleaning the N region and the Gap region on the back side of the N-type silicon substrate, as well as the boron-doped polysilicon layer, the first tunneling layer and the first PN junction on the front side, and the area not removed is the P region;

[0023] Step S5: depositing a second tunneling layer and a second intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0024] Step S6: performing phosphorus diffusion on the first intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer, and diffusing toward the N-type silicon substrate to form a second PN junction;

[0025] Step S7: using laser to remove the PSG layer in the Gap region on the back side of the N-type silicon substrate and the first sub-region of the P region, and retaining the PSG layer in the second sub-region of the P region located on both sides of the first sub-region; etching and cleaning the PSG layer on the front side of the N-type silicon substrate, etching and cleaning the first sub-region, the Gap region on the back side of the N-type silicon substrate, and the phosphorus-doped polysilicon layer, the second tunneling layer, and the second PN junction on the front side, and forming a velvet surface in the Gap region, the second sub-region, and the front side of the N-type silicon substrate;

[0026] Step S8: depositing an aluminum oxide film and an anti-reflection film on the front and back sides of the N-type silicon substrate;

[0027] Step S9: preparing metal electrodes in the first sub-region and the N region on the back side of the N-type silicon substrate, and sintering and curing them.

[0028] In some embodiments, the thickness of the first tunneling layer is 2 nm to 2.5 nm, and the thickness of the boron-doped polysilicon layer is 320 nm to 340 nm.

[0029] In certain embodiments, the BSG layer has a thickness of 70 nm to 80 nm.

[0030] In some embodiments, in step S4, the BSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2;

[0031] The N region and the Gap region on the back side of the N-type silicon substrate and the boron-doped polysilicon layer, the first tunnel oxide layer and the first PN junction on the front side are cleaned by alkaline bath etching. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:20:3, wherein the NaOH concentration is about 3%.

[0032] In some embodiments, the thickness of the second tunneling layer is 1 nm to 1.5 nm, and the thickness of the phosphorus-doped polysilicon layer is 300 nm to 320 nm.

[0033] In certain embodiments, the PSG layer has a thickness of 70 nm to 80 nm.

[0034] In some embodiments, in step S7, the PSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2;

[0035] The first sub-region, the Gap region on the back side of the N-type silicon substrate and the phosphorus-doped polysilicon layer, the second tunnel layer and the second PN junction on the front side are cleaned by alkaline bath etching, and a velvet surface is formed on the Gap region, the second sub-region and the front side of the back side of the N-type silicon substrate. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:12:5, wherein the NaOH concentration is about 3%.

[0036] In some embodiments, the aluminum oxide film has a thickness of 3 nm to 5 nm.

[0037] In some embodiments, the anti-reflection film includes five silicon nitride layers.

[0038] Due to the application of the above technical solution, the beneficial effects of the present disclosure compared with the prior art are:

[0039] (1) By adding a phosphorus-doped polysilicon layer on the boron-doped polysilicon layer, the second tunneling layer of the interlayer will form a secondary doping effect, thereby improving the passivation level of the boron-doped polysilicon layer.

[0040] (2) The boron-doped polysilicon layer and the phosphorus-doped polysilicon layer form two PN junctions. The built-in electric field formed by the two PN junctions generates more carriers, forcing more holes to gather in the boron-doped polysilicon layer and transmit laterally, making them easier to be collected by the metal electrode.

[0041] (3) Add a back velvet structure and a carrier collection optimization structure without increasing the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 Schematic diagram of the cross-sectional structure of a TBC solar cell in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the scheme of the present disclosure, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present disclosure.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] In the present disclosure, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0047] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this disclosure can be understood according to specific circumstances.

[0048] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0049] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] An embodiment of the present disclosure provides a method for preparing a TBC solar cell, comprising the following steps:

[0051] Step S1: cleaning and polishing the N-type silicon substrate;

[0052] Step S2: depositing a first tunneling oxide layer and a first intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0053] Specifically, the cleaned and polished N-type silicon substrate is placed in an LPCVD device, and a first tunneling oxide layer of 2nm to 2.5nm is grown at 600℃ to 650℃; a first intrinsic polysilicon layer of 320nm to 340nm is grown at 550℃ to 650℃, and the deposition time is 10000s;

[0054] Step S3: performing boron diffusion on the first intrinsic polysilicon layer to form a boron-doped polysilicon layer and a BSG layer, and diffusing toward the N-type silicon substrate to form a first PN junction;

[0055] Specifically, an N-type silicon substrate is placed in a tubular diffusion device for boron diffusion at 830°C and 850°C for 150s and 500s respectively, then heated to 970°C for 800s, and oxidized at 970°C for 850s to form a 70nm-80nm BSG layer, and the first PN junction is formed by internal expansion;

[0056] Step S4: using laser to remove the BSG layer in the N region and the Gap region on the back side of the N-type silicon substrate; etching and cleaning the BSG layer on the front side of the N-type silicon substrate, etching and cleaning the N region and the Gap region on the back side of the N-type silicon substrate, as well as the boron-doped polysilicon layer, the first tunnel oxide layer and the first PN junction on the front side, and the area not removed is the P region;

[0057] Specifically, the BSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2, the pickling time is 60s, and the acid solution temperature is 30°C;

[0058] The N region and Gap region on the back of the N-type silicon substrate and the boron-doped polysilicon layer, the first tunnel oxide layer and the first PN junction on the front are cleaned by alkaline bath etching. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:20:3, where the NaOH concentration is about 3%. The temperature in the bath is 50℃~75℃, and the process time is 300s;

[0059] Step S5: depositing a second tunneling layer and a second intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate;

[0060] Specifically, an N-type silicon substrate is placed in an LPCVD device, and a second tunneling layer of 1nm to 1.5nm is grown at 600℃ to 650℃; a second intrinsic polysilicon layer of 300nm to 320nm is grown at 600℃ to 650℃, and the deposition time is 3500s;

[0061] Step S6: performing phosphorus diffusion on the first intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer, and diffusing toward the N-type silicon substrate to form a second PN junction;

[0062] Specifically, the N-type silicon substrate is placed in a tubular diffusion device for phosphorus diffusion, diffused at 860°C for 1350s, then heated to 880°C for 300s, oxidized at 900°C for 500s, to form a 70nm-80nm PSG layer, and expanded inward to form a second PN junction, while the second tunneling layer located in the first sub-region forms a silicon oxide layer containing boron and phosphorus;

[0063] Step S7: using laser to remove the PSG layer in the Gap region on the back side of the N-type silicon substrate and the first sub-region of the P region, and retaining the PSG layer in the second sub-region of the P region located on both sides of the first sub-region; etching and cleaning the PSG layer on the front side of the N-type silicon substrate, etching and cleaning the first sub-region, the Gap region on the back side of the N-type silicon substrate, and the phosphorus-doped polysilicon layer, the second tunneling layer, and the second PN junction on the front side, and forming a velvet surface in the Gap region, the second sub-region, and the front side of the N-type silicon substrate;

[0064] Specifically, the PSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2, the pickling time is 40s, and the acid solution temperature is 30°C;

[0065] The first sub-region, Gap region and phosphorus-doped polysilicon layer, second tunnel layer and second PN junction on the back of the N-type silicon substrate, as well as the front surface, are cleaned by alkaline bath etching, and a velvet surface is formed on the Gap region, second sub-region and front surface of the back of the N-type silicon substrate. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:12:5, wherein the concentration of NaOH is about 3%. The temperature in the bath is 50℃~75℃, and the process time is 450s;

[0066] Step S8: depositing an aluminum oxide film and an anti-reflection film on the front and back sides of the N-type silicon substrate;

[0067] The details are as follows: Aluminum oxide film is coated on both sides by single-insert double-sided ALD, and then anti-reflection film is coated on both sides by PECVD. The anti-reflection film includes five layers of silicon nitride. The ALD process temperature is 200°C, the process time is 400s, the thickness of the aluminum oxide film is 3nm to 5nm, the PECVD coating process temperature is 500°C, the process time of each silicon nitride layer is 180s, and the thickness of the five silicon nitride layers is 80nm;

[0068] Step S9: preparing metal electrodes in the first sub-region and the N region on the back side of the N-type silicon substrate, and sintering and curing them.

[0069] See also Figure 1 The present disclosure also relates to a TBC solar cell, which is prepared by the above-mentioned preparation method. The TBC solar cell includes an N-type silicon substrate 4, the N-type silicon substrate 4 has a front side and a back side opposite to each other, the back side of the N-type silicon substrate 4 has first regions and second regions alternately arranged along a first direction, and there is a spacing region between the first region and the second region, and the first direction is perpendicular to the thickness direction of the N-type silicon substrate 4;

[0070] The first region includes a first PN junction 5, a first tunnel oxide layer 6, and a boron-doped polysilicon layer 7 which are sequentially arranged in a direction away from the back side of the substrate;

[0071] The surface of the boron-doped polysilicon layer 7 has a first sub-region and a second sub-region arranged at both ends of the first sub-region along a first direction, the first sub-region includes a suede structure 3, an aluminum oxide film 2, and an anti-reflection film 1 arranged in sequence in a direction away from the back side of the substrate; the second sub-region includes a boron-phosphorus-containing silicon oxide layer 8, a phosphorus-doped polysilicon layer 9, an aluminum oxide film 2, and an anti-reflection film 1 arranged in sequence in a direction away from the back side of the substrate;

[0072] The spacer region includes a suede structure 3, an aluminum oxide film 2, and an anti-reflection film 1 which are sequentially arranged in a direction away from the back surface of the substrate;

[0073] The second region includes a second PN junction 11, a second tunneling layer 12, a phosphorus-doped polysilicon layer 9, an aluminum oxide film 2, and an anti-reflection film 1, which are sequentially arranged in a direction away from the back surface of the substrate;

[0074] The front side of the N-type silicon substrate 4 includes a velvet structure 3, an aluminum oxide film 2, and an anti-reflection film 1 arranged in sequence in a direction away from the front side of the substrate;

[0075] The TBC solar cell also includes a first electrode 10 and a second electrode 13. The first electrode 10 is located in the first sub-area, and the first electrode 10 passes through the anti-reflection film 1, the aluminum oxide film 2, and the velvet structure 3 to contact the boron-doped polysilicon layer 7; the second electrode 13 is located in the second area, and the second electrode 13 passes through the anti-reflection film 1 and the aluminum oxide film 2 to contact the phosphorus-doped polysilicon layer 9.

[0076] Finally, it should be noted that the above are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A TBC solar cell, characterized in that: The TBC solar cell comprises a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, wherein the back side of the silicon substrate has first regions and second regions arranged alternately and spaced along a first direction, wherein a spacer region is provided between the first regions and the second regions, and wherein the first direction is perpendicular to a thickness direction of the silicon substrate; The first region includes a first PN junction, a first tunneling layer, and a first doped polysilicon layer arranged in sequence in a direction away from the back side of the substrate; The surface of the first doped polysilicon layer has a first sub-region and a second sub-region arranged at two ends of the first sub-region along a first direction, the first sub-region includes a suede structure and a passivation layer arranged in sequence in a direction away from the back side of the substrate; the second sub-region includes a dielectric layer, a second doped polysilicon layer, and a passivation layer arranged in sequence in a direction away from the back side of the substrate; The spacer region includes a suede structure and a passivation layer arranged in sequence in a direction away from the back side of the substrate; The second region includes a second PN junction, a second tunneling layer, a second doped polysilicon layer, and a passivation layer which are sequentially arranged in a direction away from the back side of the substrate; The front side of the silicon substrate comprises a suede structure and a passivation layer arranged in sequence in a direction away from the front side of the substrate; The TBC solar cell further comprises a first electrode and a second electrode, the first electrode being located in the first sub-region, and the first electrode respectively passing through the passivation layer and contacting the first doped polysilicon layer; The second electrodes are located in the second region, and the second electrodes respectively pass through the passivation layer and contact the second doped polysilicon layer.

2. The TBC solar cell according to claim 1, characterized in that: The doping element of the first doped polysilicon or the second doped silicon is a group III or group V element, wherein the conductivity of the doping element of the second doped polysilicon layer is opposite to that of the first doped polysilicon layer.

3. The TBC solar cell according to claim 1, characterized in that: The passivation layer is a stack of aluminum oxide and silicon nitride, wherein the thickness of the aluminum oxide film is 3nm to 5nm.

4. The TBC solar cell according to claim 1, characterized in that: The first tunneling layer is a tunneling oxide layer, the thickness of the first tunneling layer is 1 nm to 2.5 nm, and the thickness of the first doped polysilicon layer is 320 nm to 340 nm.

5. The TBC solar cell according to claim 1, characterized in that: The thickness of the second tunneling layer is 1 nm to 1.5 nm, and the thickness of the second doped polysilicon layer is 300 nm to 320 nm.

6. The TBC solar cell according to claim 1, characterized in that: The dielectric layer is a silicon oxide layer containing a first doping element and a second doping element.

7. A method for preparing a TBC solar cell according to any one of claims 1 to 6, characterized in that: The following steps are involved: Step S1: cleaning and polishing the N-type silicon substrate; Step S2: depositing a first tunneling layer and a first intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate; Step S3: performing boron diffusion on the first intrinsic polysilicon layer to form a boron-doped polysilicon layer and a BSG layer, and diffusing toward the N-type silicon substrate to form a first PN junction; Step S4: using laser to remove the BSG layer in the back N region and the Gap region of the N-type silicon substrate; Etching and cleaning the BSG layer on the front side of the N-type silicon substrate, etching and cleaning the N region, the Gap region on the back side of the N-type silicon substrate, and the boron-doped polysilicon layer, the first tunneling layer and the first PN junction on the front side, and the area not removed is the P region; Step S5: depositing a second tunneling layer and a second intrinsic polysilicon layer in sequence on the back side of the N-type silicon substrate; Step S6: performing phosphorus diffusion on the first intrinsic polysilicon layer to form a phosphorus-doped polysilicon layer and a PSG layer, and diffusing toward the N-type silicon substrate to form a second PN junction; Step S7: using laser to remove the back Gap region of the N-type silicon substrate and the PSG layer of the first sub-region of the P region, and retaining the PSG layer of the second sub-region of the P region located on both sides of the first sub-region; Etching and cleaning the PSG layer on the front side of the N-type silicon substrate, etching and cleaning the first sub-region, the Gap region on the back side of the N-type silicon substrate, and the phosphorus-doped polysilicon layer, the second tunneling layer, and the second PN junction on the front side, and forming a velvet surface on the Gap region, the second sub-region, and the front side of the back side of the N-type silicon substrate; Step S8: depositing an aluminum oxide film and an anti-reflection film on the front and back sides of the N-type silicon substrate; Step S9: preparing metal electrodes in the first sub-region and the N region on the back side of the N-type silicon substrate, and sintering and curing them.

8. The method for preparing a TBC solar cell according to claim 7, characterized in that: The thickness of the BSG layer is 70 nm to 80 nm.

9. The method for preparing a TBC solar cell according to claim 7, characterized in that: In the step S4, the BSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2; The N region and the Gap region on the back of the N-type silicon substrate and the boron-doped polysilicon layer, the first tunneling layer and the first PN junction on the front are cleaned by alkaline bath etching. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:20:3, wherein the NaOH concentration is about 3%.

10. The method for preparing a TBC solar cell according to claim 7, characterized in that: In the step S7, the PSG layer on the front side of the N-type silicon substrate is cleaned by wet chain etching, and the reagent used is an acid solution composed of HF and H2O in a volume ratio of 3:2; The first sub-region, the Gap region on the back side of the N-type silicon substrate and the phosphorus-doped polysilicon layer, the second tunnel layer and the second PN junction on the front side are cleaned by alkaline bath etching, and a velvet surface is formed on the Gap region, the second sub-region and the front side of the back side of the N-type silicon substrate. The reagent used is an alkaline solution composed of H2O, NaOH and polishing additives in a volume ratio of 300:12:5, wherein the NaOH concentration is about 3%.

Images