Miniature light-emitting diode chip, manufacturing method and miniature light-emitting diode device

Abstract

The invention provides a miniature light-emitting diode chip, a manufacturing method and a miniature light-emitting diode device. The manufacturing method comprises the following steps: providing an initial light-emitting framework comprising a plurality of mesa structures; each table-board structure comprises a side wall and a top surface, and at least two areas of the side wall and a plane parallel to the top surface form different inclined included angles; forming a first passivation layer on the outer surface of the initial light-emitting framework; forming a metal layer on the outer surface of the first passivation layer; and exposing the electrode area of each mesa structure to obtain the micro light-emitting diode chip. On the basis of the structure, the metal layer not only can reduce the side wall light crosstalk, but also can reduce the stress generated in the metal layer, and improves the reliability of the miniature light-emitting diode chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor light emitting technology, and in particular to a micro light emitting diode chip and a manufacturing method thereof, and a micro light emitting diode device. Background Art

[0002] Micro-LED (Micro-Light Emitting Diode) display technology is a display technology that miniaturizes and arrays the traditional LED (Light Emitting Diode) structure and uses CMOS (Complementary Metal Oxide Semiconductor) or TFT (Thin Film Transistor) to make driving circuits to achieve addressing control and individual drive of each pixel.

[0003] Among them, the spacing between adjacent pixels in the Micro-LED chip is small, and there is a serious optical crosstalk problem between the pixels. Therefore, it is urgent to provide a Micro-LED chip with less optical crosstalk. Summary of the invention

[0004] The purpose of the present application is to provide a micro light emitting diode chip and a manufacturing method, and a micro light emitting diode device.

[0005] In order to solve the above problems, in a first aspect, the present application provides a method for manufacturing a micro light emitting diode chip, comprising:

[0006] Providing an initial light-emitting structure including a plurality of mesa structures; each of the mesa structures includes a side wall and a top surface, and at least two regions of the side wall form different inclined angles with a plane parallel to the top surface;

[0007] forming a first passivation layer on the outer surface of the initial light-emitting structure;

[0008] forming a metal layer on the outer surface of the first passivation layer;

[0009] The electrode region of each mesa structure is exposed, and the micro light emitting diode chip is obtained.

[0010] Optionally, the initial light-emitting structure further includes a substrate carrying the mesa structure, each of the mesa structures includes a first semiconductor layer and a light-emitting layer, and the first semiconductor layer is disposed between the substrate and the light-emitting layer; wherein,

[0011] The side wall of the first semiconductor layer forms a first tilt angle with a plane parallel to the top surface, and the side wall of the light emitting layer forms a second tilt angle different from the first tilt angle with a plane parallel to the top surface; or,

[0012] A portion of the sidewall of the first semiconductor layer close to the substrate forms a first tilt angle with a plane parallel to the top surface, and another portion of the sidewall of the first semiconductor layer and the sidewall of the light-emitting layer form a second tilt angle with a plane parallel to the top surface.

[0013] Optionally, the first inclination angle is greater than the second inclination angle.

[0014] Optionally, each of the mesa structures includes a first semiconductor layer; and the step of forming a first passivation layer on the outer surface of the initial light-emitting structure includes:

[0015] Forming a first passivation layer on the outer surface of the initial light-emitting structure, and forming a plurality of first through-hole structures penetrating the first passivation layer along a thickness direction on the first passivation layer;

[0016] The step of forming a metal layer on the outer surface of the first passivation layer comprises:

[0017] A metal layer is formed on the outer surface of the first passivation layer, and a portion of the metal layer is disposed in each of the first through-hole structures and connected to the first semiconductor layer to achieve electrical connection.

[0018] Optionally, the step of forming a plurality of first through-hole structures penetrating the first passivation layer along the thickness direction on the first passivation layer includes:

[0019] forming a plurality of first through-hole structures penetrating the first passivation layer along the thickness direction on the first passivation layer, and making four of the first through-hole structures evenly distributed around each of the mesa structures and at least one of the first through-hole structures being located at the center of the coverage areas of the four mesa structures; and / or,

[0020] A plurality of first through-hole structures penetrating the first passivation layer along a thickness direction are formed on the first passivation layer, and at least one first through-hole structure is disposed between two adjacent mesa structures.

[0021] Optionally, after the step of forming a metal layer on the outer surface of the first passivation layer, the method further includes:

[0022] A second passivation layer is formed on the outer surface of the metal layer.

[0023] Optionally, before the step of forming a second passivation layer on the outer surface of the metal layer, exposing the electrode region of each mesa structure includes:

[0024] removing the metal layer corresponding to the electrode region of each mesa structure, and forming a second through-hole structure in the metal layer;

[0025] The step of forming a second passivation layer on the outer surface of the metal layer comprises:

[0026] forming a second passivation layer on the outer surface of the metal layer, and disposing a portion of the second passivation layer in the second through-hole structure and connected to the first passivation layer;

[0027] The step of exposing the electrode region of each mesa structure further includes:

[0028] The first passivation layer and the second passivation layer corresponding to the electrode region of each mesa structure are removed to expose the electrode region of each mesa structure.

[0029] In a second aspect, the present application further provides a micro light emitting diode chip, comprising:

[0030] An initial light-emitting structure comprises a plurality of mesa structures, each of the mesa structures comprises a side wall and a top surface, and at least two regions of the side wall form different inclined angles with a plane parallel to the top surface;

[0031] A first passivation layer is disposed on the outer surface of the initial light-emitting structure; and

[0032] The metal layer is disposed on the outer surface of the first passivation layer. The metal layer and the first passivation layer expose the electrode region of each mesa structure.

[0033] Optionally, the initial light-emitting structure further includes a substrate carrying the mesa structure, each of the mesa structures includes a first semiconductor layer and a light-emitting layer, and the first semiconductor layer is disposed between the substrate and the light-emitting layer; wherein,

[0034] The side wall of the first semiconductor layer forms a first tilt angle with a plane parallel to the top surface, and the side wall of the light emitting layer forms a second tilt angle different from the first tilt angle with a plane parallel to the top surface; or,

[0035] A portion of the sidewall of the first semiconductor layer close to the substrate forms a first tilt angle with a plane parallel to the top surface, and another portion of the sidewall of the first semiconductor layer and the sidewall of the light-emitting layer form a second tilt angle with a plane parallel to the top surface.

[0036] Optionally, the first inclination angle is greater than the second inclination angle.

[0037] Optionally, each of the mesa structures includes a first semiconductor layer, and the first passivation layer is provided with a plurality of first through-hole structures penetrating the first passivation layer along the thickness direction, and a portion of the metal layer is arranged in each of the first through-hole structures and connected to the first semiconductor layer to achieve electrical connection.

[0038] Optionally, four first through-hole structures are evenly distributed around each of the mesa structures, and at least one first through-hole structure is located at the center of the coverage area of ​​the four mesa structures; and / or,

[0039] At least one first through hole structure is disposed between two adjacent mesa structures.

[0040] Optionally, the micro light emitting diode chip further includes:

[0041] The second passivation layer is disposed on the outer surface of the metal layer. The metal layer, the first passivation layer and the second passivation layer expose the electrode region of each mesa structure.

[0042] Optionally, the metal layer has a second through hole structure extending through the metal layer in a thickness direction, and a portion of the second passivation layer is disposed in the second through hole structure and covers a side wall of the metal layer.

[0043] In a third aspect, the present application further provides a micro light emitting diode device, comprising:

[0044] A micro light emitting diode chip prepared by the method for preparing a micro light emitting diode chip as described above; or, a micro light emitting diode chip as described above; and

[0045] A driving chip is bonded to the micro light emitting diode chip.

[0046] Based on the above technical scheme, the micro-LED chip and manufacturing method of the present application, and the micro-LED device, form a first passivation layer on the outer surface of the initial light-emitting structure, and form a metal layer on the outer surface of the first passivation layer. On the one hand, the first passivation layer separates the metal layer and the mesa structure, which can avoid the metal layer from having an adverse effect on the mesa structure; on the other hand, the metal layer can block the light emitted by the pixel points formed by the mesa structure, and can avoid light crosstalk between multiple pixel points; on the other hand, at least two areas of the side wall of the mesa structure form different inclined angles with the plane parallel to the top surface, and the mesa structure forms a double-step structure and its side wall has at least two inclinations. When the first passivation layer and the metal layer cover the outer surface of the mesa structure, the stress generated inside the metal layer can be reduced, and the metal layer can be prevented from cracking or breaking the entire layer under the action of stress, which causes the micro-LED chip to have abnormal current and resistance. Therefore, the present application sets a metal layer on the outer surface of the mesa structure with double inclined steps, and the micro-LED chip has better optical performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solution in this application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0048] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0049] Figure 1 A schematic diagram of a process for manufacturing a micro light emitting diode chip provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the structure of the initial light-emitting architecture provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of a structure after the first passivation layer is formed in the initial light-emitting structure provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of a structure after a metal layer is formed in the initial light-emitting structure provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of an electrode region of an exposed mesa structure of an initial light-emitting architecture provided in an embodiment of the present application;

[0054] Figure 6A schematic diagram of the first structure of a micro light emitting diode chip provided in an embodiment of the present application;

[0055] Figure 7 A scanning electron microscope image of the micro light emitting diode chip 100 provided in an embodiment of the present application;

[0056] Figure 8 A second structural schematic diagram of a micro light emitting diode chip provided in an embodiment of the present application;

[0057] Fig. 9 A third structural schematic diagram of the micro light emitting diode chip provided in the embodiment of the present application;

[0058] Fig.10 for Figure 8 and Fig. 9 A schematic diagram of the brightness curve of the micro light emitting diode chip shown;

[0059] Fig.11 A schematic diagram of a structure after a first through-hole structure is formed in the initial light-emitting structure provided in an embodiment of the present application;

[0060] Fig.12 A fourth structural schematic diagram of the micro light emitting diode chip provided in an embodiment of the present application;

[0061] Fig.13 A schematic top view of a micro light emitting diode chip provided in an embodiment of the present application;

[0062] Fig.14 A fifth structural schematic diagram of a micro light emitting diode chip provided in an embodiment of the present application;

[0063] Fig.15 A second schematic flow chart of a method for manufacturing a micro-LED chip 100 provided in an embodiment of the present application;

[0064] Fig.16 A sixth structural schematic diagram of a micro light emitting diode chip provided in an embodiment of the present application;

[0065] Fig.17 A schematic diagram of a process for manufacturing a micro light emitting diode device provided in an embodiment of the present application;

[0066] Fig.18 A schematic diagram of the structure of a driver chip provided in an embodiment of the present application;

[0067] Fig.19 A schematic diagram of the structure after the micro light emitting diode chip and the driver chip provided in the embodiment of the present application are bonded;

[0068] Fig. 20A schematic diagram of the first structure of a micro light emitting diode device provided in an embodiment of the present application;

[0069] Fig.21 A second structural schematic diagram of a micro light emitting diode device provided in an embodiment of the present application;

[0070] Fig. 22 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0071] The reference numerals are as follows:

[0072] 10. Micro-LED device; 20. Display device; 100. Micro-LED chip; 200. Driver chip; 300. Bonding structure; 400. Optical structure; 110. Initial light-emitting architecture; 120. First passivation layer; 130. Metal layer; 140. Second passivation layer; 150. Solder joint structure; 160. First through-hole structure; 170. Second through-hole structure; 180. Third through-hole structure; 210. Second substrate; 220. Driver circuit ; 230, driving pad; 240, electrical connection part; 410, quantum dot color film structure; 420, filter layer; 430, glass layer; 111, first substrate; 112, table structure; 411, black matrix structure; 412, quantum dot color film; 1121, first semiconductor layer; 1122, light-emitting layer; 1123, second semiconductor layer; 1124, first electrode layer; 1125, second electrode layer; 1126, buffer layer; 1127, current diffusion layer. DETAILED DESCRIPTION

[0073] The following will be combined with the appendix of this application Figure 1 To Attachment Fig. 22 The technical solutions in this application are clearly and completely described in the following embodiments. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0074] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0075] With the continuous development of Micro-LED display technology, it is gradually moving towards small size and high resolution. Due to the small spacing between the pixels of Micro-LED, there is serious optical crosstalk between the GaN mesa structures (GaN Mesa). In particular, the optical crosstalk caused by light leakage from the surrounding side walls significantly reduces the clarity of the Micro-LED screen.

[0076] In order to solve the above technical problems, the present application provides a micro-LED chip 100 and a manufacturing method, and a micro-LED device 10. The metal layer 130 of the micro-LED chip 100 covers the outer surface of the table structure 112 with at least two inclinations. The metal layer 130 can reduce the optical crosstalk caused by light leakage from the surrounding side walls of the table structure 112 of the micro-LED chip 100, and can also reduce the stress generated inside the metal layer 130, thereby avoiding cracks or whole-layer breakage under the action of stress, which may cause current and resistance abnormalities in the micro-LED chip 100. The reliability of the micro-LED chip 100 is good.

[0077] The following is a detailed description with reference to specific embodiments. It should be noted that the embodiments of the present application can be presented in various forms, some examples of which will be described below.

[0078] Please refer to Figure 1 , Figure 1 A schematic flow chart of a method for manufacturing a micro-light emitting diode chip 100 provided in an embodiment of the present application. The method for manufacturing a micro-light emitting diode chip 100 of the present application includes:

[0079] In S11 , an initial light-emitting structure 110 including a plurality of mesa structures 112 is provided; each mesa structure 112 includes a side wall and a top surface, and at least two regions of the side wall form different inclined angles with a plane parallel to the top surface.

[0080] In this step, please refer to Figure 2 , Figure 2 A schematic diagram of the structure of an initial light-emitting architecture 110 provided in an embodiment of the present application. The initial light-emitting architecture 110 includes a substrate, such as a first substrate 111, and a plurality of (two or more) mesa structures 112 formed on the substrate, such as the first substrate 111, wherein adjacent mesa structures 112 are arranged at intervals, and each mesa structure 112 can form a pixel.

[0081] like Figure 2As shown, each mesa structure 112 includes a first semiconductor layer 1121, a light-emitting layer 1122, a second semiconductor layer 1123 and a first electrode layer 1124 which are sequentially stacked on a first substrate 111. The first substrate 111 is used to support the film structure thereon, and the first substrate 111 is a sapphire substrate, a silicon substrate or a silicon carbide substrate, etc. The light-emitting layer 1122 is a quantum well layer, for example, the light-emitting layer 1122 is an indium gallium nitride quantum well layer, or an indium gallium nitride / gallium nitride multi-quantum well layer. The first semiconductor layer 1121 is one of an N-type semiconductor layer and a P-type semiconductor layer, and the second semiconductor layer 1123 is the other of an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor layer is an N-type gallium nitride layer or an N-type gallium arsenide layer, and the P-type semiconductor layer is a P-type gallium nitride layer or a P-type aluminum gallium nitride layer. For example, in Figure 2 In the illustrated embodiment, the first semiconductor layer 1121 is an N-type semiconductor layer, and the second semiconductor layer 1123 is a P-type semiconductor layer. The first electrode layer 1124 is disposed on a side of the second semiconductor layer 1123 away from the light emitting layer 1122 and is electrically connected to the second semiconductor layer 1123 .

[0082] like Figure 2 As shown, the initial light-emitting structure 110 further includes a second electrode layer 1125, which is disposed in an exposed area of ​​the first semiconductor layer 1121 and is electrically connected to the first semiconductor layer 1121. The first electrode layer 1124 and the second electrode layer 1125 are used to be electrically connected to the driver chip 200 described later. The initial light-emitting structure 110 further includes a buffer layer 1126, which can relieve the stress generated by the lattice mismatch and thermal expansion coefficient mismatch between the film layer on it and the first substrate 111. The buffer layer 1126 can be, but is not limited to, silicon nitride, silicon oxide layer, gallium nitride layer or aluminum nitride layer. Each mesa structure 112 of the micro-LED chip 100 can also include a current diffusion layer 1127 formed on a side of the second semiconductor layer 1123 away from the first substrate 111. The current diffusion layer 1127 can evenly distribute the current to the entire second semiconductor layer 1123 (such as a P-type gallium nitride layer), thereby effectively improving the luminous efficiency of the micro-LED chip 100. It should be noted that Figure 2 This is only an exemplary description of the initial light emitting structure 110 of the present application. The initial light emitting structure 110 of the present application can also be other structures. For example, each mesa structure 112 of the initial light emitting structure 110 of the present application includes an independent second electrode layer 1125 .

[0083] It is understandable that if Figure 2As shown, the top surface of the mesa structure 112 is the side of the first electrode layer 1124 away from the current diffusion layer 1127. The sidewall of the mesa structure 112 is a structure formed by the sidewalls of each film layer of the initial light-emitting architecture 110, that is, the sidewalls of the first semiconductor layer 1121, the light-emitting layer 1122, the second semiconductor layer 1123, the current diffusion layer 1127 and the first electrode layer 1124 together form the sidewall of the mesa structure 112. Figure 2 As shown, part of the sidewall area of ​​the mesa structure 112 has an inclined angle with the plane parallel to the top surface, and another part of the sidewall area of ​​the mesa structure 112 has another inclined angle with the plane parallel to the top surface. The mesa structure 112 of the present application is a double inclined step structure.

[0084] It is understandable that in the production process, a double-inclined step structure can be formed by inductively coupled plasma etching (ICP) method. Exemplarily, the present application bakes the mask layer at 130°C-150°C for 1-3 minutes before the etching process, and selects the process conditions of upper power of 150W-300W, lower power of 20W-60W, working pressure of 100Pa-160Pa, and etching temperature of 0°C-20°C; a mixed gas of argon (Ar), chlorine (Cl2) and boron trichloride (BCl3) is used during the etching process, and the flow ratio of Ar, Cl2 and BCl3 is 1:1:9 to 1:2:10, divided into 2 etching cycles, each etching cycle time is 400-700s, and the mesa structure 112 of the double-inclined step of the present application is formed.

[0085] In S12 , a first passivation layer 120 is formed on the outer surface of the initial light emitting structure 110 .

[0086] like Figure 3 As shown, Figure 3A schematic diagram of a structure after the first passivation layer 120 is formed on the initial light-emitting structure 110 provided in an embodiment of the present application. In this step, the first passivation layer 120 is formed on the outer surface of the initial light-emitting structure 110 away from the first substrate 111 by means of a plasma enhanced chemical vapor deposition process (PECVD), a thin film deposition process, an atomic layer deposition process (ALD), etc. The outer surface in this step includes the area of ​​the top surface of the initial light-emitting structure 110 parallel to the first substrate 111, the area of ​​the side wall connected to the top surface and the first substrate 111, and the gap area between adjacent mesa structures 112. The first passivation layer 120 adheres to the outer surface of the mesa structure 112 and covers all the mesa structures 112 and the spacing area between the mesa structures 112. The first passivation layer 120 is an integral structure and can form a double inclined step shape. At least two areas of the side wall of the first passivation layer 120 can also form different inclined angles with the plane parallel to the top surface.

[0087] In some examples, the material of the first passivation layer 120 includes insulating materials such as silicon oxide, silicon nitride and / or aluminum oxide. In some examples, the thickness of the first passivation layer 120 is between 150 micrometers (μm) and 250 μm, for example, the thickness of the first passivation layer 120 is about 150 μm, 200 μm or 250 μm. At this time, the first passivation layer 120 is not too thin so that the first passivation layer 120 cannot well separate the metal layer 130 and the mesa structure 112 described later; at the same time, the first passivation layer 120 is not too thick so that the distance between two adjacent mesa structures 112 is small, which reduces the setting space of the metal layer 130 and increases the thickness of the entire micro-LED chip 100, which is not conducive to the lightweight design of the micro-LED chip 100. The above-mentioned thickness design of the first passivation layer 120 of the present application can take into account the safety and lightweight design of the micro-LED chip 100.

[0088] In S13 , a metal layer 130 is formed on an outer surface of the first passivation layer 120 .

[0089] Each mesa structure 112 protrudes from the first substrate 111 along the thickness direction of the initial light-emitting structure 110, so that each mesa structure 112 has a side wall and a top surface protruding from the first substrate 111, the top surface is arranged opposite to the first substrate 111, and the side wall is located between the top surface area and the first substrate 111. Figure 4 , Figure 4A schematic diagram of a structure after the metal layer 130 is formed on the initial light-emitting structure 110 provided in an embodiment of the present application. In this step, a metal layer 130 is formed on the sidewall and top surface area of ​​each mesa structure 112, and the metal layer 130 covers and adheres to the first passivation layer 120. The first passivation layer 120 separates the metal layer 130 from the mesa structure 112, and the first passivation layer 120 can avoid the metal layer 130 and the mesa structure 112 from being electrically connected and causing adverse effects; at the same time, the metal layer 130 can form a double inclined step shape, and at least two areas of the sidewall of the metal layer 130 can also form different inclined angles with the plane parallel to the top surface, which can reduce the stress generated inside the metal layer 130.

[0090] It is understandable that in this step, a metal layer 130 can be formed on the outer surface of each mesa structure 112 by processes such as thermal evaporation, electron beam evaporation or magnetron sputtering. The metal layer 130 has excellent light reflection performance and is not easy to absorb light. The metal layer 130 can ensure the optical performance of the micro-LED chip 100.

[0091] It is understood that in some examples, the thickness of the metal layer 130 is between 150 μm and 250 μm, for example, the thickness of the metal layer 130 is about 150 μm, 200 μm or 250 μm. At this time, the metal layer 130 is not too thin to make it difficult to form the metal layer 130 on the first passivation layer 120 in the production process, and at the same time, the metal layer 130 is not too thick to cause the metal layers 130 of two adjacent mesa structures 112 to be electrically interconnected and cause adverse effects.

[0092] In S14 , the electrode region of each mesa structure 112 is exposed, and the micro light emitting diode chip 100 is obtained.

[0093] In this step, the film structure covering the electrode region of each mesa structure 112 is removed by photolithography, etching, etc. to expose the electrode region of each mesa structure 112. Here, the electrode region of the mesa structure 112 includes the region where the aforementioned first electrode layer 1124 is located. Figure 5 and Figure 6 As shown, Figure 5 A schematic diagram of an electrode region of an initial light-emitting structure 110 exposing a mesa structure 112 provided in an embodiment of the present application, Figure 6 This is a schematic diagram of the first structure of the micro-light emitting diode chip 100 provided in an embodiment of the present application. In this step, after the first passivation layer 120 and the metal layer 130 covering the surface of the first electrode layer 1124 facing away from the first substrate 111 are removed, the first electrode layer 1124 is exposed to the air to facilitate the subsequent formation of the solder joint structure 150.

[0094] It is understandable that if Figure 5 and Figure 6 As shown, in this step, the portion of the metal layer 130 corresponding to the first electrode layer 1124 can be removed first, and then the portion of the first passivation layer 120 corresponding to the first electrode layer 1124 can be removed, and the first electrode layer 1124 can be exposed to the air. Of course, in other examples, the portion of the metal layer 130 and the portion of the first passivation layer 120 corresponding to the first electrode layer 1124 can be removed simultaneously through one process.

[0095] In some embodiments, the method for manufacturing the micro-LED chip 100 of the present application further removes the film structure covering the second electrode layer 1125 of the initial light-emitting structure 110 through a photolithography process, an etching process, etc., and exposes the second electrode layer 1125 .

[0096] In the manufacturing method of the micro-LED chip 100 of the embodiment of the present application, a first passivation layer 120 is formed on the outer surface of the initial light-emitting structure 110, and a metal layer 130 is formed on the outer surface of the first passivation layer 120. On the one hand, the first passivation layer 120 separates the metal layer 130 and the mesa structure 112, which can prevent the metal layer 130 from having an adverse effect on the mesa structure 112; on the other hand, the metal layer 130 can block the light emitted by the pixel points formed by the mesa structure 112, which can prevent light crosstalk between multiple pixel points; on the other hand, at least two regions of the side wall of the mesa structure 112 form different inclined angles with the plane parallel to the top surface, and the mesa structure 112 forms a double-step structure and its side wall has at least two inclinations. When the first passivation layer 120 and the metal layer 130 cover the outer surface of the mesa structure 112, the stress generated inside the metal layer 130 can be reduced, and the metal layer 130 can be prevented from cracking or breaking under the stress, which causes the micro-LED chip 100 to have abnormal current and resistance. Therefore, the present application sets the metal layer 130 on the outer surface of the mesa structure 112 with double inclined steps, and the micro light emitting diode chip 100 has better optical performance and reliability.

[0097] Please refer again to Figures 2 to 6 Please also refer to Figure 7 , Figure 7A scanning electron microscope image of a micro-LED chip 100 provided in an embodiment of the present application, a portion of the side wall of the first semiconductor layer 1121 close to the first substrate 111 forms a first tilt angle β with a plane parallel to the top surface, and another portion of the side wall of the first semiconductor layer 1121, the light-emitting layer 1122 and the side wall of the second semiconductor layer 1123 thereon form a second tilt angle α with a plane parallel to the top surface. At this time, the interface between the first tilt angle β and the second tilt angle α of the mesa structure 112 is located inside the first semiconductor layer 1121, a portion of the side wall of the first semiconductor layer 1121 has the first tilt angle β, and another portion of the side wall has the second tilt angle α. It can be understood that in some examples, the interface between the first tilt angle β and the second tilt angle α of the mesa structure 112 is closer to the stacking surface of the first semiconductor layer 1121 and the light-emitting layer 1122, so that the interface is closer to the light-emitting layer 1122.

[0098] In other embodiments, please refer to Figure 8 , Figure 8 A second structural schematic diagram of a micro-LED chip 100 provided in an embodiment of the present application. The sidewall of the first semiconductor layer 1121 of the mesa structure 112 forms a first tilt angle β with a plane parallel to the top surface, and the light-emitting layer 1122 forms a second tilt angle α with a plane parallel to the top surface. The interface between the first tilt angle β and the second tilt angle α is the stacking surface of the first semiconductor layer 1121 and the light-emitting layer 1122. At this time, the sidewalls of the light-emitting layer 1122 and the second semiconductor layer 1123 above it have the first tilt angle β, and the sidewalls of the first semiconductor layer 1121 and the film layer structure below have the second tilt angle α.

[0099] In the mesa structure 112 of the embodiment of the present application, since the sidewall thickness of the first semiconductor layer 1121 along the vertical direction is relatively large, when the interface of the two inclined angles of the mesa structure 112 is located between the first semiconductor layer 1121 and the light-emitting layer 1122, or located inside the first semiconductor layer 1121, the metal layer 130 and the first passivation layer 120 are more likely to be deposited on the outside of the mesa structure 112 and form a structure with a variable inclination angle, and at the same time, the stress generated inside the metal layer 130 can be reduced, thereby improving the reliability of the micro-LED chip 100. Moreover, the film layer near the light-emitting layer 1122 has a variable inclination angle, and the light emitted by the light-emitting layer 1122 is reflected by the sidewalls with different inclination angles, so that the light is more easily gathered, and the light extraction rate of the micro-LED chip 100 can also be improved.

[0100] It should be noted that the interface between the first tilt angle β and the second tilt angle α of the mesa structure 112 can also be located between other film layers, for example but not limited to, between the light emitting layer 1122 and the second semiconductor layer 1123 .

[0101] Among them, in some examples, the first tilt angle β is greater than the second tilt angle α. At this time, the entire mesa structure 112 forms a double-inclined step structure in which the film layer structure close to the first substrate 111 has a larger tilt angle with the horizontal plane, and the film layer structure away from the first substrate 111 has a smaller tilt angle with the horizontal plane. Looking from bottom to top, the spacing between adjacent mesa structures 112 is larger. A larger spacing can reduce the aspect ratio, and under the same conditions, a mesa structure 112 with a deeper mesa in the vertical direction can be etched, thereby blocking the lateral light crosstalk of the adjacent mesa structure 112 from the first semiconductor layer 1121.

[0102] It is understandable that, in some examples, the first tilt angle β is in the range of 65 to 80 degrees. Further, the first tilt angle β is between 70 and 75 degrees. For example, the first tilt angle β is 65, 70, 75, 78 or 80 degrees. In other examples, the second tilt angle α is in the range of 35 to 50 degrees. Further, the second tilt angle α is between 40 and 45 degrees. For example, the first tilt angle β is 35, 40, 43, 44, 45 or 50 degrees. The first tilt angle β and the second tilt angle α of the embodiment of the present application are in the above range, and the mesa structure 112 forming a double-tilted step structure can form a dual-resonance cavity structure, which is more conducive to the convergence of light to the middle of the mesa structure 112 within the above tilt angle range, thereby improving the light extraction efficiency of the chip.

[0103] For comparison, see Fig. 9 and Fig.10 , Fig. 9 This is a third structural schematic diagram of the micro light emitting diode chip 100 provided in the embodiment of the present application. Fig.10 for Figure 8 and Fig. 9 FIG. 1 is a schematic diagram of a brightness curve of a micro-LED chip 100. Fig. 9 As shown, when the mesa structure 112 of the micro LED chip 100 has an inclination angle so that the mesa structure 112 is a single-inclined step structure, the first passivation layer 120 and the metal layer 130 cover the outer side of the single-inclined step structure. Figures 1 to 8 As shown, when the mesa structure 112 of the micro-LED chip 100 has two tilt angles so that the mesa structure 112 is a double-tilted step structure, the first passivation layer 120 and the metal layer 130 cover the outer side of the double-tilted step structure, and the micro-LED chip 100 can form a dual-resonance cavity structure. Fig.10 As shown, curve S1 is Fig. 9 The luminescence curve of the single inclined step structure shown in FIG. 1 is curve S2. Figures 1 to 8From the luminous curves of the double-inclined step structure shown, it can be clearly seen from the comparison between curve S1 and curve S2 that the luminous efficiency of the micro-LED chip 100 with the double-inclined step structure of the present application is higher than that of the micro-LED chip 100 with the single-inclined step structure, which is about 12% higher. The luminous efficiency of the micro-LED chip 100 with the double-inclined step structure of the present application is higher.

[0104] The first tilt angle β of the mesa structure 112 of the embodiment of the present application is greater than the second tilt angle α. On the one hand, the spacing between adjacent mesa structures 112 from bottom to top is larger, which is more conducive to the deposition of the sidewall metal layer 130; on the other hand, a larger mesa spacing can reduce the aspect ratio, and under the same conditions, a mesa structure 112 with a deeper mesa in the vertical direction can be etched, thereby blocking the lateral light crosstalk from the first semiconductor layer 1121 of the adjacent mesa structure 112; on the other hand, the gradual inclination of the double-inclined step structure can reduce the stress generated inside the metal layer 130 when the metal layer 130 is formed on the insulating layer of the side wall, avoiding cracks in the metal layer 130 or the entire layer breaking under the action of stress, resulting in current and resistance abnormalities in the light-emitting diode chip, thereby improving the reliability of the light-emitting diode chip; on the other hand, the mesa structure 112 with a double-inclined step structure can form a dual-resonance cavity structure, which is more conducive to the convergence of light to the middle of the mesa structure 112, thereby improving the light extraction efficiency of the chip and having a better light crosstalk prevention effect.

[0105] In some examples, step S13: forming a metal layer 130 on the outer surface of the first passivation layer 120 includes: forming a metal layer 130 on the outer surface of the first passivation layer 120, and electrically connecting the metal layer 130 to the first semiconductor layer 1121. The metal layer 130 is electrically connected to the first semiconductor layer 1121 of each mesa structure 112, and the metal layer 130 can be used as a wire network to expand the current and reduce the voltage drop (IR drop) between different pixel points of the micro-LED chip 100, so that the micro-LED chip 100 obtains uniform brightness, and the micro-LED chip 100 has better optical performance.

[0106] Among them, please refer to Fig.11 and Fig.12 , Fig.11 A schematic diagram of a structure after the initial light-emitting structure 110 provided in an embodiment of the present application forms a first through-hole structure 160. Fig.12A fourth structural schematic diagram of the micro-LED chip 100 provided in an embodiment of the present application. In some examples, step S12 forms a first passivation layer 120 on the outer surface of the initial light-emitting architecture 110, including: forming the first passivation layer 120 on the outer surface of the initial light-emitting architecture 110, and forming a plurality of first through-hole structures 160 penetrating the first passivation layer 120 along the thickness direction on the first passivation layer 120. At this time, step S13 forms a metal layer 130 on the outer surface of the first passivation layer 120, and electrically connects the metal layer 130 to the first semiconductor layer 1121, including: forming a metal layer 130 on the outer surface of the first passivation layer 120, and a portion of the metal layer 130 is disposed or deposited in each first through-hole structure 160, and the metal layer 130 is connected to the first semiconductor layer 1121 and electrically connected.

[0107] It is understandable that the first through hole structure 160 can be arranged around the mesa structure 112 or between two adjacent mesa structures 112. Fig.13 , Fig.13 A schematic top view of a micro-LED chip 100 provided in an embodiment of the present application, wherein a plurality of mesa structures 112 on a first substrate 111 of an initial light-emitting structure 110 are arranged in an array, and four first through-hole structures 160 are evenly distributed around each mesa structure 112, and none of the four first through-hole structures 160 are located between two adjacent mesa structures 112, and except for the first through-hole structure 160 located at the edge of the initial light-emitting structure 110, each of the other first through-hole structures 160 can be surrounded by four mesa structures 112, and the center of the first through-hole structure 160 can coincide with the center of the coverage area of ​​the four mesa structures 112. For example, Fig.13 Four first through-hole structures 160 are evenly distributed around the middle mesa structure 112a. The first through-hole structure 160 is located in the central area of ​​the area enclosed by the four mesa structures 112a, 112b, 112c and 112d. The center of the first through-hole structure 160 coincides with the center of the area enclosed by the four mesa structures 112a, 112b, 112c and 112d. In the present embodiment, four first through-hole structures 160 are distributed around each mesa structure 112. On the one hand, the metal layer 130 can be electrically connected to more areas of the first semiconductor layer 1121 through the first through-hole structures 160. The wire network formed by the metal layer 130 can expand the current more evenly, and the brightness between multiple pixels of the micro-LED chip 100 is more uniform. On the other hand, the four first through-hole structures 160 distributed around the mesa structure 112 are not located between two adjacent mesa structures 112. The micro-LED chip 100 has more space to set the first through-hole structure 160, and can also open a larger first through-hole structure 160. The larger first through-hole structure 160 is more conducive to the deposition of the metal layer 130.

[0108] It should be noted that the micro-LED chip 100 of the embodiment of the present application can also be provided with a first through hole structure 160 between two adjacent mesa structures 112. Alternatively, a first through hole structure 160 is provided between two adjacent mesa structures 112, and four first through hole structures 160 are evenly distributed around each mesa structure 112, and at least one first through hole structure 160 is located at the center of the coverage area of ​​the four mesa structures 112. It should be noted that Fig.13 FIG. 1 is a top view of only a local area of ​​the micro-LED chip 100. Fig.13 The middle semicircular structure and the fan-shaped structure are not fully shown due to the size of the drawing, and they are also the first through-hole structure 160 .

[0109] It is understandable that the first through-hole structure 160 of the embodiment of the present application may be, but is not limited to, a circular hole structure, a square hole structure, a triangular hole structure, a hexagonal hole structure, etc. Among them, the ratio of the maximum diameter size of a first through-hole structure 160 of the embodiment of the present application to the maximum diameter size of a mesa structure 112 is between 1:6 and 2:3, for example, the ratio is 1:6, 1:3 or 2:3. In one example, when the maximum diameter size of the mesa structure 112 is about 3.2 microns, the maximum diameter size of the first through-hole structure 160 is about 0.5 microns to 2 microns. In this case, the size ratio of the first through-hole structure 160 to the mesa structure 112 is within the above range, which can not only prevent the first through-hole structure 160 from being too small and not conducive to the deposition of the metal layer 130, but also reduce the space occupied by the first through-hole structure 160, and avoid the electrical interconnection of the two mesa structures 112 to cause a short circuit.

[0110] The manufacturing method of the micro-LED chip 100 of the embodiment of the present application is to set a first through-hole structure 160 on the first passivation layer 120, and a part of the metal layer 130 is filled in the first through-hole structure 160 to realize the electrical connection with the first conductor layer. In the process production, only the process of forming the metal layer 130 is required to realize the electrical connection between the metal layer 130 and the first semiconductor layer 1121. The process flow of the micro-LED chip 100 is simpler and the production efficiency is higher. At the same time, the first through-hole structure 160 is set between two adjacent mesa structures 112, or four first through-hole structures 160 are evenly distributed around each mesa structure 112. The metal layer 130 can be electrically connected to the first semiconductor layer 1121 through more first through-hole structures 160. The wire network formed by the metal layer 130 can expand the current more evenly, and the brightness of the micro-LED chip 100 is more uniform.

[0111] It should be noted that the metal layer 130 can also be electrically connected to the first semiconductor layer 1121 in other ways. For example, in some examples, the first semiconductor layer 1121 is provided with an extension structure protruding and exposed to the first passivation layer 120, and the metal layer 130 is connected to the extension structure and electrically connected. In other embodiments, the metal layer 130 is electrically connected to the first semiconductor layer 1121 through a conductive member passing through the first passivation layer 120.

[0112] Among them, in some examples, please refer to Fig.14 , Fig.14 The fifth structural diagram of the micro-LED chip 100 provided in the embodiment of the present application further includes: forming a second passivation layer 140 on the outer surface of the metal layer 130 after the step S13 of forming the metal layer 130 on the outer surface of the first passivation layer 120 .

[0113] It is understandable that in this step, the second passivation layer 140 can be formed by PECVD, thin film deposition process, ALD, etc., and the second passivation layer 140 covers the top surface and side surfaces of the metal layer 130. The material of the second passivation layer 140 can include insulating materials such as silicon oxide, silicon nitride and / or aluminum oxide.

[0114] It is understandable that the thickness of the second passivation layer 140 can be between 150μm and 250μm. For example, the thickness of the second passivation layer 140 is approximately 150μm, 200μm or 250μm. At this time, the second passivation layer 140 is not too thick to increase the thickness of the entire micro-light-emitting diode chip 100, nor is it too thin to make the second passivation layer 140 unable to form a good protective layer to prevent water vapor and the like from corroding the metal layer 130.

[0115] The embodiment of the present application is provided with a second passivation layer 140, which can protect the metal layer 130 and prevent the air and other substances from having an adverse effect on the metal layer 130. At the same time, the thickness of the second passivation layer 140 is between 100 μm and 150 μm, and the second passivation layer 140 can simultaneously take into account the protection of the metal layer 130 and the thin and light design of the micro light emitting diode chip 100.

[0116] In some examples, before the step of forming the second passivation layer 140 on the outer surface of the metal layer 130, exposing the electrode region of each mesa structure 112 includes: removing the metal layer 130 corresponding to the electrode region of each mesa structure 112, and forming the second through-hole structure 170 in the metal layer 130. The step of forming the second passivation layer 140 on the outer surface of the metal layer 130 includes: forming the second passivation layer 140 on the outer surface of the metal layer 130, and making a part of the second passivation layer 140 disposed in the second through-hole structure 170 and connected to the first passivation layer 120. The step of exposing the electrode region of each mesa structure 112 also includes: removing the first passivation layer 120 and the second passivation layer 140 corresponding to the electrode region of each mesa structure 112, and exposing the electrode region of each mesa structure 112.

[0117] Among them, Fig.15 As shown, Fig.15 A second flow chart of the method for manufacturing the micro-LED chip 100 provided in the embodiment of the present application. The method for manufacturing the micro-LED chip 100 includes:

[0118] In S21 , an initial light emitting structure 110 including a plurality of mesa structures 112 is provided. Each mesa structure 112 includes a side wall and a top surface. At least two regions of the side wall form different inclined angles with a plane parallel to the top surface. Each mesa structure 112 also includes a first semiconductor layer 1121 .

[0119] like Figure 2 As shown, each mesa structure 112 includes a first semiconductor layer 1121, a light emitting layer 1122, a second semiconductor layer 1123 and a first electrode layer 1124 which are sequentially stacked on the first substrate 111. The mesa structure 112 can be a structure perpendicular to the first substrate 111, a single-step structure inclined to the first substrate 111, or a double-step structure inclined to the first substrate 111.

[0120] In S22 , a first passivation layer 120 is formed on the outer surface of the initial light emitting structure 110 , and a plurality of first through hole structures 160 penetrating the first passivation layer 120 along a thickness direction are formed on the first passivation layer 120 .

[0121] In this step, a first passivation layer 120 is formed on the outer surface of the initial light-emitting structure 110 facing away from the first substrate 111 by PECVD, thin film deposition process, ALD, etc., and a plurality of first through-hole structures 160 penetrating the first passivation layer 120 along the thickness direction are formed on the first passivation layer 120 by laser opening process, etching process, etc.

[0122] In S23 , a metal layer 130 is formed on the outer surface of the first passivation layer 120 , and a portion of the metal layer 130 is disposed in each first through-hole structure 160 and connected to the first semiconductor layer 1121 to achieve electrical connection.

[0123] In this step, the metal layer 130 can be formed on the outer surface of each mesa structure 112 by thermal evaporation, electron beam evaporation or magnetron sputtering.

[0124] In S24 , a second through-hole structure 170 is opened on the metal layer 130 , and the second through-hole structure 170 covers the electrode region of the mesa structure 112 .

[0125] In this step, a plurality of second through-hole structures 170 penetrating the metal layer 130 can be formed on the metal layer 130 by laser drilling process, etching process, etc. The orthographic projection area of ​​the second through-hole structure 170 on the top surface of the mesa structure 112 is larger than the area of ​​the electrode region of the mesa structure 112 (for example, the top surface region of the first electrode layer 1124), so that the orthographic projection of the second through-hole structure 170 on the top surface of the mesa structure 112 can cover the electrode region of the mesa structure 112, remove the metal layer 130 corresponding to the electrode region of each mesa structure 112, and form the second through-hole structure 170 on the metal layer 130.

[0126] In S25 , a second passivation layer 140 is formed on the outer surface of the metal layer 130 , and a portion of the second passivation layer 140 is disposed in the second through-hole structure 170 and connected to the first passivation layer 120 .

[0127] In this step, the second passivation layer 140 can be formed by PECVD, thin film deposition process, ALD, etc. The second passivation layer 140 covers the top surface and side surfaces of the metal layer 130, and at the same time, part of the second passivation layer 140 is also filled in the second through hole structure 170 and covers the side wall of the metal layer 130 located in the second through hole structure 170.

[0128] In S26 , the first passivation layer 120 and the second passivation layer 140 corresponding to the electrode region of each mesa structure 112 are removed, and the electrode region of each mesa structure 112 is exposed.

[0129] In this step, the first passivation layer 120 and the second passivation layer 140 corresponding to the electrode region of each mesa structure 112 are removed by etching process or the like. At this time, a third through-hole structure 180 penetrating the first passivation layer 120 and the second passivation layer 140 in the thickness direction is also formed on the micro-LED chip 100. In some examples, the orthographic projection area of ​​the third through-hole structure 180 on the top surface of the mesa structure 112 is smaller than the orthographic projection area of ​​the second through-hole structure 170 on the top surface of the mesa structure 112, so that the third through-hole structure 180 is located inside the second through-hole structure 170. At this time, part of the second passivation layer 140 is located in the area between the second through-hole structure 170 and the third through-hole structure 180, and part of the second passivation layer 140 can cover the side wall of the metal layer 130 located in the second through-hole structure 170. The second passivation layer 140 can prevent the metal layer 130 from being electrically connected to the solder joint structure 150 described later to cause a short circuit.

[0130] The manufacturing method of the micro-LED chip 100 of the present application first removes the metal layer 130 corresponding to the electrode region of each mesa structure 112, then forms the second passivation layer 140 on the outer surface of the second metal layer 130, and then simultaneously removes the first passivation layer 120 and the second passivation layer 140 corresponding to the electrode region of each mesa structure 112, thereby exposing the electrode region of each mesa structure 112. The solution of the present application exposes the electrode region through two removal processes. Compared with the solution of the related art that removes the second passivation layer 140, the metal layer 130 and the first passivation layer 120 respectively through three processes, the process flow of the present application is simpler, and the production efficiency of the micro-LED chip 100 is better. Moreover, the cross-sectional area of ​​the second through-hole structure 170 formed on the metal layer 130 of the present application is larger than the cross-sectional area of ​​the third through-hole structure 180 formed on the first passivation layer 120 and the second passivation layer 140. Part of the second passivation layer 140 can cover the side wall of the metal layer 130 within the second through-hole structure 170 and avoid a short circuit between the metal layer 130 and the subsequent solder joint structure 150, thereby greatly improving the reliability of the micro light-emitting diode chip 100.

[0131] Based on the above description, the present embodiment also provides a micro-LED chip 100, which can be prepared by any of the above methods for preparing the micro-LED chip 100. Please refer to the description of the above embodiment for its specific content, which will not be repeated here.

[0132] Based on the above description, the present application embodiment further provides a micro light emitting diode chip 100. Figures 1 to 15As shown, the micro-LED chip 100 includes an initial light-emitting structure 110, a first passivation layer 120 and a metal layer 130. The initial light-emitting structure 110 includes a first substrate 111 and a plurality of mesa structures 112 formed on the first substrate 111, each mesa structure 112 includes a side wall and a top surface, and at least two regions of the side wall form different tilt angles with a plane parallel to the top surface. The first passivation layer 120 is disposed on the outer surface of the initial light-emitting structure 110 away from the substrate, such as the first substrate 111. The metal layer 130 is disposed on the outer surface of the first passivation layer 120. The metal layer 130 and the first passivation layer 120 are staggered with the electrode region of each mesa structure 112, and the metal layer 130 and the first passivation layer 120 expose the electrode region of each mesa structure 112.

[0133] The micro-LED chip 100 provided by the present application forms a first passivation layer 120 on the outer surface of the initial light-emitting structure 110, and forms a metal layer 130 on the outer surface of the first passivation layer 120. On the one hand, the first passivation layer 120 separates the metal layer 130 from the mesa structure 112, which can prevent the metal layer 130 from having an adverse effect on the mesa structure 112; on the other hand, the metal layer 130 can block the light emitted by the pixel points formed by the mesa structure 112, which can prevent light crosstalk between multiple pixel points; on the other hand, at least two regions of the side wall of the mesa structure 112 form different inclined angles with the plane parallel to the top surface, and the mesa structure 112 forms a double-step structure and its side wall has at least two inclinations. When the first passivation layer 120 and the metal layer 130 cover the outer surface of the mesa structure 112, the stress generated inside the metal layer 130 can be reduced, and the metal layer 130 can be prevented from cracking or breaking under the action of stress, which causes the micro-LED chip 100 to have current and resistance abnormalities. Based on this, the present application sets a metal layer 130 on the outer surface of the mesa structure 112 with double inclined steps, and the micro light emitting diode chip 100 has better optical performance and reliability.

[0134] In some examples, each mesa structure 112 includes a first semiconductor layer 1121 and a light-emitting layer 1122, wherein the first semiconductor layer 1121 is disposed between the substrate and the light-emitting layer 1122. The sidewall of the first semiconductor layer 1121 forms a first tilt angle β with a plane parallel to the top surface, and the light-emitting layer 1122 forms a second tilt angle α with a plane parallel to the top surface. Alternatively, a portion of the sidewall of the first semiconductor layer 1121 close to the first substrate 111 forms a first tilt angle β with a plane parallel to the top surface, and another portion of the sidewall of the first semiconductor layer 1121 and the sidewall of the light-emitting layer 1122 and the film layer thereon form a second tilt angle α with a plane parallel to the top surface. The first tilt angle β is different from the second tilt angle α.

[0135] In the embodiment of the present application, the interface between the two inclined angles is located between the first semiconductor layer 1121 and the light-emitting layer 1122, or is located inside the first semiconductor layer 1121. The metal layer 130 and the first passivation layer 120 are more easily deposited on the outside of the mesa structure 112 and form a structure with a changing inclination angle. At the same time, it can also reduce the stress generated inside the metal layer 130 and improve the reliability of the micro light-emitting diode chip 100.

[0136] In some examples, the first tilt angle β is greater than the second tilt angle α. At this time, the spacing between adjacent mesa structures 112 from bottom to top of the micro-LED chip 100 of the present application is larger, which is more conducive to the deposition of the sidewall metal layer 130; at the same time, a larger mesa spacing can reduce the aspect ratio, and under the same conditions, a mesa structure 112 with a deeper mesa in the vertical direction can be etched, thereby blocking the lateral light crosstalk of the adjacent mesa structure 112 from the first semiconductor layer 1121; moreover, the mesa structure 112 with a double tilted step structure can form a double resonant cavity structure, which is more conducive to the convergence of light to the middle of the mesa structure 112, thereby improving the light extraction efficiency of the chip and having a better light crosstalk prevention effect.

[0137] In some examples, each mesa structure 112 includes a first semiconductor layer 1121, and the metal layer 130 is electrically connected to the first semiconductor layer 1121. The metal layer 130 can serve as a wire network to expand the current and reduce the voltage drop (IR drop) between multiple pixels of the micro-LED chip 100, so that the micro-LED chip 100 obtains uniform brightness and has better optical performance.

[0138] In some examples, the first passivation layer 120 is provided with a plurality of first through-hole structures 160 penetrating the first passivation layer 120 in the thickness direction; a portion of the metal layer 130 is disposed in each first through-hole structure 160, and is connected to and electrically connected to the first semiconductor layer 1121. In the embodiment of the present application, when the metal layer 130 is formed on the outer surface of the first passivation layer 120 by a process such as thermal evaporation, electron beam evaporation, or magnetron sputtering, the metal layer 130 is filled in the first through-hole structure 160 to achieve electrical connection with the first conductor layer, and the process flow of the micro light-emitting diode chip 100 is simpler.

[0139] In some examples, the first semiconductor layer 1121 of each mesa structure 112 is connected as a whole. Four first through-hole structures 160 are evenly distributed around each mesa structure 112; and / or, at least one first through-hole structure 160 is provided between two adjacent mesa structures 112. In the embodiment of the present application, the metal layer 130 can be electrically connected to the first semiconductor layer 1121 through more first through-hole structures 160, and the wire network formed by the metal layer 130 can expand the current more evenly, and the brightness of the micro light-emitting diode chip 100 is more uniform.

[0140] In some examples, the micro LED chip 100 further includes a second passivation layer 140 disposed on the surface of the metal layer 130 and exposing the electrode region of each mesa structure 112. The second passivation layer 140 can protect the metal layer 130 and improve the reliability of the micro LED chip 100.

[0141] In some examples, the metal layer 130 is provided with a second through hole structure 170 running through the metal layer 130 in the thickness direction, and a portion of the second passivation layer 140 is disposed in the second through hole structure 170 and covers the sidewall of the metal layer 130. In this embodiment, a portion of the second passivation layer 140 covers the sidewall of the metal layer 130 located in the second through hole structure 170, which can prevent the metal layer 130 from short-circuiting with the solder joint structure 150 described later, thereby greatly improving the reliability of the micro light emitting diode chip 100.

[0142] Among them, in some examples, please refer to Fig.16 , Fig.16 The sixth structural schematic diagram of the micro-LED chip 100 provided in the embodiment of the present application. The micro-LED chip 100 also includes a plurality of solder joint structures 150, which are arranged on the side of the first electrode layer 1124 away from the first substrate 111, and on the side of the second electrode layer 1125 away from the first substrate 111. The solder joint structure 150 can be made of, but not limited to, metals such as indium (In), aluminum (Al), tin (Sn), silver (Ag), gold (Au), gold-tin alloy, and nickel-gold alloy, and the solder joint structure 150 is used for bonding with the driver chip 200.

[0143] Based on the above description, the embodiment of the present application further provides a micro-LED device 10, which includes a driving chip 200 and a micro-LED chip 100, wherein the micro-LED chip 100 is a micro-LED chip 100 prepared by the method for preparing the micro-LED chip 100 described in any of the above embodiments, or a micro-LED chip 100 described in any of the above embodiments. The driving chip 200 is bonded to the micro-LED chip 100.

[0144] Based on the above description, please refer to Fig.17 , Fig.17 The present invention is a flowchart of a method for manufacturing a micro-light emitting diode device 10 provided in an embodiment of the present invention. The present invention also provides a method for manufacturing a micro-light emitting diode device 10, the method comprising:

[0145] In S31 , a driving chip 200 and a micro light emitting diode chip 100 according to any of the above embodiments are provided.

[0146] like Fig.16 As shown, the micro-LED chip 100 includes a first substrate 111, a mesa structure 112, a first passivation layer 120, a metal layer 130, a second passivation layer 140 and a solder joint structure 150. The first substrate 111 is used to carry the mesa structure 112, and the mesa structure 112 is used to emit light under the drive of the driver chip 200. The solder joint structure 150 is used to bond with the driver chip 200. It should be noted that Fig.16 It is only used to illustrate the structure of the micro-LED chip 100 without limiting its specific structure. For example, the micro-LED chip 100 also includes a micro-lens structure for improving optical performance, a quantum dot color film structure 410 for realizing color function, and other structures.

[0147] like Fig.18 As shown, Fig.18 A schematic diagram of the structure of a driver chip 200 provided in an embodiment of the present application. The driver chip 200 includes a second substrate 210, a driver circuit 220 formed on the second substrate 210, and one or more driver pads 230. The driver circuit 220 may be, but is not limited to, a CMOS circuit structure or a TFT circuit structure. The driver pad 230 may be, but is not limited to, made of metals such as In, Al, Sn, Ag, Au, gold-tin alloy, and nickel-gold alloy. One or more driver pads 230 are used to be arranged in a one-to-one correspondence with one or more solder joint structures 150 of the micro light-emitting diode chip 100 and bonded in a one-to-one correspondence. It should be noted that Fig.18 It is only used to illustrate the structure of the driving chip 200 without limiting its specific structure. For example, the driving chip 200 may further include an electrical connection portion 240 electrically connected to the circuit board.

[0148] In S32 , the micro light emitting diode chip 100 and the driving chip 200 are bonded to obtain a bonding structure 300 .

[0149] In this step, the micro-LED chip 100 and the driver chip 200 are placed in a high-precision flip-chip bonding machine, and the micro-LED chip 100 and the driver chip 200 are flip-chip mounted, and the solder joint structure 150 of the micro-LED chip 100 corresponds to the driving pad 230 of the driver chip 200. The high-precision flip-chip bonding machine automatically picks up the micro-LED chip 100 and the driver chip 200 and accurately aligns the two and realizes the bonding operation. At this time, Fig.19 As shown, Fig.19 This is a schematic diagram of the structure of the micro-LED chip 100 and the driver chip 200 after bonding provided in an embodiment of the present application. The micro-LED chip 100 and the driver chip 200 are bonded to each other through a solder joint structure 150 and a driving pad 230 to obtain a bonding structure 300.

[0150] It is understandable that in this step, the micro-LED chip 100 and the driver chip 200 can complete the bonding operation once or multiple times. For example, in this step, the micro-LED chip 100 and the driver chip 200 can be pre-bonded to form a pre-bonded structure; then, the bonding area of ​​the pre-bonded structure is filled with insulating glue; then, the pre-bonded structure is bonded for the second time and the insulating glue is cured to obtain the bonding structure 300.

[0151] In S33, the bonding area of ​​the bonding structure 300 is filled with insulating glue;

[0152] In this step, the bonding structure 300 after the bonding operation is completed is transferred to the tray of the glue dispenser, and the bonding structure 300 is aligned with the positioning groove in the tray, so that the mark point on the bonding structure 300 is aligned with the mark point of the glue dispenser, and the glue dispenser performs the bottom filling operation of the bonding area of ​​the bonding structure 300 with insulating glue, and then the bonding structure 300 is left to stand until the insulating glue flows evenly in the bonding area. Among them, by adjusting the amount of glue in the glue dispenser, the amount of glue filled into the bonding area can be adjusted.

[0153] In S34 , the bonding structure 300 filled with insulating glue is cut into pieces to obtain micro light emitting diode devices 10 .

[0154] In this step, the bonding structure 300 can be cut by a cutting process such as laser cutting, diamond knife cutting or wheel cutting to obtain a micro light emitting diode device 10 including at least one mesa structure 112 .

[0155] In the manufacturing method of the micro-LED device 10 provided in the embodiment of the present application, the driving chip 200 and the micro-LED chip 100 are formed into the micro-LED device 10 through a bonding process, an underfill glue process, a slitting process, etc. The metal layer 130 of the micro-LED device 10 can block the light emitted by the pixel points formed by the mesa structure 112 to avoid light crosstalk between multiple pixel points; at the same time, the metal layer 130 can serve as a wire network to expand the current and reduce the voltage drop between multiple pixel points of the micro-LED chip 100, so that the micro-LED device 10 obtains uniform brightness, and the micro-LED device 10 has better optical performance.

[0156] In some examples, after the step of filling the bonding area of ​​the bonding structure 300 with insulating glue, the step further includes: removing the substrate of the micro-LED chip 100 in the bonding structure 300; and setting an optical structure 400 on the surface of the micro-LED chip 100 of the bonding structure 300 away from the driver chip 200, wherein the optical structure 400 includes at least one of a microlens structure (not shown in the drawings) and a quantum dot color film structure 410. In this step, the first substrate 111 of the micro-LED chip 100 can be removed by a cutting process such as laser cutting, diamond knife cutting or wheel cutting. At this time, as shown in FIG. Fig. 20 As shown, Fig. 20 This is a schematic diagram of a first structure of a micro-light emitting diode device 10 provided in an embodiment of the present application. The micro-light emitting diode device 10 does not include a first substrate 111 .

[0157] In some examples, the present application can attach the microlens structure to the side of the micro-LED chip 100 away from the driver chip 200, and make the multiple microlens units of the microlens structure correspond to the multiple mesa structures 112 of the micro-LED chip 100. The microlens structure of the present application can refract the light and gather the light generated by the micro-LED chip 100. The microlens structure has a good focusing effect, which can improve the utilization rate of light, thereby improving the display quality and luminous brightness of the micro-LED device 10.

[0158] In some examples, the present application can also attach the quantum dot color film structure 410 to the surface of the micro-LED chip 100 away from the driver chip 200, so that the multiple quantum dot color films 412 of the quantum dot color film structure 410 are attached to the multiple mesa structures 112 of the micro-LED chip 100 in a one-to-one correspondence, for example, Fig. 20 As shown, Fig. 20 This is a schematic diagram of a second structure of the micro-LED device 10 provided in an embodiment of the present application, in which the quantum dot color film structure 410 is disposed on a surface of the micro-LED chip 100 that is away from the driver chip 200 .

[0159] It is understandable that quantum dots are semiconductor nanocrystalline materials with a diameter in the range of 2-10 nanometers (nm); quantum dot materials have the advantages of concentrated luminescence spectrum, high color purity, and the luminescence color can be easily adjusted by the size, structure or composition of the quantum dot material. Among them, quantum dot ink is processed by solution, spin coated or inkjet printed, and further solidified into a film to form a quantum dot structure. It is a new generation of luminescent materials used in solid-state lighting and full-color flat panel displays. The quantum dot color film structure 410 of the present application includes a black matrix structure 411 and a quantum dot color film 412 that are alternately arranged. The quantum dot color film structure 410 is made on a substrate such as a glass sheet by a quantum dot process. Among them, the quantum dot color film 412 can be, but is not limited to, a quantum dot color filter (Quantum dot Color Converter, referred to as QDCF) structure or a quantum dot film (Quantum dot Enhancement Film, referred to as QDEF) structure, etc. Among them, such as Fig.21 As shown, the quantum dot color film 412a can be filled with red quantum dots, the quantum dot color film 412b can be filled with green quantum dots, and the quantum dot color film 412c is not filled with quantum dots, so that the structure is a light exit hole.

[0160] The micro-light emitting diode device 10 of the present application realizes full-color display under the action of the quantum dot color film structure 410, and a black matrix structure 411 is arranged on the surrounding side of the quantum dot color film 412, which can prevent the quantum dot color film 412 from leaking light and further improve the anti-cross-light performance of the micro-light emitting diode device 10.

[0161] In some examples, such as Fig.21 As shown, the optical structure 400 further includes a filter layer 420 and a glass layer 430 disposed on a side of the quantum dot color film structure 410 away from the second substrate 210. In some examples, when the optical structure 400 can include both the microlens structure and the quantum dot color film structure 410, the quantum dot color film structure 410 can be attached to a side of the microlens structure away from the driver chip 200.

[0162] Based on the above description, the embodiment of the present application further provides a micro light emitting diode device 10 , which is manufactured by any of the above-mentioned manufacturing methods of the micro light emitting diode device 10 .

[0163] Based on the above description, an embodiment of the present application also provides a micro-LED device 10, which includes a micro-LED chip 100 and a driving chip 200, wherein the driving chip 200 is bonded to the micro-LED chip 100, and the micro-LED chip 100 includes a micro-LED chip 100 prepared by the manufacturing method of the micro-LED chip 100 in any of the aforementioned embodiments; or, includes the micro-LED chip 100 in any of the aforementioned embodiments.

[0164] Based on the above description, the present application embodiment further provides a display device 20, please refer to Fig. 22 , Fig. 22 A structural schematic diagram of a display device 20 provided in an embodiment of the present application. The display device 20 can be applied to electronic devices to realize extended reality (Extended Reality, XR) technologies such as augmented reality (AR), virtual reality (VR), and mixed reality (MR). In implementation, the display device 20 can be the projection part of an electronic device, such as a projector, a head-up display (HUD), etc.; for another example, the display device 20 can also be the display part of an electronic device, for example, the electronic device can include: any device with a display screen, such as a smart phone, a smart watch, a laptop computer, a tablet computer, a driving recorder, a navigator, a head-mounted device, etc.; for another example, the display device 20 can also be the lighting part of an electronic device, for example, the electronic device can include: any device with a lighting component, such as a vehicle, a street lamp, etc.

[0165] It is understandable that the display device 20 of the embodiment of the present application includes a micro-LED device 10, and the micro-LED device 10 includes the micro-LED device 10 of any of the above embodiments, or the micro-LED device 10 can be prepared by the manufacturing method of the micro-LED device 10 of any of the above embodiments. Therefore, the micro-LED device 10 of the display device 20 of the present application can prevent sidewall light crosstalk and improve light extraction efficiency.

[0166] It should be noted that the manufacturing method of the micro-LED chip 100, the micro-LED chip 100, the manufacturing method of the micro-LED device 10, the micro-LED device 10, and the display device 20 in the embodiments of the present application are different subjects under the same inventive concept. Features not described in detail in each embodiment can be found in the description of other embodiments.

[0167] It should be noted that the "multiple" mentioned in this application generally refers to two or more. Moreover, the directional terms mentioned in the embodiments of the present application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the embodiments of the present application, rather than to limit the embodiments of the present application. In the various drawings, units with similar structures are represented by the same figure numbers. For clarity, the various parts in the drawings are not drawn to scale. In addition, certain related parts may not be shown in the drawings.

[0168] It should be understood that, in the description of this application, terms such as "first", "second", etc. are only used to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0169] It is understandable that those skilled in the art can combine various implementations in the above embodiments under the guidance of the above embodiments to obtain technical solutions of multiple implementations. The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0170] The micro-LED chip and manufacturing method, and the micro-LED device provided by the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A method for manufacturing a micro light emitting diode chip, characterized in that: include: providing an initial light emitting architecture including a plurality of mesa structures; Each of the mesa structures comprises a side wall and a top surface, and at least two regions of the side wall form different inclined angles with a plane parallel to the top surface; forming a first passivation layer on the outer surface of the initial light-emitting structure; forming a metal layer on the outer surface of the first passivation layer; The electrode region of each mesa structure is exposed, and the micro light emitting diode chip is obtained.

2. The method for manufacturing a micro light emitting diode chip according to claim 1, characterized in that: The initial light-emitting structure further includes a substrate supporting the mesa structures, each of the mesa structures includes a first semiconductor layer and a light-emitting layer, and the first semiconductor layer is disposed between the substrate and the light-emitting layer; wherein, The side wall of the first semiconductor layer forms a first tilt angle with a plane parallel to the top surface, and the side wall of the light emitting layer forms a second tilt angle different from the first tilt angle with a plane parallel to the top surface; or A portion of the sidewall of the first semiconductor layer close to the substrate forms a first tilt angle with a plane parallel to the top surface, and another portion of the sidewall of the first semiconductor layer and the sidewall of the light-emitting layer form a second tilt angle with a plane parallel to the top surface.

3. The method for manufacturing a micro light emitting diode chip according to claim 2, characterized in that: The first inclination angle is greater than the second inclination angle.

4. The method for manufacturing a micro light emitting diode chip according to claim 1, characterized in that: Each of the mesa structures comprises a first semiconductor layer; the step of forming a first passivation layer on the outer surface of the initial light-emitting structure comprises: Forming a first passivation layer on the outer surface of the initial light-emitting structure, and forming a plurality of first through-hole structures penetrating the first passivation layer along a thickness direction on the first passivation layer; The step of forming a metal layer on the outer surface of the first passivation layer comprises: A metal layer is formed on the outer surface of the first passivation layer, and a portion of the metal layer is disposed in each of the first through-hole structures and connected to the first semiconductor layer to achieve electrical connection.

5. The method for manufacturing a micro light emitting diode chip according to claim 4, characterized in that: The step of forming a plurality of first through-hole structures penetrating the first passivation layer along the thickness direction on the first passivation layer comprises: forming a plurality of first through-hole structures penetrating the first passivation layer along the thickness direction on the first passivation layer, and making four of the first through-hole structures evenly distributed around each of the mesa structures and at least one of the first through-hole structures being located at the center of the coverage areas of the four mesa structures; and / or, A plurality of first through-hole structures penetrating the first passivation layer along a thickness direction are formed on the first passivation layer, and at least one first through-hole structure is disposed between two adjacent mesa structures.

6. The method for manufacturing a micro light emitting diode chip according to any one of claims 1 to 5, characterized in that: After the step of forming a metal layer on the outer surface of the first passivation layer, the method further includes: A second passivation layer is formed on the outer surface of the metal layer.

7. The method for manufacturing a micro light emitting diode chip according to claim 6, characterized in that: Before the step of forming a second passivation layer on the outer surface of the metal layer, exposing the electrode region of each mesa structure comprises: removing the metal layer corresponding to the electrode region of each mesa structure, and forming a second through-hole structure in the metal layer; The step of forming a second passivation layer on the outer surface of the metal layer comprises: forming a second passivation layer on the outer surface of the metal layer, and disposing a portion of the second passivation layer in the second through-hole structure and connected to the first passivation layer; The step of exposing the electrode region of each mesa structure further includes: The first passivation layer and the second passivation layer corresponding to the electrode region of each mesa structure are removed to expose the electrode region of each mesa structure.

8. A micro light emitting diode chip, characterized in that: include: An initial light-emitting structure comprises a plurality of mesa structures, each of the mesa structures comprises a side wall and a top surface, and at least two regions of the side wall form different inclined angles with a plane parallel to the top surface; A first passivation layer is disposed on the outer surface of the initial light-emitting structure; and The metal layer is disposed on the outer surface of the first passivation layer. The metal layer and the first passivation layer expose the electrode region of each mesa structure.

9. The micro light emitting diode chip according to claim 8, characterized in that: The initial light-emitting structure further includes a substrate supporting the mesa structures, each of the mesa structures includes a first semiconductor layer and a light-emitting layer, and the first semiconductor layer is disposed between the substrate and the light-emitting layer; wherein, The side wall of the first semiconductor layer forms a first tilt angle with a plane parallel to the top surface, and the side wall of the light emitting layer forms a second tilt angle different from the first tilt angle with a plane parallel to the top surface; or A portion of the sidewall of the first semiconductor layer close to the substrate forms a first tilt angle with a plane parallel to the top surface, and another portion of the sidewall of the first semiconductor layer and the sidewall of the light-emitting layer form a second tilt angle with a plane parallel to the top surface.

10. The micro light emitting diode chip according to claim 9, characterized in that: The first inclination angle is greater than the second inclination angle.

11. The micro light emitting diode chip according to claim 8, characterized in that: Each of the mesa structures includes a first semiconductor layer. The first passivation layer is provided with a plurality of first through-hole structures penetrating the first passivation layer along the thickness direction. A portion of the metal layer is arranged in each of the first through-hole structures and is connected to the first semiconductor layer to achieve electrical connection.

12. The micro light emitting diode chip according to claim 11, characterized in that: Four first through-hole structures are evenly distributed around each of the mesa structures, and at least one first through-hole structure is located at the center of the coverage area of ​​the four mesa structures; and / or, At least one first through hole structure is disposed between two adjacent mesa structures.

13. The micro light emitting diode chip according to any one of claims 8 to 12, characterized in that: The micro light emitting diode chip further comprises: The second passivation layer is disposed on the outer surface of the metal layer. The metal layer, the first passivation layer and the second passivation layer expose the electrode region of each mesa structure.

14. The micro light emitting diode chip according to claim 13, characterized in that: The metal layer is provided with a second through-hole structure penetrating through the metal layer in a thickness direction, and a portion of the second passivation layer is disposed in the second through-hole structure and covers a side wall of the metal layer.

15. A micro light emitting diode device, characterized in that: include: A micro light emitting diode chip manufactured by the method for manufacturing a micro light emitting diode chip according to any one of claims 1 to 7; Or, a micro light emitting diode chip as claimed in any one of claims 8 to 14; and A driving chip is bonded to the micro light emitting diode chip.

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