Laminated cell and preparation method thereof, photovoltaic cell module and electric equipment

Abstract

The invention discloses a laminated cell and a preparation method thereof, a photovoltaic cell assembly and electric equipment, and the laminated cell comprises a substrate cell, at least a part of the surface of the substrate cell is provided with a suede structure, and the suede structure comprises a plurality of pyramid-like structures; the filling layer is arranged at the valley bottom of the suede structure, and the material of the filling layer comprises a P-type semiconductor with light transmission; and the perovskite top cell is arranged on one side, far away from the substrate cell, of the filling layer. According to the invention, the filling layer is arranged at the valley bottom of the suede structure, so that the fluctuation degree of the suede structure can be effectively reduced, the perovskite layer is prevented from being punctured due to the fact that the top of the pyramid-like structure protrudes excessively, and the open-circuit voltage (Voc), the short-circuit current density (Jsc), the filling factor (FF) and the photoelectric conversion efficiency (PCE) of the laminated cell can be effectively improved.

Description

Technical Field

[0001] The present application belongs to the technical field of laminated batteries, and specifically relates to a laminated battery and a preparation method thereof, a photovoltaic cell assembly and electrical equipment. Background Art

[0002] Single-cell perovskite cells and their stacked cells have developed rapidly and become a research hotspot in the current photovoltaic field. Solar cells made of organic and inorganic halide perovskites have the advantages of high absorption coefficient, adjustable band gap, and simple preparation process. The efficiency of perovskite / silicon stacked solar cells has also reached a relatively high level.

[0003] The crystalline silicon bottom cells used in the preparation of tandem cells generally have a light trapping structure (i.e., velvet structure), which can effectively reduce the reflectivity and improve the utilization rate of incident light by the crystalline silicon cells. However, in the preparation process of tandem cells, this velvet structure will have a negative impact on the interface between the top / bottom cells:

[0004] ① The surface of the velvet structure is covered with pyramid-like structures, and the height of the pyramid-like tower is much greater than the thickness of the perovskite layer. Therefore, the top of the pyramid structure can easily pierce the perovskite layer, resulting in damage to the integrity of the perovskite layer.

[0005] ② There are deep grooves at the connection points of the pyramid structure. It is difficult for materials prepared by conventional spin coating to fill such grooves, resulting in the appearance of undesirable morphologies such as cavities and fractures, which affects the battery efficiency. Summary of the invention

[0006] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present application is to propose a laminated battery and a method for preparing the same, a photovoltaic battery assembly and an electrical device. The present application can effectively reduce the degree of ups and downs of the velvet structure by setting a filling layer at the bottom of the valley of the velvet structure, and avoid the perovskite layer being punctured due to the excessive protrusion of the pyramid-like top, thereby effectively improving the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and photoelectric conversion efficiency (PCE) of the laminated battery.

[0007] In one aspect of the present application, the present application provides a laminated battery. According to an embodiment of the present application, the laminated battery includes:

[0008] A substrate battery, wherein at least a portion of the surface of the substrate battery has a velvet structure, wherein the velvet structure includes a plurality of pyramid-like structures;

[0009] A filling layer, the filling layer is arranged at the valley bottom of the velvet structure, and the material of the filling layer includes a light-transmitting P-type semiconductor;

[0010] A perovskite top cell is arranged on a side of the filling layer away from the base cell.

[0011] According to the stacked battery of the embodiment of the present application, the filling layer filled in the valley of the velvet structure reduces the ups and downs of the velvet structure, avoids the top of the pyramid-like structure from being pierced through the perovskite layer due to being too prominent, or avoids defects at the connection of the pyramid-like structure, thereby effectively reducing the short circuit leakage of the battery. At the same time, the bottom area of ​​the pyramid-like structure in the velvet structure has deep gullies and tortuous structures, and traditional materials are difficult to fill these gullies and tortuous structures, resulting in the occurrence of cavities and dislocations. The present application uses a P-type semiconductor material with light transmittance to fill in these gullies, avoiding the occurrence of cavities and dislocations, and avoiding the parasitic composite loss of the battery in the cavity. In addition, the P-type semiconductor has light transmittance, so that the filling layer avoids blocking light while improving the current transmission efficiency. As a result, the open circuit voltage (Voc), short-circuit current density (Jsc), filling factor (FF) and photoelectric conversion efficiency (PCE) of the stacked battery are significantly improved.

[0012] In addition, the laminated battery according to the above embodiment of the present application may also have the following additional technical features:

[0013] In some embodiments of the present application, the thickness of the filling layer is 10% to 80% of the height of the pyramid-like structure.

[0014] In some embodiments of the present application, the thickness of the filling layer is 30% to 70% of the height of the pyramid-like structure.

[0015] In some embodiments of the present application, the material of the filling layer includes at least one of cuprous thiocyanate, titanium dioxide and nickel oxide; and / or the light transmittance of the P-type semiconductor is 50% to 100%.

[0016] In some embodiments of the present application, the average height of the pyramid-like structure is 0.2 μm to 3 μm; and / or the average width of the pyramid-like structure is 0.2 μm to 3 μm.

[0017] In some embodiments of the present application, the perovskite top cell includes a hole transport layer, and the hole transport layer is disposed on at least a portion of the surface of the filling layer away from the base cell.

[0018] In some embodiments of the present application, the material of the hole transport layer includes at least one of self-assembled monolayer materials.

[0019] In some embodiments of the present application, the self-assembled monolayer material includes at least one of [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid, [2-(9H-carbazole-9-yl)ethyl]phosphonic acid, [2-(3,6-diphenyl-9H-carbazole-9-yl)ethyl]phosphonic acid, [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid, [4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl]phosphonic acid, [4-(7H-dibenzocarbazole-7-yl)butyl]phosphonic acid, and (4-(2,7-dibromo-9,9-dimethylacridine-10(9H)-yl)butyl)phosphonic acid.

[0020] In some embodiments of the present application, the thickness of the hole transport layer does not exceed 10 nm.

[0021] In some embodiments of the present application, the perovskite top cell further includes: a perovskite layer, the perovskite layer is arranged on a side of the hole transport layer away from the substrate cell; an electron transport layer, the electron transport layer is arranged on a side of the perovskite layer away from the substrate cell; a transparent conductive layer, the transparent conductive layer is arranged on a side of the electron transport layer away from the substrate cell; and an electrode, the electrode is arranged on a side of the transparent conductive layer away from the substrate cell.

[0022] In some embodiments of the present application, the substrate cell is a crystalline silicon cell.

[0023] In some embodiments of the present application, the substrate cell is a HJT solar cell or a TOPCon solar cell.

[0024] In the second aspect of the present application, the present application proposes a method for preparing the laminated battery described in the above embodiments. According to the embodiments of the present application, the method comprises:

[0025] Providing a substrate battery, wherein at least a portion of the surface of the substrate battery has a velvet structure, wherein the velvet structure includes a plurality of pyramid-like structures;

[0026] Forming a filling layer at the valley bottom of the velvet structure, wherein the material of the filling layer includes a light-transmitting P-type semiconductor;

[0027] A perovskite top cell is formed on a side of the filling layer away from the base cell.

[0028] According to the method for preparing a stacked battery in the embodiment of the present application, by forming a filling layer at the bottom of the velvet structure, the undulation of the velvet structure is effectively reduced, and the top of the pyramid is prevented from being pierced by the perovskite layer due to excessive protrusion or defects are avoided at the connection of the pyramid structure, thereby effectively reducing the short circuit leakage of the battery. At the same time, the bottom area of ​​the pyramid-like structure in the velvet structure has deep gullies and tortuous structures, and traditional materials are difficult to fill these gullies and tortuous structures, resulting in the occurrence of cavities and dislocations. This method uses a P-type semiconductor material with light transmittance to fill these gullies, avoiding the occurrence of cavities and dislocations, and avoiding the parasitic composite loss of the battery at the cavity. In addition, the P-type semiconductor has light transmittance, so that the filling layer avoids blocking light while improving the current transmission efficiency. As a result, the open circuit voltage (Voc), short circuit current density (Jsc), filling factor (FF) and photoelectric conversion efficiency (PCE) of the stacked battery are significantly improved.

[0029] In addition, the method for preparing a stacked battery according to the above embodiment of the present application may also have the following additional technical features:

[0030] In some embodiments of the present application, a solution including a filling layer material is spin-coated on the valley bottom of the texture structure, and annealed to form the filling layer on the valley bottom of the texture structure.

[0031] In some embodiments of the present application, the spin coating rotation speed is 500 rpm to 4000 rpm, and the spin coating time is 30s to 120s.

[0032] In some embodiments of the present application, during the spin coating process, an inert gas is used to purge the spin coating surface.

[0033] In some embodiments of the present application, the concentration of the filling layer material in the solution is 1 mg / mL to 25 mg / mL, preferably 10 mg / mL to 20 mg / mL.

[0034] In some embodiments of the present application, the annealing temperature is 80° C. to 120° C., and the annealing time is 5 min to 15 min.

[0035] In some embodiments of the present application, forming a perovskite top cell on a side of the filling layer away from the substrate cell includes: forming a hole transport layer on a side of the filling layer away from the substrate cell; forming a perovskite layer on a side of the hole transport layer away from the substrate cell; forming an electron transport layer on a side of the perovskite layer away from the substrate cell; forming a transparent conductive layer on a side of the electron transport layer away from the substrate cell; and forming an electrode on a side of the transparent conductive layer away from the substrate cell.

[0036] In the third aspect of the present application, the present application proposes a photovoltaic cell assembly. According to an embodiment of the present application, the photovoltaic cell assembly has a laminated cell as described in the above embodiment, and a laminated cell prepared by the method described in the above embodiment. As a result, the laminated cell in the photovoltaic cell assembly has a high open circuit voltage (Voc), short circuit current density (Jsc), and fill factor (FF), thereby improving the photoelectric conversion efficiency (PCE) of the photovoltaic cell assembly.

[0037] In the fourth aspect of the present application, the present application proposes an electric device. According to an embodiment of the present application, the electric device has a laminated battery as described in the above embodiment, a laminated battery made by the method described in the above embodiment, or a photovoltaic cell assembly as described in the above embodiment. Therefore, the electric device has all the advantages of the laminated battery, which will not be repeated here.

[0038] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0040] Figure 1 A schematic diagram of the structure of a stacked battery according to an embodiment of the present application;

[0041] Reference numerals:

[0042] 10 - base cell, 20 - filling layer, 30 - hole transport layer, 40 - perovskite layer, 50 - electron transport layer, 60 - transparent conductive layer, 70 - electrode. DETAILED DESCRIPTION

[0043] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0044] In one aspect of the present application, the present application provides a laminated battery. According to an embodiment of the present application, referring to the attached Figure 1 The stacked battery includes: a base battery 10, at least part of the surface of the base battery 10 has a velvet structure, the velvet structure includes a plurality of pyramid-like structures; a filling layer 20, the filling layer 20 is arranged at the bottom of the velvet structure, and the material of the filling layer 20 includes a light-transmitting P-type semiconductor; a perovskite top battery, the perovskite top battery is arranged on a side of the filling layer 20 away from the base battery 10.

[0045] The beneficial effects that can be achieved by the stacked battery proposed in this application are described in detail below:

[0046] In the present application, the filling layer filled in the valley of the velvet structure reduces the ups and downs of the velvet structure, avoids the top of the pyramid-like structure from being pierced through the perovskite layer due to being too prominent, or avoids defects at the connection of the pyramid-like structure, thereby effectively reducing the short circuit leakage of the battery. At the same time, the bottom area of ​​the pyramid-like structure in the velvet structure has deep gullies and tortuous structures, and traditional materials are difficult to fill these gullies and tortuous structures, resulting in the occurrence of cavities and dislocations. The present application uses a P-type semiconductor material with light transmittance to fill in these gullies, avoiding the occurrence of cavities and dislocations, and avoiding the parasitic composite loss of the battery at the cavity. In addition, the P-type semiconductor has light transmittance, so that the filling layer avoids blocking light while improving the current transmission efficiency. Thus, the open circuit voltage (Voc), short circuit current density (Jsc), filling factor (FF) and photoelectric conversion efficiency (PCE) of the stacked battery are significantly improved.

[0047] According to some specific embodiments of the present application, Figure 1 The perovskite top cell includes a hole transport layer 30, which is disposed on at least a portion of the surface of the filling layer 20 away from the base cell 10. Therefore, the filling layer comprising the P-type semiconductor material can also play a role in hole transport, and can form a complementary relationship with the hole transport layer. Therefore, when the filling layer is deposited in the bottom area of ​​the pyramid-like structure, it is equivalent to increasing the contact area between the perovskite top cell and the base cell, promoting current transmission, and improving current transmission efficiency.

[0048] According to some further specific embodiments of the present application, the thickness of the filling layer is 10% to 80% of the height of the pyramid-like structure, for example, it can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, etc., thus, by limiting the thickness of the filling layer within the above range, the degree of ups and downs of the velvet structure is further reduced, and the top of the pyramid-like structure is further prevented from being pierced through the perovskite layer due to excessive protrusion or defects are avoided at the connection of the pyramid-like structure, thereby further reducing battery short circuit leakage. Preferably, the thickness of the filling layer is 30% to 70% of the height of the pyramid-like structure.

[0049] In the embodiments of the present application, the specific type of the above-mentioned light-transmitting P-type semiconductor material is not particularly limited, and those skilled in the art can select it according to actual needs. As some preferred embodiments, the above-mentioned light-transmitting P-type semiconductor material includes at least one of cuprous thiocyanate (CuSCN), titanium dioxide and nickel oxide. Cuprous thiocyanate (CuSCN) is more preferred because cuprous thiocyanate (CuSCN) is easier to fill in the grooves at the bottom of the pyramid-like structure, further avoiding the occurrence of cavities and dislocations. At the same time, cuprous thiocyanate (CuSCN) has a better hole transport effect, which further facilitates the formation of a complementary relationship with the hole transport layer.

[0050] According to some other specific embodiments of the present application, the transmittance of the above-mentioned P-type semiconductor is 50% to 100%, for example, it can be 50%, 60%, 70%, 80%, 90%, 100%, etc., thereby further ensuring that the P-type semiconductor has a certain light transmittance, and further enabling the filling layer to avoid blocking light while improving the current transmission efficiency.

[0051] According to some other specific embodiments of the present application, the average height of the pyramid-like structure is 0.2 μm to 3 μm, for example, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.2 μm, 1.5 μm, 1.7 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc. The average width of the pyramid-like structure is 0.2 μm to 3 μm, for example, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 1 μm, 1.2 μm, 1.5 μm, 1.7 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc.

[0052] In the embodiments of the present application, the specific thickness of the filling layer is not particularly limited, and the specific thickness depends on the average height of the pyramid-like structure.

[0053] In the embodiments of the present application, the material type of the hole transport layer is not particularly limited, and those skilled in the art can select according to actual needs. As some preferred embodiments, the material of the hole transport layer includes at least one of [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid, [2-(9H-carbazole-9-yl)ethyl]phosphonic acid, [2-(3,6-diphenyl-9H-carbazole-9-yl)ethyl]phosphonic acid, [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid, [4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl]phosphonic acid, [4-(7H-dibenzocarbazole-7-yl)butyl]phosphonic acid, and (4-(2,7-dibromo-9,9-dimethylacridine-10(9H)-yl)butyl)phosphonic acid. All of the above materials are SAM materials, and all have excellent hole transport capabilities. SAM refers to: self-assembled monolayer. The main reasons for choosing SAM as a hole transport material are: first, due to the characteristics of its single-layer thickness, SAM has almost no parasitic absorption and will not affect the optical transmittance of the battery. At the same time, due to its thin thickness, the resistance loss is also low; second, SAM molecules can achieve energy level matching with various bandgap perovskites, thereby improving hole selectivity; third, SAM molecules can effectively passivate the defects of the bottom interface of perovskites, significantly improve charge transfer, improve photoelectric conversion efficiency and maintain the long-term stability of the device; fourth, SAM molecules can achieve complete conformal coating on various rough substrate surfaces, which is conducive to the construction of stacked perovskite solar cells and the formation of uniform thin films on large-area substrates.

[0054] According to some other specific embodiments of the present application, the thickness of the hole transport layer does not exceed 10 nm, for example, it can be 0.1 nm-10 nm, for example, it can be 0.1 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc., thereby further ensuring the ability of the hole transport layer to transport holes. Preferably, the thickness of the hole transport layer does not exceed 5 nm.

[0055] According to some specific embodiments of the present application, refer to the attached Figure 1 The above-mentioned perovskite top cell also includes: a perovskite layer 40, which is arranged on the side of the hole transport layer 30 away from the base cell 10; an electron transport layer 50, which is arranged on the side of the perovskite layer 40 away from the base cell 10; a transparent conductive layer 60, which is arranged on the side of the electron transport layer 50 away from the base cell 10; and an electrode 70, which is arranged on the side of the transparent conductive layer 60 away from the base cell 10.

[0056] The working process of the perovskite part in the above-mentioned tandem battery mainly includes: the generation and separation of excitons, the transmission of free carriers, the collection of carriers and the generation of current. The specific process is as follows: In the tandem battery, sunlight is absorbed by the perovskite layer, and the perovskite layer absorbs photons to generate excitons. Since the perovskite layer has a lower Coulomb force binding, the excitons are then separated into free electrons and holes. The separated free carriers are transmitted in the perovskite layer and transmitted out through the transport layer. The electron transport layer plays the role of transmitting electrons and blocking holes, and the hole transport layer plays the role of transmitting holes and blocking electrons.

[0057] In the embodiments of the present application, the perovskite layer serves as a light absorption layer, which can convert photons into holes and electrons. The material can be selected from conventional materials in the art, which are not limited here, and can be selected according to actual needs by those skilled in the art. As some specific examples, the material of the above-mentioned perovskite layer can be an ABX3 type perovskite material, wherein the A ion can be at least one of cesium ion, rubidium ion, potassium ion, methylamine ion, formamidine ion, methylenediamine ion, benzamidine cation, and guanidine cation, the B ion can be at least one of divalent lead ion or divalent tin ion, and X can be at least one of fluoride ion, chloride ion, bromide ion, iodide ion, thiocyanate ion, tetrafluoroborate ion, hexafluorophosphate ion, formate ion, and acetate ion.

[0058] In the embodiments of the present application, the thickness of the perovskite layer is not particularly limited. As some specific embodiments, the thickness of the perovskite layer can be 100nm-10μm, for example, it can be 100nm, 200nm, 500nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc. The thickness of the perovskite layer is controlled within this range mainly to balance multiple factors such as light absorption, carrier transport, preparation process, cost-effectiveness, stability and industrial compatibility, so as to achieve high-efficiency, low-cost and high-stability perovskite stacked cells.

[0059] In the embodiments of the present application, the electron transport layer is a transport layer that can effectively transport electrons. The material of the electron transport layer can be selected from conventional materials in the art, which is not limited here. Personnel in the art can select according to actual needs. As some specific examples, the material of the electron transport layer includes at least one of fullerene and its derivatives (C60, C70, PCBM).

[0060] According to some other specific embodiments of the present application, the thickness of the electron transport layer can be 0.1nm-100nm, for example, it can be 0.1nm, 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc., thereby further ensuring the ability of the electron transport layer to transport electrons.

[0061] In the embodiments of the present application, the transparent conductive layer is used to improve the transmission efficiency of electrons, and at the same time, it can also improve the contact quality between the electron transport layer and the electrode, which is also conducive to charge transmission. As some specific examples, the material of the buffer layer includes at least one of bathocuproine (BCP) or atomic layer deposited tin dioxide (SnO2).

[0062] In the embodiment of the present application, the substrate cell may be a crystalline silicon substrate cell, and its specific type is not particularly limited, for example, it may be a HJT solar cell or a TOPCon solar cell.

[0063] Specifically, the structure of HJT solar cells is as follows:

[0064] As some specific examples, HJT solar cells usually use N-type monocrystalline silicon wafers as substrates. On the front of the N-type monocrystalline silicon wafers, very thin intrinsic amorphous silicon films (ia-Si:H) and p-type amorphous silicon films (pa-Si:H) are deposited in sequence to form a pn heterojunction. On the back of the silicon wafer, intrinsic amorphous silicon films (ia-Si:H) and n-type amorphous silicon films (na-Si:H) are deposited in sequence to form a back surface field. Then, transparent oxide conductive films, such as ITO, are deposited on both sides of the cell by PVD, which not only reduces the series resistance when collecting current, but also plays an anti-reflection role. Finally, metal electrodes are made on the TCO, and the electrodes are usually formed by screen printing technology. It should be noted that there is no need to set an electrode on the side in contact with the perovskite top cell.

[0065] Specifically, the structure of TOPCon solar cells is as follows:

[0066] As some specific examples, TOPCon solar cells usually use N-type single-crystal silicon wafers as substrates, and deposit an ultra-thin layer of silicon oxide (SiO x ), this ultra-thin silicon oxide layer forms a good interface passivation with the silicon substrate, effectively reducing surface recombination. A thin layer of N-type doped polycrystalline silicon (poly-Si) is deposited on the ultra-thin silicon oxide layer. This layer of N-type doped polycrystalline silicon and the ultra-thin silicon oxide layer together form a back passivation contact structure, providing good interface passivation for the back of the silicon wafer, while also achieving selective collection of carriers. The front structure of a TOPCon solar cell is essentially the same as that of a conventional N-type solar cell. Specifically, the front of an N-type monocrystalline silicon wafer is sequentially provided with a P-type emitter, an aluminum oxide film, and a SiN x membrane.

[0067] In the second aspect of the present application, the present application proposes a method for preparing the above-mentioned laminated battery. According to an embodiment of the present application, the method comprises the following steps:

[0068] S100: providing a substrate battery;

[0069] In this step, a base cell is provided, at least a portion of the surface of the base cell has a velvet structure, and the velvet structure includes a plurality of pyramid-like structures.

[0070] According to some specific embodiments of the present application, before forming a filling layer at the valley bottom of the suede structure, the following steps are also included:

[0071] The substrate battery is pretreated, for example, the substrate battery is cleaned by dynamic spin coating with a solvent (such as anhydrous ethanol) at a certain rotation speed, and then the cleaned substrate battery is treated with a plasma cleaning machine to increase the wettability of the substrate battery surface.

[0072] S200: A filling layer is formed at the bottom of the velvet structure;

[0073] In this step, a filling layer is formed at the bottom of the velvet structure, which can effectively reduce the undulation of the velvet structure, prevent the top of the pyramid from being too protruding, resulting in the perovskite layer being punctured, or prevent defects from being generated at the connection of the pyramid structure, thereby effectively reducing battery short circuit leakage. At the same time, the material of the filling layer includes a light-transmitting P-type semiconductor.

[0074] According to some specific embodiments of the present application, the filling layer material is first dissolved in a solvent to form a solution, and then the solution including the filling layer material is spin-coated on the valley bottom of the suede structure and annealed to form a filling layer at the valley bottom of the suede structure.

[0075] According to some further specific embodiments of the present application, during the spin coating process, an inert gas is used to purge the spin coating surface. For example, an inert gas gun (such as a nitrogen gas gun) is used to purge the spin coating surface when the spin coating lasts for 5s to 15s, so as to dry the surface solution quickly and uniformly. This process can be called gas extraction drying. Therefore, the use of the above-mentioned gas extraction drying method is further conducive to the formation of a filling layer in the gullies and tortuous structures at the bottom of the velvet structure, effectively avoiding the occurrence of cavities and dislocations, and avoiding parasitic composite losses of the battery in the cavity.

[0076] According to some other specific embodiments of the present application, the spin coating speed is 500rpm to 4000rpm, such as 500rpm, 1000rpm, 2000rpm, 3000rpm, 4000rpm, etc., and the spin coating time is 30s to 120s, such as 30s, 50s, 60s, 80s, 100s, 120s, etc. Therefore, the above-mentioned low-speed spin coating method is further conducive to the formation of a filling layer in the gullies and tortuous structures at the bottom of the velvet structure, effectively avoiding the occurrence of cavities and dislocations, and avoiding parasitic composite losses of the battery in the cavity. The inventors found that if the spin coating speed is too low, it may cause the filling layer material solution to be unable to be spin-coated, resulting in uneven spin coating; if the spin coating speed is too high, it may cause the filling layer material solution to be directly thrown away, which will also cause uneven spin coating.

[0077] According to some other specific embodiments of the present application, a filling layer is prepared between the bottom battery and the hole transport layer by low-speed spin coating + gas extraction drying, which is further beneficial to the formation of a filling layer in the grooves and tortuous structures at the bottom of the velvet structure, effectively avoiding the occurrence of cavities and dislocations, and avoiding parasitic recombination losses of the battery in the cavity.

[0078] According to some other specific embodiments of the present application, the concentration of the filling layer material in the solution is 1 mg / mL to 25 mg / mL, such as 1 mg / mL, 3 mg / mL, 5 mg / mL, 7 mg / mL, 10 mg / mL, 12 mg / mL, 15 mg / mL, 18 mg / mL, 20 mg / mL, 25 mg / mL, etc., which is further conducive to forming a filling layer at the bottom of the valley of the velvet structure, thereby effectively reducing the degree of ups and downs of the velvet structure, and avoiding the perovskite layer from being punctured due to the excessive protrusion of the pyramid-like top. Preferably 10 mg / mL to 20 mg / mL. The inventors found that if the concentration of the filling layer material in the solution is too low, it will result in the inability to form an effective and continuous filling layer; if the concentration of the filling layer material in the solution is too high, it will result in the inability of the filling layer material to be effectively dissolved in the solution, and thus effective spin coating will not be possible.

[0079] It should be noted that the thickness of the formed filling layer is determined by the concentration of the filling layer material in the solution and the spin coating speed. Specifically, the greater the concentration of the filling layer material in the solution, the greater the thickness of the formed filling layer; the greater the spin coating speed, the smaller the thickness of the formed filling layer.

[0080] According to some other specific embodiments of the present application, the annealing temperature is 80°C to 120°C (for example, it can be 80°C, 90°C, 100°C, 110°C, 120°C, etc.), and the annealing time is 5min to 15min (for example, it can be 5min, 6min, 7min, 8min, 9min, 10min, 11min, 12min, 13min, 14min, 15min, etc.).

[0081] S300: forming a perovskite top cell on a side of the filling layer away from the substrate cell;

[0082] According to some specific embodiments of the present application, a hole transport layer is formed on the side of the filling layer away from the base battery. In the embodiments of the present application, the preparation method of the hole transport layer is not particularly limited, and the conventional preparation method in the art can be used, and the person skilled in the art can choose according to actual needs. As some specific examples, the hole transport layer can be prepared by spin coating, vacuum evaporation, magnetron sputtering, atomic layer deposition, electrochemical deposition, molecular beam evaporation, solvent-soluble dip coating, blade coating, slit coating, rod coating or inkjet printing.

[0083] According to some further specific embodiments of the present application, the above method further includes:

[0084] S400: forming a perovskite layer on a side of the hole transport layer away from the substrate cell;

[0085] In the embodiments of the present application, the preparation method of the perovskite layer is not particularly limited, and conventional preparation methods in the art can be used. As some specific examples, the perovskite layer can be prepared by a wet method, a dry method, and a wet-dry two-step method. The wet method includes any one of spin coating, blade coating, slit coating, inkjet printing, screen printing, etc.; the dry method includes any one of sequential evaporation deposition and co-evaporation deposition methods; and the wet-dry two-step method includes any one of evaporation deposition and wet deposition.

[0086] S500: forming an electron transport layer on a side of the perovskite layer away from the substrate cell;

[0087] In the embodiments of the present application, the preparation method of the electron transport layer is not particularly limited, and a conventional preparation method in the art can be used, and those skilled in the art can select according to actual needs. As some specific examples, the electron transport layer can be prepared by vacuum evaporation, magnetron sputtering, atomic layer deposition, electrochemical deposition, molecular beam evaporation, solvent-dissolved dip coating, spin coating, blade coating, slit coating, rod coating or inkjet printing.

[0088] S600: forming a transparent conductive layer on a side of the electron transport layer away from the substrate battery;

[0089] In the embodiments of the present application, the preparation method of the transparent conductive layer is not particularly limited, and conventional preparation methods in the art may be used, and those skilled in the art may select according to actual needs. As some specific examples, the transparent conductive layer may be prepared by ALD deposition equipment.

[0090] S700: forming an electrode on a side of the transparent conductive layer away from the substrate cell.

[0091] In the embodiments of the present application, the preparation method of the electrode is not particularly limited, and conventional preparation methods in the art may be used, and those skilled in the art may select according to actual needs. As some specific examples, the electrode may be prepared by vacuum evaporation.

[0092] The method for preparing the above-mentioned laminated battery according to the embodiment of the present application has at least the following advantages:

[0093] (1) This method effectively reduces the ups and downs of the velvet structure by forming a filling layer at the bottom of the velvet structure, avoiding the puncture of the perovskite layer due to the excessive protrusion of the pyramid-like top or avoiding defects at the connection of the pyramid structure, thereby effectively reducing the short circuit leakage of the battery. At the same time, the bottom area of ​​the pyramid-like structure in the velvet structure has deep gullies and tortuous structures, and traditional materials are difficult to fill these gullies and tortuous structures, resulting in the occurrence of cavities and dislocations. This method uses a light-transmitting P-type semiconductor material to fill these gullies, avoiding the occurrence of cavities and dislocations, and avoiding parasitic recombination losses of the battery in the cavity. In addition, the filling layer containing the P-type semiconductor material can also play a role in hole transport, and forms a complementary relationship with the hole transport layer. Therefore, when the filling layer is deposited in the bottom area of ​​the pyramid-like structure, it is equivalent to increasing the contact area between the top battery and the bottom battery, promoting current transmission, and improving the current transmission efficiency; at the same time, the P-type semiconductor is light-transmitting, so that the filling layer can improve the current transmission efficiency while avoiding blocking light. As a result, the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and photoelectric conversion efficiency (PCE) of the stacked cell are significantly improved.

[0094] (2) This method uses low-speed spin coating + gas extraction drying to prepare a filling layer between the bottom battery and the hole transport layer, which is further conducive to the formation of a filling layer in the grooves and tortuous structures at the bottom of the velvet structure, effectively avoiding the occurrence of cavities and dislocations, and avoiding parasitic recombination losses in the battery at the cavity.

[0095] In the third aspect of the present application, the present application proposes a photovoltaic cell assembly. According to an embodiment of the present application, the photovoltaic cell assembly has a laminated cell as described in the above embodiment, and a laminated cell prepared by the method described in the above embodiment. As a result, the laminated cell in the photovoltaic cell assembly has a high open circuit voltage (Voc), short circuit current density (Jsc), and fill factor (FF), thereby improving the photoelectric conversion efficiency (PCE) of the photovoltaic cell assembly.

[0096] A photovoltaic cell assembly is a finished module with power generation output function produced by connecting multiple of the above-mentioned laminated cells in series and / or in parallel, and undergoing processes such as lamination and packaging. Specifically, a photovoltaic cell assembly includes photovoltaic glass, packaging film, laminated cells, packaging film, backplane, etc.

[0097] In the fourth aspect of the present application, the present application proposes an electric device. According to an embodiment of the present application, the electric device has the above laminated battery or the laminated battery made by the above method or the photovoltaic cell assembly as described in the above embodiment. Therefore, the electric device has all the advantages of the laminated battery, which will not be repeated here.

[0098] Specifically, electrical equipment may include lighting elements, display elements, mobile devices, etc., and may specifically include street lights, signal indicators, insect killer lamps, electric fans, electric toys, electric tools, battery vehicles, electric vehicles, ships, spacecraft, etc., among which electric toys may include fixed or mobile electric toys, for example, game consoles, electric car toys, electric ship toys and electric airplane toys, etc., and spacecraft may include airplanes, rockets, space shuttles and spacecraft, etc.; photovoltaic power generation systems may include large-scale ground photovoltaic power generation systems, distributed photovoltaic power generation and building integrated photovoltaic power generation systems, etc.

[0099] The embodiments of the present application are described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, unless otherwise explicitly stated, all reagents used in the following embodiments are commercially available or can be synthesized according to this article or known methods, and the reaction conditions not listed are also easily available to those skilled in the art.

[0100] Example 1

[0101] This embodiment provides a stacked battery, and the preparation method thereof is as follows:

[0102] 1) A HJT solar cell (without silver grid) is used as a base cell, and the front surface of the base cell has a velvet structure, which includes a plurality of pyramid-like structures, and the average height of the pyramid-like structures is about 1 μm, and the average width of the pyramid-like structures is about 1 μm. The base cell is cleaned by dynamic spin coating with anhydrous ethanol at a speed of 6000 rpm, and then the cleaned base cell is treated with a plasma cleaning machine for 8 minutes.

[0103] 2) Dissolve cuprous thiocyanate (CuSCN, whose transmittance is about 85%) in ether to form a CuSCN solution, the concentration of which is 10 mg / mL. Then spread the CuSCN solution over the battery surface, spin-coat at 1000 rpm for 60 seconds, and use a nitrogen air gun to blow dry the surface solution at a uniform speed after 10 seconds of spin coating. After the spin coating is completed, anneal at 100° C. for 10 minutes to form a CuSCN filling layer with a thickness of about 0.5 μm, that is, the thickness of the CuSCN filling layer is 50% of the average height of the pyramid-like structure.

[0104] 3) First, prepare 1 mg / mL of MEO-2PACZ (2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl, molecular formula C 16 H 18 NO5P) ethanol solution, and then the MEO-2PACZ ethanol solution was spin-coated on the side of the CuSCN filling layer away from the substrate battery at a rotation speed of 6000 rpm to form a hole transport layer with a thickness of about 1 nm.

[0105] 4) First, use MABr, CsI, PbI2, FAI, and PbBr2 to prepare Cs with a concentration of 1.7 mol / L. 0.05 (FA 0.79 MA 0.21 ) 0.95 Pb(I 0.74 Br 0.26 )3 perovskite solution, and then spin-coated the perovskite solution on the side of the hole transport layer away from the substrate battery at a speed of 3000 rpm for 45 seconds. 13 seconds before the end of spin coating, 250 μL of 1 mg / ml FPEAI (4-fluoro-phenylethylammonium iodide, molecular formula C8H 11 The ethyl acetate solution of NFI was used as the anti-solvent, and the film was annealed at 110°C for 20 min after the spin coating to form a perovskite layer with a thickness of about 500 nm.

[0106] 5) Fullerene (C60) with a thickness of about 30 nm is used as the electron transport layer by vacuum evaporation.

[0107] 6) Use ALD deposition equipment to deposit a SnO2 layer with a thickness of about 10 nm.

[0108] 7) Vacuum evaporate a silver electrode with a thickness of about 9 nm.

[0109] Example 2

[0110] The preparation method of Example 2 is substantially the same as that of Example 1, except that:

[0111] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 8 mg / mL. Then spread the CuSCN solution over the battery surface, spin-coat at 4100 rpm for 60 seconds, and use a nitrogen air gun to blow dry the surface solution at a uniform speed after 10 seconds of spin coating. After the spin coating is completed, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.05 μm, that is, the thickness of the CuSCN filling layer is 5% of the average height of the pyramid-like structure.

[0112] Example 3

[0113] The preparation method of Example 3 is substantially the same as that of Example 1, except that:

[0114] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 10 mg / mL. Then spread the CuSCN solution over the battery surface, spin-coat at 4000 rpm for 60 seconds, and use a nitrogen air gun to blow dry the surface solution at a uniform speed after 10 seconds of spin coating. After the spin coating is completed, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.1 μm, that is, the thickness of the CuSCN filling layer is 10% of the average height of the pyramid-like structure.

[0115] Example 4

[0116] The preparation method of Example 4 is substantially the same as that of Example 1, except that:

[0117] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 10 mg / mL. Then spread the CuSCN solution over the battery surface and spin-coat at 2500 rpm for 60 seconds. After 10 seconds of spin-coating, use a nitrogen air gun to blow dry the surface solution at a uniform speed. After the spin-coating is completed, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.3 μm, that is, the thickness of the CuSCN filling layer is 30% of the average height of the pyramid-like structure.

[0118] Example 5

[0119] The preparation method of Example 5 is substantially the same as that of Example 1, except that:

[0120] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 15 mg / mL. Then spread the CuSCN solution over the battery surface, spin-coat at 1000 rpm for 60 seconds, and use a nitrogen air gun to blow dry the surface solution at a uniform speed after 10 seconds of spin coating. After the spin coating is completed, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.7 μm, that is, the thickness of the CuSCN filling layer is 70% of the average height of the pyramid-like structure.

[0121] Example 6

[0122] The preparation method of Example 6 is substantially the same as that of Example 1, except that:

[0123] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 18 mg / mL. Then spread the CuSCN solution over the battery surface, spin-coat at 1000 rpm for 60 seconds, and use a nitrogen air gun to blow dry the surface solution at a uniform speed after 10 seconds of spin coating. After the spin coating is completed, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.8 μm, that is, the thickness of the CuSCN filling layer is 80% of the average height of the pyramid-like structure.

[0124] Example 7

[0125] The preparation method of Example 7 is substantially the same as that of Example 1, except that:

[0126] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 20 mg / mL. Then spread the CuSCN solution over the battery surface, spin-coat at 1000 rpm for 60 seconds, and use a nitrogen air gun to blow dry the surface solution at a uniform speed after 10 seconds of spin coating. After the spin coating is completed, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.85 μm, that is, the thickness of the CuSCN filling layer is 85% of the average height of the pyramid-like structure.

[0127] Example 8

[0128] The preparation method of Example 8 is substantially the same as that of Example 1, except that:

[0129] 1) The average height of the pyramid-like structure is about 0.2 μm.

[0130] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 10 mg / mL. Then spread the CuSCN solution over the battery surface and spin-coat at 4000 rpm for 60 seconds. After 10 seconds of spin-coating, use a nitrogen air gun to blow dry the surface solution at a uniform speed. After spin-coating, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 0.1 μm.

[0131] Example 9

[0132] The preparation method of Example 9 is substantially the same as that of Example 1, except that:

[0133] 1) The average height of the pyramid-like structures is about 2 μm.

[0134] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 20 mg / mL. Then spread the CuSCN solution over the battery surface and spin-coat at 1000 rpm for 60 seconds. After 10 seconds of spin-coating, use a nitrogen air gun to blow dry the surface solution at a uniform speed. After spin-coating, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 1 μm.

[0135] Example 10

[0136] The preparation method of Example 10 is substantially the same as that of Example 1, except that:

[0137] 1) The average height of the pyramid-like structures is about 3 μm.

[0138] 2) Dissolve cuprous thiocyanate (CuSCN) in ether to form a CuSCN solution with a concentration of 25 mg / mL. Then spread the CuSCN solution over the battery surface and spin-coat at 500 rpm for 60 seconds. After 10 seconds of spin-coating, use a nitrogen air gun to blow dry the surface solution at a uniform speed. After spin-coating, anneal at 100°C for 10 minutes to form a CuSCN filling layer with a thickness of about 1.5 μm.

[0139] Embodiment 11

[0140] The preparation method of Example 11 is substantially the same as that of Example 1, except that:

[0141] 2) Replace cuprous thiocyanate (CuSCN) with titanium dioxide (whose transmittance is about 85%).

[0142] Example 12

[0143] The preparation method of Example 12 is substantially the same as that of Example 1, except that:

[0144] 2) Replace cuprous thiocyanate (CuSCN) with nickel oxide (whose transmittance is about 80%).

[0145] Comparative Example 1

[0146] The difference between the preparation method of this comparative example and that of Example 1 is that:

[0147] Step 2) is not included, that is, a CuSCN filling layer is not formed between the base cell and the hole transport layer.

[0148] Comparative Example 2

[0149] The difference between the preparation method of this comparative example and that of Example 1 is that:

[0150] Step 3) is not included, that is, a hole transport layer is not formed between the CuSCN filling layer and the perovskite layer.

[0151] JV (current density-voltage) tests were performed on the stacked batteries of Examples 1 to 12 and Comparative Examples 1 to 2, respectively. The test results are shown in Table 1.

[0152] The JV test was conducted using a Qinglang 300W solar light source simulator under simulated amplitude modulation, and a xenon lamp-based solar simulator was used for 1.5G illumination (100mW / cm 2 ), the device effective area is 1cm 2 .

[0153] Table 1

[0154] Best Voc(V) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) PCE(%) Example 1 1.91 19.36 75.2 27.8 Example 2 1.78 18.73 62.79 20.93 Example 3 1.79 18.75 64.44 21.63 Example 4 1.89 19.11 73.25 26.45 Example 5 1.91 19.25 73.82 27.14 Example 6 1.88 19.01 71.21 25.45 Example 7 1.85 18.46 62.51 21.34 Example 8 1.91 19.32 75.3 27.78 Example 9 1.90 19.38 74.25 27.34 Example 10 1.88 19.38 69.51 25.32 Embodiment 11 1.90 19.29 74.88 27.44 Example 12 1.69 18.56 74.58 23.39 Comparative Example 1 1.77 18.72 62.54 20.72 Comparative Example 2 1.86 14.44 61.52 16.52

[0155] The EQE (external quantum efficiency) tests were performed on the stacked cells of Examples 1 to 12 and Comparative Examples 1 to 2, respectively. The test results are shown in Table 2.

[0156] The Zhuoli Hanguang solar cell quantum efficiency test system SCS-600MAX was used, with 808nm red light auxiliary irradiation. The external quantum efficiency is the ratio of the number of collected electrons to the number of incident photons, and is one of the main performance indicators of perovskite cell devices. The higher the external quantum conversion efficiency, the higher the integrated current density, indicating that the stacked cell has a higher absorption rate in the 300nm-800nm ​​band.

[0157] Table 2

[0158]

[0159] As can be seen from Table 1, compared with Comparative Example 1, the photoelectric conversion efficiency (PCE) of the tandem cells of Examples 1 to 12 is effectively improved. It can be seen that by filling the CuSCN filling layer at the bottom of the velvet structure, the undulation of the velvet structure can be effectively reduced, and the perovskite layer can be prevented from being punctured due to the excessive protrusion of the pyramid-like top, thereby effectively improving the photoelectric conversion efficiency (PCE) of the tandem cell.

[0160] As can be seen from Table 1, compared with Example 2 and Example 7, the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and photoelectric conversion efficiency (PCE) of Example 1 and Examples 3-6 are effectively improved. It can be seen that by limiting the thickness of the filling layer to 10% to 80% of the height of the pyramid-like structure, the open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF) and photoelectric conversion efficiency (PCE) of the stacked battery are excellent.

[0161] It can be seen from Table 1 that the short circuit current density (Jsc) and photoelectric conversion efficiency (PCE) of the stacked cells of Examples 1 to 12 are effectively improved compared with Comparative Example 2. It can be seen that if a hole transport layer is not provided between the CuSCN filling layer and the perovskite layer, the short circuit current density (Jsc) and photoelectric conversion efficiency (PCE) of the stacked cells are poor.

[0162] It can be seen from Table 2 that compared with Comparative Example 1, the external quantum conversion efficiency and integrated current density of the stacked cells of Examples 1 to 6 and Examples 8 to 11 are effectively improved. It can be seen that by filling the CuSCN filling layer at the bottom of the velvet structure, the ups and downs of the velvet structure can be effectively reduced, and the perovskite layer can be prevented from being punctured due to the excessive protrusion of the top of the pyramid-like structure, and the thickness of the filling layer is limited to 10% to 80% of the height of the pyramid-like structure, which can effectively improve the external quantum conversion efficiency and integrated current density of the stacked cell.

[0163] It can be seen from Table 2 that the external quantum conversion efficiency and integrated current density of Example 1 and Examples 3-6 are effectively improved compared with Example 2 and Example 7. It can be seen that by limiting the thickness of the filling layer to 10% to 80% of the height of the pyramid-like structure, the external quantum conversion efficiency and integrated current density of the stacked battery are excellent.

[0164] It can be seen from Table 2 that the external quantum conversion efficiency and integrated current density of the stacked cells of Examples 1 to 12 are effectively improved compared with Comparative Example 2. It can be seen that if a hole transport layer is not provided between the CuSCN filling layer and the perovskite layer, the external quantum conversion efficiency and integrated current density of the stacked cell are poor.

[0165] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0166] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A laminated battery, characterized in that: include: A substrate battery, wherein at least a portion of the surface of the substrate battery has a velvet structure, wherein the velvet structure includes a plurality of pyramid-like structures; A filling layer, the filling layer is arranged at the valley bottom of the velvet structure, and the material of the filling layer includes a light-transmitting P-type semiconductor; A perovskite top cell is arranged on a side of the filling layer away from the base cell.

2. The laminated battery according to claim 1, characterized in that: The thickness of the filling layer is 10% to 80% of the height of the pyramid-like structure.

3. The laminated battery according to claim 1, characterized in that: The thickness of the filling layer is 30% to 70% of the height of the pyramid-like structure.

4. The laminated battery according to claim 1, characterized in that: The material of the filling layer includes at least one of cuprous thiocyanate, titanium dioxide and nickel oxide; And / or, the light transmittance of the P-type semiconductor is 50% to 100%.

5. The laminated battery according to claim 1, characterized in that: The average height of the pyramid-like structure is 0.2 μm to 3 μm; And / or, the average width of the pyramid-like structure is 0.2 μm to 3 μm.

6. The laminated battery according to any one of claims 1 to 5, characterized in that: The perovskite top cell comprises a hole transport layer, which is disposed on at least a portion of the surface of the filling layer away from the base cell.

7. The laminated battery according to claim 6, characterized in that: The material of the hole transport layer includes at least one of self-assembled monolayer materials.

8. The laminated battery according to claim 7, characterized in that: The self-assembled monolayer material includes at least one of [2-(3,6-dimethoxy-9H-carbazole-9-yl)ethyl]phosphonic acid, [2-(9H-carbazole-9-yl)ethyl]phosphonic acid, [2-(3,6-diphenyl-9H-carbazole-9-yl)ethyl]phosphonic acid, [4-(3,6-dimethyl-9H-carbazole-9-yl)butyl]phosphonic acid, [4-(3,6-dimethoxy-9H-carbazole-9-yl)butyl]phosphonic acid, [4-(7H-dibenzocarbazole-7-yl)butyl]phosphonic acid and (4-(2,7-dibromo-9,9-dimethylacridine-10(9H)-yl)butyl)phosphonic acid.

9. The laminated battery according to claim 6, characterized in that: The thickness of the hole transport layer is no more than 10 nm.

10. The laminated battery according to any one of claims 6, characterized in that: The perovskite top cell also includes: A perovskite layer, wherein the perovskite layer is disposed on a side of the hole transport layer away from the base cell; An electron transport layer, the electron transport layer being arranged on a side of the perovskite layer away from the substrate cell; A transparent conductive layer, wherein the transparent conductive layer is disposed on a side of the electron transport layer away from the substrate cell; An electrode is disposed on a side of the transparent conductive layer away from the substrate cell.

11. The laminated battery according to any one of claims 1 to 5, characterized in that: The base cell is a crystalline silicon cell.

12. The laminated battery according to claim 11, characterized in that: The substrate cell is a HJT solar cell or a TOPCon solar cell.

13. A method for preparing a laminated battery according to any one of claims 1 to 12, characterized in that: include: Providing a substrate battery, wherein at least a portion of the surface of the substrate battery has a velvet structure, wherein the velvet structure includes a plurality of pyramid-like structures; Forming a filling layer at the valley bottom of the velvet structure, wherein the material of the filling layer includes a light-transmitting P-type semiconductor; A perovskite top cell is formed on a side of the filling layer away from the base cell.

14. The method for preparing a laminated battery according to claim 13, characterized in that: A solution including a filling layer material is spin-coated on the valley bottom of the texture structure, and annealed to form the filling layer on the valley bottom of the texture structure.

15. The method for preparing a laminated battery according to claim 14, characterized in that: The rotation speed of the spin coating is 500 rpm to 4000 rpm, and the time of the spin coating is 30 s to 120 s.

16. The method for preparing a laminated battery according to claim 14, characterized in that: During the spin coating process, an inert gas is used to purge the spin coating surface.

17. The method for preparing a laminated battery according to claim 14, characterized in that: The concentration of the filling layer material in the solution is 1 mg / mL to 25 mg / mL, preferably 10 mg / mL to 20 mg / mL.

18. The method for preparing a laminated battery according to claim 14, characterized in that: The annealing temperature is 80° C. to 120° C., and the annealing time is 5 min to 15 min.

19. The method for preparing a stacked battery according to any one of claims 13 to 18, characterized in that: The forming of a perovskite top cell on a side of the filling layer away from the base cell comprises: forming a hole transport layer on a side of the filling layer away from the base cell; forming a perovskite layer on a side of the hole transport layer away from the substrate cell; forming an electron transport layer on a side of the perovskite layer away from the substrate cell; forming a transparent conductive layer on a side of the electron transport layer away from the substrate cell; An electrode is formed on a side of the transparent conductive layer away from the base cell.

20. A photovoltaic cell assembly, characterized in that: The invention comprises the laminated battery according to any one of claims 1 to 12 or the laminated battery produced by the method according to any one of claims 13 to 19.

21. An electrical equipment, characterized in that: A laminated cell according to any one of claims 1 to 12, a laminated cell made by the method according to any one of claims 13 to 19, or a photovoltaic cell assembly according to claim 20.

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