Perovskite and crystalline silicon laminated cell assembly and photovoltaic system

Abstract

The invention discloses a perovskite and crystalline silicon laminated battery assembly and a photovoltaic system. The perovskite and crystalline silicon laminated battery assembly comprises a crystalline silicon battery layer, a perovskite battery layer, a packaging material layer and a first light-transmitting protection layer, the perovskite cell layer and the crystalline silicon cell layer are distributed in a laminated manner, the perovskite cell layer and the crystalline silicon cell layer have mutually matched rated output voltages, the perovskite cell layer and the crystalline silicon cell layer are both provided with positive and negative bus bars, and the bus bars with the same polarity have safety gaps on projection surfaces in the lamination direction; the packaging material layer is arranged between the crystalline silicon cell layer and the perovskite cell layer in a stacked manner; the crystalline silicon cell layer is covered with the first light-transmitting protection layer, the first light-transmitting protection layer is provided with a positive-polarity junction box and a negative-polarity junction box, the junction boxes are provided with parallel wires, the parallel wires are provided with two conductive paths, and the two conductive paths are conductively connected to bus bars, with the same polarity, of the crystalline silicon cell layer and the perovskite cell layer respectively. According to the invention, the number of junction boxes can be reduced, the cable cost is reduced, and the compatibility of downstream products is improved.

Description

Technical Field

[0001] The present invention relates to the field of new energy technology, and in particular to a perovskite and crystalline silicon stacked battery assembly and a photovoltaic system. Background Art

[0002] Among photovoltaic cells, four-terminal perovskite-crystalline silicon stacked cell modules have been put into mass production due to their simple process (perovskite modules and crystalline silicon modules only need to be mechanically stacked). However, since both the perovskite modules and crystalline silicon modules in the four-terminal stacked structure need to be independently connected to the junction box, the cable cost is high and the compatibility with downstream products is low. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a perovskite and crystalline silicon stacked cell assembly and a photovoltaic system, which can reduce the number of junction boxes, thereby reducing cable costs and improving the compatibility of downstream products.

[0004] On the one hand, an embodiment of the present invention provides a perovskite and crystalline silicon stacked battery assembly, comprising: Crystalline silicon cell layer; The perovskite battery layer is stacked with the crystalline silicon battery layer and has a rated output voltage that matches the crystalline silicon battery layer. The perovskite battery layer and the crystalline silicon battery layer are both provided with positive and negative busbars, and the busbars of the same polarity have a safety gap on the projection surface in the stacking direction. A packaging material layer, which is stacked between the crystalline silicon cell layer and the perovskite cell layer; A first light-transmitting protective layer covers the crystalline silicon battery layer, and a junction box with a positive polarity and a negative polarity is arranged on the first light-transmitting protective layer. The junction box is provided with parallel wires, and the parallel wires have two conductive paths. The two conductive paths are respectively conductively connected to bus bars of the same polarity of the crystalline silicon battery layer and the perovskite battery layer.

[0005] According to some embodiments of the present invention, the perovskite battery layer is divided into a plurality of battery cells based on a scribing segmentation method, and the plurality of battery cells are connected in series to obtain a rated output voltage matching the crystalline silicon battery layer.

[0006] According to some embodiments of the present invention, the two conductive paths of the parallel conductive line are coaxially arranged, and an insulating layer is arranged between the two conductive paths.

[0007] According to some embodiments of the present invention, the two conductive paths of the parallel conductive line are respectively connected to a first electrode and a second electrode, and the first electrode and the second electrode are coaxially arranged.

[0008] According to some embodiments of the present invention, the two conductive paths of the parallel wires are respectively connected to a first terminal and a second terminal that are adjacently arranged, the first terminal is provided with a first electrode, and the second terminal is provided with a second electrode.

[0009] According to some embodiments of the present invention, the positive polarity junction box is connected to a male terminal via the corresponding parallel wires, and the negative polarity junction box is connected to a female terminal via the corresponding parallel wires, and the male terminal and the female terminal are adapted to each other.

[0010] According to some embodiments of the present invention, the two conductive paths of the parallel conductive line are integrated into one.

[0011] According to some embodiments of the present invention, the first light-transmitting protective layer is provided with a first air-avoiding hole and a second air-avoiding hole arranged adjacent to each other, the first air-avoiding hole extends to the crystalline silicon battery layer, the second air-avoiding hole penetrates the packaging material layer and extends to the perovskite battery layer, the bus bar of the crystalline silicon battery layer is passed through the first air-avoiding hole, and the bus bar of the perovskite battery layer is passed through the second air-avoiding hole.

[0012] According to some embodiments of the present invention, the bus bar of the perovskite battery layer has a first segment, a second segment and a third segment, the first segment is located in the perovskite battery layer, the second segment is located in the second air avoidance hole, the third segment is located in the junction box, and the first segment and the third segment are both located on the same side of the second segment and are both connected to the second segment at an angle.

[0013] On the other hand, an embodiment of the present invention provides a photovoltaic system, including the above-mentioned perovskite and crystalline silicon stacked cell assembly.

[0014] The embodiments of the present invention have at least the following beneficial effects: Through voltage matching design and safe gap design of bus bars with the same polarity, the mutual interference between the outputs of the crystalline silicon cell layer and the perovskite cell layer can be reduced, meeting the stability and safety requirements of the output voltage. By using parallel wires to output the signals of bus bars with the same polarity in parallel, the number of junction boxes can be reduced, thereby reducing cable costs and improving the compatibility of downstream products.

[0015] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1A schematic diagram of the stacked structure of a perovskite and crystalline silicon stacked battery assembly according to an embodiment of the present invention; Figure 2 It is a schematic diagram of the structure of a perovskite and crystalline silicon stacked battery assembly according to an embodiment of the present invention; Figure 3 for Figure 2 A perspective structural diagram of a perovskite and crystalline silicon stacked cell assembly is shown (one of the junction boxes is hidden); Figure 4 for Figure 2 Schematic cross-sectional views of two examples of parallel wires of a perovskite and crystalline silicon tandem battery assembly are shown; Figure 5 for Figure 2 The middle circle shows a partial enlarged view of position A; Figure 6 for Figure 2 The middle circle shows a partial enlarged view of position B; Figure 7 It is a schematic diagram of the structure of the connection terminal of some embodiments of the present invention; Figure 8 for Figure 3 A schematic diagram of the cross-sectional structure marked CC in the figure; Fig. 9 for Figure 8 The middle circle shows a partial enlarged view of position D.

[0017] Reference numerals: Crystalline silicon battery layer 100, first positive bus bar 110, first negative bus bar 120, perovskite battery layer 200, second positive bus bar 210, second negative bus bar 220, first segment 211, second segment 212, third segment 213, packaging material layer 300, first light-transmitting protective layer 400, first air-avoiding hole 401, second air-avoiding hole 402, second light-transmitting protective layer 500, junction box 600, parallel wire 610, first passage 611, second passage 612, insulating layer 613, first electrode 614, second electrode 615, first terminal 616, second terminal 617. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0020] In the description of the present invention, "several" means one or more, "multiple" means more than two, greater than, less than, and exceeding are understood as not including the number itself, and "above", "below", and "within" are understood as including the number itself. If there is a description of "first", "second", etc., it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0021] In the description of the present invention, unless otherwise clearly defined, words such as “setting”, “installation” and “connection” should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above words in the present invention based on the specific content of the technical solution.

[0022] As a clean and renewable energy source, solar energy has received widespread attention. As a key device for converting solar energy into electrical energy, the conversion efficiency and stability of solar cells have always been a hot topic of research. Perovskite cells and crystalline silicon cells are two important technologies in the field of solar cells. Perovskite cells have the advantages of low cost, high conversion efficiency, and flexible preparation, while crystalline silicon cells have mature technology and high stability. Stacking perovskite cells with crystalline silicon cells can fully utilize the advantages of both and improve the overall performance of solar cells. However, traditional stacked cells have technical bottlenecks in current matching and process compatibility, which limits their development.

[0023] The wiring structure design of perovskite and crystalline silicon stacked cells is directly related to the efficiency, cost and compatibility of battery components with the downstream industry chain. The current mainstream technical routes are two-terminal stacking and four-terminal stacking, and there are significant differences in the wiring methods, busbar lead-out and number of junction boxes between the two.

[0024] The core of the structural design of the two-terminal stacked battery is to connect the perovskite battery and the crystalline silicon battery in series through the tunnel connection layer (composite junction) to form a single circuit output (i.e. one positive and one negative electrode). Its wiring features include: 1) Internal series connection: The perovskite cell layer and the crystalline silicon cell layer are directly connected through a tunnel junction, without the need for external wiring, and the current is transmitted inside the stack; 2) Simplified electrodes: Only one layer of transparent conductive electrode (such as TCO, Transparent Conductive Oxide) is required, avoiding the metal grid line design of traditional crystalline silicon cells and reducing light absorption loss; 3) No need for laser scribing: The electrode adopts a conductive film + gate line process and is directly integrated with the crystalline silicon substrate, eliminating the P1~P3 laser scribing steps of the perovskite single-junction cell.

[0025] In terms of busbars and junction boxes, since the output of the stacked cells at both ends is a single positive and negative pole, the busbars are usually led out from the edge of the component and only one junction box is required.

[0026] The core of the structural design of the four-terminal stacked battery is that it is mechanically stacked with independent perovskite battery layers and crystalline silicon battery layers. The circuits are independent of each other. Its wiring features include: 1) Parallel optical coupling: The perovskite cell layer and the crystalline silicon module cell layer are only optically coupled (i.e., sharing incident light), and the circuit has no direct connection, requiring an external circuit to achieve energy output; 2) Dual circuit output: The perovskite battery layer and the crystalline silicon battery layer each have a pair of positive and negative electrodes, that is, a total of four electrodes are required (two positive and two negative).

[0027] In terms of busbars and junction boxes, due to the use of mechanical stacking technology, the perovskite cell layer and the crystalline silicon cell layer do not need to consider the matching of voltage and current. They only need to independently lead out the busbars, which are arranged up and down along the stacking direction and isolated by packaging materials. Due to the need for independent wiring, the amount of cables and junction boxes used is significantly higher than the stacking at both ends, resulting in increased material costs, complex wiring, and difficulty in compatibility with downstream products.

[0028] In terms of application, the two-terminal stacked battery is compatible with the existing industrial chain and has lower costs, making it suitable for large-scale promotion, but the current matching problem needs to be solved; and the four-terminal stacked battery is easier to mass-produce in the short term due to its simple process (only mechanical stacking), but it faces the challenge of industrial chain adaptation due to the split wiring and the design of four junction boxes.

[0029] To this end, the present embodiment discloses a photovoltaic system including a perovskite and crystalline silicon stacked cell assembly, which can reduce the number of junction boxes, thereby reducing cable costs and improving the compatibility of downstream products.

[0030] Please refer to Figure 1 , Figure 2 and Figure 3The perovskite and crystalline silicon stacked cell assembly includes a crystalline silicon cell layer 100, a perovskite cell layer 200, a packaging material layer 300 (such as EVA, ethylene-vinyl acetate copolymer, Ethylene Vinyl Acetate Copolymer) and a first light-transmitting protective layer 400. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are stacked and have a rated output voltage that matches the crystalline silicon cell layer 100. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are both provided with positive and negative busbars, and the busbars of the same polarity have a safety gap on the projection surface in the stacking direction (such as Figure 3 The packaging material layer 300 is stacked between the crystalline silicon cell layer 100 and the perovskite cell layer 200; the first light-transmitting protective layer 400 covers the crystalline silicon cell layer 100, and the first light-transmitting protective layer 400 is provided with a junction box 600 of positive polarity and negative polarity, and the junction box 600 is provided with a parallel wire 610, and the parallel wire 610 has two conductive paths, and the two conductive paths are conductively connected to the bus bars of the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200 respectively.

[0031] Exemplarily, the crystalline silicon cell layer 100 is located below the stack of the perovskite cell layer 200, and the surface of the perovskite cell layer 200 is covered with a second light-transmitting protective layer 500. The crystalline silicon cell layer 100 and the perovskite cell layer 200 follow the design concept of four-terminal stacking. The crystalline silicon cell layer 100 and the perovskite cell layer 200 are processed by mechanical stacking, which has a simple process and enables the crystalline silicon cell layer 100 and the perovskite cell layer 200 to have independent positive and negative electrodes, respectively, that is, the crystalline silicon cell layer 100 is provided with a first positive bus bar 110 and a first negative bus bar 120, and the perovskite cell layer 200 is provided with a second positive bus bar 210 and a second negative bus bar 220, which can ensure the working independence of the crystalline silicon cell layer 100 and the perovskite cell layer 200 without considering the problem of current matching. Unlike conventional four-terminal stacked cells, this embodiment performs voltage matching on the crystalline silicon cell layer 100 and the perovskite cell layer 200, that is, the crystalline silicon cell layer 100 and the perovskite cell layer 200 have mutually matching rated output voltages, and adjusts the spatial layout of bus bars of the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200, that is, bus bars of the same polarity have a safety gap on the projection surface in the stacking direction, for example, the first positive bus bar 110 and the second positive bus bar 210 have a first safety gap on the projection surface in the stacking direction, and the first negative bus bar 120 and the second negative bus bar 220 have a second safety gap on the projection surface in the stacking direction. The busbars of the same polarity are connected and output through the parallel wire 610 of the same junction box 600, wherein the parallel wire 610 has two conductive paths connected in parallel, which can ensure the independence of the output of the crystalline silicon battery layer 100 and the perovskite battery layer 200, and the voltage matching design can reduce the voltage difference between the two conductive paths, thereby reducing the potential difference during parallel transmission, avoiding circulating current or power loss caused by voltage imbalance, and is conducive to improving the stability of energy transmission. In addition, the same polarity busbars are provided with a safety gap on the projection surface in the stacking direction, and the electric field coupling and leakage current interference between the conductors are weakened by physical isolation, reducing the risk of short circuit, and meeting the insulation redundancy requirements under complex conditions such as high humidity and mechanical deformation. By using a parallel conductor 610 with dual conductive paths to connect the bus bars of the crystalline silicon cell layer 100 and the perovskite cell layer 200 in parallel, the number of junction boxes 600 can be reduced, the processing technology can be simplified, and the cost of cable materials can be reduced. By integrating the same-polarity outputs of the dual cell layers through a single junction box 600, the number of connection nodes can be reduced, and the impedance mismatch and thermal failure risks caused by multiple contact points can be avoided, while improving the compatibility of downstream products (such as inverters or energy storage devices).

[0032] In order to ensure the stability of the output of the same-pole parallel connection of the dual battery layers, it is necessary to design the voltage matching of the dual battery layers. In this embodiment, the perovskite battery layer 200 is divided into multiple battery cells based on the line segmentation method, and the multiple battery cells are connected in series to obtain a rated output voltage that matches the crystalline silicon battery layer 100. It is worth mentioning that the open circuit voltage (Voc) of the perovskite battery layer 200 can be estimated using formula (1) based on parameters such as the band gap (Eg) of the perovskite material, temperature (T) and Boltzmann constant (k), where n i is the intrinsic carrier concentration, N A and N D are the acceptor and donor impurity concentrations, respectively, and q is the basic charge.

[0033] Formula (1): The related technology optimizes the open circuit voltage of the perovskite cell layer 200 by adjusting the band gap and impurity concentration of the material, thereby increasing the rated output voltage. However, the voltage matching of the two cell layers by adjusting the band gap and impurity concentration of the material has high process requirements. According to formula (1), when the temperature condition remains unchanged, the open circuit voltage of the solar cell module is determined by the material, that is, when the material is determined, the open circuit voltage remains basically unchanged. For perovskite materials, when the product area is certain, different rated output voltages can be obtained by cutting into multiple battery cells and connecting multiple battery cells in series. For example, assuming that in the design stage, the rated output voltage of the crystalline silicon battery layer 100 is first determined, such as 240V. For a product with an area of ​​1600*1200mm, the material used in the perovskite battery layer 200 is methylammonium lead iodide perovskite (MAPbI3), and the open circuit voltage is about 1.2V. The perovskite methylammonium lead iodine battery panel can be laser scribed to cut it into 200 battery cells, and the 200 battery cells are connected in series to form the perovskite battery layer 200, obtaining a rated output voltage of about 240V. It should be noted that in this embodiment, the perovskite battery layer 200 and the crystalline silicon battery layer 100 are independently output in parallel, and a safety gap is set between the bus bars of the same polarity. Therefore, the voltage matching of the perovskite battery layer 200 and the crystalline silicon battery layer 100 allows a certain range of voltage difference between the two, which is conducive to increasing the redundancy of voltage matching and reducing the design difficulty and processing difficulty of voltage matching. In this way, different rated output voltages can be formed by scribing and connecting multiple battery cells in series, reducing the voltage matching difficulty of the voltage dual battery layer. In actual processing, scribing and dividing the crystalline silicon battery layer 100 has a greater damage to the photoelectric conversion efficiency of the battery layer, while the scribing processing difficulty and damage to the photoelectric conversion efficiency of the perovskite battery layer 200 are relatively low. Therefore, in the design stage, the rated output voltage of the crystalline silicon battery layer 100 is set first, and then the perovskite battery layer 200 is scribed and divided for voltage matching. Among them, the open circuit voltage reflects the theoretical voltage output capability of the battery, while the output voltage reflects the voltage output of the battery under actual working conditions. The output voltage is always less than or equal to the open circuit voltage.

[0034] Please refer to Figure 4 The two conductive paths of the parallel conductor 610 are coaxially arranged. Figure 4(a) shows the first path 611 and the second path 612. The first path 611 is arranged radially inward of the second path 612, which can effectively reduce the self-inductance and mutual inductance of the parallel wire 610, reduce battery interference and solve battery compatibility issues. The coaxial setting can also ensure that the current is evenly distributed in the two conductive paths, avoid local overheating and current congestion, and help improve the service life and safety of the wires. An insulating layer 613 is provided between the two conductive paths, which can control the capacitance effect between the wires, improve the stability and reliability of transmission, and has good mechanical strength and anti-bending ability, which is conducive to improving the durability of the parallel wire 610. In other application examples, the two conductive paths of the parallel wire 610 can be arranged in parallel, such as Figure 4 (b) shows a first via 611 and a second via 612 , with an insulating layer 613 provided between the first via 611 and the second via 612 .

[0035] In some application examples, the two conductive paths of the parallel wire 610 are respectively connected to the first electrode 614 and the second electrode 615, and the first electrode 614 and the second electrode 615 are coaxially arranged. Figure 5 , Figure 5 In the terminal shown in FIG. 1 , the first electrode 614 is disposed on the inner side wall of the terminal, the second electrode 615 is located radially inward of the first electrode 614, and the second electrode 615 protrudes out of the terminal relative to the first electrode 614 in the axial direction. Figure 6 , Figure 6 In the terminal shown in FIG. 1 , the first electrode 614 is arranged on the outer side wall of the terminal, and the second electrode 615 ( Figure 6 Not shown, please refer to Figure 5 ) is arranged on the inner side wall of the terminal (located in the jack K), and the second electrode 615 is recessed into the terminal relative to the first electrode 614 in the axial direction. The coaxial arrangement of the first electrode 614 and the second electrode 615 can realize the parallel output of the double battery layer, reduce the number of terminals, and improve the compatibility of downstream products.

[0036] For other application examples, see Figure 7 The two conductive paths of the parallel wire 610 are respectively connected to the adjacently arranged first terminal 616 and the second terminal 617, the first terminal 616 is provided with the first electrode 614, and the second terminal 617 is provided with the second electrode 615. The first electrode 614 and the second electrode 615 are respectively provided in the adjacently arranged first terminal 616 and the second terminal 617, which can increase the safety gap between the first electrode 614 and the second electrode 615 and reduce the risk of short circuit. Among them, the two conductive paths in the parallel wire 610 can be coaxially arranged or arranged side by side.

[0037] Please refer to Figure 2 , Figure 5 and Figure 6 The positive terminal box 600 is connected to a male terminal (such as Figure 2 As shown in the middle circle position A), the negative terminal box 600 is connected to a female terminal (such as Figure 2 As shown in the circled position B), the male connector and the female connector are adapted to each other. Figure 5 The terminal shown in the figure is a male terminal. Figure 6 The wiring terminal shown in is a female terminal, and the first positive busbar 110 and the second positive busbar 210 are both connected to the male terminal through the parallel wire 610 corresponding to the positive polarity terminal box 600. Similarly, the first negative busbar 120 and the second negative busbar 220 are both connected to the female terminal through the parallel wire 610 corresponding to the negative polarity terminal box 600. It should be noted that before assembly, the terminal box 600 does not distinguish between positive and negative polarity. When the terminal box 600 is connected to the positive polarity busbar, the polarity of the terminal box 600 becomes positive; similarly, when the terminal box 600 is connected to the negative polarity busbar, the polarity of the terminal box 600 becomes negative. In application, the number of perovskite and crystalline silicon stacked battery assemblies is multiple to form a photovoltaic array, and adjacent perovskite and crystalline silicon stacked battery assemblies can be connected in series through the cooperation of the male terminal and the female terminal.

[0038] The two conductive paths of the parallel wire 610 are integrated into one, which is conducive to improving the mechanical strength of the parallel wire 610, reducing the number of wires, reducing the wiring complexity during application, and keeping the wiring neat and simple, thereby reducing the error rate and cost during the wiring process. At the same time, simplifying the wiring structure is also conducive to improving the reliability and maintainability of use, and reducing the possible fault points due to complex wiring.

[0039] Please refer to Figure 3 , Figure 8 and Fig. 9The first light-transmitting protective layer 400 is provided with a first air-avoiding hole 401 and a second air-avoiding hole 402 arranged adjacent to each other. The first air-avoiding hole 401 extends to the crystalline silicon battery layer 100, and the second air-avoiding hole 402 penetrates the packaging material layer 300 and extends to the perovskite battery layer 200. The bus bar of the crystalline silicon battery layer 100 is passed through the first air-avoiding hole 401, and the bus bar of the perovskite battery layer 200 is passed through the second air-avoiding hole 402. The bus bars of the crystalline silicon cell layer 100 and the bus bars of the perovskite cell layer 200 extend to the surface of the first light-transmitting protective layer 400 through the first air-avoiding hole 401 and the second air-avoiding hole 402 respectively to enter the junction box 600. The bus bars can be protected by the first light-transmitting protective layer 400 and the packaging material layer 300. The positions of the first air-avoiding hole 401 and the second air-avoiding hole 402 both avoid the crystalline silicon cell layer 100 and the perovskite cell layer 200, which can avoid damage or obstruction to the crystalline silicon cell layer 100 and the perovskite cell layer 200, which is beneficial to ensure the photoelectric conversion efficiency of the crystalline silicon cell layer 100 and the perovskite cell layer 200.

[0040] Please refer to Fig. 9 , the busbar of the perovskite battery layer 200 has a first segment 211, a second segment 212 and a third segment 213, the first segment 211 is located in the perovskite battery layer 200, the second segment 212 is located in the second air avoidance hole 402, and the third segment 213 is located in the junction box 600, and the first segment 211 and the third segment 213 are both located on the same side of the second segment 212 and are both connected to the second segment 212 at an angle. In this way, the first segment 211, the second segment 212 and the third segment 213 can form a 180° bending structure, increasing the spatial distance between the busbar of the perovskite battery layer 200 and the busbar of the crystalline silicon battery layer 100 in the stacking direction (such as Fig. 9 As shown in the figure marked H), safe isolation between bus bars of the same polarity is achieved, which is beneficial to reduce mutual interference between bus bars of the same polarity and reduce the risk of short circuit.

[0041] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A perovskite and crystalline silicon stacked battery assembly, characterized in that: include: Crystalline silicon cell layer (100); A perovskite cell layer (200) is stacked and distributed with the crystalline silicon cell layer (100) and has a rated output voltage that matches the crystalline silicon cell layer (100), the perovskite cell layer (200) and the crystalline silicon cell layer (100) are both provided with positive and negative polarity bus bars, and the bus bars with the same polarity have a safety gap on a projection surface in the stacking direction; An encapsulation material layer (300), stacked and arranged between the crystalline silicon cell layer (100) and the perovskite cell layer (200); A first light-transmitting protective layer (400) is covered on the crystalline silicon cell layer (100), and a junction box (600) of positive polarity and negative polarity is arranged on the first light-transmitting protective layer (400), and the junction box (600) is provided with a parallel conductor (610), and the parallel conductor (610) has two conductive paths, and the two conductive paths are respectively conductively connected to bus bars of the same polarity of the crystalline silicon cell layer (100) and the perovskite cell layer (200).

2. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The perovskite battery layer (200) is divided into a plurality of battery units based on a line segmentation method, and the plurality of battery units are connected in series to obtain a rated output voltage matching the crystalline silicon battery layer (100).

3. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The two conductive paths of the parallel conductive wire (610) are coaxially arranged, and an insulating layer (613) is arranged between the two conductive paths.

4. The perovskite and crystalline silicon stacked battery assembly according to claim 1 or 3, characterized in that: The two conductive paths of the parallel conductive wire (610) are respectively connected to a first electrode (614) and a second electrode (615), and the first electrode (614) and the second electrode (615) are coaxially arranged.

5. The perovskite and crystalline silicon stacked battery assembly according to claim 1 or 3, characterized in that: The two conductive paths of the parallel wire (610) are respectively connected to a first terminal (616) and a second terminal (617) arranged adjacent to each other; a first electrode (614) is provided in the first terminal (616) and a second electrode (615) is provided in the second terminal (617).

6. The perovskite and crystalline silicon stacked battery assembly according to claim 1 or 3, characterized in that: The positive-polarity junction box (600) is connected to a male junction box via the corresponding parallel wire (610), and the negative-polarity junction box (600) is connected to a female junction box via the corresponding parallel wire (610), and the male junction box and the female junction box are adapted to each other.

7. The perovskite and crystalline silicon stacked battery assembly according to claim 1 or 3, characterized in that: The two conductive paths of the parallel conductor (610) are integrated into one.

8. The perovskite and crystalline silicon stacked battery assembly according to claim 1, characterized in that: The first light-transmitting protective layer (400) is provided with a first air-avoiding hole (401) and a second air-avoiding hole (402) which are arranged adjacent to each other; the first air-avoiding hole (401) extends to the crystalline silicon battery layer (100); the second air-avoiding hole (402) penetrates the packaging material layer (300) and extends to the perovskite battery layer (200); the bus bar of the crystalline silicon battery layer (100) is arranged through the first air-avoiding hole (401); and the bus bar of the perovskite battery layer (200) is arranged through the second air-avoiding hole (402).

9. The perovskite and crystalline silicon stacked battery assembly according to claim 8, characterized in that: The bus bar of the perovskite battery layer (200) comprises a first segment (211), a second segment (212) and a third segment (213); the first segment (211) is located in the perovskite battery layer (200); the second segment (212) is located in the second air avoidance hole (402); the third segment (213) is located in the junction box (600); the first segment (211) and the third segment (213) are both located on the same side of the second segment (212) and are both connected to the second segment (212) at an angle.

10. A photovoltaic system, characterized in that: It comprises a perovskite and crystalline silicon stacked battery assembly as described in any one of claims 1 to 9.

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