Display panel and display device

Abstract

The invention relates to a display panel and a display device. According to the display panel, the orthographic projection of a first capacitor dielectric layer is overlapped with the orthographic projection of a first pole region of a first transistor and the orthographic projection of a second pole region of the first transistor, and the orthographic projection of a second capacitor dielectric layer is at least partially overlapped with the orthographic projection of the second pole region of the first transistor and is not overlapped with the orthographic projection of the first pole region of the first transistor; the orthographic projection of the first metal structure is at least partially overlapped with the orthographic projection of the first pole region of the first transistor, and the orthographic projection of the second metal structure is at least partially overlapped with the orthographic projection of the second pole region of the first transistor. Therefore, in the process of initializing the gate structure of the driving transistor by adopting the initialization signal, the initialization of the gate structure of the driving transistor is sufficient enough, so that the threshold voltage offset of the driving transistor is improved, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] An active matrix organic light emitting diode (AMOLED) display device is a self-luminous display device, which generally includes a plurality of organic light emitting diodes and a plurality of pixel circuits. The pixel circuits are used to control the corresponding organic light emitting diodes to emit light.

[0003] The pixel circuit usually includes a plurality of thin film transistors (TFTs), and among the plurality of thin film transistors, the thin film transistor used to generate a driving current to drive the organic light emitting diode to emit light is called a driving transistor. In the related art, when the display device is displayed at a low frequency, due to the long frame time, the threshold voltage of the driving transistor is prone to shift, resulting in poor display effects such as afterimages and low-frequency flickering in the display device. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device that can improve the threshold voltage shift of the driving transistor and thus enhance the display effect in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a display panel, the display panel comprising:

[0006] substrate;

[0007] A first transistor, located on one side of the substrate;

[0008] An active layer, located on one side of the substrate, the active layer comprising a first polar region and a second polar region of the first transistor;

[0009] A gate insulating layer, located on a side of the active layer away from the substrate;

[0010] A first metal layer, located on a side of the gate insulating layer away from the active layer, the first metal layer comprising a gate structure of the first transistor;

[0011] A first capacitor dielectric layer is located on a side of the first metal layer away from the gate insulating layer;

[0012] a second capacitor dielectric layer, located on a side of the first capacitor dielectric layer away from the first metal layer;

[0013] wherein the orthographic projection of the first capacitor dielectric layer in the first direction overlaps with the orthographic projections of the first electrode region of the first transistor and the second electrode region of the first transistor in the first direction, and the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction and does not overlap with the orthographic projection of the first electrode region of the first transistor in the first direction, wherein the first direction is a direction perpendicular to the surface where the display panel is located;

[0014] The second metal layer includes a first metal structure and a second metal structure, wherein the first metal structure is located on a side of the first capacitor dielectric layer away from the first metal layer, and the second metal structure is located on a side of the second capacitor dielectric layer away from the first capacitor dielectric layer, wherein the orthographic projection of the first metal structure in the first direction at least partially overlaps with the orthographic projection of the first electrode region of the first transistor in the first direction, and the orthographic projection of the second metal structure in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction.

[0015] Optionally, an overlapping area of ​​the first metal structure with the first electrode region of the first transistor in the first direction is greater than a first preset area, and an overlapping area of ​​the second metal structure with the second electrode region of the first transistor in the first direction is less than a second preset area, wherein the first preset area is greater than the second preset area;

[0016] Optionally, the second metal layer further includes a data signal line for transmitting a data signal and an initialization signal line for transmitting an initialization signal, and in a second direction, the first metal structure is located between the data signal line and the gate structure of the first transistor, and the second metal structure is located between the gate structure of the first transistor and the initialization signal line, wherein the second direction is a direction parallel to the surface where the display panel is located;

[0017] Optionally, the first metal structure and the second metal structure are power signal lines for transmitting power signals.

[0018] Optionally, the first metal layer further includes a scan line for transmitting a scan signal, and the second metal layer further includes a gate connection metal, wherein the gate connection metal is connected to the gate structure of the first transistor;

[0019] The orthographic projections of the first capacitor dielectric layer and the second capacitor dielectric layer in the first direction at least partially overlap with the orthographic projections of the scan line and the gate connection metal in the first direction.

[0020] Optionally, the first metal layer further includes a scan line for transmitting a scan signal, and the second metal layer further includes a gate connection metal, wherein the gate connection metal is used to connect the gate structure of the first transistor;

[0021] The gate connection metal has no overlap with the orthographic projection of the scan line in the first direction;

[0022] Optionally, the display panel also includes an anode layer located on a side of the second metal layer away from the substrate, the anode layer includes a jumper trace, and the jumper trace is electrically connected to the gate connection metal located on both sides of the jumper area, respectively, wherein the orthographic projection of the jumper area in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

[0023] Optionally, the display panel further comprises a first shielding structure, the first shielding structure is insulated from the gate connection metal, and an orthographic projection of the first shielding structure in the first direction at least partially overlaps with an orthographic projection of the scan line in the first direction;

[0024] Optionally, in the first direction, the first shielding structure is located in the second capacitor dielectric layer between the scan line and the gate connection metal;

[0025] Optionally, the first shielding structure is connected to the power signal.

[0026] Optionally, the second metal layer further includes a second shielding structure, the second shielding structure is insulated from the gate connection metal, and an orthographic projection of the second shielding structure in the first direction at least partially overlaps with an orthographic projection of the scan line in the first direction;

[0027] Optionally, in the first direction, the second shielding structure is located between the scan line and the jumper line;

[0028] Optionally, the second shielding structure is connected to the power signal.

[0029] Optionally, the first metal layer further includes a first capacitor plate, and the second metal layer further includes a second capacitor plate;

[0030] The orthographic projection of the first capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the first capacitor plate in the first direction, the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of part of the first capacitor plate in the first direction, and the orthographic projection of the second capacitor plate in the first direction at least partially overlaps with the orthographic projection of the remaining first capacitor plate in the first direction.

[0031] Optionally, the first capacitor dielectric layer includes an inorganic capacitor dielectric layer; the second capacitor dielectric layer includes an organic capacitor dielectric layer;

[0032] Optionally, the thickness of the first capacitor dielectric layer is smaller than the thickness of the second capacitor dielectric layer.

[0033] Optionally, the first electrode region is a source region of the first transistor, and the second electrode region is a drain region of the first transistor;

[0034] Optionally, the first transistor is a driving transistor for driving the light-emitting device to emit light.

[0035] In a second aspect, the present application further provides a display device, comprising a display panel as provided in any of the above embodiments.

[0036] The display panel and the display device include a stacked substrate, an active layer, a gate insulating layer, a first metal layer, a first capacitor dielectric layer, a second capacitor dielectric layer, and a second metal layer; the active layer includes a first electrode region and a second electrode region of a first transistor, the gate insulating layer is located between the active layer and the first metal layer, and the first metal layer includes a gate structure of the first transistor; the first transistor is, for example, a driving transistor;

[0037] A first capacitor dielectric layer is located on a side of the first metal layer away from the gate insulating layer; a second capacitor dielectric layer is located on a side of the first capacitor dielectric layer away from the first metal layer; wherein an orthographic projection of the first capacitor dielectric layer in the first direction overlaps with an orthographic projection of a first electrode region of the first transistor and an orthographic projection of a second electrode region of the first transistor in the first direction, and an orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with an orthographic projection of the second electrode region of the first transistor in the first direction and has no overlap with an orthographic projection of the first electrode region of the first transistor in the first direction, wherein the first direction is a direction perpendicular to a surface where the display panel is located;

[0038] A second metal layer, comprising a first metal structure and a second metal structure, wherein the first metal structure is located on a side of the first capacitor dielectric layer away from the first metal layer, and the second metal structure is located on a side of the second capacitor dielectric layer away from the first capacitor dielectric layer, wherein an orthographic projection of the first metal structure in the first direction at least partially overlaps with an orthographic projection of the first electrode region of the first transistor in the first direction, and an orthographic projection of the second metal structure in the first direction at least partially overlaps with an orthographic projection of the second electrode region of the first transistor in the first direction;

[0039] In this way, in the first direction, the first metal structure, the first capacitor dielectric layer and the first electrode region can constitute the source capacitor of the source of the first transistor, and the second metal structure, the second capacitor dielectric layer, the first capacitor dielectric layer and the second electrode region can constitute the drain capacitor of the drain of the first transistor. Since the capacitor dielectric layer in the source capacitor is the first capacitor dielectric layer, that is, a single layer, and the capacitor dielectric layer in the drain capacitor is the first capacitor dielectric layer and the second capacitor dielectric layer, that is, a double layer, the source capacitor is large and can store a large amount of positive charge, while the drain capacitor is small and can only store a small amount of negative charge. This makes it possible that in the process of initializing the gate structure of the first transistor using an initialization signal, the gate-source voltage difference and the gate-drain voltage difference of the first transistor are both large, so that the initialization of the gate structure of the first transistor is sufficient, and the initialization of the gate structure of the first transistor is sufficient to achieve calibration of the threshold voltage of the first transistor. The embodiment of the present application improves the threshold voltage offset of the first transistor, thereby avoiding the afterimage, low-frequency flicker and other phenomena that occur in the display device during low-frequency display, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic top view of a display panel in one embodiment;

[0042] Figure 2 for Figure 1 A schematic diagram of the structure of a pixel circuit in a part of FIG.

[0043] Figure 3 for Figure 2 One of the partial layout diagrams of the pixel circuit;

[0044] Figure 4 for Figure 3 A partial cross-sectional schematic diagram of ;

[0045] Figure 5 for Figure 2 The second schematic diagram of the local layout of the pixel circuit;

[0046] Figure 6 for Figure 5 A partial cross-sectional schematic diagram of ;

[0047] Figure 7 for Figure 2 The third schematic diagram of the local layout of the pixel circuit;

[0048] Figure 8 for Figure 7 One of the partial cross-sectional schematic diagrams;

[0049] Fig. 9 for Figure 7 The second schematic diagram of the partial section.

[0050] Description of reference numerals:

[0051] 100 - display panel, 110 - substrate, 120 - active layer, 130 - gate insulating layer, 140 - first metal layer, 150 - first capacitor dielectric layer, 160 - second capacitor dielectric layer, 170 - second metal layer, 180 - planarization layer, 190 - anode layer, 121 - source region, 122 - drain region, 141 - gate structure, 142 - scanning line, 171 - first shielding structure, 172 - second shielding structure, 191 - jumper wiring. DETAILED DESCRIPTION

[0052] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0054] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0056] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0057] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0058] As described in the background technology, in the related technology, when the display device is displaying at a low frequency, due to the long frame time, the threshold voltage offset problem of the driving transistor is prone to occur, resulting in the display device to have afterimages, low-frequency flickering and other phenomena. The inventors have found that the reason for this problem is that when the display device is displaying at a low frequency, the driving transistor will gradually shift its threshold voltage positively or negatively due to the hot carrier effect within the low-frequency long frame time, thereby causing the display device to have afterimages, low-frequency flickering and other phenomena.

[0059] Based on the above reasons, the present invention provides a solution that can improve the threshold voltage shift of the driving transistor and thus improve the display effect.

[0060] In an exemplary embodiment, referring to Figure 1, a display panel 100 is provided. Exemplarily, the display panel 100 may be an OLED display panel. The display panel 100 includes a plurality of organic light emitting diodes and a plurality of pixel circuits. Exemplarily, referring to Figure 2 The pixel circuit includes a driving transistor T1, a storage capacitor C ST , a data writing transistor T2, a threshold compensation transistor T3, a first initialization transistor T4, a first light emission control transistor T5, a second light emission control transistor T6 and a second initialization transistor T7.

[0061] At least one of the driving transistor T1 , the data writing transistor T2 , the threshold compensation transistor T3 , the first initialization transistor T4 , the first light emission control transistor T5 , the second light emission control transistor T6 and the second initialization transistor T7 may be an N-type thin film transistor or a P-type thin film transistor.

[0062] The gate of the first initialization transistor T4 is connected to the first scan line SCAN1 , and the first initialization transistor T4 is used to initialize the gate of the driving transistor T1 according to the initialization signal VREF.

[0063] The gate of the data writing transistor T2 is connected to the second scan line SCAN2, and the data writing transistor T2 is used to write the data signal VDATA into the gate of the driving transistor T1; the gate of the threshold compensation transistor T3 is connected to the second scan line SCAN2, and the threshold compensation transistor T3 is used to compensate the threshold voltage VTH of the driving transistor T1; the storage capacitor C ST The driving transistor T1 is used to store the gate voltage of the driving transistor T1; the driving transistor T1 is used to generate a driving current I according to the gate voltage of the driving transistor T1. DS , driving current I DS It is used to drive a light-emitting device, where the light-emitting device is, for example, an organic light-emitting diode D to emit light.

[0064] The gate of the second initialization transistor T7 is connected to the third scan line SCAN3, and the second initialization transistor T7 is used to initialize the anode ANODE of the organic light emitting diode D according to the initialization signal VREF; the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 are both connected to the light emitting control signal line EM, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are used to control the light emitting of the organic light emitting diode D.

[0065] In the embodiment of the present application, the display panel 100 includes a substrate 110 and a first transistor, and the first transistor is located on one side of the substrate 110. The first transistor includes a first electrode region, a second electrode region and a gate structure. Optionally, the first electrode region of the first transistor is a source region of the first transistor, and the second electrode region of the first transistor is a drain region of the second transistor. Exemplarily, the first transistor is a driving transistor T1.

[0066] The following uses the example that the first transistor is a driving transistor T1, the first electrode region of the first transistor is a source region of the driving transistor T1, and the second electrode region of the first transistor is a drain region of the driving transistor T1 to illustrate the technical solution of the present invention, but it is not intended to limit the technical solution of the present invention. It should be understood that the first transistor in the present invention can be a transistor with other functions, the first electrode region of the first transistor can also be a drain region or other electrode region, and the second electrode region of the first transistor can also be a source region or other electrode region, all of which fall within the protection scope of the present invention.

[0067] In the layout structure, combined Figure 3 and Figure 4 , the display panel 100 includes a substrate 110, an active layer 120, a gate insulating layer 130, a first metal layer 140, a first capacitor dielectric layer 150, a second capacitor dielectric layer 160, and a second metal layer 170. In the drawings of the specification of the embodiment of the present application, the area encircled by the dotted line of the "line-dot-line" type in the layout schematic diagram is the area where the first capacitor dielectric layer 150 is dug out, and the area encircled by the dotted line of the "line-dot-dot-line" type is the area where the second capacitor dielectric layer 160 is dug out.

[0068] The substrate 110 mainly plays a supporting role. The substrate 110 can be a hard substrate made of materials such as glass or plastic, or a flexible substrate made of materials such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP).

[0069] The active layer 120 is located on one side of the substrate 110, and the active layer 120 includes a source region 121 and a drain region 122. That is, the active layer 120 may include a source region 121 and a drain region 122 formed by doping N-type impurity ions or P-type impurity ions, and a channel region formed between the source region 121 and the drain region 122. The material of the active layer 120 includes, but is not limited to, amorphous silicon material, amorphous oxide semiconductor, polycrystalline silicon material, or metal oxide material. In this embodiment, the active layer 120 may be the active layer 120 of the driving transistor T1.

[0070] The gate insulating layer 130 is located on a side of the active layer 120 away from the substrate 110 . The material of the gate insulating layer 130 may be, but is not limited to, one or a combination of silicon nitride, silicon oxynitride and silicon oxide.

[0071] The first metal layer 140 is located on a side of the gate insulating layer 130 away from the active layer 120, and the first metal layer 140 includes a gate structure 141. The first metal layer 140 can be understood as one of the multiple metal layers between the substrate 110 and the organic light emitting diode D in the display panel 100. The orthographic projection of the gate structure 141 in the first direction can cover the channel region, that is, the gate insulating layer 130 is provided between the channel region and the gate structure 141, wherein the first direction is a direction perpendicular to the surface where the display panel 100 is located. In this embodiment, the gate structure 141 can be the gate structure 141 of the driving transistor T1.

[0072] The first capacitor dielectric layer 150 is located on a side of the first metal layer 140 away from the gate insulating layer 130 , and an orthographic projection of the first capacitor dielectric layer 150 in the first direction overlaps with an orthographic projection of the source region 121 and the drain region 122 in the first direction.

[0073] The second capacitor dielectric layer 160 is located on a side of the first capacitor dielectric layer 150 away from the first metal layer 140 . The orthographic projection of the second capacitor dielectric layer 160 in the first direction at least partially overlaps with the orthographic projection of the drain region 122 in the first direction and does not overlap with the orthographic projection of the source region 121 in the first direction.

[0074] The first capacitor dielectric layer 150 can be understood as an insulating medium layer between the substrate 110 and the organic light emitting diode D in the display panel 100 , and the second capacitor dielectric layer 160 can be understood as an interlayer insulating layer between the substrate 110 and the organic light emitting diode D.

[0075] The second metal layer 170 includes a first metal structure and a second metal structure; the first metal structure is located on a side of the first capacitor dielectric layer 150 away from the first metal layer 140, and the orthographic projection of the first metal structure in the first direction at least partially overlaps with the orthographic projection of the source region 121 in the first direction; the second metal structure is located on a side of the second capacitor dielectric layer 160 away from the first capacitor dielectric layer 150, and the orthographic projection of the second metal structure in the first direction at least partially overlaps with the orthographic projection of the drain region 122 in the first direction and covers the drain region 122. The second metal layer 170 can be understood as one of the multiple metal layers between the substrate 110 and the organic light emitting diode D in the display panel 100, except for the first metal layer 140.

[0076] In the embodiment of the present application, in a direction perpendicular to the plane where the display panel 100 is located, the first metal structure, the first capacitor dielectric layer 150 and the source region 121 constitute the source capacitor C of the source of the driving transistor T1. SOURCE , and the second metal structure, the second capacitor dielectric layer 160, the first capacitor dielectric layer 150 and the drain region 122 constitute the drain capacitor C of the drain of the driving transistor T1 DRAIN , due to the source capacitance C SOURCE The capacitor dielectric layer in the capacitor is the first capacitor dielectric layer 150, that is, a single layer, the capacitor dielectric layer thickness is small, and the drain capacitor C DRAIN The capacitor dielectric layer in the capacitor is the first capacitor dielectric layer 150 and the second capacitor dielectric layer 160, that is, a double layer, and the capacitor dielectric layer thickness is large. Therefore, according to the capacitance C=εS / d=εS / 4πkd (ε is the dielectric constant, S is the facing area between the two electrode plates, k is the electrostatic force constant, and d is the thickness of the capacitor dielectric layer), it can be known that the source capacitance C SOURCE large, capable of storing a large amount of positive charge, while the drain capacitance C DRAIN The gate structure 141 of the driving transistor T1 is small and can only store a small amount of negative charge. This makes the gate-source voltage difference |VGS| and the gate-drain voltage difference |VGD| of the driving transistor T1 large during the process of initializing the gate structure 141 of the driving transistor T1 using the initialization signal VREF, so that the initialization of the gate structure 141 of the driving transistor T1 is sufficient. The initialization of the gate structure 141 of the driving transistor T1 is sufficient to achieve calibration of the threshold voltage VTH of the driving transistor T1. The embodiment of the present application improves the threshold voltage VTH offset of the driving transistor T1, thereby avoiding the phenomenon of afterimage, low-frequency flicker and the like that occurs when the display device displays at a low frequency, thereby improving the display effect.

[0077] In an exemplary embodiment, continue to combine Figure 3 and Figure 4 , an overlapping area of ​​the first metal structure with the source region 121 in the first direction is greater than a first preset area, and an overlapping area of ​​the second metal structure with the drain region 122 in the first direction is less than a second preset area, wherein the first preset area is greater than the second preset area.

[0078] In this embodiment, the source capacitor C SOURCE The facing area between the two electrode plates is greater than the first preset area, and the drain capacitor C DRAIN The facing area between the two electrode plates is smaller than the second preset area, and the first preset area is larger than the second preset area. According to the capacitance C=εS / d=εS / 4πkd (ε is the dielectric constant, S is the facing area between the two electrode plates, k is the electrostatic force constant, and d is the thickness of the capacitor dielectric layer), it can be known that the source capacitance C SOURCE large, can store a large amount of positive charge, and can further make the drain capacitance CDRAIN The gate structure 141 of the driving transistor T1 is sufficiently initialized, and the initialization of the gate structure 141 of the driving transistor T1 is sufficient to achieve calibration of the threshold voltage VTH of the driving transistor T1. The embodiment of the present application improves the threshold voltage VTH offset of the driving transistor T1, thereby avoiding the phenomenon of afterimage, low-frequency flicker and the like during low-frequency display of the display device, and improving the display effect.

[0079] In an exemplary embodiment, by setting the source capacitance C SOURCE The capacitor dielectric layer in the capacitor is the first capacitor dielectric layer 150, that is, a single layer, the capacitor dielectric layer thickness d is small, and the source capacitor C SOURCE The facing area S between the two electrode plates is greater than the first preset area, and the drain capacitor C DRAIN The capacitor dielectric layer in the capacitor is a first capacitor dielectric layer 150 and a second capacitor dielectric layer 160, that is, a double layer, the capacitor dielectric layer thickness d is large, and the drain capacitor C DRAIN The facing area S between the two electrode plates is smaller than the second preset area, so the source capacitance C SOURCE is large enough to store a large amount of positive charge, while the drain capacitance C DRAIN It is small enough to store only a small amount of negative charge, so that in the process of initializing the gate structure 141 of the driving transistor T1 using the initialization signal VREF, the gate-source voltage difference |VGS| and the gate-drain voltage difference |VGD| of the driving transistor T1 are large enough, so that the initialization of the gate structure 141 of the driving transistor T1 is sufficient, and the initialization of the gate structure 141 of the driving transistor T1 is sufficient to achieve calibration of the threshold voltage VTH of the driving transistor T1. The embodiment of the present application improves the threshold voltage VTH offset of the driving transistor T1, thereby avoiding the phenomenon of afterimage, low-frequency flicker and the like that occurs when the display device displays at a low frequency, thereby improving the display effect.

[0080] In an exemplary embodiment, continue to combine Figure 3 and Figure 4 The second metal layer 170 also includes a data signal line for transmitting a data signal and an initialization signal line for transmitting an initialization signal. In the second direction, the first metal structure is located between the data signal line and the gate structure 141, and the second metal structure is located between the gate structure 141 and the initialization signal line, wherein the second direction is a direction parallel to the surface where the display panel 100 is located.

[0081] In this embodiment, the data signal line is used to transmit the data signal VDATA to the data writing transistor T2, and the initialization signal line is used to transmit the initialization signal VREF to the first initialization transistor T4 and the second initialization transistor T7. The second metal layer 170 can be used to form the data signal line, the initialization signal line, the first metal structure and the second metal structure. In other words, the data signal line, the initialization signal line, the first metal structure and the second metal structure are located in the same metal layer, and the first metal structure and the second metal structure are formed by a part of the structure in the second metal layer 170, so that the first metal structure and the source region 121 constitute the source capacitance C of the source of the driving transistor T1. SOURCE The second metal structure and the drain region 122 constitute the drain capacitance C of the drain of the driving transistor T1. DRAIN Two electrode plates.

[0082] In an exemplary embodiment, the first metal structure and the second metal structure are power signal lines for transmitting power signals.

[0083] In this embodiment, the power signal line is used to transmit the power signal ELVDD to the pixel circuit, for example, to transmit the first power signal ELVDD to the first light emitting control transistor T5, and the cathode CATHODE of the organic light emitting diode D receives the second power signal ELVSS, thereby providing a power signal for the light emission of the organic light emitting diode D. The first metal structure and the second metal structure may both be partial structures of the power signal line. In other words, the partial structure of the power signal line in the second metal layer 170 and the source region 121 of the driving transistor T1 and the drain region 122 of the driving transistor T1 respectively form a source capacitance C of the source of the driving transistor T1. SOURCE and the drain capacitance C of the drain of the driving transistor T1 DRAIN .

[0084] In an exemplary embodiment, in combination Figure 5 , Figure 6 and Figure 8 The first metal layer 140 also includes a scanning line 142 for transmitting a scanning signal, and the second metal layer 170 also includes a gate connection metal, wherein the gate connection metal is connected to the gate structure 141; the orthographic projection of the first capacitor dielectric layer 150 and the second capacitor dielectric layer 160 in the first direction at least partially overlaps with the orthographic projection of the scanning line 142 and the gate connection metal in the first direction.

[0085] The gate connection metal is a metal used to lead out the gate structure 141, and can form the gate of the driving transistor T1 together with the gate structure 141. According to the layout structure of the pixel circuit, the scan line 142 can be a second scan line SCAN2 used to connect the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3.

[0086] In the related art, the gate connection metal of the driving transistor T1 overlaps with the second scan line SCAN2 in the first direction, so there is a parasitic capacitance C between the gate connection metal of the driving transistor T1 and the second scan line SCAN2. STR , when the second scan line SCAN2 jumps from high level VGL to low level VGH or from low level VGH to high level VGL, the coupling effect of the second scan line SCAN2 on the gate connection metal of the driving transistor T1 weakens the compensation ability of the pixel circuit to the gate of the driving transistor T1, causing the potential of the gate of the driving transistor T1 to deviate from the ideal value and become VDATA-|VTH|+V SWITCH ERROE , thus reducing the display effect, where V SWITCH ERROE With parasitic capacitance C STR , and the potential changes of the second scan line SCAN2 are positively correlated, V SWITCH ERROE With storage capacitor C ST Negative correlation.

[0087] Based on the above reasons, in this embodiment, the capacitor dielectric layer between the second scan line SCAN2 and the gate connection metal of the driving transistor T1 is set to the first capacitor dielectric layer 150 and the second capacitor dielectric layer 160, that is, a double layer with a large capacitor dielectric layer thickness. According to the capacitance C=εS / d=εS / 4πkd (ε is the dielectric constant, S is the facing area between the two electrode plates, k is the electrostatic force constant, and d is the capacitor dielectric layer thickness), the parasitic capacitance C between the second scan line SCAN2 and the gate connection metal of the driving transistor T1 is STR is greatly reduced. When the second scan line SCAN2 jumps from the high level VGL to the low level VGH or from the low level VGH to the high level VGL, it is difficult for the second scan line SCAN2 to pass through the parasitic capacitor C STR The gate of the driving transistor T1 is coupled, that is, due to V SWITCH ERROE With parasitic capacitance C STR Positive correlation V SWITCH ERROE is greatly reduced, so that the final potential of the gate of the driving transistor T1 is very close to the ideal compensation potential VDATA-|VTH|, thereby improving the display effect.

[0088] In an exemplary embodiment, continue to combine Figure 5 and Figure 6The first metal layer 140 also includes a first capacitor plate, the second metal layer 170 also includes a second capacitor plate, the orthographic projection of the first capacitor dielectric layer 150 in the first direction at least partially overlaps with the orthographic projection of the first capacitor plate in the first direction, the orthographic projection of the second capacitor dielectric layer 160 in the first direction at least partially overlaps with the orthographic projection of part of the first capacitor plate in the first direction, and the orthographic projection of the second capacitor plate in the first direction at least partially overlaps with the orthographic projection of the remaining first capacitor plate in the first direction.

[0089] In this embodiment, according to the layout structure of the pixel circuit, the first capacitor plate and the second capacitor plate can form a storage capacitor C ST The two electrode plates are connected by placing the storage capacitor C ST The capacitor dielectric layer between the two electrode plates is set as the first capacitor dielectric layer 150, that is, a single layer, and the capacitor dielectric layer thickness is small. According to the capacitance C=εS / d=εS / 4πkd (ε is the dielectric constant, S is the facing area between the two electrode plates, k is the electrostatic force constant, and d is the capacitor dielectric layer thickness), the storage capacitor C ST is significantly increased due to V SWITCH ERROE With storage capacitor C ST negatively correlated, so that V SWITCH ERRO E is significantly reduced, thus further ensuring that the final potential of the gate of the driving transistor T1 is substantially the ideal compensation potential VDATA-|VTH|, thereby ensuring a good display effect.

[0090] In an exemplary embodiment, in combination Figure 7 and Figure 8 The display panel 100 further includes a first shielding structure 171, which is insulated from the gate connection metal. The orthographic projection of the first shielding structure 171 in the first direction at least partially overlaps with the orthographic projection of the scan line 142 in the first direction.

[0091] In this embodiment, the first shielding structure 171 may be a metal shielding structure, and the first shielding structure 171 is inserted into the capacitor dielectric layer between the second scan line SCAN2 and the gate connection metal of the driving transistor T1, for example, inserted into the second capacitor dielectric layer 160 between the second scan line SCAN2 and the gate connection metal Gate-M3 of the driving transistor T1, so that the parasitic capacitor C between the gate connection metal Gate-M3 of the driving transistor T1 and the second scan line SCAN2 STR is close to zero, thus further avoiding the second scan line SCAN2 from passing through the parasitic capacitor C STRThe gate of the driving transistor T1 is coupled, so that the final potential of the gate of the driving transistor T1 is substantially the ideal compensation potential VDATA-|VTH|, thereby further improving the display effect. Optionally, the first shielding structure 171 can be connected to the power signal ELVDD.

[0092] In an exemplary embodiment, in combination Figure 7 and Fig. 9 The first metal layer 140 further includes a scan line 142, and the second metal layer 170 further includes a gate connection metal, wherein the gate connection metal is used to connect the gate structure 141; and the gate connection metal and the orthographic projection of the scan line 142 in the first direction do not overlap. Figure 7 and Fig. 9 The display panel 100 also includes an anode layer 190 located on a side of the second metal layer 170 away from the substrate 110, and the anode layer 190 includes a jumper line 191, and the jumper line 191 is electrically connected to the gate connection metal located on both sides of the jumper area, wherein the orthographic projection of the jumper area in the first direction at least partially overlaps with the orthographic projection of the scan line 142 in the first direction.

[0093] Thus, the jumper trace 191, the gate connection metal and the gate structure 141 together form the gate of the driving transistor T1. Figure 7 and Fig. 9 The second metal layer 170 further includes a second shielding structure 172, which is insulated from the gate connection metal. The orthographic projection of the second shielding structure 172 in the first direction at least partially overlaps with the orthographic projection of the scan line 142 in the first direction.

[0094] In this embodiment, the second shielding structure 172 is inserted into the planarization layer 180 between the second scan line SCAN2 and the jumper line 191, so that the parasitic capacitance C between the jumper line 191 and the second scan line SCAN2 STR is close to zero, thus further avoiding the second scan line SCAN2 from passing through the parasitic capacitor C STR The gate of the driving transistor T1 is coupled, so that the final potential of the gate of the driving transistor T1 is substantially the ideal compensation potential VDATA-|VTH|, thereby further improving the display effect. Optionally, the second shielding structure 172 can be connected to the power signal ELVDD.

[0095] In an exemplary embodiment, the second metal layer 170 also includes a source metal and a drain metal, and the source metal and the drain metal are both located on the side of the second capacitor dielectric layer 160 away from the first capacitor dielectric layer 150, wherein the source metal is used to connect the source region 121, and the drain metal is used to connect the drain region 122; in this way, the source and drain of the driving transistor T1 can be correspondingly constituted.

[0096] In an exemplary embodiment, the first capacitor dielectric layer 150 includes an inorganic capacitor dielectric layer, and the second capacitor dielectric layer 160 includes an organic capacitor dielectric layer.

[0097] In this embodiment, the material of the first capacitor dielectric layer 150 can be the material of a conventional insulating medium layer, such as at least one of silicon oxide and silicon nitride; the material of the second capacitor dielectric layer 160 can be organic glue, which is a commonly used material in the display panel 100, and is therefore beneficial for reducing the types of materials used in the display panel 100, thereby saving the production cost of the display panel 100.

[0098] In an exemplary embodiment, the thickness of the first capacitor dielectric layer 150 is less than the thickness of the second capacitor dielectric layer 160; thus, it is more conducive to increasing the source capacitance C of the source of the driving transistor T1. SOURCE , reducing the drain capacitance C of the drain of the driving transistor T1 DRAIN , thereby being more conducive to ensuring that the gate of the driving transistor T1 is fully initialized to improve the threshold voltage VTH offset of the driving transistor T1, and being more conducive to increasing the storage capacitor C ST , reducing the parasitic capacitance C between the scanning line 142 and the gate connection metal of the driving transistor T1 STR , which is more conducive to ensuring that the final potential of the gate of the driving transistor T1 is the ideal compensation potential VDATA-|VTH|.

[0099] In an exemplary embodiment, a display device is provided, which includes a display panel 100 as provided in any of the above embodiments, wherein it can be known from any of the above embodiments that the display panel 100 provided in the embodiment of the present application can complete the production of pixel circuits using only the first metal layer 140 and the second metal layer 170, that is, the technology of the display panel belongs to the display panel technology of two metal layers.

[0100] The display device and the display panel provided in the embodiments of the present application belong to the same inventive concept and can achieve the same technical effects, and the repeated contents will not be repeated here.

[0101] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0102] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; A first transistor, located on one side of the substrate; An active layer, located on one side of the substrate, the active layer comprising a first polar region and a second polar region of the first transistor; A gate insulating layer, located on a side of the active layer away from the substrate; A first metal layer, located on a side of the gate insulating layer away from the active layer, the first metal layer comprising a gate structure of the first transistor; A first capacitor dielectric layer is located on a side of the first metal layer away from the gate insulating layer; a second capacitor dielectric layer, located on a side of the first capacitor dielectric layer away from the first metal layer; wherein the orthographic projection of the first capacitor dielectric layer in the first direction overlaps with the orthographic projections of the first electrode region of the first transistor and the second electrode region of the first transistor in the first direction, the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction, and the orthographic projection of the second capacitor dielectric layer in the first direction does not overlap with the orthographic projection of the first electrode region of the first transistor in the first direction, wherein the first direction is a direction perpendicular to the surface where the display panel is located; The second metal layer includes a first metal structure and a second metal structure, wherein the first metal structure is located on a side of the first capacitor dielectric layer away from the first metal layer, and the second metal structure is located on a side of the second capacitor dielectric layer away from the first capacitor dielectric layer, wherein the orthographic projection of the first metal structure in the first direction at least partially overlaps with the orthographic projection of the first electrode region of the first transistor in the first direction, and the orthographic projection of the second metal structure in the first direction at least partially overlaps with the orthographic projection of the second electrode region of the first transistor in the first direction.

2. The display panel according to claim 1, characterized in that: An overlapping area of ​​the first metal structure with the first electrode region of the first transistor in the first direction is larger than a first preset area, and an overlapping area of ​​the second metal structure with the second electrode region of the first transistor in the first direction is smaller than a second preset area, wherein the first preset area is larger than the second preset area; Optionally, the second metal layer further includes a data signal line for transmitting a data signal and an initialization signal line for transmitting an initialization signal, and in a second direction, the first metal structure is located between the data signal line and the gate structure of the first transistor, and the second metal structure is located between the gate structure of the first transistor and the initialization signal line, wherein the second direction is a direction parallel to the surface where the display panel is located; Optionally, the first metal structure and the second metal structure are power signal lines for transmitting power signals.

3. The display panel according to claim 2, characterized in that: The first metal layer further includes a scan line for transmitting a scan signal, and the second metal layer further includes a gate connection metal, wherein the gate connection metal is connected to the gate structure of the first transistor; The orthographic projections of the first capacitor dielectric layer and the second capacitor dielectric layer in the first direction at least partially overlap with the orthographic projections of the scan line and the gate connection metal in the first direction.

4. The display panel according to claim 2, characterized in that: The first metal layer further includes a scan line for transmitting a scan signal, and the second metal layer further includes a gate connection metal, wherein the gate connection metal is used to connect a gate structure of the first transistor; The gate connection metal has no overlap with the orthographic projection of the scan line in the first direction; Optionally, the display panel also includes an anode layer located on a side of the second metal layer away from the substrate, the anode layer includes a jumper trace, and the jumper trace is electrically connected to the gate connection metal located on both sides of the jumper area, respectively, wherein the orthographic projection of the jumper area in the first direction at least partially overlaps with the orthographic projection of the scan line in the first direction.

5. The display panel according to claim 3, characterized in that: The display panel further comprises a first shielding structure, the first shielding structure is insulated from the gate connection metal, and an orthographic projection of the first shielding structure in the first direction at least partially overlaps with an orthographic projection of the scanning line in the first direction; Optionally, in the first direction, the first shielding structure is located between the scan line and the gate connection metal; Optionally, the first shielding structure is connected to the power signal.

6. The display panel according to claim 4, characterized in that: The second metal layer further includes a second shielding structure, the second shielding structure is insulated from the gate connection metal, and an orthographic projection of the second shielding structure in the first direction at least partially overlaps with an orthographic projection of the scan line in the first direction; Optionally, in the first direction, the second shielding structure is located between the scan line and the jumper line; Optionally, the second shielding structure is connected to the power signal.

7. The display panel according to claim 3 or 4, characterized in that: The first metal layer further includes a first capacitor plate, and the second metal layer further includes a second capacitor plate; The orthographic projection of the first capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of the first capacitor plate in the first direction, the orthographic projection of the second capacitor dielectric layer in the first direction at least partially overlaps with the orthographic projection of part of the first capacitor plate in the first direction, and the orthographic projection of the second capacitor plate in the first direction at least partially overlaps with the orthographic projection of the remaining first capacitor plate in the first direction.

8. The display panel according to any one of claims 1, characterized in that: The first capacitor dielectric layer comprises an inorganic capacitor dielectric layer; the second capacitor dielectric layer comprises an organic capacitor dielectric layer; Optionally, the thickness of the first capacitor dielectric layer is smaller than the thickness of the second capacitor dielectric layer.

9. The display panel according to claim 1, characterized in that: The first electrode region is a source region of the first transistor, and the second electrode region is a drain region of the first transistor; Optionally, the first transistor is a driving transistor for driving the light-emitting device to emit light.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 9.

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