Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, and belongs to the technical field of display. The array substrate comprises a substrate and a plurality of conductive layers stacked on one side of the substrate, and the plurality of conductive layers are used for forming a pixel circuit; the pixel circuit comprises a driving transistor, a storage capacitor and at least one auxiliary transistor, the plurality of conductive layers comprise a first conductive layer and a second conductive layer; the first conductive layer comprises a first gate structure of each pixel circuit; the first gate structure is multiplexed as a first pole plate of the storage capacitor, and the second conductive layer comprises a second pole plate of each storage capacitor; in the same pixel circuit, the first gate structure is an integrated structure comprising a gate of a driving transistor and a gate of at least one auxiliary transistor; the orthographic projection of the second polar plate and the orthographic projection of the first gate structure on the substrate are overlapped, and the outer contour of the orthographic projection of the second polar plate on the substrate surrounds the outer contour of the orthographic projection of the first gate structure on the substrate. The layout space utilization rate can be improved, and the capacitance value of the storage capacitor can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Organic Light Emitting Display (OLED) and flat display panels based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops and desktop computers due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices. However, in related display panels, the capacitance value of the storage capacitor in the pixel circuit is difficult to increase due to the limited layout space. Summary of the invention

[0003] The present invention provides an array substrate and a display device, so as to improve the layout space utilization rate of the array substrate, which is beneficial to improve the capacitance value of the storage capacitor.

[0004] In a first aspect, an embodiment of the present invention provides an array substrate, including:

[0005] A substrate, and a plurality of conductive layers stacked on one side of the substrate; wherein the plurality of conductive layers are used to form at least one pixel circuit; the pixel circuit comprises: a driving transistor, a storage capacitor and at least one auxiliary transistor;

[0006] The multiple conductive layers include: a first conductive layer and a second conductive layer; the first conductive layer includes a first gate structure of each pixel circuit; in the same pixel circuit, the first gate structure is an integrated structure including a gate of the driving transistor and a gate of at least one auxiliary transistor;

[0007] The first gate structure is reused as the first plate of the storage capacitor in the pixel circuit, and the second conductive layer includes the second plate of the storage capacitor in each pixel circuit; in the same pixel circuit, the orthographic projection of the second plate on the substrate overlaps with the orthographic projection of the first gate structure on the substrate, and the outer contour of the orthographic projection of the second plate on the substrate surrounds the outer contour of the orthographic projection of the first gate structure on the substrate.

[0008] Optionally, a first opening is formed on the second electrode plate; in the same pixel circuit, an orthographic projection of the gate of the driving transistor on the substrate covers an orthographic projection of the first opening on the substrate;

[0009] Preferably, an orthographic projection area of ​​the first opening on the substrate is negatively correlated with a capacitance value of the storage capacitor.

[0010] Optionally, at least one second opening is further formed on the second electrode plate; in the same pixel circuit, the orthographic projection of the first gate structure on the substrate overlaps with the orthographic projection of each of the second openings on the substrate;

[0011] Preferably, in the same pixel circuit, the orthographic projection of the first gate structure on the substrate covers the orthographic projection of each second opening on the substrate;

[0012] Preferably, the orthographic projection area of ​​the second opening on the substrate is negatively correlated with the capacitance value of the storage capacitor, and / or the number of the second openings is negatively correlated with the capacitance value of the storage capacitor;

[0013] Preferably, at least a portion of the second opening is in communication with the first opening.

[0014] Optionally, the pixel circuit further includes: at least one first type switch transistor; the array substrate further includes: a first active layer arranged on a side of the second conductive layer away from the substrate; the multiple conductive layers further include a third conductive layer and a fourth conductive layer stacked in sequence on a side of the first active layer away from the substrate;

[0015] The first electrode, the channel region, and the second electrode of the first type switch transistor are connected in sequence and are all located in the first active layer; the gate of the first type switch transistor is located in the third conductive layer, and the orthographic projection of the gate of the first type switch transistor on the substrate at least partially overlaps with the orthographic projection of the channel region of the first type switch transistor on the substrate;

[0016] The fourth conductive layer includes a first connecting line of each pixel circuit; the second electrode of the first type transistor is connected to the gate of the driving transistor through the first connecting line; wherein the first opening is arranged around the via hole between the gate of the driving transistor and the first connecting line;

[0017] Preferably, the material of the first active layer includes indium gallium zinc oxide;

[0018] Preferably, the pixel circuit comprises two first-type switch transistors, namely a first transistor and a second transistor;

[0019] In the same pixel circuit, the first electrode of the first transistor is connected to the second electrode of the driving transistor through the second connecting line, the second electrode of the first transistor is connected to the gate of the driving transistor through the first connecting line, the second electrode of the first transistor is multiplexed as the second electrode of the second transistor, and the first electrode of the second transistor is connected to the first initialization signal line through the third connecting line;

[0020] Wherein, the second connection line and the third connection line are both located in the fourth conductive layer; the first initialization signal line is located in the third conductive layer;

[0021] The array substrate further comprises: a plurality of first scanning lines and a plurality of second scanning lines; the array substrate comprises a plurality of pixel circuits arranged in an array; the gates of the first transistors in the pixel circuits in the same row are all located on the same first scanning line, and the gates of the second transistors in the pixel circuits in the same row are all located on the same second scanning line;

[0022] Preferably, the first scan line includes a first sub-line located in the third conductive layer; the second scan line includes a second sub-line located in the third conductive layer; the gates of the first transistors in the pixel circuits in the same row are all located on the same first sub-line, and the gates of the second transistors in the pixel circuits in the same row are all located on the same second sub-line;

[0023] Preferably, the first scanning line further comprises a third sub-line located in the second conductive layer, an orthographic projection of the first sub-line on the substrate at least partially overlaps with an orthographic projection of the third sub-line on the substrate, and the first sub-line is electrically connected to the third sub-line;

[0024] The second scanning line further includes a fourth sub-line located in the second conductive layer, an orthographic projection of the second sub-line on the substrate at least partially overlaps with an orthographic projection of the fourth sub-line on the substrate, and the second sub-line is electrically connected to the fourth sub-line;

[0025] Preferably, the first initialization signal line, the first scan line and the second scan line all extend along a first direction and are arranged along a second direction; the first direction is perpendicular to the second direction.

[0026] Optionally, the array substrate further comprises: a second active layer, which is arranged on a side of the first conductive layer close to the substrate; wherein the second active layer comprises a first active region of each pixel circuit, and the first active region comprises a first active portion and a second active portion arranged along a first direction and connected to each other; in the same pixel circuit, the first active portion comprises a channel region of the driving transistor, and the second active portion comprises a channel region of at least one auxiliary transistor;

[0027] The first gate structure includes a first gate portion and a second gate portion arranged along the first direction and connected to each other; in the same pixel circuit, the first gate portion includes a gate of the driving transistor, and the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the first active portion on the substrate, and the second gate portion includes at least one gate of the auxiliary transistor, and the orthographic projection of the second gate portion on the substrate covers the orthographic projection of the second active portion on the substrate;

[0028] Preferably, the pixel circuit includes two auxiliary transistors; in the same pixel circuit, the second active portion includes channel regions of the two auxiliary transistors, the channel regions of the two auxiliary transistors are connected to the first active portion, and the second gate portion includes gates of the two auxiliary transistors, the gates of the two auxiliary transistors are connected to the first gate portion, forming the first gate structure of an integrated structure;

[0029] Preferably, in the same pixel circuit, an outer contour of an orthographic projection of the first gate structure on the substrate surrounds an outer contour of an orthographic projection of the first active region on the substrate;

[0030] Preferably, the second gate portion includes a first edge away from the first gate portion along the first direction, and the second active portion includes a second edge away from the first active portion along the first direction; the first edge and the second edge both extend along a second direction, and the second direction is perpendicular to the first direction;

[0031] A distance between an orthographic projection of the first edge on the substrate and an orthographic projection of the second edge on the substrate is greater than or equal to 1 micrometer.

[0032] Optionally, the pixel circuit includes two auxiliary transistors, namely a third transistor and a fourth transistor; the second active portion includes a channel region of the third transistor and a channel region of the fourth transistor arranged along the second direction and connected to each other;

[0033] The channel region of the driving transistor is respectively connected to the channel region of the third transistor and the channel region of the fourth transistor; the second electrode of the driving transistor is located in the second active layer and connected to a side of the first active portion away from the second active portion; the first electrode of the third transistor is located in the second active layer and connected to the channel region of the third transistor; the first electrode of the fourth transistor is located in the second active layer and connected to the channel region of the fourth transistor;

[0034] Preferably, the first electrode of the third transistor is connected to a side of the channel region of the third transistor away from the channel region of the fourth transistor along the second direction; the first electrode of the fourth transistor is connected to a side of the channel region of the fourth transistor away from the channel region of the third transistor along the second direction;

[0035] Preferably, the channel width of the third transistor is equal to the channel width of the fourth transistor, and the channel length of the third transistor is equal to the channel length of the fourth transistor.

[0036] Optionally, the pixel circuit further includes: a plurality of second-type switch transistors; a first electrode, a channel region, and a second electrode of the second-type switch transistor are connected in sequence and are all located in the second active layer; a gate of the second-type switch transistor is located in the first conductive layer, and an orthographic projection of the gate of the second-type switch transistor on the substrate at least partially overlaps with an orthographic projection of the channel region of the second-type switch transistor on the substrate;

[0037] Preferably, the plurality of the second-type switch transistors include: a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0038] In the same pixel circuit, the first electrode of the fifth transistor is connected to the data line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor; the first electrode of the sixth transistor is connected to the second electrode plate of the storage capacitor through a fourth connecting line, and the second electrode plate is connected to the first power line; the second electrode of the sixth transistor is connected to the first electrode of the fourth transistor; the first electrode of the seventh transistor is connected to the second electrode of the driving transistor, the second electrode of the seventh transistor is connected to the second electrode of the eighth transistor, and the first electrode of the eighth transistor is connected to the second initialization signal line through the fifth connecting line;

[0039] The plurality of conductive layers further include: a fourth conductive layer and a fifth conductive layer stacked in sequence on a side of the second conductive layer away from the substrate; the data line and the first power line are both located in the fifth conductive layer; the second initialization signal line, the fourth connection line and the fifth connection line are all located in the fourth conductive layer;

[0040] Preferably, the array substrate comprises a plurality of pixel circuits arranged in an array; the first conductive layer further comprises: a plurality of third scanning lines, a plurality of fourth scanning lines and a plurality of light emitting control signal lines;

[0041] Wherein, the gates of the fifth transistors in the pixel circuits in the same row are all located on the same third scan line; the gates of the sixth transistors and the gates of the seventh transistors in the pixel circuits in the same row are all located on the same light-emitting control signal line; the gates of the eighth transistors in the pixel circuits in the same row are all located on the same fourth scan line; the first electrodes of the eighth transistors in the pixel circuits in the same row are connected to the same second initialization signal line;

[0042] Preferably, the third scan line, the light emitting control signal line, the fourth scan line and the second initialization signal line all extend along the first direction and are arranged along the second direction; the first direction is perpendicular to the second direction.

[0043] Optionally, the plurality of second-type switch transistors further include: a ninth transistor; the gate of the ninth transistor is located on the fourth scan line, the first electrode of the ninth transistor is connected to the third initialization signal line, and the second electrode of the ninth transistor is connected to the second electrode of the sixth transistor via a sixth connection line;

[0044] Wherein, the third initialization signal line and the sixth connection line are both located in the fourth conductive layer; the third initialization signal line extends along the first direction;

[0045] Preferably, the array substrate comprises a plurality of pixel circuits arranged in an array; the gates of the ninth transistors in the pixel circuits in the same row are all located on the same fourth scanning line; the first electrodes of the ninth transistors in the pixel circuits in the same row are all connected to the same third initialization signal line;

[0046] Preferably, in the same row of pixel circuits, an orthographic projection of the third initialization signal line on the substrate overlaps with an orthographic projection of the fourth scanning line on the substrate.

[0047] Optionally, the plurality of conductive layers are used to form a plurality of pixel circuits arranged in an array; any two adjacent pixel circuits in the same row are mirror-symmetrical along a first direction; the first direction is a row direction in which the pixel circuits are arranged;

[0048] Preferably, the first gate structure includes a first gate portion and a second gate portion arranged along the first direction and connected to each other; in the same pixel circuit, the first gate portion includes a gate of the driving transistor, and the second gate portion includes a gate of at least one of the auxiliary transistors;

[0049] The pixel circuits in the same row include at least one pixel unit, and the pixel unit includes two adjacent pixel circuits whose second gate portions are adjacent and spaced apart, and the second plates of the two pixel circuits in the same pixel unit are connected into an integrated structure.

[0050] In a second aspect, an embodiment of the present invention further provides a display panel, comprising: an array substrate provided by any embodiment of the present invention.

[0051] In a third aspect, an embodiment of the present invention further provides a display device, comprising: the array substrate provided by any embodiment of the present invention or the display panel provided by the second aspect of the present invention.

[0052] In the array substrate provided by the embodiment of the present invention, a pixel circuit is formed by stacking a plurality of conductive layers. Considering the characteristic that the gate potentials of the driving transistor and the auxiliary transistor in the pixel circuit are consistent, the first gate structure is set as an integrated structure including the gate of the driving transistor and the gate of at least one auxiliary transistor. Compared with the scheme of setting the gates of different transistors separately, it can effectively save space and improve the utilization rate of the layout space. Compared with the scheme in which the gate of the driving transistor needs to be set separately in the related art, it can effectively increase the area of ​​the first gate structure. Since the first gate structure is reused as the first plate of the storage capacitor, this embodiment is equivalent to increasing the area of ​​the first plate. In addition, in the embodiment of the present invention, the outer contour of the positive projection of the second plate on the substrate is set to surround the outer contour of the positive projection of the first gate structure on the substrate. Therefore, the size of the first plate determines the upper limit of the capacitance value of the storage capacitor to a certain extent. By increasing the area of ​​the first plate, it is beneficial to make the storage capacitor larger, and by controlling the overlapping area of ​​the second plate and the first plate, the capacitance value of the storage capacitor can be flexibly adjusted, so that the selection range of the capacitance value of the storage capacitor is wider and the layout design is more flexible.

[0053] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0055] Figure 1 It is a schematic diagram of a layout of an array substrate in the related art;

[0056] Figure 2 is a schematic diagram of a layout of a storage capacitor provided by an embodiment of the present invention;

[0057] Figure 3 is a schematic diagram of a layout of another storage capacitor provided in an embodiment of the present invention;

[0058] Figure 4 is a schematic diagram of a layout of an array substrate provided by an embodiment of the present invention;

[0059] Figure 5 is a schematic diagram of a film layer structure of an array substrate provided by an embodiment of the present invention;

[0060] Figure 6 is a schematic diagram of a film layer structure of another array substrate provided by an embodiment of the present invention;

[0061] Figure 7 is a circuit diagram of a pixel circuit provided by an embodiment of the present invention;

[0062] Figure 8 is a schematic diagram of a layout of a pixel circuit provided by an embodiment of the present invention;

[0063] Fig. 9 is a schematic diagram of a layout of a pixel unit provided by an embodiment of the present invention;

[0064] Fig.10 is a schematic diagram of a layout of another pixel unit provided by an embodiment of the present invention;

[0065] Fig.11 is a circuit diagram of another pixel circuit provided by an embodiment of the present invention;

[0066] Fig.12 It is a schematic diagram of a layout of another pixel unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0068] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0069] As mentioned in the background art, it is difficult to increase the capacitance of the storage capacitor in the related art. The reasons for this problem are briefly described below. Figure 1 is a schematic diagram of a layout of an array substrate in the related art. Figure 1 The structure related to the storage capacitor Cst in the pixel circuit is given as an example, and the shapes of each film layer are shown for the convenience of illustration. The array substrate includes an active layer 03, a first conductive layer 01 and a second conductive layer 02 stacked on one side of the substrate. The active layer 03 includes an active region of a driving transistor in the pixel circuit, and the active region includes a first direction ( Figure 1 The first conductive layer 01 includes a drain region D01, a channel region G01 and a source region S01 connected in sequence (in the horizontal direction); the first conductive layer 01 includes a gate of the driving transistor, which is reused as a first plate C01 of the storage capacitor Cst; the second conductive layer 02 includes a second plate C02 of the storage capacitor Cst. Among them, the first plate C01 at least partially overlaps with the channel region G01 of the driving transistor, the second plate C02 at least partially overlaps with the first plate C01, and the overlapping portion of the second plate C02 and the first plate C01 constitutes the storage capacitor Cst. It can be understood that when the orthographic projections of two wiring structures located in different film layers on the substrate overlap, the two wiring structures can be said to overlap.

[0070] Among them, according to the requirements and limitations of the current process capability, the following size limitations are imposed on the layout structure: the spacing d10 between the gate of the driving transistor (i.e., the first plate C01) and the source region S01 of the driving transistor in the first direction, and the spacing d20 between the gate of the driving transistor (i.e., the first plate C01) and the drain region D01 of the driving transistor in the first direction are generally designed to be ≥0.5um. The reason is that the gate overlaps with the active layer 01 to form a TFT (thin film transistor) device. The above size limitation of ≥0.5um mainly considers that the gate cannot overlap with the source region S01 and the drain region D01 when the wiring and the size of the related vias fluctuate, so as to avoid forming a new TFT device. Therefore, in the related art, the gate of the driving transistor is located between the source region S01 and the drain region D01, and only overlaps with the channel region G01. The above reasons lead to the limitation of the size of the first plate C01; and because the overlapping part of the second plate C02 and the first plate C01 constitutes the storage capacitor Cst, the capacitance value of the storage capacitor Cst is also limited and difficult to increase.

[0071] To solve the above technical problems, an embodiment of the present invention provides an array substrate. The array substrate includes: a substrate, and a plurality of conductive layers stacked on one side of the substrate. The plurality of conductive layers are used to form at least one pixel circuit. The pixel circuit includes: a driving transistor, a storage capacitor and at least one auxiliary transistor. The storage capacitor is used to store the gate potential of the driving transistor; the auxiliary transistor is used to extend the channel region of the driving transistor to improve the width-to-length ratio of the driving transistor and enhance the driving capability of the driving transistor.

[0072] Figure 2 is a schematic diagram of a storage capacitor provided by an embodiment of the present invention, Figure 2 The stacked structure of the storage capacitor is given in FIG, and the shapes of each film layer are shown separately for the convenience of illustration. Figure 2 The plurality of conductive layers may include: a first conductive layer M1 and a second conductive layer M2. The first conductive layer M1 includes a first gate structure G1 of each pixel circuit. Figure 2 A first gate structure G1 is shown in FIG. 1 . In the same pixel circuit, the first gate structure G1 is an integrated structure including a gate of a driving transistor and a gate of at least one auxiliary transistor. Figure 2, the first gate structure G1 may include a first gate portion GD and a second gate portion GA, the first gate portion GD includes the gate of the driving transistor; the second gate portion GA includes the gate of at least one auxiliary transistor, for example, it may include the gates of all auxiliary transistors in the same pixel circuit, so as to maximize the area of ​​the first gate structure G1. Among them, since the gate potential of the driving transistor is the same as the gate potential of the auxiliary transistor, the gate of the driving transistor and the gate of the auxiliary transistor can be connected together as a first gate structure G1 as a whole, so that the area of ​​the first gate structure G1 can be effectively increased compared to only including the gate of the driving transistor. Among them, if the gate of the driving transistor and the gate of the auxiliary transistor are set in the same conductive layer and spaced apart, it is necessary to consider the limitations of the current equipment and process capabilities, and consider the size fluctuation to set the spacing between adjacent gates, thereby reducing the layout space utilization; in this embodiment, by directly setting the first gate structure G1 as a whole, there is no need to consider the distance limit between adjacent structures in the same layer, thereby effectively saving space.

[0073] The first gate structure G1 is reused as the first plate C1 of the storage capacitor Cst in the pixel circuit; the second conductive layer M2 includes the second plate C2 of the storage capacitor Cst in each pixel circuit. Figure 2 A second electrode plate C2 is shown in FIG. In the same pixel circuit, the orthographic projection of the second electrode plate C2 on the substrate overlaps with the orthographic projection of the first gate structure G1 on the substrate, and the overlapping portion of the second electrode plate C2 and the first gate structure G1 constitutes a storage capacitor Cst; and the outer contour of the orthographic projection of the second electrode plate C2 on the substrate surrounds the outer contour of the orthographic projection of the first gate structure G1 on the substrate.

[0074] For example, the orthographic projection of the second electrode plate C2 on the substrate can completely cover the orthographic projection of the first gate structure G1 on the substrate to obtain a sufficiently large storage capacitor Cst; or, when the first gate structure G1 needs to be connected to other wiring structures through vias, corresponding openings can also be provided on the second electrode plate C2 to insulate the first gate structure G1 from the second electrode plate C2. Figure 1 and Figure 2 In the case where the shape and size of the second electrode plate are exactly the same, this embodiment can significantly increase the area of ​​the first electrode plate relative to the second electrode plate by adding at least one auxiliary transistor gate on the basis of the gate of the driving transistor to form an integrated first gate structure G1, provide a larger storage capacitor Cst, and increase the upper limit of the capacitance value. For example, Figure 2 On the basis of the structure, the capacitance value of the storage capacitor Cst can be adjusted by adjusting the size of the opening on the second electrode plate C2, so that more optional capacitance values ​​can be provided to obtain the storage capacitor Cst that meets the circuit driving requirements.

[0075] In the array substrate provided by the embodiment of the present invention, a pixel circuit is formed by a plurality of conductive layers stacked together. Considering the characteristic that the gate potentials of the driving transistor and the auxiliary transistor in the pixel circuit are consistent, the first gate structure G1 is set as an integrated structure including the gate of the driving transistor and the gate of at least one auxiliary transistor. Compared with the solution of separately setting the gates of different transistors, it can effectively save space and improve the utilization rate of the layout space. Compared with the solution in the related art that the gate of the driving transistor needs to be set separately, it can effectively increase the area of ​​the first gate structure G1. Since the first gate structure G1 is reused as the first plate C1 of the storage capacitor Cst, this embodiment is equivalent to increasing the area of ​​the first plate C1. Moreover, in the embodiment of the present invention, the outer contour of the orthographic projection of the second electrode plate C2 on the substrate is set to surround the outer contour of the orthographic projection of the first gate structure G1 on the substrate. Therefore, the size of the first electrode plate C1 determines the upper limit of the capacitance value of the storage capacitor Cst to a certain extent. By increasing the area of ​​the first electrode plate C1, it is beneficial to make the storage capacitor Cst larger, and by controlling the overlapping area of ​​the second electrode plate C2 and the first electrode plate C1, the capacitance value of the storage capacitor Cst can be flexibly adjusted, so that the selection range of the capacitance value of the storage capacitor Cst is wider and the layout design is more flexible.

[0076] Continue to see Figure 2 , based on the above embodiments, optionally, a first opening H1 is provided on the second electrode plate C2. In the same pixel circuit, the orthographic projection of the gate of the driving transistor on the substrate covers the orthographic projection of the first opening H1 on the substrate. The first opening H1 can be used as the gate potential lead-out opening of the driving transistor. Since the second electrode plate C2 completely covers the first electrode plate C1, when the gate of the driving transistor needs to be connected to other wiring structures in the pixel circuit, the first opening H1 can be provided on the second electrode plate C2, and the vias required for connecting the gate of the driving transistor to the other wiring structures are provided in the first opening H1. Among them, the shape and area of ​​the first opening H1 can be set according to actual needs. The first opening H1 needs to ensure that it can surround the vias required for connecting the gate of the driving transistor to the other wiring structures and does not contact the vias, so as to ensure that the first electrode plate C1 and the second electrode plate C2 are insulated and have no electrical connection.

[0077] On the basis of the above embodiments, optionally, the orthographic projection area of ​​the first opening H1 on the substrate is negatively correlated with the capacitance value of the storage capacitor Cst. The larger the area of ​​the first opening H1, the smaller the area of ​​the overlap between the second plate C2 and the first plate C1, and the smaller the capacitance value of the storage capacitor Cst. Exemplarily, a first opening H1 is provided on the second plate C2. According to the actual demand for the capacitance value of the storage capacitor Cst, the storage capacitor Cst can be reduced by increasing the area of ​​the first opening H1, or the storage capacitor Cst can be increased by reducing the area of ​​the first opening H1.

[0078] Figure 3 FIG. 1 is a schematic diagram of another storage capacitor provided by an embodiment of the present invention. Figure 3 On the basis of the above-mentioned embodiments, optionally, at least one second opening H2 is further provided on the second plate C2. In the same pixel circuit, the orthographic projection of the first gate structure G1 on the substrate overlaps with the orthographic projection of each second opening H2 on the substrate. The second opening H2 can be used as an opening for adjusting the capacitance value of the storage capacitor Cst. Since the first plate C1 itself is also used as the gate of the driving transistor and the gate of the auxiliary transistor, it is limited by the driving requirements of the pixel circuit. The area of ​​the first plate C1 is not easy to adjust and it is difficult to make it smaller. In this embodiment, by providing the second opening H2 on the second plate C2, it is equivalent to reducing the overlapping area of ​​the second plate C2 and the first plate C1 by adjusting the area of ​​the second plate C1, thereby obtaining a smaller storage capacitor Cst.

[0079] On the basis of the above-mentioned embodiments, optionally, in the same pixel circuit, the orthographic projection of the first gate structure G1 on the substrate covers the orthographic projection of each second opening H2 on the substrate. In this way, each time a second opening H2 is provided, the overlapping area of ​​the second electrode plate C2 and the first electrode plate C1 can be reduced by the area of ​​the second opening H2, so that the second opening H2 can fully act on the adjustment of the capacitance value of the storage capacitor Cst.

[0080] On the basis of the above embodiments, optionally, the positive projection area of ​​the second opening H2 on the substrate is negatively correlated with the capacitance value of the storage capacitor Cst; when the number of second openings H2 is constant, the larger the area of ​​the second opening H2, the smaller the area of ​​the overlap between the second plate C2 and the first plate C1, and the smaller the capacitance value of the storage capacitor Cst. And / or, the number of second openings H2 is negatively correlated with the capacitance value of the storage capacitor Cst; when the area of ​​the second opening H2 is constant, the more the number of second openings H2, the smaller the area of ​​the overlap between the second plate C2 and the first plate C1, and the smaller the capacitance value of the storage capacitor Cst. In practical applications, the number and area of ​​the second openings H2 can be set according to actual needs, and the areas and shapes of different second openings H2 can be the same or different. It should be noted that after the first opening H1 and the second opening H2 are opened on the second plate C2, it is still necessary to ensure that the remaining part of the second plate C2 is a whole.

[0081] On the basis of the above embodiments, optionally, at least part of the second openings H2 may be arranged to communicate with the first openings H1 . For example, the first openings H1 and all the second openings H2 in the same second electrode plate C2 may be arranged to communicate with each other to form a large opening.

[0082] Figure 4 is a schematic diagram of a layout of an array substrate provided by an embodiment of the present invention, Figure 4, the stacked structure related to the driving transistor DTFT and the auxiliary transistor ATFT is shown, and the shapes of the second active layer LA2 and the first gate structure G1 are shown for the convenience of illustration. Figure 4 On the basis of the above embodiments, optionally, the array substrate further comprises: a second active layer LA2, located on a side of the first conductive layer M1 close to the substrate. The second active layer LA2 comprises a first active region 10 of each pixel circuit, Figure 4 The structure of a first active area 10 is exemplarily given in FIG. The first active area 10 includes a first active portion 11 and a second active portion 12 arranged along a first direction X and connected to each other; in the same pixel circuit, the first active portion 11 includes a channel region of a driving transistor DTFT, and the second active portion 12 includes a channel region of at least one auxiliary transistor ATFT.

[0083] The first gate structure G1 includes a first gate portion GD and a second gate portion GA which are arranged along a first direction X and are interconnected; in the same pixel circuit, the first gate portion GD includes a gate of a driving transistor DTFT, and the orthographic projection of the first gate portion G1 on the substrate covers the orthographic projection of the first active portion 11 on the substrate, and the second gate portion GA includes a gate of at least one auxiliary transistor ATFT, and the orthographic projection of the second gate portion GA on the substrate covers the orthographic projection of the second active portion 12 on the substrate.

[0084] Since the gate potential of the driving transistor DTFT is electrically the same as the gate potential of the auxiliary transistor ATFT, the gate of the driving transistor DTFT and the gate of the auxiliary transistor ATFT can be connected together in design to exist as a whole; and the channel region of the driving transistor DTFT and the channel region of the auxiliary transistor ATFT can be connected together to exist as a whole, thereby extending the channel region of the driving transistor DTFT.

[0085] In this embodiment, in the first active area 10, the first active part 11 is directly connected to the second active part 12, which is equivalent to directly connecting the channel area of ​​the driving transistor DTFT to the channel area of ​​at least one auxiliary transistor ATFT, and extending the gate of the driving transistor DTFT to cover the second active part 12 to form the first gate structure G1, which is equivalent to using the source area position of the driving transistor DTFT to form the channel area of ​​each auxiliary transistor ATFT, and on the basis of not increasing the layout area, the extension of the channel area of ​​the driving transistor DTFT can be achieved; and because the channel area of ​​the driving transistor DTFT is directly connected to the channel area of ​​each auxiliary transistor ATFT, the space occupied by the source area of ​​the driving transistor DTFT and the drain area of ​​the auxiliary transistor ATFT can be saved, and the layout space can be maximized. Exemplarily, the channel areas of all auxiliary transistors ATFT in the same pixel circuit can be connected to the channel area of ​​the driving transistor DTFT, and the second active part 12 is an integrated structure formed by connecting the channel areas of all auxiliary transistors ATFT.

[0086] On the basis of the above embodiments, optionally, the pixel circuit includes two auxiliary transistors ATFT. In the same pixel circuit, the second active portion 12 may include channel regions of two auxiliary transistors ATFT, and the channel regions of the two auxiliary transistors ATFT are both connected to the first active portion 11; the channel regions of the two auxiliary transistors ATFT are, for example, arranged along the second direction Y, and the second direction Y is perpendicular to the first direction X. Exemplarily, the action phases of the two auxiliary transistors ATFT may be different, and the channel regions of the two auxiliary transistors ATFT have the same length and width, so as to achieve the same extension effect on the channel region of the driving transistor DTFT at different stages. The second gate portion GA includes the gates of the two auxiliary transistors ATFT, and the gates of the two auxiliary transistors ATFT are both connected to the first gate portion GD to form a first gate structure G1 of an integrated structure; the gates of the two auxiliary transistors ATFT are, for example, arranged along the second direction Y.

[0087] On the basis of the above embodiments, optionally, the orthographic projection area of ​​the first gate structure G1 on the substrate is larger than the orthographic projection area of ​​the first active area 10 on the substrate, so as to ensure that the orthographic projection of the first gate structure G1 on the substrate completely covers the orthographic projection of the first active area 10 on the substrate, so that the device size of each auxiliary transistor ATFT is stable. For example, in the same pixel circuit, the outer contour of the orthographic projection of the first gate structure G1 on the substrate surrounds the outer contour of the orthographic projection of the first active area 10 on the substrate.

[0088] Further, the second gate portion GA includes a first edge LL1 away from the first gate portion GD along the first direction X, and the second active portion 12 includes a second edge LL2 away from the first active portion 11 along the first direction X; the first edge LL1 and the second edge LL2 both extend along the second direction Y, and the distance between the orthographic projection of the first edge LL1 on the substrate and the orthographic projection of the second edge LL2 on the substrate (see Figure 4 The spacing d1) is greater than or equal to 1 micron.

[0089] In the present embodiment, the interval d1 is set to be ≥1 um, which can ensure that the device size of the auxiliary transistor ATFT formed by the overlap of the second gate portion GA and the second active portion 12 is stable and is not affected by process fluctuations.

[0090] In the above embodiments, the layout structures related to the storage capacitor Cst, the driving transistor DTFT and the auxiliary transistor ATFT are described in detail. The layout structures of other parts of the pixel circuit are described exemplarily below, but are not intended to limit the present invention.

[0091] Figure 5 Schematic diagram of a film structure of an array substrate provided by an embodiment of the present invention. Figure 5 , based on the above embodiments, optionally, the pixel circuit further includes: at least one first-type switch transistor TFT1. The array substrate further includes: a first active layer LA1 disposed on the side of the second conductive layer M2 away from the substrate 200; the plurality of conductive layers further include a third conductive layer M3 and a fourth conductive layer M4 stacked in sequence on the side of the first active layer LA1 away from the substrate 200. Among them, the first electrode, the channel region, and the second electrode of the first-type switch transistor TFT1 are connected in sequence and are all located in the first active layer LA1; the gate of the first-type switch transistor TFT1 is located in the third conductive layer M3; the orthographic projection of the gate of the first-type switch transistor TFT1 on the substrate 200 at least partially overlaps with the orthographic projection of the channel region of the first-type switch transistor TFT1 on the substrate 200.

[0092] The wiring structures located at different layers in the pixel circuit can be bridged mainly through the connection line located on the fourth conductive layer M4. Among them, any one of the first electrode and the second electrode of the first type switching transistor TFT1 can be extended from the first active layer LA1 to the fourth conductive layer M4 to achieve electrical connection with other wiring structures in the pixel circuit. The fourth conductive layer M4 may include a first connection line L1 for each pixel circuit; the second electrode of the first type transistor TFT1 can be connected to the gate of the driving transistor through the first connection line L1. Among them, the first opening H1 is arranged around the via hole between the gate of the driving transistor and the first connection line L1.

[0093] Exemplarily, the material of the first active layer LA1 includes indium gallium zinc oxide (IGZO), and the first type switching transistor TFT1 may be an N-type IGZO transistor. In this way, the leakage current of the first type switching transistor TFT1 may be smaller. Since the first type switching transistor TFT1 is connected to the gate of the driving transistor, the smaller leakage current of the first type switching transistor TFT1 may make the gate potential of the driving transistor more stable, which is beneficial to realize low-frequency refresh of the pixel circuit, for example, the pixel circuit may support broadband refresh of 1-120Hz.

[0094] Figure 6 Schematic diagram of the film layer structure of another array substrate provided by an embodiment of the present invention. Figure 6 On the basis of the above embodiments, optionally, the array substrate further comprises: a second active layer LA2, which is arranged between the substrate 200 and the first conductive layer M1. The pixel circuit further comprises: a plurality of second-type switch transistors TFT2. The first electrode, the channel region and the second electrode of the second-type switch transistor TFT2 are connected in sequence and are all located on the second active layer LA2; the gate of the second-type switch transistor TFT2 is located on the first conductive layer M1, and the positive projection of the gate of the second-type switch transistor TFT2 on the substrate 200 overlaps at least partially with the positive projection of the channel region of the second-type switch transistor TFT2 on the substrate 200. Exemplarily, any one of the first electrode and the second electrode of the second-type switch transistor TFT2 can be extended from the second active layer LA2 to the fourth conductive layer M4 to achieve electrical connection with other wiring structures in the pixel circuit. The second active layer LA2 can be made of polycrystalline silicon (PSI) material, and the second-type switch transistor TFT2 and the driving transistor can both be P-type LTPS transistors.

[0095] Based on the above embodiments, the plurality of conductive layers may further include: a fifth conductive layer M5 disposed on a side of the fourth conductive layer M4 away from the substrate 200. The fourth conductive layer M4 may be used to lay signal lines required for driving the pixel circuit, such as data lines and power lines.

[0096] In summary, the array substrate includes a second active layer LA2, a first conductive layer M1, a second conductive layer M2, a first active layer LA1, a third conductive layer M3, a fourth conductive layer M4 and a fifth conductive layer M5 which are sequentially stacked on one side of a substrate 200. The substrate 200 is used to provide protection and support for other film layers of the array substrate. The substrate 200 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. Each conductive layer can be made of any conductive material, such as a metal, an alloy, a metal oxide or a non-metallic conductive material, and specific materials may include silver, molybdenum, titanium, aluminum and copper. It can be understood that at least one insulating layer is provided between each two adjacent conductive layers, and at least one insulating layer is also provided between the first active layer LA1 and the conductive layer adjacent thereto, and at least one insulating layer is also provided between the second active layer LA2 and the conductive layer adjacent thereto; the material of the insulating layer can be set to an inorganic material or an organic material according to requirements, and is not specifically limited here. Specifically, a first gate insulating layer 31 can be provided between the second active layer LA2 and the first conductive layer M1, a capacitor insulating layer 32 can be provided between the first conductive layer M1 and the second conductive layer M2, a second gate insulating layer 33 can be provided between the second conductive layer M2 and the first active layer LA1, a third gate insulating layer 34 can be provided between the first active layer LA1 and the third conductive layer M3, a first interlayer insulating layer 35 can be provided between the third conductive layer M3 and the fourth conductive layer M4, a second interlayer insulating layer 36 can be provided between the fourth conductive layer M4 and the fifth conductive layer M5, and a planarization layer 37 can also be provided on the side of the fifth conductive layer M5 away from the substrate 200. Among them, each insulating layer can be set to include inorganic materials and / or organic materials according to requirements, and any of the above insulating layers can be a single-layer structure or a stacked structure composed of multiple sub-insulating layers. Two wiring structures located in different film layers can be directly connected through vias, or can be bridged through connecting wires located in other conductive layers (that is, the two wiring structures are connected to the two ends of the same connecting wire through vias).

[0097] The specific layout structure of the array substrate is described below in conjunction with the specific structure of the pixel circuit, but this is not intended to limit the present invention.

[0098] Figure 7 is a circuit diagram of a pixel circuit provided by an embodiment of the present invention, Figure 8 is a schematic diagram of a layout of a pixel circuit provided by an embodiment of the present invention. Figure 7 and Figure 8 Specifically, the pixel circuit includes two first type switch transistors, namely a first transistor T1 and a second transistor T2.

[0099] In the same pixel circuit, the first electrode of the first transistor T1 is connected to the second electrode of the driving transistor DTFT through the second connecting line L2, the second electrode of the first transistor T1 is connected to the gate of the driving transistor DTFT through the first connecting line L1, the second electrode of the first transistor T1 is multiplexed as the second electrode of the second transistor T2, or connected to the second electrode of the second transistor T2, and the first electrode of the second transistor T2 is connected to the first initialization signal line LREF1 through the third connecting line L3, and is connected to the first initialization signal Vrefn1.

[0100] The first connection line L1 , the second connection line L2 and the third connection line L3 are all located in the fourth conductive layer M4 ; and the first initialization signal line LREF1 is located in the third conductive layer M3 .

[0101] The array substrate further includes: a plurality of first scan lines LS1 for providing a first scan signal SN1; and a plurality of second scan lines LS2 for providing a second scan signal SN2. The array substrate may include a plurality of pixel circuits arranged in an array. The gates of the first transistors T1 in each pixel circuit in the same row are all located on the same first scan line LS1, and the gates of the second transistors T2 in each pixel circuit in the same row are all located on the same second scan line LS2.

[0102] Specifically, the first scan line LS1 may include a first sub-line LS11 located in the third conductive layer M3; the second scan line LS2 may include a second sub-line LS21 located in the third conductive layer M3; the gates of the first transistors T1 in each pixel circuit in the same row are all located on the same first sub-line LS11, and the gates of the second transistors T2 in each pixel circuit in the same row are all located on the same second sub-line LS21.

[0103] Further, the first scanning line LS1 may also include a third sub-line LS12 located on the second conductive layer M2, the orthographic projection of the first sub-line LS11 on the substrate 200 and the orthographic projection of the third sub-line LS12 on the substrate 200 at least partially overlap, and the first sub-line LS11 is electrically connected to the third sub-line LS12. Among them, the orthographic projection of the channel region of the first transistor T1 on the third sub-line LS12 can be used as the bottom gate of the first transistor T1, and the gate of the first transistor T1 located on the first sub-line LS11 can be used as the top gate of the first transistor T1, so that a first transistor T1 with a double-gate structure can be formed, and the top gate and the bottom gate of the first transistor T1 are connected to the same signal. In this way, during the driving process, current can flow through the upper and lower surfaces of the channel of the first transistor T1, thereby increasing the driving current, which is conducive to quickly realizing the on-off control of the first transistor T1, and the use of a double-gate structure can effectively reduce the size of the transistor compared to a single-gate structure.

[0104] The second scanning line LS2 may also include a fourth sub-line LS22 located in the second conductive layer M2, the orthographic projection of the second sub-line LS21 on the substrate 200 and the orthographic projection of the fourth sub-line LS22 on the substrate 200 at least partially overlap, and the second sub-line LS21 is electrically connected to the fourth sub-line LS22. Among them, the orthographic projection of the channel region of the second transistor T2 on the fourth sub-line LS22 can be used as the bottom gate of the second transistor T2, and the gate of the second transistor T2 located on the second sub-line LS21 can be used as the top gate of the second transistor T2, so that a second transistor T2 with a double-gate structure can be formed, and the top gate and the bottom gate of the second transistor T2 are connected to the same signal. Such a setting is conducive to quickly realizing the on-off control of the second transistor T2, and the use of a double-gate structure can effectively reduce the size of the transistor compared to a single-gate structure.

[0105] On the basis of the above embodiments, optionally, the first initialization signal line LREF1, the first scan line LS1 and the second scan line LS2 all extend along the first direction X and are arranged along the second direction Y; the first direction X is perpendicular to the second direction Y. It can be understood that each sub-line in the first scan line LS1 and the second scan line LS2 has the same extension direction as the scan line where it is located.

[0106] Continue to see Figure 7 and Figure 8 On the basis of the above embodiments, optionally, the pixel circuit includes two auxiliary transistors, namely a third transistor T3 and a fourth transistor T4. Figure 4 The structure shown can be viewed as Figure 8 The second active portion 12 may include a channel region of a third transistor T3 and a channel region of a fourth transistor T4 arranged along the second direction Y and connected to each other. The channel region of the driving transistor DTFT is connected to the channel region of the third transistor T3 and the channel region of the fourth transistor T4 respectively. The second electrode of the driving transistor DTFT is located in the second active layer LA2 and is connected to the side of the first active portion 11 away from the second active portion 12. The first electrode of the third transistor T1 is located in the second active layer LA2 and is connected to the channel region of the third transistor T3. The first electrode of the fourth transistor T4 is located in the second active layer LA2 and is connected to the channel region of the fourth transistor T4.

[0107] For example, the third transistor T3 and the fourth transistor T4 are arranged from top to bottom, and the first electrode of the third transistor T3 is connected to a side of the channel region of the third transistor T3 away from the channel region of the fourth transistor T4 along the second direction Y, that is, above the channel region of the third transistor T3. The first electrode of the fourth transistor T4 is connected to a side of the channel region of the fourth transistor T4 away from the channel region of the third transistor T3 along the second direction Y, that is, below the channel region of the fourth transistor T4.

[0108] Specifically, one end of the channel region of the third transistor T3 is connected to the channel region of the driving transistor DTFT, and the other end of the channel region of the third transistor T3 is connected to the first electrode of the third transistor T3, and then connected to the fifth transistor T5; the fifth transistor T5 is used to respond to the third scan signal SP1, and transmit the data voltage Vdata to the driving transistor DTFT in the data writing stage. Then, the third transistor T3 can be used to extend the channel region of the driving transistor DTFT in the data writing stage. One end of the channel region of the fourth transistor T4 is connected to the channel region of the driving transistor DTFT, and the other end of the channel region of the fourth transistor T4 is connected to the first electrode of the fourth transistor T4, and then connected to the sixth transistor T6; the sixth transistor T6 and the seventh transistor T7 are used to respond to the light emitting control signal EM, and are turned on in the light emitting stage, so that the driving transistor DTFT generates a driving current to drive the light emitting device OLED to emit light. Then, the fourth transistor T4 can be used to extend the channel region of the driving transistor DTFT in the light emitting stage. In this embodiment, by providing two auxiliary transistors, the channel region of the driving transistor DTFT can be extended in different driving stages of the pixel circuit, so as to improve the driving capability of the driving transistor DTFT as much as possible.

[0109] On the basis of the above-mentioned embodiments, optionally, the channel region size of the third transistor T3 and the fourth transistor T4 can be arbitrarily set according to actual needs and wiring space, for example, set to the same size or different sizes. Preferably, the channel region width of the third transistor T3 is equal to the channel region width of the fourth transistor T4, and the channel region length of the third transistor T3 is equal to the channel region length of the fourth transistor T4. In this embodiment, by setting the size parameters of the third transistor T3 and the fourth transistor T4 to be completely consistent, the channel region size is consistent, so that in the data writing stage and the light emitting stage, the auxiliary transistor can extend the channel of the driving transistor DTFT in a consistent manner, so that the threshold voltage of the driving transistor DTFT in the data writing stage and the light emitting stage is consistent, thereby ensuring the best display effect.

[0110] Continue to see Figure 7 and Figure 8On the basis of the above embodiments, optionally, the plurality of second-type switch transistors include: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. In the same pixel circuit, the first electrode of the fifth transistor T5 is connected to the data line (not shown in the figure), and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3; the first electrode of the sixth transistor T6 is connected to the second electrode plate C2 of the storage capacitor Cst through the fourth connection line L4, and the second electrode plate C2 is connected to the first power line (not shown in the figure), and is connected to the first power signal VDD; the second electrode of the sixth transistor T6 is connected to the first electrode of the fourth transistor T4; the first electrode of the seventh transistor T7 is connected to the second electrode of the driving transistor DTFT, the second electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8, and the first electrode of the eighth transistor T8 is connected to the second initialization signal line LREF2 through the fifth connection line L5, and is connected to the second initialization voltage Vrefn2.

[0111] The data line and the first power line are both located in the fifth conductive layer M5 , for example, both extend along the second direction Y. The second initialization signal line LREF2 , the fourth connection line L4 and the fifth connection line L5 are all located in the fourth conductive layer M4 .

[0112] On the basis of the above embodiments, optionally, the array substrate includes a plurality of pixel circuits arranged in an array. The first conductive layer M1 also includes: a plurality of third scan lines LS3 for providing a third scan signal SP1; a plurality of fourth scan lines LS4 for providing a fourth scan signal SP2; and a plurality of light-emitting control signal lines LEM for providing a light-emitting control signal EM. Among them, the gates of the fifth transistors T5 in each pixel circuit in the same row are all located on the same third scan line LS3. In other words, the orthographic projection of each third scan line LS3 on the substrate 200 overlaps with the orthographic projection of the channel region of each fifth transistor T5 on the substrate 200, and the orthographic projection position of the channel region of the fifth transistor T5 on the third scan line LS3 constitutes the gate of the fifth transistor T5. The gates of the sixth transistor T6 and the seventh transistor T7 in each pixel circuit in the same row are all located on the same light-emitting control signal line LEM; the gates of the eighth transistors T8 in each pixel circuit in the same row are all located on the same fourth scan line LS4; the first electrodes of the eighth transistors T8 in each pixel circuit in the same row are connected to the same second initialization signal line LREF2. The relationship between each signal line and the gate of the corresponding transistor can refer to the corresponding relationship between the gate of the fifth transistor T5 and the third scanning line LS3, which will not be described in detail.

[0113] Based on the above embodiments, optionally, the third scan line LS3, the light emitting control signal line LEM, the fourth scan line LS4 and the second initialization signal line LREF2 all extend along the first direction X and are arranged along the second direction Y; the first direction X is perpendicular to the second direction Y.

[0114] On the basis of the above embodiments, optionally, for the same row of pixel circuits, the first initialization signal line LREF1, the second scan line LS2, the third scan line LS3, the first scan line LS1, the first gate structure G1, the light emitting control signal line LEM, the fourth scan line LS4 and the second initialization signal line LREF2 are arranged in sequence along the second direction Y, for example, from top to bottom.

[0115] On this basis, in order to save layout space, the orthographic projection of the second scan line LS2 in the pixel circuit of this row on the substrate 200 can be set to overlap with the orthographic projection of the second initialization signal line LREF2' in the pixel circuit of the previous row on the substrate 200. And / or, the orthographic projection of the fourth scan line LS4 in the pixel circuit of this row on the substrate 200 can be set to overlap with the orthographic projection of the first initialization signal line LREF1' in the pixel circuit of the next row on the substrate 200.

[0116] Fig. 9 is a schematic diagram of a layout of a pixel unit provided by an embodiment of the present invention; Fig.10 is a schematic diagram of a layout of another pixel unit provided by an embodiment of the present invention; Fig. 9 and Fig.10 For the same pixel unit structure, Fig. 9 In order to clearly show the positions of the vias, the structure of the fourth metal layer M4 is hidden. Fig.10 is a complete structure including the fourth metal layer M4. Fig. 9 and Fig.10 Based on the above embodiments, optionally, multiple conductive layers are used to form multiple pixel circuits arranged in an array; any two adjacent pixel circuits in the same row are mirror-symmetric along a first direction X; and the first direction X is a row direction of the pixel circuit arrangement.

[0117] The same row of pixel circuits includes at least one pixel unit 400, and the pixel unit 400 includes two adjacent pixel circuits whose second gate portions are adjacent and spaced apart. The two pixel circuits in one pixel unit 400 are, for example, mirror-symmetric about the center line LC of the pixel unit in the first direction X; the center line LC extends along the second direction Y.

[0118] The second electrodes C2 of two pixel circuits in the same pixel unit 400 can be connected into an integral structure. Figure 7 It can be seen that the second plate C2 of the storage capacitor Cst is connected to the first power line and is connected to the first power signal VDD. Therefore, the signals connected to the second plates C2 of the two storage capacitors Cst in the same pixel unit 400 are consistent and can be connected together; and the integrated structure can be connected to the same first power line through a via located on the center line LC to reduce the vias in the array substrate.

[0119] Based on the above embodiments, two pixel circuits in the same pixel unit 400 may share the same fourth connection line L4. The fourth connection line L4 may extend along the second direction Y and be symmetrical about the center line LC in the first direction X with the center line LC as the axis of symmetry.

[0120] Fig.11 is a circuit diagram of another pixel circuit provided by an embodiment of the present invention. Fig.11 , based on the above embodiments, optionally, the plurality of second-type switch transistors further include: a ninth transistor T9. Fig.12 FIG. 1 is a schematic diagram of another layout of a pixel unit provided by an embodiment of the present invention. Fig.11 and Fig.12 The gate of the ninth transistor T9 is located on the fourth scanning line LS4 and is connected to the fourth scanning signal SP2; the first electrode of the ninth transistor T9 is connected to the third initialization signal line LREF3 and is connected to the third initialization signal Vrefp; the second electrode of the ninth transistor T9 is connected to the second electrode of the sixth transistor T6 through the sixth connecting line L6.

[0121] Among them, the third initialization signal line LREF3 and the sixth connection line L6 are both located in the fourth conductive layer M4; the third initialization signal line LREF3 extends along the first direction X; illustratively, the array substrate includes a plurality of pixel circuits arranged in an array; the gates of the ninth transistors T9 in each pixel circuit in the same row are all located on the same fourth scanning line LS4; the first electrodes of the ninth transistors T9 in each pixel circuit in the same row are all connected to the same third initialization signal line LREF3.

[0122] Based on the above embodiments, optionally, in the same row of pixel circuits, the orthographic projection of the third initialization signal line LREF3 on the substrate 200 overlaps with the orthographic projection of the fourth scanning line LS4 on the substrate 200. By setting signal lines of different layers to overlap, the layout size can be saved.

[0123] It can be understood that when the array substrate includes a plurality of pixel circuits arranged in an array, each pixel circuit can be arranged in an array in a display area of ​​the array substrate, each pixel unit has the same structure, and adjacent pixel units are connected.

[0124] On the basis of the above embodiments, optionally, the array substrate also includes an anode layer, a light-emitting material layer and a cathode layer stacked on the side of the fifth conductive layer M5 away from the substrate 200; the anode layer includes the anode of each light-emitting device OLED, which is connected to the second electrode of the seventh transistor T7 in the corresponding pixel circuit; the light-emitting material layer includes the light-emitting layer of each light-emitting device OLED, the cathode layer includes the cathode of each light-emitting device OLED, and each cathode is connected to the second power line and connected to the second power signal VSS.

[0125] Figure 6 and Fig. 9 The various types of vias required in the pixel circuit are also shown. Figure 6 and Fig. 9 On the basis of the above embodiments, optionally, the second active layer LA2 and the fourth conductive layer M4 are connected through a first type via K11, the first conductive layer M1 and the fourth conductive layer M4 are connected through a second type via K12, the second conductive layer M2 and the fourth conductive layer M4 are connected through a third type via K13, the first active layer LA1 and the fourth conductive layer M4 are connected through a fourth type via K21, and the third conductive layer M3 and the fourth conductive layer M4 are connected through a fifth type via K22.

[0126] For example, the first type via K11, the second type via K12 and the third type via K13 can be prepared in the same mask process. Fig. 9 The fourth type via K21 and the fifth type via K22 can be prepared in the same mask process. For details, please refer to Fig. 9 The red vias in the middle.

[0127] It should be noted that the extension direction of each signal line mentioned in the embodiment of the present invention is the overall extension direction of the signal line on the array substrate. When it is refined to the structure in a pixel circuit, in order to avoid the wiring positions of each signal line and related structures, the signal line may have some bending and step areas.

[0128] It should also be noted that the drawings of the embodiments of the present invention provide the general morphology of the wiring of each film layer, but this is not intended to limit the present invention. In particular, for the positions where there are right angles in the wiring of each film layer, due to the influence of the optical proximity effect, the shape of the mask can be appropriately adjusted during the patterning process, such as removing a pattern or adding a pattern, so that the wiring pattern finally formed in the array substrate after considering the optical proximity effect can present a right angle.

[0129] An embodiment of the present invention further provides a display panel, including the array substrate provided by any embodiment of the present invention, and having corresponding beneficial effects.

[0130] The embodiment of the present invention further provides a display device, comprising the array substrate provided by any embodiment of the present invention, and having corresponding beneficial effects. Exemplarily, the display device can be a mobile phone, a television, a laptop computer, a desktop computer, and the like.

[0131] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0132] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: A substrate, and a plurality of conductive layers stacked on one side of the substrate; wherein the plurality of conductive layers are used to form at least one pixel circuit; the pixel circuit comprises: a driving transistor, a storage capacitor and at least one auxiliary transistor; The multiple conductive layers include: a first conductive layer and a second conductive layer; the first conductive layer includes a first gate structure of each pixel circuit; in the same pixel circuit, the first gate structure is an integrated structure including a gate of the driving transistor and a gate of at least one auxiliary transistor; The first gate structure is reused as the first plate of the storage capacitor in the pixel circuit, and the second conductive layer includes the second plate of the storage capacitor in each pixel circuit; in the same pixel circuit, the orthographic projection of the second plate on the substrate overlaps with the orthographic projection of the first gate structure on the substrate, and the outer contour of the orthographic projection of the second plate on the substrate surrounds the outer contour of the orthographic projection of the first gate structure on the substrate.

2. The array substrate according to claim 1, characterized in that: A first opening is formed on the second electrode plate; in the same pixel circuit, the orthographic projection of the gate of the driving transistor on the substrate covers the orthographic projection of the first opening on the substrate; Preferably, an orthographic projection area of ​​the first opening on the substrate is negatively correlated with a capacitance value of the storage capacitor.

3. The array substrate according to claim 2, characterized in that: At least one second opening is also formed on the second electrode plate; in the same pixel circuit, the orthographic projection of the first gate structure on the substrate overlaps with the orthographic projection of each of the second openings on the substrate; Preferably, in the same pixel circuit, the orthographic projection of the first gate structure on the substrate covers the orthographic projection of each second opening on the substrate; Preferably, the orthographic projection area of ​​the second opening on the substrate is negatively correlated with the capacitance value of the storage capacitor, and / or the number of the second openings is negatively correlated with the capacitance value of the storage capacitor; Preferably, at least a portion of the second opening is in communication with the first opening.

4. The array substrate according to claim 2, characterized in that: The pixel circuit further includes: at least one first type switch transistor; the array substrate further includes: a first active layer arranged on a side of the second conductive layer away from the substrate; the plurality of conductive layers further include a third conductive layer and a fourth conductive layer stacked in sequence on a side of the first active layer away from the substrate; The first electrode, the channel region, and the second electrode of the first type switch transistor are connected in sequence and are all located in the first active layer; the gate of the first type switch transistor is located in the third conductive layer, and the orthographic projection of the gate of the first type switch transistor on the substrate at least partially overlaps with the orthographic projection of the channel region of the first type switch transistor on the substrate; The fourth conductive layer includes a first connecting line of each pixel circuit; the second electrode of the first type transistor is connected to the gate of the driving transistor through the first connecting line; wherein the first opening is arranged around the via hole between the gate of the driving transistor and the first connecting line; Preferably, the material of the first active layer includes indium gallium zinc oxide; Preferably, the pixel circuit comprises two first-type switch transistors, namely a first transistor and a second transistor; In the same pixel circuit, the first electrode of the first transistor is connected to the second electrode of the driving transistor through the second connecting line, the second electrode of the first transistor is connected to the gate of the driving transistor through the first connecting line, the second electrode of the first transistor is multiplexed as the second electrode of the second transistor, and the first electrode of the second transistor is connected to the first initialization signal line through the third connecting line; Wherein, the second connection line and the third connection line are both located in the fourth conductive layer; the first initialization signal line is located in the third conductive layer; The array substrate further comprises: a plurality of first scanning lines and a plurality of second scanning lines; the array substrate comprises a plurality of pixel circuits arranged in an array; the gates of the first transistors in the pixel circuits in the same row are all located on the same first scanning line, and the gates of the second transistors in the pixel circuits in the same row are all located on the same second scanning line; Preferably, the first scan line includes a first sub-line located in the third conductive layer; the second scan line includes a second sub-line located in the third conductive layer; the gates of the first transistors in the pixel circuits in the same row are all located on the same first sub-line, and the gates of the second transistors in the pixel circuits in the same row are all located on the same second sub-line; Preferably, the first scanning line further comprises a third sub-line located in the second conductive layer, an orthographic projection of the first sub-line on the substrate at least partially overlaps with an orthographic projection of the third sub-line on the substrate, and the first sub-line is electrically connected to the third sub-line; The second scanning line further includes a fourth sub-line located in the second conductive layer, an orthographic projection of the second sub-line on the substrate at least partially overlaps with an orthographic projection of the fourth sub-line on the substrate, and the second sub-line is electrically connected to the fourth sub-line; Preferably, the first initialization signal line, the first scan line and the second scan line all extend along a first direction and are arranged along a second direction; the first direction is perpendicular to the second direction.

5. The array substrate according to any one of claims 1 to 4, characterized in that: Also includes: A second active layer is arranged on a side of the first conductive layer close to the substrate; wherein the second active layer includes a first active region of each pixel circuit, and the first active region includes a first active portion and a second active portion arranged along a first direction and connected to each other; in the same pixel circuit, the first active portion includes a channel region of the driving transistor, and the second active portion includes a channel region of at least one auxiliary transistor; The first gate structure includes a first gate portion and a second gate portion arranged along the first direction and connected to each other; in the same pixel circuit, the first gate portion includes a gate of the driving transistor, and the orthographic projection of the first gate portion on the substrate covers the orthographic projection of the first active portion on the substrate, and the second gate portion includes at least one gate of the auxiliary transistor, and the orthographic projection of the second gate portion on the substrate covers the orthographic projection of the second active portion on the substrate; Preferably, the pixel circuit comprises two auxiliary transistors; In the same pixel circuit, the second active portion includes channel regions of two auxiliary transistors, and the channel regions of the two auxiliary transistors are both connected to the first active portion; the second gate portion includes gates of two auxiliary transistors, and the gates of the two auxiliary transistors are both connected to the first gate portion, forming the first gate structure of an integrated structure; Preferably, in the same pixel circuit, an outer contour of an orthographic projection of the first gate structure on the substrate surrounds an outer contour of an orthographic projection of the first active region on the substrate; Preferably, the second gate portion includes a first edge away from the first gate portion along the first direction, and the second active portion includes a second edge away from the first active portion along the first direction; the first edge and the second edge both extend along a second direction, and the second direction is perpendicular to the first direction; A distance between an orthographic projection of the first edge on the substrate and an orthographic projection of the second edge on the substrate is greater than or equal to 1 micrometer.

6. The array substrate according to claim 5, characterized in that: The pixel circuit includes two auxiliary transistors, namely a third transistor and a fourth transistor; the second active portion includes a channel region of the third transistor and a channel region of the fourth transistor arranged along the second direction and connected to each other; The channel region of the driving transistor is respectively connected to the channel region of the third transistor and the channel region of the fourth transistor; the second electrode of the driving transistor is located in the second active layer and connected to a side of the first active portion away from the second active portion; the first electrode of the third transistor is located in the second active layer and connected to the channel region of the third transistor; the first electrode of the fourth transistor is located in the second active layer and connected to the channel region of the fourth transistor; Preferably, the first electrode of the third transistor is connected to a side of the channel region of the third transistor away from the channel region of the fourth transistor along the second direction; the first electrode of the fourth transistor is connected to a side of the channel region of the fourth transistor away from the channel region of the third transistor along the second direction; Preferably, the channel width of the third transistor is equal to the channel width of the fourth transistor, and the channel length of the third transistor is equal to the channel length of the fourth transistor.

7. The array substrate according to claim 6, characterized in that: The pixel circuit further includes: a plurality of second-type switch transistors; a first electrode, a channel region, and a second electrode of the second-type switch transistors are connected in sequence and are all located in the second active layer; a gate of the second-type switch transistor is located in the first conductive layer, and an orthographic projection of the gate of the second-type switch transistor on the substrate at least partially overlaps with an orthographic projection of the channel region of the second-type switch transistor on the substrate; Preferably, the plurality of the second-type switch transistors include: a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; In the same pixel circuit, the first electrode of the fifth transistor is connected to the data line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor; the first electrode of the sixth transistor is connected to the second electrode plate of the storage capacitor through a fourth connecting line, and the second electrode plate is connected to the first power line; the second electrode of the sixth transistor is connected to the first electrode of the fourth transistor; the first electrode of the seventh transistor is connected to the second electrode of the driving transistor, the second electrode of the seventh transistor is connected to the second electrode of the eighth transistor, and the first electrode of the eighth transistor is connected to the second initialization signal line through the fifth connecting line; The plurality of conductive layers further include: a fourth conductive layer and a fifth conductive layer stacked in sequence on a side of the second conductive layer away from the substrate; the data line and the first power line are both located in the fifth conductive layer; the second initialization signal line, the fourth connection line and the fifth connection line are all located in the fourth conductive layer; Preferably, the array substrate comprises a plurality of pixel circuits arranged in an array; the first conductive layer further comprises: a plurality of third scanning lines, a plurality of fourth scanning lines and a plurality of light emitting control signal lines; Wherein, the gates of the fifth transistors in the pixel circuits in the same row are all located on the same third scan line; the gates of the sixth transistors and the gates of the seventh transistors in the pixel circuits in the same row are all located on the same light-emitting control signal line; the gates of the eighth transistors in the pixel circuits in the same row are all located on the same fourth scan line; the first electrodes of the eighth transistors in the pixel circuits in the same row are connected to the same second initialization signal line; Preferably, the third scan line, the light emitting control signal line, the fourth scan line and the second initialization signal line all extend along the first direction and are arranged along the second direction; the first direction is perpendicular to the second direction.

8. The array substrate according to claim 7, characterized in that: The plurality of second-type switch transistors further include: a ninth transistor; the gate of the ninth transistor is located on the fourth scan line, the first electrode of the ninth transistor is connected to the third initialization signal line, and the second electrode of the ninth transistor is connected to the second electrode of the sixth transistor via a sixth connection line; Wherein, the third initialization signal line and the sixth connection line are both located in the fourth conductive layer; the third initialization signal line extends along the first direction; Preferably, the array substrate comprises a plurality of pixel circuits arranged in an array; the gates of the ninth transistors in the pixel circuits in the same row are all located on the same fourth scanning line; the first electrodes of the ninth transistors in the pixel circuits in the same row are all connected to the same third initialization signal line; Preferably, in the same row of pixel circuits, an orthographic projection of the third initialization signal line on the substrate overlaps with an orthographic projection of the fourth scanning line on the substrate.

9. The array substrate according to claim 1, characterized in that: The plurality of conductive layers are used to form a plurality of pixel circuits arranged in an array; any two adjacent pixel circuits in the same row are mirror-symmetrical along a first direction; the first direction is the row direction in which the pixel circuits are arranged; Preferably, the first gate structure includes a first gate portion and a second gate portion arranged along the first direction and connected to each other; in the same pixel circuit, the first gate portion includes a gate of the driving transistor, and the second gate portion includes a gate of at least one of the auxiliary transistors; The pixel circuits in the same row include at least one pixel unit, and the pixel unit includes two adjacent pixel circuits whose second gate portions are adjacent and spaced apart, and the second electrodes of the two pixel circuits in the same pixel unit are connected into an integrated structure.

10. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 9.

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