Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate; the pixel circuits are distributed in an array mode in the first direction and the second direction which intersect with each other, each pixel circuit comprises a first semiconductor part, a semiconductor connecting part, a main body part and a branch connected with the main body part, the main body part extends in the first direction, and the branch extends in the second direction. Two first semiconductor portions adjacent in the second direction are connected by a branch. According to the embodiment of the invention, the performance of a display product can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide an array substrate, a display panel and a display device, which can improve the performance of display products.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, comprising a substrate; a pixel circuit, wherein a plurality of pixel circuits are distributed in an array in intersecting first and second directions, each pixel circuit comprising a first semiconductor portion, a semiconductor connecting portion, comprising a main portion and a branch connected to the main portion, the main portion extending along the first direction, the branch extending along the second direction, and two adjacent first semiconductor portions in the second direction are connected via the branch.

[0006] In a possible implementation of the first aspect, the pixel circuit includes a gate reset transistor and an anode reset transistor, the first semiconductor portion includes a first end and a second end, the first electrode of the gate reset transistor is connected to the first end, the first electrode of the anode reset transistor is connected to the second end, and in two first semiconductor portions adjacent to each other in the second direction, the first end of one first semiconductor portion and the second end of the other first semiconductor portion are connected through a branch;

[0007] Preferably, in the second direction, the anode reset transistor of the i-th pixel circuit and the gate reset transistor of the i+1-th pixel circuit are adjacent;

[0008] Preferably, the first semiconductor portion further comprises a gate connection point and an anode connection point, the gate connection point connects the second electrode of the gate reset transistor and the gate of the driving transistor, the anode connection point connects the second electrode of the anode reset transistor and the anode of the light emitting element, and the gate connection points and the anode connection points of two adjacent first semiconductor portions in the second direction are located on the same side of the branch;

[0009] Preferably, the gate reset transistor is a dual-gate transistor.

[0010] In a possible implementation manner of the first aspect, the array substrate further includes:

[0011] A reset signal line connected to the semiconductor connection portion through a first via hole;

[0012] Preferably, the orthographic projection of the first via on the substrate and the orthographic projection of the connection point of the main body on the substrate at least partially overlap, and the orthographic projection of the branch on the substrate and the orthographic projection of the connection point of the main body on the substrate at least partially overlap.

[0013] In a possible implementation of the first aspect, the array substrate includes a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer that are stacked, the reset signal line is located in the second metal layer, and the reset signal line extends along a first direction;

[0014] Preferably, the second metal layer further comprises a first plate of a capacitor in the pixel circuit;

[0015] Preferably, the first plates adjacent to each other in the first direction are connected to each other;

[0016] Preferably, the third metal layer includes a data line, and the data line extends along the second direction;

[0017] Preferably, the third metal layer comprises a power line, and the power line extends along the second direction.

[0018] In a possible implementation of the first aspect, the array substrate includes a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer that are stacked, the reset signal line is located in the third metal layer, and the reset signal line extends along the second direction;

[0019] Preferably, the third metal layer includes a data line, and the data line extends along the second direction;

[0020] Preferably, the third metal layer includes a power line, and the power line extends along the second direction;

[0021] Preferably, the second metal layer comprises a first plate of a capacitor in the pixel circuit;

[0022] Preferably, the first electrode plates adjacent to each other in the first direction are connected to each other.

[0023] In a possible implementation of the first aspect, the array substrate includes an auxiliary metal layer, a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer which are stacked, and the reset signal line is located in the auxiliary metal layer;

[0024] Preferably, the reset signal line includes a first branch line and a second branch line, the first branch line extends along the first direction, and the second branch line extends along the second direction;

[0025] Preferably, the second metal layer comprises a first plate of a capacitor in the pixel circuit;

[0026] Preferably, the first plates adjacent to each other in the first direction are connected to each other;

[0027] Preferably, the third metal layer includes a data line, and the data line extends along the second direction;

[0028] Preferably, the third metal layer comprises a power line, and the power line extends along the second direction.

[0029] In a possible implementation manner of the first aspect, the branch includes a first branch and a second branch, the first branch is connected to the first end, the second branch is connected to the second end, and an orthographic projection of the first branch on the substrate and an orthographic projection of the second branch on the substrate are on the same straight line;

[0030] Preferably, the active layer of the gate reset transistor comprises a first active layer and a second active layer connected to each other, the first active layer is connected to the second branch, the second active layer is connected to the gate connection point, the first active layer extends along the second direction, and the second active layer extends along the first direction;

[0031] Preferably, the orthographic projection of the first active layer on the substrate and the orthographic projection of the second branch on the substrate are on the same straight line.

[0032] In a possible implementation manner of the first aspect, the branch includes a first branch and a second branch, the first branch is connected to the first end, the second branch is connected to the second end, and an orthographic projection of the first branch on the substrate and an orthographic projection of the second branch on the substrate are on different straight lines;

[0033] Preferably, the active layer of the gate reset transistor comprises a first active layer and a second active layer connected to each other, the first active layer is connected to the second branch, the second active layer is connected to the gate connection point, and the orthographic projection of the first active layer on the substrate and the orthographic projection of the second active layer on the substrate are on the same straight line;

[0034] Preferably, the first active layer and the second branch are on the same straight line.

[0035] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display panel, comprising the array substrate as described in the embodiment of the first aspect.

[0036] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display device, comprising a display panel as described in the embodiment of the second aspect.

[0037] According to the array substrate, display panel and display device provided by the embodiments of the present application, a semiconductor connecting portion is provided. Since the semiconductor connecting portion includes a main portion extending along a first direction and a branch extending along a second direction, the branch connects the adjacent first semiconductor portions in the second direction, and the branch is connected to the main portion. In this way, the semiconductor connecting portion can connect the first semiconductor portions distributed in the array to each other. The semiconductor connecting portion and the first semiconductor portions form a grid-like structure as a whole, so that the charge attachment on the first semiconductor portions distributed in the array is uniform, thereby making the characteristics of the pixel circuit uniform, so as to improve the display uniformity and improve the problem of display unevenness (for example, S-direction mura).

[0038] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0040] Figure 1 A schematic diagram of a top view structure of a display substrate provided in an embodiment of the present application is shown;

[0041] Figure 2 A schematic diagram showing a layout structure of a display substrate provided in an embodiment of the present application is shown;

[0042] Figure 3 Another schematic diagram of the layout structure of the display substrate provided in the embodiment of the present application is shown;

[0043] Figure 4 An equivalent structural schematic diagram of a pixel circuit in a display substrate provided in an embodiment of the present application is shown;

[0044] Figure 5 Another schematic diagram of the layout structure of the display substrate provided in the embodiment of the present application is shown;

[0045] Figure 6 Another schematic diagram of the layout structure of the display substrate provided in the embodiment of the present application is shown;

[0046] Figure 7 Another schematic diagram of the layout structure of the display substrate provided in the embodiment of the present application is shown;

[0047] Figure 8A schematic diagram showing a film layer stacking structure of a display substrate provided in an embodiment of the present application is shown;

[0048] Fig. 9 Another schematic diagram of a film layer stacking structure of a display substrate provided in an embodiment of the present application is shown;

[0049] Fig.10 Another schematic diagram of the layout structure of the display substrate provided in the embodiment of the present application is shown;

[0050] Fig.11 Another schematic diagram of the layout structure of the display substrate provided in the embodiment of the present application is shown;

[0051] Fig.12 Another schematic diagram of the layout structure of the display substrate provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0052] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0053] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0054] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0055] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "attached" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0056] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0057] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0058] With the development of display technology, the functions of display products are becoming more and more diversified. For example, a hole area is provided in the display area of ​​the screen, and a camera and / or other functional components are arranged in the hole area correspondingly. No pixel circuit is arranged in the hole area, and a pixel circuit is arranged in the display area outside the hole area. In this way, the semiconductor part of the pixel circuit is separated by the hole area, and the semiconductor parts of the pixel circuits above and below or to the left and right of the hole area are no longer connected to each other. As a result, the semiconductor pattern on one side of the hole area is very short, and the semiconductor patterns in other areas are very long. The areas are different, the difference is relatively large, and the degree of adsorption of charge is different, resulting in different characteristics, which leads to different display effects on one side of the hole area and other areas.

[0059] In order to solve the above technical problems, the embodiments of the present application provide an array substrate, a display panel and a display device. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0060] Combined with reference Figures 1 to 4 The array substrate 100 provided in the embodiment of the present application includes a substrate 01 , a pixel circuit 10 and a semiconductor connection portion 12 .

[0061] It should be noted that in order to clearly show the structure of each component, Figure 2 Only the structure of the film layer where the semiconductor is located is shown. Figure 3 The structure of the semiconductor part and the film layer where the gate wiring (such as the scanning line and the light control signal line) is located is shown. Figure 2 and Figure 3In the figure, the pink pattern represents the structure of the film layer where the semiconductor is located, and the blue pattern represents the structure of the film layer where the gate wiring (gate part) is located.

[0062] The array substrate 100 may include a substrate 01 and a pixel circuit 10 located on one side of the substrate 01, and a plurality of pixel circuits 10 may be distributed in an array in the intersecting first direction G and second direction S. Each pixel circuit 10 may include a continuous first semiconductor portion 11. The first semiconductor portion 11 includes a portion for forming an active layer of each transistor of the pixel circuit 10 and a portion connecting adjacent transistor active layers. The first semiconductor portion 11 of a single pixel circuit is continuous.

[0063] As an example, Figure 4 As shown, the pixel circuit may include a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a gate reset transistor T4, an anode reset transistor T7, a power writing transistor T5 and a light emitting control transistor T6. In the multiple transistors in a pixel circuit, each transistor structure includes an active layer, and the active layers of the multiple transistors in a pixel circuit can be connected together to form a Figure 2 and Figure 3 The patterned first semiconductor portion 11 is shown.

[0064] The semiconductor connection part 12 includes a main body 120 and a branch 121 connected to the main body 120 . The main body 120 and the branch 121 can be integrally formed. The main body 120 extends along a first direction G, and the branch 121 extends along a second direction S. Two adjacent first semiconductor parts 11 in the second direction S are connected by the branch 121 .

[0065] Taking the first direction G as the row direction and the second direction S as the column direction as an example, a plurality of branches 121 may be connected to one main body portion 120 , and different branches 121 are connected to two adjacent first semiconductor portions 11 in different columns.

[0066] For example, the number of rows of the pixel circuit is M, the number of columns is N, the number of the main bodies 120 may be M-1, and the number of the branches 121 is (M-1)×N.

[0067] For example, the material of the first semiconductor portion 11 and the semiconductor connection portion 12 may include P-type silicon (P-Si). The first semiconductor portion 11 and the semiconductor connection portion 12 may be integrally formed.

[0068] The array substrate provided in the embodiment of the present application is provided with a semiconductor connecting portion. Since the semiconductor connecting portion includes a main portion extending along a first direction and a branch extending along a second direction, the branch connects the adjacent first semiconductor portions in the second direction, and the branch is connected to the main portion. In this way, the semiconductor connecting portion can connect the first semiconductor portions distributed in the array to each other. The semiconductor connecting portion and the first semiconductor portions form a grid-like structure as a whole, so that the charge attachment on the first semiconductor portions distributed in the array is uniform, thereby making the characteristics of the pixel circuit uniform, so as to improve the display uniformity and improve the problem of display unevenness (for example, S-direction mura).

[0069] As an example, Figure 1 As shown, the array substrate 100 provided in the embodiment of the present application can be applied to a screen with a hole area Hole, the hole area Hole is surrounded by the display area AA, and the pixel circuits 10 are arrayed in the display area AA. The first semiconductor parts 11 of the pixel circuits 10 in the display area AA are connected by semiconductor connecting parts 12 to form a grid structure.

[0070] Of course, in other examples, the array substrate 100 provided in the embodiment of the present application can also be applied to a screen without a hole area Hole in the display area AA, which will not be listed one by one here.

[0071] In some embodiments, please refer to Figure 3 and Figure 4 , the pixel circuit 10 includes a gate reset transistor T4 and an anode reset transistor T7. The first semiconductor portion 11 includes a first end N1 and a second end N2. The first electrode of the gate reset transistor T4 is connected to the first end N1, and the second electrode of the gate reset transistor T4 is connected to the gate of the driving transistor T1. The gate reset transistor T4 is used to reset the gate potential of the driving transistor T1. The first electrode of the anode reset transistor T7 is connected to the second end N2, and the second electrode of the anode reset transistor T7 is connected to the anode of the light emitting element D. The anode reset transistor T7 is used to reset the potential of the anode of the light emitting element.

[0072] In two first semiconductor portions 11 adjacent to each other in the second direction S, the first end N1 of one first semiconductor portion 11 and the second end N2 of the other first semiconductor portion 11 are connected by a branch 121 .

[0073] For example, Figure 3 The figure shows a pixel circuit of 2 rows and 2 columns, namely the i-th row, i+1-th row, j-th column, and j+1-th column. The first end N1(i) of the first semiconductor portion 11 of the i-th row and the second end N2(i+1) of the first semiconductor portion 11 are connected via a branch 121.

[0074] The gate reset transistor T4 and the anode reset transistor T7 are both used for resetting, and the same reset signal can be connected to the two. The first end N1 and the second end N2 respectively connected to the two are connected through a branch. In this way, the array-distributed first semiconductor part 11 and the semiconductor connection part 12 form a grid shape as a whole, and signal crosstalk between different pixel circuits will not be caused.

[0075] Exemplarily, in the second direction S, the anode reset transistor T7(i) of the i-th pixel circuit and the gate reset transistor T4(i+1) of the i+1-th pixel circuit are adjacent to each other. In this way, the branch 121 can connect the first end N1 and the second end N2 nearby.

[0076] Exemplarily, the first semiconductor portion 11 further includes a gate connection point N3 and an anode connection point N4, the gate connection point N3 connects the second electrode of the gate reset transistor T4 and the gate of the driving transistor T1, and the anode connection point N4 connects the second electrode of the anode reset transistor T7 and the light emitting element ( Figure 3 The gate connection point N3 and the anode connection point N4 of two adjacent first semiconductor portions 11 in the second direction S are located on the same side of the branch 121. For example, Figure 3 In the same column of pixel circuits, the gate connection point N3 and the anode connection point N4 are located on the left side of the branch 121 corresponding to the pixel circuit of the column.

[0077] In addition, the threshold compensation transistor T3 is also connected to the gate connection point N3.

[0078] Exemplarily, the gate reset transistor T4 is a dual-gate transistor. The threshold compensation transistor T3 may also be a dual-gate transistor.

[0079] Figure 3 and Figure 4 As exemplarily shown in the figure, the gate of the gate reset transistor T4 is connected to the first scan line S1, the gates of the threshold compensation transistor T3 and the data write transistor T2 are connected to the second scan line S2, the gate of the anode reset transistor T7 is connected to the third scan line S3, and the power write transistor T5 and the light emitting control transistor T6 are connected to the light emitting control signal line EM.

[0080] Figure 3 In the figure, S1(i), S2(i), S3(i) represent the first scan line, the second scan line and the third scan line connected to the pixel circuit in the i-th row, and EM(i) represents the light emitting control signal line connected to the pixel circuit in the i-th row; S1(i+1), S2(i+1), S3(i+1) represent the first scan line, the second scan line and the third scan line connected to the pixel circuit in the i+1-th row, and EM(i+1) represents the light emitting control signal line connected to the pixel circuit in the i+1-th row.

[0081] In addition, T4(i) represents the gate reset transistor of the pixel circuit in the i-th row, T4(i+1) represents the gate reset transistor of the pixel circuit in the i+1-th row, T7(i) represents the anode reset transistor of the pixel circuit in the i-th row, and T7(i+1) represents the anode reset transistor of the pixel circuit in the i+1-th row.

[0082] The scanning line and the light-emitting control signal line can be collectively referred to as a gate wiring. Part of the gate wiring overlaps with the first semiconductor portion, and part of the gate wiring is the gate of the transistor. Part of the first semiconductor portion overlaps with the gate wiring, and part of the first semiconductor portion is the channel of the transistor. Both sides of the channel are the source and drain regions of the transistor. The channel and the source and drain regions constitute the active layer of the transistor.

[0083] In some embodiments, Figures 5 to 7 As shown, the array substrate 100 further includes a reset signal line Vref, and the reset signal line Vref is connected to the semiconductor connection part 12 through a first via hole h1.

[0084] The reset signal line Vref is used to provide a reset signal. The potential of the semiconductor connection part 12 is the same as the potential of the reset signal line Vref. The semiconductor connection part 12 is equivalent to the wiring for transmitting the reset signal, which can reduce the impedance of the reset signal line Vref, thereby facilitating the improvement of display uniformity.

[0085] Exemplarily, the reset signal line Vref is connected to the main body 120 of the semiconductor connection part 12 through the first via h1. As an example, the orthographic projections of the connection points of the first via h1 and the main body 120 on the substrate at least partially overlap, and the orthographic projections of the connection points of the branch 121 and the main body 120 on the substrate at least partially overlap. In other words, the connection point between the first via h1 and the main body 120 and at least one connection point between the branch 121 and the main body 120 are the same connection point. To ensure connectivity, the connection point can be designed to be thickened. In the embodiment of the present application, the connection point between the first via h1 and the main body 120 and at least one connection point between the branch 121 and the main body 120 are set to be the same connection point, which can reduce the number of connection points that need to be thickened, which is beneficial to improving pixel density.

[0086] In some embodiments, Figure 8 As shown, the array substrate includes a semiconductor layer 02, a first metal layer M1, a second metal layer M2 and a third metal layer M3 which are stacked, and the first metal layer M1, the second metal layer M2 and the third metal layer M3 are sequentially arranged away from the semiconductor layer 02. Insulating layers are arranged between different metal layers and between the metal layers and the semiconductor layers, which will not be described one by one here.

[0087] The first metal layer M1 may include gate wirings, such as a first scan line S1, a second scan line S2, a third scan line S3, and a light emitting control signal line EM. In addition, the gate of the driving transistor T1 is disposed in the first metal layer M1.

[0088] like Figure 4 As shown, the pixel circuit includes a capacitor Cst, a first plate of the capacitor Cst (not shown in the layout) is connected to the power line VDD, and the second metal layer M2 may include the first plate of the capacitor Cst. Exemplarily, the first plates of adjacent capacitors Cst in the first direction S may be connected to each other.

[0089] The third metal layer M3 may include a data line Data (not shown in the layout) and a power line VDD (not shown in the layout), and both the data line Data and the power line VDD extend along the second direction S. As an example, Figure 5 As shown, the reset signal line Vref is located in the second metal layer M2, and the reset signal line Vref extends along the first direction G. The extension direction of the reset signal line Vref is the same as the extension direction of the main body 120. The reset signal line Vref and the main body 120 can be arranged in a one-to-one correspondence. The orthographic projections of the reset signal line Vref and the main body 120 on the substrate can at least partially overlap. In this example, the reset signal line Vref and the first plate of the capacitor Cst are both located in the second metal layer M2.

[0090] It is understandable that the reset signal line Vref is located in the second metal layer M2 , the semiconductor connection part 12 is located in the semiconductor layer 01 , and the first via h1 between the reset signal line Vref and the semiconductor connection part 12 refers to: a via extending from the second metal layer M2 to the semiconductor layer 01 .

[0091] As another example, Figure 6 As shown, the reset signal line Vref is located in the third metal layer M3, and the reset signal line Vref extends along the second direction S. The extension direction of the reset signal line Vref intersects with the extension direction of the main body 120. The reset signal line Vref and the main body 120 form a grid structure, which is more conducive to reducing the impedance of the reset signal line Vref.

[0092] In this example, the reset signal line Vref, the data line Data, and the power line VDD are all located in the third metal layer M3.

[0093] It is understandable that the reset signal line Vref is located in the second metal layer M2 , the semiconductor connection part 12 is located in the semiconductor layer 01 , and the first via h1 between the reset signal line Vref and the semiconductor connection part 12 refers to: a via extending from the third metal layer M3 to the semiconductor layer 01 .

[0094] In other embodiments, please refer to Figure 7and Fig. 9 The array substrate includes an auxiliary metal layer M0, a semiconductor layer 02, a first metal layer M1, a second metal layer M2 and a third metal layer M3 which are stacked. The first metal layer M1, the second metal layer M2 and the third metal layer M3 are located on the first side of the semiconductor layer 02 and are sequentially arranged away from the semiconductor layer 02. The auxiliary metal layer M0 is located on the second side of the semiconductor layer 02. The first side and the second side of the semiconductor layer 02 are opposite sides. Insulating layers are provided between different metal layers and between metal layers and semiconductor layers, which will not be described one by one here.

[0095] The reset signal line Vref may be located in the auxiliary metal layer M0. In this way, the second metal layer M2 and the third metal layer M3 may have more space for wiring design; in addition, the reset signal line Vref located in the auxiliary metal layer M0 may at least block a portion of the transistor channel to reduce the influence of light on the transistor characteristics.

[0096] Exemplarily, the reset signal line Vref located in the auxiliary metal layer M0 may include a first branch line Vref1 and a second branch line Vref2, the first branch line Vref1 extends along the first direction G, and the second branch line Vref2 extends along the second direction S. A plurality of first branch lines Vref1 and a plurality of second branch lines Vref2 intersect each other to form a grid structure, which can further reduce the impedance of the reset signal line Vref.

[0097] It is understandable that the reset signal line Vref is located in the auxiliary metal layer M0 , the semiconductor connection part 12 is located in the semiconductor layer 01 , and the first via h1 between the reset signal line Vref and the semiconductor connection part 12 refers to: a via extending from the auxiliary metal layer M0 to the semiconductor layer 01 .

[0098] Of course, the above introduction to the reset signal line Vref is only some examples and is not used to limit the present application. The reset signal line Vref may also be set in other ways, which are not listed here one by one.

[0099] As described above, the branch 121 of the semiconductor connection portion 12 connects the first end N1 of one of the first semiconductor portions 11 and the second end N2 of the other first semiconductor portion 11. The branch 121 may include a first branch 1211 and a second branch 1212, wherein the first branch 1211 connects the first end N1 and the second branch 1212 connects the second end N2.

[0100] As an example, Figure 2As shown, the orthographic projection of the first branch 1211 on the substrate and the orthographic projection of the second branch 1212 on the substrate are on the same straight line. In other words, the first branch 1211 and the second branch 1212 are connected to the same position of the main body 120. In this case, the grids of multiple rows and columns formed by the first semiconductor part 11 and the semiconductor connecting part 12 are aligned.

[0101] For example, please refer to Figure 4 and Figure 5 The gate reset transistor T4 is a dual-gate transistor, whose active layer includes a first active layer b41 and a second active layer b42 connected to each other, the first active layer b41 is connected to the second branch 1212, the second active layer b42 is connected to the gate connection point N3, the first active layer b41 extends along the second direction S, and the second active layer b42 extends along the first direction G.

[0102] In addition, the first scan line S1 may also include a main portion and branches connected to each other, the main portion of the first scan line S1 overlaps with the first active layer b41, and the branch of the first scan line S1 overlaps with the second active layer b42.

[0103] For example, please refer to Figure 4 and Figure 5 , the orthographic projection of the first active layer b41 on the substrate and the orthographic projection of the second branch 121 2 on the substrate may be on the same straight line.

[0104] As another example, Fig.10 As shown, Fig.10 and Figure 2 and Figure 3 The similarities of the structures shown are not repeated here, and the differences include: the orthographic projection of the first branch 1211 on the substrate and the orthographic projection of the second branch 1212 on the substrate are on different straight lines. In other words, the first branch 1211 and the second branch 1212 are connected to different positions of the main body 120. In this case, the grid of multiple rows and columns formed by the first semiconductor part 11 and the semiconductor connecting part 12 is equivalent to being misaligned.

[0105] For example, Fig.10 As shown, the gate reset transistor T4 is a dual-gate transistor, whose active layer includes a first active layer b41 and a second active layer b42 connected to each other, the first active layer b41 is connected to the second branch 1212, the second active layer b42 is connected to the gate connection point N3, the first active layer b41 and the second active layer b42 extend along the second direction G, and the orthographic projection of the first active layer b41 on the substrate and the orthographic projection of the second active layer b42 on the substrate are on the same straight line. In this case, there is no corner between the two active layers of the gate reset transistor T4.

[0106] Exemplarily, the orthographic projection of the first active layer b41 on the substrate and the orthographic projection of the second branch 1212 on the substrate are on the same straight line.

[0107] It should be noted that, when the grids of multiple rows and columns formed by the first semiconductor portion 11 and the semiconductor connecting portion 12 are staggered, such as Fig.11 As shown, the reset signal line Vref may be disposed in the second metal layer M2 and extend along the first direction G; or Fig.12 As shown, the reset signal line Vref may be disposed in the third metal layer M3 and extend along the second direction S; or Figure 7 As shown, the reset signal line Vref may be disposed in the auxiliary metal layer M0 and may be in a grid shape.

[0108] It should be noted that, in each embodiment of the present application, a P-type transistor is used as an example for explanation. For the P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first electrode and the second electrode are connected, and when the control terminal of the P-type transistor is at a high level, the first electrode and the second electrode are disconnected.

[0109] For those skilled in the art, the equivalent circuit structure of the pixel circuit and / or the layout structure of the array plate can be appropriately changed to set at least part of the transistors as N-type transistors. For N-type transistors, the on level is a high level and the off level is a low level. That is, when the gate of the N-type transistor is at a high level, the first electrode and the second electrode are connected, and when the gate of the N-type transistor is at a low level, the first electrode and the second electrode are disconnected.

[0110] In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present invention are both general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / shut down the transistor.

[0111] Based on the same inventive concept, the embodiment of the present application also provides a display panel, which includes the array substrate provided in the embodiment of the present application. Therefore, the display panel has the technical features of the array substrate provided in the embodiment of the present application, and can achieve the beneficial effects of the array substrate provided in the embodiment of the present application. The similarities can be referred to the above description of the array substrate provided in the embodiment of the present application, and will not be repeated here.

[0112] Based on the same inventive concept, the embodiment of the present application also provides a display device, which includes the display panel provided in the embodiment of the present application. Therefore, the display device has the technical features of the display panel provided in the embodiment of the present application, and can achieve the beneficial effects of the display panel provided in the embodiment of the present application. For the similarities, please refer to the above description of the display panel provided in the embodiment of the present application, and no further description will be given here.

[0113] It can be understood that the display device provided in the embodiment of the present application can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not specifically limit this.

[0114] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that: include: substrate; A pixel circuit, wherein a plurality of the pixel circuits are arranged in an array in a first direction and a second direction intersecting each other, each of the pixel circuits comprising a first semiconductor portion, The semiconductor connection part includes a main body and a branch connected to the main body, wherein the main body extends along the first direction, the branch extends along the second direction, and two adjacent first semiconductor parts in the second direction are connected via the branch.

2. The array substrate according to claim 1, characterized in that: The pixel circuit includes a gate reset transistor and an anode reset transistor, the first semiconductor portion includes a first end and a second end, the first electrode of the gate reset transistor is connected to the first end, the first electrode of the anode reset transistor is connected to the second end, and of two first semiconductor portions adjacent to each other in the second direction, the first end of one first semiconductor portion and the second end of the other first semiconductor portion are connected via the branch; Preferably, in the second direction, the anode reset transistor of the i-th pixel circuit and the gate reset transistor of the i+1-th pixel circuit are adjacent; Preferably, the first semiconductor portion further comprises a gate connection point and an anode connection point, the gate connection point connects the second electrode of the gate reset transistor and the gate of the driving transistor, the anode connection point connects the second electrode of the anode reset transistor and the anode of the light emitting element, and the gate connection point and the anode connection point of two adjacent first semiconductor portions in the second direction are located on the same side of the branch; Preferably, the gate reset transistor is a dual-gate transistor.

3. The array substrate according to claim 1 or 2, characterized in that: The array substrate further includes: A reset signal line connected to the semiconductor connection portion through a first via hole; Preferably, the orthographic projection of the first via on the substrate and the orthographic projection of the connection point of the main body on the substrate at least partially overlap, and the orthographic projection of the branch on the substrate and the orthographic projection of the connection point of the main body on the substrate at least partially overlap.

4. The array substrate according to claim 3, characterized in that: The array substrate comprises a semiconductor layer, a first metal layer, a second metal layer and a third metal layer which are stacked, the reset signal line is located in the second metal layer, and the reset signal line extends along the first direction; Preferably, the second metal layer further comprises a first plate of a capacitor in the pixel circuit; Preferably, the first pole plates adjacent to each other in the first direction are connected to each other; Preferably, the third metal layer includes a data line, and the data line extends along the second direction; Preferably, the third metal layer comprises a power line, and the power line extends along the second direction.

5. The array substrate according to claim 3, characterized in that: The array substrate comprises a semiconductor layer, a first metal layer, a second metal layer and a third metal layer which are stacked, the reset signal line is located in the third metal layer, and the reset signal line extends along the second direction; Preferably, the third metal layer includes a data line, and the data line extends along the second direction; Preferably, the third metal layer comprises a power line, and the power line extends along the second direction; Preferably, the second metal layer comprises a first plate of a capacitor in the pixel circuit; Preferably, the first pole plates adjacent to each other in the first direction are connected to each other.

6. The array substrate according to claim 3, characterized in that: The array substrate comprises an auxiliary metal layer, a semiconductor layer, a first metal layer, a second metal layer and a third metal layer which are stacked, and the reset signal line is located in the auxiliary metal layer; Preferably, the reset signal line includes a first branch line and a second branch line, the first branch line extends along the first direction, and the second branch line extends along the second direction; Preferably, the second metal layer comprises a first plate of a capacitor in the pixel circuit; Preferably, the first pole plates adjacent to each other in the first direction are connected to each other; Preferably, the third metal layer includes a data line, and the data line extends along the second direction; Preferably, the third metal layer comprises a power line, and the power line extends along the second direction.

7. The array substrate according to claim 2, characterized in that: The branch comprises a first branch and a second branch, the first branch is connected to the first end, the second branch is connected to the second end, and the orthographic projection of the first branch on the substrate and the orthographic projection of the second branch on the substrate are on the same straight line; Preferably, the active layer of the gate reset transistor comprises a first active layer and a second active layer connected to each other, the first active layer is connected to the second branch, the second active layer is connected to the gate connection point, the first active layer extends along the second direction, and the second active layer extends along the first direction; Preferably, an orthographic projection of the first active layer on the substrate and an orthographic projection of the second branch on the substrate are on the same straight line.

8. The array substrate according to claim 1 or 2, characterized in that: The branch comprises a first branch and a second branch, the first branch is connected to the first end, the second branch is connected to the second end, and the orthographic projection of the first branch on the substrate and the orthographic projection of the second branch on the substrate are on different straight lines; Preferably, the active layer of the gate reset transistor comprises a first active layer and a second active layer connected to each other, the first active layer is connected to the second branch, the second active layer is connected to the gate connection point, and the orthographic projection of the first active layer on the substrate and the orthographic projection of the second active layer on the substrate are on the same straight line; Preferably, an orthographic projection of the first active layer on the substrate and an orthographic projection of the second branch on the substrate are on the same straight line.

9. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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