Display panel and display module

Abstract

The invention discloses a display panel and a display module, and belongs to the technical field of display. The display panel comprises a substrate, a plurality of sub-pixels and a gate drive circuit, the plurality of sub-pixels are positioned on one side of the substrate and are distributed in the display area; the gate drive circuit is located on one side of the substrate and located in the non-display area; the gate drive circuit comprises a plurality of gate drive units and a plurality of connection signal lines. Wherein at least one connecting signal line in the plurality of connecting signal lines is a target connecting signal line, the target connecting signal line comprises a first sub-signal line and a second sub-signal line which are stacked, the first sub-signal line is closer to the substrate than the second sub-signal line, and the second sub-signal line is in lap joint with the first sub-signal line. According to the display panel, on the basis that the line width of the target connection signal line is not increased, the impedance of the target connection signal line is reduced in the mode that the first sub-signal line and the second sub-signal line are in lap joint, so that the signal load can be reduced, and the display effect of the display panel is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display module. Background Art

[0002] With the continuous development of Organic Light Emitting Diode (OLED) technology, the industry has placed increasingly higher demands on narrowing the borders of OLED display screens in recent years.

[0003] Typically, a display module (i.e., a display screen) may include: a display panel, and a driving component bound and connected to the display panel. The display panel has a display area and a non-display area, and the display panel includes: a plurality of sub-pixels located in the display area, and a gate driver on array (GOA) circuit located in the non-display area. Among them, the GateGOA circuit is a circuit for applying a drive scan signal (Gate signal) to the sub-pixels in the display panel.

[0004] In order to increase the screen-to-body ratio of the display module, it is necessary to reduce the width of the area in the display panel for setting the GOA circuit, which results in the line width of the signal line in the GOA circuit also needing to be reduced. When the line width of the signal line in the GOA circuit is too narrow, the impedance of the signal line in the GOA circuit is large, resulting in poor stability of the drive scanning signal applied by the GOA circuit to the sub-pixel, which in turn results in poor display effect of the display panel. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a display module, which can solve the problem that the frame of the existing display device is difficult to be further narrowed. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel having a display area and a non-display area located outside the display area; the display panel comprises: a substrate, a plurality of sub-pixels and a gate driving circuit;

[0007] The plurality of sub-pixels are located on one side of the substrate and distributed in the display area;

[0008] The gate driving circuit is located at one side of the substrate and in the non-display area; the gate driving circuit comprises: a plurality of gate driving units and a plurality of connection signal lines, one gate driving unit is electrically connected to a row of sub-pixels, and at least some of the plurality of gate driving units are connected via the plurality of connection signal lines;

[0009] Among them, at least one connecting signal line among the multiple connecting signal lines is a target connecting signal line, and the target connecting signal line includes: a first sub-signal line and a second sub-signal line arranged in a stacked manner, the first sub-signal line is closer to the substrate than the second sub-signal line, and the second sub-signal line overlaps the first sub-signal line.

[0010] Optionally, in a direction perpendicular to an extension direction of the target connection signal line and parallel to the substrate, a width of the first sub-signal line is greater than or equal to a width of the second sub-signal line.

[0011] Optionally, the display panel further includes: an insulating protective layer;

[0012] The first sub-signal line is located on a side of the insulating protection layer facing the substrate, and the second sub-signal line is located on a side of the insulating protection layer facing away from the substrate;

[0013] The insulating protection layer has a hollow area; the orthographic projection of the hollow area on the substrate is located within the orthographic projection of the first sub-signal line on the substrate; and the second sub-signal line is overlapped with the first sub-signal line through the hollow area.

[0014] Optionally, for the hollow area between the first sub-signal line and the second sub-signal line distributed in the same target connection signal line, the hollow area includes a hollow groove and / or a plurality of hollow holes;

[0015] Among them, the extension direction of the hollow groove is the same as the extension direction of the target connection signal line; the arrangement direction of the plurality of hollow holes is the same as the extension direction of the target connection signal line.

[0016] Optionally, the insulating protection layer includes: an inorganic insulating layer and an organic insulating layer stacked together, and the inorganic insulating layer is closer to the substrate than the organic insulating layer;

[0017] Wherein, at least one of the inorganic insulating layer and the organic insulating layer has the hollow area.

[0018] Optionally, in the case where the hollow area includes the hollow groove, the hollow groove includes: a first sub-hollow groove penetrating the inorganic insulating layer, and a second sub-hollow groove penetrating the organic insulating layer, and the first sub-hollow groove is connected to the second sub-hollow groove;

[0019] Among them, the orthographic projection of the second sub-hollow groove on the substrate is located within the orthographic projection of the first sub-hollow groove on the substrate.

[0020] Optionally, in a direction perpendicular to an extension direction of the target connection signal line and parallel to the substrate, a minimum width of the second sub-hollow groove is smaller than a minimum width of the first sub-hollow groove.

[0021] Optionally, when the hollow area includes the plurality of hollow holes, the hollow holes include: a first sub-hollow hole penetrating the inorganic insulating layer, and a second sub-hollow hole penetrating the organic insulating layer, and the first sub-hollow hole is connected to the second sub-hollow hole;

[0022] The orthographic projection of the first sub-hollow hole on the substrate is located within the orthographic projection of the second sub-hollow hole on the substrate.

[0023] Optionally, in a direction perpendicular to an extension direction of the target connection signal line and parallel to the substrate, a minimum width of the second sub-hollow hole is greater than a minimum width of the first sub-hollow hole.

[0024] Optionally, in the case where the hollow area includes the hollow groove and the plurality of hollow holes, the hollow area includes: a hollow groove penetrating the inorganic insulating layer, and a plurality of hollow holes penetrating the organic insulating layer, and the hollow groove is connected to the plurality of hollow holes;

[0025] The orthographic projection of the hollow groove on the substrate overlaps with the orthographic projection of the plurality of hollow holes on the substrate; in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the hollow groove is smaller than the minimum width of the hollow hole.

[0026] Optionally, the inorganic insulating layer has a first climbing portion on a side facing the hollow area; the angle between the climbing slope of the first climbing portion and a side of the inorganic insulating layer facing the substrate is an acute angle; the orthographic projection of the first climbing portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate;

[0027] And / or, the organic insulating layer has a second climbing portion on the side facing the hollow area; the angle between the climbing slope of the second climbing portion and the side of the organic insulating layer facing the substrate is an acute angle; a part of the orthographic projection of the second climbing portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate, and the other part is located outside the orthographic projection of the first sub-signal line on the substrate.

[0028] Optionally, when the line width of the target connection signal line is greater than or equal to a first line width threshold, the hollow area includes the hollow groove;

[0029] In the case where the line width of the target connection signal line is greater than or equal to the second line width threshold and less than the first line width threshold, the hollow area includes the plurality of hollow holes, or the hollow area includes the hollow groove and the plurality of hollow holes;

[0030] In a case where the line width of the target connection signal line is less than a second line width threshold, the hollow area includes the plurality of hollow holes;

[0031] The first line width threshold is greater than or equal to the second line width threshold.

[0032] Optionally, when the line width of the target connection signal line is greater than or equal to a third line width threshold and less than the first line width threshold, the long side direction of the hollow hole is perpendicular to the extension direction of the target connection signal line;

[0033] When the line width of the target connection signal line is less than the third line width threshold, the long side direction of the hollow hole is parallel to the extension direction of the target connection signal line;

[0034] The second line width threshold is greater than the third line width threshold.

[0035] Optionally, the target connection signal line includes at least one signal line among a row drive clock signal line, a clock signal line and a power signal line.

[0036] On the other hand, a display module is provided, comprising: any one of the display panels described above, and a driving component bound and connected to the display panel.

[0037] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0038] At least one target connection signal line is set in the connection signal line of the gate driving circuit, and the target connection signal line includes a first sub-signal line and a second sub-signal line which are stacked. On the basis of not increasing the line width of the target connection signal line, the impedance of the target connection signal line can be reduced by overlapping the first sub-signal line and the second sub-signal line, thereby reducing the signal load, improving the stability of the driving scanning signal applied by the gate driving circuit to the sub-pixel, and ensuring the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0041] Figure 2 for Figure 1 The schematic diagram of the film structure of the display panel at AA' is shown;

[0042] Figure 3 A schematic diagram of a hollow area provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of the preparation process of the insulating protective layer provided in the embodiment of the present application;

[0044] Figure 5 for Figure 1 A schematic diagram of the film layer structure of another display panel at AA' is shown;

[0045] Figure 6 A schematic diagram of another hollow area provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of a preparation process of another insulating protective layer provided in an embodiment of the present application;

[0047] Figure 8 for Figure 1 A schematic diagram of the film structure of another display panel at AA' is shown;

[0048] Fig. 9 A schematic diagram of another hollow area provided in an embodiment of the present application;

[0049] Fig.10 A schematic diagram of a preparation process of another insulating protective layer provided in an embodiment of the present application;

[0050] Fig.11 for Figure 1 A schematic diagram of the film layer structure of a display panel at AA' in another embodiment is shown;

[0051] Fig.12 for Figure 1 A schematic diagram of a film layer structure of another display panel at AA' in another embodiment is shown;

[0052] Fig.13 A schematic diagram of a hollow area provided in an embodiment of the present application as a hollow hole;

[0053] Fig.14 A schematic diagram of another hollow area provided in an embodiment of the present application as a hollow hole;

[0054] Fig.15 for Figure 1 A schematic diagram of the film layer structure of the display panel at BB' is shown;

[0055] Fig.16 This is a schematic diagram of the structure of the display module provided in this application. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0057] The present application embodiment provides a display panel. Figure 1 and Figure 2 , Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application, Figure 2 for Figure 1 The display panel 00 has a display area 02 and a non-display area 01 located outside the display area 02 ; the display panel 00 may include: a substrate 10 , a plurality of sub-pixels 20 and a gate driving circuit 30 .

[0058] A plurality of sub-pixels 20 are located on one side of the substrate 10 and distributed in the display area 02 .

[0059] The gate driving circuit 30 is located on one side of the substrate 10 and in the non-display area 01; the gate driving circuit 30 may include: multiple gate driving units 31 and multiple connecting signal lines 32, one gate driving unit 31 is electrically connected to a row of sub-pixels 20, and at least some of the multiple gate driving units 31 are connected through multiple connecting signal lines 32.

[0060] Among them, at least one connecting signal line 32 among the multiple connecting signal lines 32 is a target connecting signal line 320, and the target connecting signal line 320 may include: a first sub-signal line 321 and a second sub-signal line 322 arranged in a stacked manner, the first sub-signal line 321 is closer to the substrate 10 than the second sub-signal line 322, and the second sub-signal line 322 overlaps the first sub-signal line 321.

[0061] Exemplarily, the gate driving circuit 30 may include a plurality of gate driving units 31 arranged in cascade, and the gate driving circuit 30 has two functions. One function is an output function, that is, the gate driving circuit 30 can output a gate scanning driving signal to the sub-pixel 20, and the gate scanning driving signal can be used to drive the sub-pixel 20 circuit, thereby achieving the effect of driving the sub-pixel 20 to emit light. The other function is a shift register function. The driving circuit includes a plurality of gate driving units 31 arranged in cascade, and the plurality of gate driving units 31 can adopt a step-by-step shifting method to transmit the shift signal from the first-stage gate driving unit 31 downward. The cascade relationship of the plurality of gate driving units 31 can be specifically determined by the circuit structure of the gate driving unit 31, and the embodiment of the present application does not limit this.

[0062] In the embodiment of the present application, at least one target connection signal line is set in the connection signal line of the gate drive circuit, and the target connection signal line includes a first sub-signal line and a second sub-signal line which are stacked. On the basis of not increasing the line width of the target connection signal line, the impedance of the target connection signal line can be reduced by overlapping the first sub-signal line and the second sub-signal line, thereby reducing the signal load, improving the stability of the drive scanning signal applied by the gate drive circuit to the sub-pixel, and ensuring the display effect of the display panel. Moreover, the line width of the target connection signal line can be further reduced, which can reduce the width occupied by the gate drive circuit in the non-display area, so that the non-display area can be further narrowed, and the screen ratio of the display mode can be improved.

[0063] In some possible implementations, in a direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to Figure 2 In the X direction in FIG. 1 , the width of the first sub-signal line 321 is greater than or equal to the width of the second sub-signal line 322 .

[0064] To ensure a narrow frame, the width of the second sub-signal line 322 is less than or equal to the width of the first sub-signal line 321 so that the width of the target connection signal line 320 will not increase, ensuring that the width occupied by the gate driving circuit 30 in the non-display area 01 will not increase.

[0065] In some possible implementations, the display panel 00 may further include: an insulating protective layer 40 ; a first sub-signal line 321 located on a side of the insulating protective layer 40 facing the substrate 10 , and a second sub-signal line 322 located on a side of the insulating protective layer 40 facing away from the substrate 10 .

[0066] The insulating protection layer 40 has a hollow area 400 ; the orthographic projection of the hollow area 400 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10 ; and the second sub-signal line 322 overlaps the first sub-signal line 321 through the hollow area 400 .

[0067] Generally, the connection signal line 32 in the display panel 00 adopts a stacked titanium-aluminum-titanium three-layer metal layer structure, in which the aluminum metal layer is exposed on the side of the connection signal line 32. In some patterning processes, the aluminum metal layer will react with part of the etchant to form a side depression phenomenon (or called drilling), which will affect the conductivity of the signal line. Therefore, the first sub-signal line 321 is formed earlier than the second sub-signal line 322. In the subsequent process of the display panel 00, in order to protect the side of the first sub-signal line 321, it is necessary to use an insulating protective layer 40 to protect the side of the first sub-signal line 321. In order to ensure the protection effect, the edge of the first sub-signal line 321 also needs to be coated. Then, there will be an insulating protective layer 40 between the first sub-signal line 321 and the second sub-signal line 322. In order to achieve the overlap between the second sub-signal line 322 and the first sub-signal line 321, the insulating protective layer 40 needs to be provided with a hollow area 400 to achieve the above-mentioned overlap, and the orthographic projection of the hollow area 400 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10. In other words, it is ensured that the edge of the first sub-signal line 321 is covered by the insulating protective layer 40, and the side of the first sub-signal line 321 will not be exposed.

[0068] In some possible implementations, for the hollow area 400 between the first sub-signal line 321 and the second sub-signal line 322 distributed in the same target connection signal line 320 , the hollow area 400 may include a hollow groove and / or a plurality of hollow holes.

[0069] The extending direction of the hollow groove is the same as the extending direction of the target connection signal line 320 ; and the arrangement direction of the plurality of hollow holes is the same as the extending direction of the target connection signal line 320 .

[0070] In the embodiment of the present application, a hollow groove and / or multiple hollow holes can be selected according to the width of the target connection signal line 320 to achieve the overlap of the second sub-signal line 322 and the first sub-signal line 321, so that the second sub-signal line 322 and the first sub-signal line 321 are effectively overlapped, thereby reducing the impedance of the target connection signal line 320.

[0071] In the embodiment of the present application, the insulating protection layer 40 between the first sub-signal line 321 and the second sub-signal line 322 may include at least one of an organic insulating layer 42 and an inorganic insulating layer 41 .

[0072] Some possible implementation methods include Figure 2 As shown, the insulating protection layer 40 may include: an inorganic insulating layer 41 and an organic insulating layer 42 which are stacked, and the inorganic insulating layer 41 is closer to the substrate 10 than the organic insulating layer 42 .

[0073] At least one of the inorganic insulating layer 41 and the organic insulating layer 42 has a hollow region 400. For example, the inorganic insulating layer 41 may be a passivation layer in the display panel 00, and the organic insulating layer 42 may be a first planar layer in the display panel 00.

[0074] For some possible implementations, see Figure 3 to Figure 4 , Figure 3 A schematic diagram of a hollow area provided in an embodiment of the present application, Figure 4 The schematic diagram of the preparation process of the insulating protection layer provided in the embodiment of the present application shows that, when the hollow area 400 may include a hollow groove, the hollow groove may include: a first sub-hollow groove 411 penetrating the inorganic insulating layer 41, and a second sub-hollow groove 421 penetrating the organic insulating layer 42. The first sub-hollow groove 411 is connected to the second sub-hollow groove 421.

[0075] Among them, the orthographic projection of the second sub-hollow groove 421 on the substrate 10 is located within the orthographic projection of the first sub-hollow groove 411 on the substrate 10.

[0076] For example, Figure 4 As shown, an inorganic insulating layer 41 covering the first sub-signal line 321 is first formed, and the inorganic insulating layer 41 is patterned to form a first sub-hollow groove 411; then an organic insulating layer 42 covering the inorganic insulating layer 41 is formed, and the organic insulating layer 42 is patterned to form a second sub-hollow groove 421.

[0077] Taking the example of the organic insulating layer 42 made of photosensitive organic materials, in the process of patterning the organic insulating layer 42, the organic insulating layer 42 can be exposed using a mask, and then the exposed organic insulating layer 42 is developed, so that the pattern on the mask can be transferred to the organic insulating layer 42 to achieve patterning of the organic insulating layer 42. However, there is a certain numerical deviation between the pattern actually processed on the organic insulating layer 42 and the designed pattern on the mask, which is CD Bias. In the process of patterning the inorganic insulating layer 41, it cannot be formed directly through the exposure-development process. It is necessary to first transfer the mask pattern to the photoresist, and then etch and remove the excess part through the etching process. Therefore, the CD Bias of the inorganic insulating layer 41 is the sum of the CD Bias generated by the exposure and development of the photoresist and the etching of the inorganic insulating layer 41.

[0078] In addition, in the process of patterning the organic insulating layer 42 to form the second sub-hollow groove 421, the extension direction ( Figure 4There is no mask to block the light in the Y direction), and there is light leakage at the edge. The optical path of the light is complex and changeable, resulting in enhanced light effect in the X direction. Therefore, a photosensitive material is used as the organic insulating layer 42. In the X direction, the CD Bias of the second sub-hollow groove 421 will increase and may be greater than the CD Bias of the first sub-hollow groove 411 formed on the inorganic insulating layer 41.

[0079] Therefore, the orthographic projection of the second sub-hollow groove 421 on the substrate 10 needs to be located within the orthographic projection of the first sub-hollow groove 411 on the substrate 10 to ensure that there is enough organic insulating layer 42 to cover the edge of the first sub-signal line 321 .

[0080] In some possible implementations, in a direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to Figure 3 and Figure 4 In the X direction), the minimum width of the second sub-hollow groove 421 is smaller than the minimum width of the first sub-hollow groove 411.

[0081] like Figure 3 As shown, in the exposure process, the current optical system cannot irradiate the light strictly vertically onto the mask and project it onto the substrate, and the deviation of the light in the vertical direction causes the pattern boundary of the organic layer or inorganic layer actually produced to be not horizontal and vertical, but a slope with a certain inclination angle. Therefore, the widths of the second sub-hollow groove 421 and the first sub-hollow groove 411 are gradual. In order to ensure that the orthographic projection of the second sub-hollow groove 421 on the substrate 10 is within the orthographic projection of the first sub-hollow groove 411 on the substrate 10, it is necessary to ensure that the minimum width of the second sub-hollow groove 421 is smaller than the minimum width of the first sub-hollow groove 411.

[0082] For some possible implementations, see Figures 5 to 7 , Figure 5 for Figure 1 Another schematic diagram of the film structure of a display panel at AA' is shown. Figure 6 A schematic diagram of another hollow area provided in an embodiment of the present application, Figure 7 A schematic diagram of another process flow for preparing an insulating protective layer provided in an embodiment of the present application. In the case where the hollow area 400 may include a plurality of hollow holes, the hollow holes may include: a first sub-hollow hole 412 penetrating the inorganic insulating layer 41, and a second sub-hollow hole 422 penetrating the organic insulating layer 42, the first sub-hollow hole 412 being connected to the second sub-hollow hole 422.

[0083] The orthographic projection of the first sub-hollow hole 412 on the substrate 10 is located within the orthographic projection of the second sub-hollow hole 422 on the substrate 10 .

[0084] For example, Figure 7As shown, an inorganic insulating layer 41 covering the first sub-signal line 321 is first formed, and the inorganic insulating layer 41 is patterned to form a plurality of first sub-hollow holes 412; then an organic insulating layer 42 covering the inorganic insulating layer 41 is formed, and the organic insulating layer 42 is patterned to form a plurality of second sub-hollow holes 422.

[0085] When the second sub-hollow hole 422 is patterned on the organic insulating layer 42, the photosensitive organic material extends in the extension direction of the second sub-hollow hole 422 ( Figure 7 The Y direction in the figure is blocked by a mask template, and the light leakage at the edge is very small, so a photosensitive material is used as the organic insulating layer 42 to prepare the second sub-hollow hole 422. The CD Bias of the second sub-hollow groove 421 is much smaller, and the CD Bias of the second sub-hollow hole 422 is smaller than the CD Bias of the first sub-hollow hole 421. Therefore, the width of the second sub-hollow hole 422 can be greater than the width of the first sub-hollow hole 421. In this way, the overlap area through the second sub-hollow hole 422 is larger.

[0086] Some possible implementation methods include Figure 6 As shown, in a direction perpendicular to the extending direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to Figure 6 In the X direction), the minimum width of the second sub-hollow hole 422 is greater than the minimum width of the first sub-hollow hole 412.

[0087] Since the widths of the second sub-hollow hole 422 and the first sub-hollow hole 412 are gradual, in order to ensure that the orthographic projection of the first sub-hollow hole 412 on the substrate 10 is located within the orthographic projection of the second sub-hollow hole 422 on the substrate 10, it is necessary to ensure that the minimum width of the second sub-hollow groove 421 is greater than the minimum width of the first sub-hollow groove 411.

[0088] For some possible implementations, see Figures 8 to 10 , Figure 8 for Figure 1 A schematic diagram of the film structure of another display panel at line AA' is shown. Fig. 9 A schematic diagram of another hollow area provided in an embodiment of the present application, Fig.10 A schematic diagram of the preparation process of another insulating protective layer provided in an embodiment of the present application, in the case where the hollow area 400 may include a hollow groove 401 and a plurality of hollow holes 402, the hollow area 400 may include: a hollow groove 401 penetrating the inorganic insulating layer 41, and a plurality of hollow holes 402 penetrating the organic insulating layer 42, and the hollow groove 401 is connected to the plurality of hollow holes 402.

[0089] The orthographic projection of the hollow groove 401 on the substrate 10 overlaps with the orthographic projection of the plurality of hollow holes 402 on the substrate 10; in a direction perpendicular to the extension direction of the target connection signal line 320 and parallel to the substrate 10 (corresponding to Figures 8 to 10 The minimum width of the hollow groove 401 is smaller than the minimum width of the hollow hole 402.

[0090] When the inorganic insulating layer 41 is etched with the hollow groove 401, the inorganic insulating layer 41 is generally very thin, and the thickness of the photoresist required is also very thin. The phenomenon that the CD Bias in the X direction increases due to no shielding in the Y direction is very small, and the CD Bias generated by the above phenomenon can be ignored. Therefore, the hollow groove 401 can be formed in the inorganic insulating layer 41. Therefore, the hollow area 400 can include: the hollow groove 401 penetrating the inorganic insulating layer 41, and a plurality of hollow holes 402 are still formed in the organic insulating layer 42.

[0091] In this way, compared with Figures 5 to 7 The hollow area 400 shown in the figure uses the first sub-hollow groove 411 and the second sub-hollow groove 421. Figures 8 to 10 The hollow area 400 shown in the figure, which uses the hollow groove 401 and the plurality of hollow holes 402, has a larger spatial volume and can provide a better overlapping effect.

[0092] Some possible implementation methods include Figure 2 , Figure 5 and Figure 8 As shown, the side of the inorganic insulating layer 41 facing the hollow area 400 has a first climbing portion 413; the angle between the climbing slope of the first climbing portion 413 and the side of the inorganic insulating layer 41 facing the substrate 10 is an acute angle; the orthographic projection of the first climbing portion 413 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10.

[0093] And / or, the side of the organic insulating layer 42 facing the hollow area 400 has a second climbing portion 423; the angle between the climbing slope of the second climbing portion 423 and the side of the organic insulating layer 42 facing the substrate 10 is an acute angle; a part of the orthographic projection of the second climbing portion 423 on the substrate 10 is located inside the orthographic projection of the first sub-signal line 321 on the substrate 10, and another part is located outside the orthographic projection of the first sub-signal line 321 on the substrate 10. In addition, the orthographic projection of the second climbing portion 423 on the substrate 10 can also be inside the orthographic projection on the substrate 10.

[0094] As mentioned above, the boundary of the organic insulating layer 42 after the actual process is a gentle slope with a gradual thickness change, and the climbing distance is positively correlated with the thickness of the glue coating. There is also a gentle slope at the boundary of the inorganic insulating layer 41, because this gentle slope is formed by the etching process, and the etching reaction is isotropic, and the climbing distance is close to the vertical etching depth. The thickness of the inorganic insulating layer 41 is less than that of the organic insulating layer 42, so the climbing distance of the inorganic insulating layer 41 is much smaller than that of the organic insulating layer 42. Since the thickness of the organic insulating layer 42 is relatively large, the reference value is 1.2 microns to 1.7 microns, and the second climbing portion 423 can be used for the boundary coating of the first sub-signal line 321, as long as the actual coating thickness is guaranteed to be above 0.5 microns. The thickness of the inorganic insulating layer 41 is relatively thin, and the reference value is 0.3 microns to 0.5 microns. The first climbing portion 413 needs to avoid the boundary of the first sub-signal line 321. When only the inorganic insulating layer 41 is used as the insulating protection layer 40 , the thickness of the inorganic insulating layer 41 can be appropriately increased to be above 0.5 microns.

[0095] like Figure 2 , Figure 5 and Figure 8 As shown, the second climbing portion 423 of the organic insulating layer 42 is thicker overall and can be used to protect the edge of the first sub-signal line 321, while the first climbing portion 413 of the inorganic insulating layer 41 is thinner and needs to avoid covering the edge of the first sub-signal line 321. Therefore, the width a of the edge of the first sub-signal line 321 covered by the inorganic insulating layer 41 needs to be greater than the width of the first climbing portion 413, and the width b of the edge of the first sub-signal line 321 covered by the organic insulating layer 42 can be smaller than the width of the second climbing portion 423.

[0096] For some possible implementations, see Figure 11 to Figure 12 , Fig.11 for Figure 1 A schematic diagram of the film structure of a display panel at line AA' in another embodiment is shown, Fig.12 for Figure 1 In another embodiment, another display panel at AA′ is shown as a schematic diagram of a film structure. The insulating protection layer 40 between the first sub-signal line 321 and the second sub-signal line 322 may include only one of an organic insulating layer 42 and an inorganic insulating layer 41 .

[0097] like Fig.11 As shown, only the inorganic insulating layer 41 may be used to protect the first signal sub-line 321 , and the orthographic projection of the first climbing portion 413 of the inorganic insulating layer 41 on the substrate 10 is located within the orthographic projection of the first signal sub-line 321 on the substrate 10 .

[0098] Exemplarily, the display panel 00 may include an organic insulating layer 42 covering the inorganic insulating layer 41 , but the organic insulating layer 42 in a region near the target connection signal line 320 is removed.

[0099] like Fig.12 As shown, only the organic insulating layer 42 may be used to protect the first sub-signal line 321, and a portion of the orthographic projection of the second climbing portion 423 of the organic insulating layer 42 on the substrate 10 is located within the orthographic projection of the first sub-signal line 321 on the substrate 10, and another portion is located outside the orthographic projection of the first sub-signal line 321 on the substrate 10. In addition, the orthographic projection of the second climbing portion 423 on the substrate 10 may also be within the orthographic projection on the substrate 10.

[0100] Exemplarily, the display panel 00 may not include the inorganic insulating layer 41 , and the organic insulating layer 42 directly covers the substrate 10 and the first sub-signal line 321 .

[0101] In the embodiment of the present application, corresponding to the target connection signal line 320 with different line widths, it is necessary to adopt a corresponding hollow area 400 design to realize the overlap of the second sub-signal line 322 and the first sub-signal line 321, so as to achieve the basis of ensuring that the line width does not increase and the hollow area 400 does not expose the side of the first sub-signal line 321, which is described in detail below.

[0102] In some possible implementations, when the line width of the target connection signal line 320 is greater than or equal to the first line width threshold, the hollow area 400 may include a hollow groove.

[0103] When the line width of the target connection signal line 320 is greater than or equal to the second line width threshold and less than the first line width threshold, the hollow area 400 may include a plurality of hollow holes, or the hollow area 400 may include a hollow groove and a plurality of hollow holes.

[0104] In the case where the line width of the target connection signal line 320 is less than the second line width threshold, the hollow area 400 may include a plurality of hollow holes.

[0105] The first line width threshold is greater than or equal to the second line width threshold. For example, the first line width threshold is 9 micrometers, and the second line width threshold is 7 micrometers.

[0106] For example, Figure 2As shown, in the case of adopting the hollow groove solution, an empirical value of the coverage value a of the inorganic insulating layer 41 on the first sub-signal line 321 is 1.5 microns, and an empirical value of the coverage value b of the organic insulating layer 42 on the first sub-signal line 321 is 2.5 microns, and the width c of the second sub-hollow groove 421 of the organic insulating layer 42 is at least 4 microns according to mass production experience. In this way, the minimum width D of the first sub-signal line 321 can be obtained as 2b+c=9 microns, which can simultaneously meet the requirements of the hemming and overlapping of the insulating protection layer 40.

[0107] like Figure 5 As shown, in the case of using a plurality of hollow holes, an empirical value of the coverage value a of the inorganic insulating layer 41 on the first sub-signal line 321 is 1.5 microns, an empirical value of the coverage value b of the organic insulating layer 42 on the first sub-signal line 321 is 1.35 microns, and the width c of the second hollow hole of the organic insulating layer 42 is at least 3 microns according to mass production experience. In this way, the minimum width D of the first sub-signal line 321 can be obtained as 2b+c=6.7 microns.

[0108] like Figure 8 As shown, in the case of adopting the hollow groove 401 and the plurality of hollow holes 402, an empirical value of the coverage value a of the inorganic insulating layer 41 on the first sub-signal line 321 is 1.5 microns, and an empirical value of the coverage value b of the organic insulating layer 42 on the first sub-signal line 321 is 1.35 microns, and the width d of the hollow groove 401 of the inorganic insulating layer 41 is at least 4 microns according to mass production experience. In this way, the minimum width D of the first sub-signal line 321 can be obtained as 2a+d=7 microns.

[0109] Therefore, when the line width of the target connection signal line 320 is greater than or equal to the second line width threshold (such as 7 microns), the hollow area 400 may include a plurality of hollow holes, or the hollow area 400 may include a hollow groove and a plurality of hollow holes. Figure 5 or Figure 8 The scheme shown.

[0110] That is, when the line width of the target connection signal line 320 is greater than or equal to 9 microns, the hollow area 400 may include a hollow groove. When the line width of the target connection signal line 320 is greater than or equal to 7 microns and less than 9 microns, the hollow area 400 may include a plurality of hollow holes, or the hollow area 400 may include a hollow groove and a plurality of hollow holes. When the line width of the target connection signal line 320 is less than 7 microns, the hollow area 400 may include a plurality of hollow holes.

[0111] For some possible implementations, see Figure 13 to Figure 14 , Fig.13 A schematic diagram of a hollow area provided in an embodiment of the present application as a hollow hole; Fig.14Another schematic diagram of another hollow area provided in the embodiment of the present application is a hollow hole. When the hollow area includes a plurality of hollow holes, the hollow hole can be rectangular, and the hollow hole has a long side x and a short side y. When the line width of the target connection signal line 320 is greater than or equal to the third line width threshold and less than the first line width threshold, the long side direction of the hollow hole is perpendicular to the extension direction of the target connection signal line 320 (such as Fig.13 and Fig.14 Y direction in ).

[0112] When the line width of the target connection signal line 320 is smaller than the third line width threshold, the long side direction of the hollow hole is parallel to the extension direction of the target connection signal line 320 .

[0113] The second line width threshold is greater than the third line width threshold. For example, the third line width threshold is 6.7 micrometers.

[0114] When the line width of the target connection signal line 320 is less than the second line width threshold, only the technical solution that the hollow area 400 can include a plurality of hollow holes can be adopted, that is, Figure 5 In the case where the hollow holes are rectangular holes, the orientation of the hollow holes can be adjusted according to the line width of the target connection signal line 320, so that when the line width of the target connection signal line 320 is greater than or equal to the third line width threshold and less than the first line width threshold, the density of the hollow holes in the target connection signal line 320 is higher, achieving a better overlap effect.

[0115] For example, Fig.13 and Fig.14 As shown, in Fig.13 In the example, the line width of a target connection signal line 320 is 7 microns. Fig.14 , the line width of another target connection signal line 320 is 6.5 microns, the minimum size of the hollow hole is 3 microns × 4 microns, and the spacing distance between the hollow holes is equal. Under the premise of the same length, when the line width of the target connection signal line 320 is greater than or equal to the third line width threshold and less than the first line width threshold, the long side direction of the hollow hole is perpendicular to the extension direction of the target connection signal line 320, and 3 hollow holes can be arranged; and when the line width of the target connection signal line 320 is less than the third line width threshold, the long side direction of the hollow hole is parallel to the extension direction of the target connection signal line 320, and only 2 hollow holes can be arranged at this time. It can be seen that the short side of the hollow hole is parallel to the extension direction of the signal line, and more hollow holes can be placed to increase the overlap area compared to the long side parallel to the extension direction. In the case where the long side of the hollow hole is parallel to the extension direction of the signal line, although the overlap area is small, the line width of the signal line needs to be narrower, which is conducive to further narrowing the width occupied by the gate drive circuit 30.

[0116] In some possible implementations, the target connection signal line 320 may include at least one of a row driving clock signal line, a clock signal line, and a power signal line.

[0117] Among them, the row drive clock signal line can also be a GSTV signal line, the clock signal line is generally designed in pairs, including a GCB signal line and a GCK signal line, and the power signal line can include a high level signal line (VGH signal line) and a low level signal line (VGL signal line). The design scheme of the target connection signal line 320 provided in the embodiment of the present application can be applied to any of the above signal lines.

[0118] Please refer to Fig.15 , Fig.15 for Figure 1 The schematic diagram of the film layer structure of the display panel at BB' is shown. In the embodiment of the present application, the display panel may include: a substrate 10, and an active layer 2003, a first gate insulating layer 2004, a first conductive layer (arranged in the same layer as the first electrode 2006 and the gate layer 2005 and made of the same material), a passivation layer 2007, a second conductive layer (arranged in the same layer as the second electrode 2008 and made of the same material), an interlayer dielectric layer 2100, a third conductive layer 4000, a first flat layer 6000, a fourth conductive layer 7000, an organic flat layer 8000, an anode layer 3001, a pixel definition layer 3004, a light-emitting layer 3002, a supporting layer 3005, a cathode layer 3003, an encapsulation layer 9002, a touch electrode layer 9001 and an organic touch protection layer 9000.

[0119] Among them, the active layer 2003, the gate layer 2005, the first conductive layer, the third conductive layer 4000, and the fourth conductive layer 7000 are used to form a plurality of pixel driving circuits 2000 electrically connected to the light-emitting device 3000, and various signal lines electrically connected to the pixel driving circuits 2000. The light-emitting device 3000 includes: an anode layer 3001, a light-emitting layer 3002, and a cathode layer 3003 that are stacked. The pixel driving circuit 2000 can be electrically connected to the anode layer 3001 in the light-emitting device 3000.

[0120] A pixel driving circuit 2000 may include at least two transistors and a storage capacitor, the third conductive layer 4000 may include the drain and drain of the transistor, the first conductive layer may include the gate layer 2005 of the transistor and the first plate 2006 of the storage capacitor, and the second conductive layer may include the second plate 2008 of the storage capacitor.

[0121] In an embodiment of the present application, when the insulating protection layer 40 includes an inorganic insulating layer 41 and an organic insulating layer 42, the first sub-signal line 321 can be set on the same layer as the first conductive layer or one of the second conductive layers, the second sub-signal line 322 can be set on the same layer as the fourth conductive layer 7000, the inorganic insulating layer 41 can be set on the same layer as the passivation layer 2007 or one of the interlayer dielectric layers 2100, and the organic insulating layer 42 can be set on the same layer as the first planarizing layer 6000.

[0122] When the insulating protection layer 40 only includes the organic insulating layer 42, the first sub-signal line 321 can be set on the same layer as the first conductive layer, the second conductive layer or the third conductive layer 4000; the second sub-signal line 322 can be set on the same layer as the third conductive layer 4000 or the fourth conductive layer 7000. When the first sub-signal line 321 is set on the same layer as the third conductive layer 4000, the second sub-signal line 322 is set on the same layer as the fourth conductive layer 7000; the organic insulating layer 42 can be set on the same layer as the first planarizing layer 6000.

[0123] When the insulating protection layer 40 only includes the organic insulating layer 41, the first sub-signal line 321 can be set on the same layer as one of the first conductive layer or the second conductive layer; the second sub-signal line 322 can be set on the same layer as one of the third conductive layer 4000 or the fourth conductive layer 7000; the inorganic insulating layer 41 can be set on the same layer as one of the passivation layer 2007 or the interlayer dielectric layer 2100.

[0124] In summary, the display panel and display module provided in the embodiments of the present application include: a substrate, a plurality of sub-pixels, and a gate drive circuit. By setting at least one target connection signal line in the connection signal line of the gate drive circuit, the target connection signal line includes a first sub-signal line and a second sub-signal line that are stacked, and the impedance of the target connection signal line can be reduced by overlapping the first sub-signal line and the second sub-signal line without increasing the line width of the target connection signal line, thereby reducing the signal load, improving the stability of the drive scanning signal applied by the gate drive circuit to the sub-pixel, and ensuring the display effect of the display panel.

[0125] Please refer to Fig.16 , Fig.16 The structural diagram of the display module provided in the present application may include: the display panel 00 described in any of the above embodiments, and a driving component 50 bound and connected to the display panel 00. The driving component 50 may be electrically connected to the above connection signal line 32. The display module may have the technical effects of the above display panel 00, which will not be described again.

[0126] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0127] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0128] The above descriptions are merely embodiments of some possible implementations of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area and a non-display area located outside the display area; the display panel includes: a substrate, a plurality of sub-pixels and a gate driving circuit; The plurality of sub-pixels are located on one side of the substrate and distributed in the display area; The gate driving circuit is located at one side of the substrate and in the non-display area; the gate driving circuit comprises: a plurality of gate driving units and a plurality of connection signal lines, one gate driving unit is electrically connected to a row of sub-pixels, and at least some of the plurality of gate driving units are connected via the plurality of connection signal lines; Among them, at least one connecting signal line among the multiple connecting signal lines is a target connecting signal line, and the target connecting signal line includes: a first sub-signal line and a second sub-signal line arranged in a stacked manner, the first sub-signal line is closer to the substrate than the second sub-signal line, and the second sub-signal line overlaps the first sub-signal line.

2. The display panel according to claim 1, characterized in that: In a direction perpendicular to an extending direction of the target connection signal line and parallel to the substrate, a width of the first sub-signal line is greater than or equal to a width of the second sub-signal line.

3. The display panel according to claim 1, characterized in that: The display panel further includes: an insulating protection layer; The first sub-signal line is located on a side of the insulating protection layer facing the substrate, and the second sub-signal line is located on a side of the insulating protection layer facing away from the substrate; The insulating protection layer has a hollow area; the orthographic projection of the hollow area on the substrate is located within the orthographic projection of the first sub-signal line on the substrate; and the second sub-signal line is overlapped with the first sub-signal line through the hollow area.

4. The display panel according to claim 3, characterized in that: For a hollow area between the first sub-signal line and the second sub-signal line distributed in the same target connection signal line, the hollow area includes a hollow groove and / or a plurality of hollow holes; Among them, the extension direction of the hollow groove is the same as the extension direction of the target connection signal line; the arrangement direction of the plurality of hollow holes is the same as the extension direction of the target connection signal line.

5. The display panel according to claim 4, characterized in that: The insulating protection layer comprises: an inorganic insulating layer and an organic insulating layer stacked together, wherein the inorganic insulating layer is closer to the substrate than the organic insulating layer; Wherein, at least one of the inorganic insulating layer and the organic insulating layer has the hollow area.

6. The display panel according to claim 5, characterized in that: In the case where the hollow area includes the hollow groove, the hollow groove includes: a first sub-hollow groove penetrating the inorganic insulating layer, and a second sub-hollow groove penetrating the organic insulating layer, and the first sub-hollow groove is connected to the second sub-hollow groove; Among them, the orthographic projection of the second sub-hollow groove on the substrate is located within the orthographic projection of the first sub-hollow groove on the substrate.

7. The display panel according to claim 6, characterized in that: In a direction perpendicular to an extension direction of the target connection signal line and parallel to the substrate, a minimum width of the second sub-hollow groove is smaller than a minimum width of the first sub-hollow groove.

8. The display panel according to claim 5, characterized in that: In the case where the hollow area includes the plurality of hollow holes, the hollow holes include: a first sub-hollow hole penetrating the inorganic insulating layer, and a second sub-hollow hole penetrating the organic insulating layer, and the first sub-hollow hole is connected to the second sub-hollow hole; The orthographic projection of the first sub-hollow hole on the substrate is located within the orthographic projection of the second sub-hollow hole on the substrate.

9. The display panel according to claim 8, characterized in that: In a direction perpendicular to an extending direction of the target connection signal line and parallel to the substrate, a minimum width of the second sub-hollow hole is greater than a minimum width of the first sub-hollow hole.

10. The display panel according to claim 5, characterized in that: In the case where the hollow area includes the hollow groove and the plurality of hollow holes, the hollow area includes: a hollow groove penetrating the inorganic insulating layer, and a plurality of hollow holes penetrating the organic insulating layer, and the hollow groove is connected to the plurality of hollow holes; The orthographic projection of the hollow groove on the substrate overlaps with the orthographic projection of the plurality of hollow holes on the substrate; in a direction perpendicular to the extension direction of the target connection signal line and parallel to the substrate, the minimum width of the hollow groove is smaller than the minimum width of the hollow hole.

11. The display panel according to any one of claims 5 to 10, characterized in that: The inorganic insulating layer has a first climbing portion on one side facing the hollow area; the angle between the climbing slope of the first climbing portion and the side of the inorganic insulating layer facing the substrate is an acute angle; The orthographic projection of the first climbing portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate; And / or, the side of the organic insulating layer facing the hollow area has a second climbing portion; the angle between the climbing slope of the second climbing portion and the side of the organic insulating layer facing the substrate is an acute angle; A portion of the orthographic projection of the second climbing portion on the substrate is located within the orthographic projection of the first sub-signal line on the substrate, and another portion is located outside the orthographic projection of the first sub-signal line on the substrate.

12. The display panel according to any one of claims 4 to 10, characterized in that: In a case where the line width of the target connection signal line is greater than or equal to a first line width threshold, the hollow area includes the hollow groove; In the case where the line width of the target connection signal line is greater than or equal to the second line width threshold and less than the first line width threshold, the hollow area includes the plurality of hollow holes, or the hollow area includes the hollow groove and the plurality of hollow holes; In a case where the line width of the target connection signal line is less than a second line width threshold, the hollow area includes the plurality of hollow holes; The first line width threshold is greater than or equal to the second line width threshold.

13. The display panel according to claim 12, characterized in that: When the line width of the target connection signal line is greater than or equal to the third line width threshold and less than the first line width threshold, the long side direction of the hollow hole is perpendicular to the extension direction of the target connection signal line; When the line width of the target connection signal line is less than the third line width threshold, the long side direction of the hollow hole is parallel to the extension direction of the target connection signal line; The second line width threshold is greater than the third line width threshold.

14. The display panel according to any one of claims 1 to 10, characterized in that: The target connection signal line includes at least one of a row drive clock signal line, a clock signal line and a power signal line.

15. A display module, characterized in that: include: A display panel as claimed in any one of claims 1 to 14, and a driving component bound and connected to the display panel.

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